2 * Copyright (c) 2003-2013 Broadcom Corporation
4 * Copyright (c) 2009-2010 Micron Technology, Inc.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/module.h>
18 #include <linux/delay.h>
19 #include <linux/mtd/mtd.h>
20 #include <linux/mtd/partitions.h>
21 #include <linux/mtd/nand.h>
22 #include <linux/spi/spi.h>
24 #include "mt29f_spinand.h"
26 #define BUFSIZE (10 * 64 * 2048)
27 #define CACHE_BUF 2112
29 * OOB area specification layout: Total 32 available free bytes.
32 static inline struct spinand_state *mtd_to_state(struct mtd_info *mtd)
34 struct nand_chip *chip = (struct nand_chip *)mtd->priv;
35 struct spinand_info *info = (struct spinand_info *)chip->priv;
36 struct spinand_state *state = (struct spinand_state *)info->priv;
41 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
42 static int enable_hw_ecc;
43 static int enable_read_hw_ecc;
45 static struct nand_ecclayout spinand_oob_64 = {
49 17, 18, 19, 20, 21, 22,
50 33, 34, 35, 36, 37, 38,
51 49, 50, 51, 52, 53, 54, },
67 * spinand_cmd - to process a command to send to the SPI Nand
69 * Set up the command buffer to send to the SPI controller.
70 * The command buffer has to initialized to 0.
73 static int spinand_cmd(struct spi_device *spi, struct spinand_cmd *cmd)
75 struct spi_message message;
76 struct spi_transfer x[4];
79 spi_message_init(&message);
80 memset(x, 0, sizeof(x));
83 x[0].tx_buf = &cmd->cmd;
84 spi_message_add_tail(&x[0], &message);
87 x[1].len = cmd->n_addr;
88 x[1].tx_buf = cmd->addr;
89 spi_message_add_tail(&x[1], &message);
93 x[2].len = cmd->n_dummy;
95 spi_message_add_tail(&x[2], &message);
100 x[3].tx_buf = cmd->tx_buf;
101 spi_message_add_tail(&x[3], &message);
105 x[3].len = cmd->n_rx;
106 x[3].rx_buf = cmd->rx_buf;
107 spi_message_add_tail(&x[3], &message);
110 return spi_sync(spi, &message);
114 * spinand_read_id- Read SPI Nand ID
116 * Read ID: read two ID bytes from the SPI Nand device
118 static int spinand_read_id(struct spi_device *spi_nand, u8 *id)
122 struct spinand_cmd cmd = {0};
124 cmd.cmd = CMD_READ_ID;
126 cmd.rx_buf = &nand_id[0];
128 retval = spinand_cmd(spi_nand, &cmd);
130 dev_err(&spi_nand->dev, "error %d reading id\n", retval);
139 * spinand_read_status- send command 0xf to the SPI Nand status register
141 * After read, write, or erase, the Nand device is expected to set the
143 * This function is to allow reading the status of the command: read,
145 * Once the status turns to be ready, the other status bits also are
148 static int spinand_read_status(struct spi_device *spi_nand, uint8_t *status)
150 struct spinand_cmd cmd = {0};
153 cmd.cmd = CMD_READ_REG;
155 cmd.addr[0] = REG_STATUS;
159 ret = spinand_cmd(spi_nand, &cmd);
161 dev_err(&spi_nand->dev, "err: %d read status register\n", ret);
166 #define MAX_WAIT_JIFFIES (40 * HZ)
167 static int wait_till_ready(struct spi_device *spi_nand)
169 unsigned long deadline;
173 deadline = jiffies + MAX_WAIT_JIFFIES;
175 retval = spinand_read_status(spi_nand, &stat);
178 else if (!(stat & 0x1))
182 } while (!time_after_eq(jiffies, deadline));
184 if ((stat & 0x1) == 0)
190 * spinand_get_otp- send command 0xf to read the SPI Nand OTP register
192 * There is one bit( bit 0x10 ) to set or to clear the internal ECC.
193 * Enable chip internal ECC, set the bit to 1
194 * Disable chip internal ECC, clear the bit to 0
196 static int spinand_get_otp(struct spi_device *spi_nand, u8 *otp)
198 struct spinand_cmd cmd = {0};
201 cmd.cmd = CMD_READ_REG;
203 cmd.addr[0] = REG_OTP;
207 retval = spinand_cmd(spi_nand, &cmd);
209 dev_err(&spi_nand->dev, "error %d get otp\n", retval);
214 * spinand_set_otp- send command 0x1f to write the SPI Nand OTP register
216 * There is one bit( bit 0x10 ) to set or to clear the internal ECC.
217 * Enable chip internal ECC, set the bit to 1
218 * Disable chip internal ECC, clear the bit to 0
220 static int spinand_set_otp(struct spi_device *spi_nand, u8 *otp)
223 struct spinand_cmd cmd = {0};
225 cmd.cmd = CMD_WRITE_REG,
227 cmd.addr[0] = REG_OTP,
231 retval = spinand_cmd(spi_nand, &cmd);
233 dev_err(&spi_nand->dev, "error %d set otp\n", retval);
238 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
240 * spinand_enable_ecc- send command 0x1f to write the SPI Nand OTP register
242 * There is one bit( bit 0x10 ) to set or to clear the internal ECC.
243 * Enable chip internal ECC, set the bit to 1
244 * Disable chip internal ECC, clear the bit to 0
246 static int spinand_enable_ecc(struct spi_device *spi_nand)
251 retval = spinand_get_otp(spi_nand, &otp);
255 if ((otp & OTP_ECC_MASK) == OTP_ECC_MASK)
258 retval = spinand_set_otp(spi_nand, &otp);
261 return spinand_get_otp(spi_nand, &otp);
265 static int spinand_disable_ecc(struct spi_device *spi_nand)
270 retval = spinand_get_otp(spi_nand, &otp);
274 if ((otp & OTP_ECC_MASK) == OTP_ECC_MASK) {
275 otp &= ~OTP_ECC_MASK;
276 retval = spinand_set_otp(spi_nand, &otp);
279 return spinand_get_otp(spi_nand, &otp);
285 * spinand_write_enable- send command 0x06 to enable write or erase the
288 * Before write and erase the Nand cells, the write enable has to be set.
289 * After the write or erase, the write enable bit is automatically
290 * cleared (status register bit 2)
291 * Set the bit 2 of the status register has the same effect
293 static int spinand_write_enable(struct spi_device *spi_nand)
295 struct spinand_cmd cmd = {0};
297 cmd.cmd = CMD_WR_ENABLE;
298 return spinand_cmd(spi_nand, &cmd);
301 static int spinand_read_page_to_cache(struct spi_device *spi_nand, u16 page_id)
303 struct spinand_cmd cmd = {0};
309 cmd.addr[1] = (u8)((row & 0xff00) >> 8);
310 cmd.addr[2] = (u8)(row & 0x00ff);
312 return spinand_cmd(spi_nand, &cmd);
316 * spinand_read_from_cache- send command 0x03 to read out the data from the
317 * cache register(2112 bytes max)
319 * The read can specify 1 to 2112 bytes of data read at the corresponding
323 static int spinand_read_from_cache(struct spi_device *spi_nand, u16 page_id,
324 u16 byte_id, u16 len, u8 *rbuf)
326 struct spinand_cmd cmd = {0};
330 cmd.cmd = CMD_READ_RDM;
332 cmd.addr[0] = (u8)((column & 0xff00) >> 8);
333 cmd.addr[0] |= (u8)(((page_id >> 6) & 0x1) << 4);
334 cmd.addr[1] = (u8)(column & 0x00ff);
335 cmd.addr[2] = (u8)(0xff);
340 return spinand_cmd(spi_nand, &cmd);
344 * spinand_read_page-to read a page with:
345 * @page_id: the physical page number
346 * @offset: the location from 0 to 2111
347 * @len: number of bytes to read
348 * @rbuf: read buffer to hold @len bytes
351 * The read includes two commands to the Nand: 0x13 and 0x03 commands
352 * Poll to read status to wait for tRD time.
354 static int spinand_read_page(struct spi_device *spi_nand, u16 page_id,
355 u16 offset, u16 len, u8 *rbuf)
360 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
361 if (enable_read_hw_ecc) {
362 if (spinand_enable_ecc(spi_nand) < 0)
363 dev_err(&spi_nand->dev, "enable HW ECC failed!");
366 ret = spinand_read_page_to_cache(spi_nand, page_id);
370 if (wait_till_ready(spi_nand))
371 dev_err(&spi_nand->dev, "WAIT timedout!!!\n");
374 ret = spinand_read_status(spi_nand, &status);
376 dev_err(&spi_nand->dev,
377 "err %d read status register\n", ret);
381 if ((status & STATUS_OIP_MASK) == STATUS_READY) {
382 if ((status & STATUS_ECC_MASK) == STATUS_ECC_ERROR) {
383 dev_err(&spi_nand->dev, "ecc error, page=%d\n",
391 ret = spinand_read_from_cache(spi_nand, page_id, offset, len, rbuf);
393 dev_err(&spi_nand->dev, "read from cache failed!!\n");
397 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
398 if (enable_read_hw_ecc) {
399 ret = spinand_disable_ecc(spi_nand);
401 dev_err(&spi_nand->dev, "disable ecc failed!!\n");
404 enable_read_hw_ecc = 0;
411 * spinand_program_data_to_cache--to write a page to cache with:
412 * @byte_id: the location to write to the cache
413 * @len: number of bytes to write
414 * @rbuf: read buffer to hold @len bytes
417 * The write command used here is 0x84--indicating that the cache is
419 * Since it is writing the data to cache, there is no tPROG time.
421 static int spinand_program_data_to_cache(struct spi_device *spi_nand,
422 u16 page_id, u16 byte_id, u16 len, u8 *wbuf)
424 struct spinand_cmd cmd = {0};
428 cmd.cmd = CMD_PROG_PAGE_CLRCACHE;
430 cmd.addr[0] = (u8)((column & 0xff00) >> 8);
431 cmd.addr[0] |= (u8)(((page_id >> 6) & 0x1) << 4);
432 cmd.addr[1] = (u8)(column & 0x00ff);
436 return spinand_cmd(spi_nand, &cmd);
440 * spinand_program_execute--to write a page from cache to the Nand array with
441 * @page_id: the physical page location to write the page.
444 * The write command used here is 0x10--indicating the cache is writing to
446 * Need to wait for tPROG time to finish the transaction.
448 static int spinand_program_execute(struct spi_device *spi_nand, u16 page_id)
450 struct spinand_cmd cmd = {0};
454 cmd.cmd = CMD_PROG_PAGE_EXC;
456 cmd.addr[1] = (u8)((row & 0xff00) >> 8);
457 cmd.addr[2] = (u8)(row & 0x00ff);
459 return spinand_cmd(spi_nand, &cmd);
463 * spinand_program_page--to write a page with:
464 * @page_id: the physical page location to write the page.
465 * @offset: the location from the cache starting from 0 to 2111
466 * @len: the number of bytes to write
467 * @wbuf: the buffer to hold the number of bytes
470 * The commands used here are 0x06, 0x84, and 0x10--indicating that
471 * the write enable is first sent, the write cache command, and the
472 * write execute command.
473 * Poll to wait for the tPROG time to finish the transaction.
475 static int spinand_program_page(struct spi_device *spi_nand,
476 u16 page_id, u16 offset, u16 len, u8 *buf)
481 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
484 enable_read_hw_ecc = 0;
485 wbuf = devm_kzalloc(&spi_nand->dev, CACHE_BUF, GFP_KERNEL);
486 spinand_read_page(spi_nand, page_id, 0, CACHE_BUF, wbuf);
488 for (i = offset, j = 0; i < len; i++, j++)
492 retval = spinand_enable_ecc(spi_nand);
494 dev_err(&spi_nand->dev, "enable ecc failed!!\n");
501 retval = spinand_write_enable(spi_nand);
503 dev_err(&spi_nand->dev, "write enable failed!!\n");
506 if (wait_till_ready(spi_nand))
507 dev_err(&spi_nand->dev, "wait timedout!!!\n");
509 retval = spinand_program_data_to_cache(spi_nand, page_id,
513 retval = spinand_program_execute(spi_nand, page_id);
517 retval = spinand_read_status(spi_nand, &status);
519 dev_err(&spi_nand->dev,
520 "error %d reading status register\n",
525 if ((status & STATUS_OIP_MASK) == STATUS_READY) {
526 if ((status & STATUS_P_FAIL_MASK) == STATUS_P_FAIL) {
527 dev_err(&spi_nand->dev,
528 "program error, page %d\n", page_id);
534 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
536 retval = spinand_disable_ecc(spi_nand);
538 dev_err(&spi_nand->dev, "disable ecc failed!!\n");
549 * spinand_erase_block_erase--to erase a page with:
550 * @block_id: the physical block location to erase.
553 * The command used here is 0xd8--indicating an erase command to erase
554 * one block--64 pages
555 * Need to wait for tERS.
557 static int spinand_erase_block_erase(struct spi_device *spi_nand, u16 block_id)
559 struct spinand_cmd cmd = {0};
563 cmd.cmd = CMD_ERASE_BLK;
565 cmd.addr[1] = (u8)((row & 0xff00) >> 8);
566 cmd.addr[2] = (u8)(row & 0x00ff);
568 return spinand_cmd(spi_nand, &cmd);
572 * spinand_erase_block--to erase a page with:
573 * @block_id: the physical block location to erase.
576 * The commands used here are 0x06 and 0xd8--indicating an erase
577 * command to erase one block--64 pages
578 * It will first to enable the write enable bit (0x06 command),
579 * and then send the 0xd8 erase command
580 * Poll to wait for the tERS time to complete the tranaction.
582 static int spinand_erase_block(struct spi_device *spi_nand, u16 block_id)
587 retval = spinand_write_enable(spi_nand);
588 if (wait_till_ready(spi_nand))
589 dev_err(&spi_nand->dev, "wait timedout!!!\n");
591 retval = spinand_erase_block_erase(spi_nand, block_id);
593 retval = spinand_read_status(spi_nand, &status);
595 dev_err(&spi_nand->dev,
596 "error %d reading status register\n",
601 if ((status & STATUS_OIP_MASK) == STATUS_READY) {
602 if ((status & STATUS_E_FAIL_MASK) == STATUS_E_FAIL) {
603 dev_err(&spi_nand->dev,
604 "erase error, block %d\n", block_id);
613 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
614 static int spinand_write_page_hwecc(struct mtd_info *mtd,
615 struct nand_chip *chip, const uint8_t *buf, int oob_required)
617 const uint8_t *p = buf;
618 int eccsize = chip->ecc.size;
619 int eccsteps = chip->ecc.steps;
622 chip->write_buf(mtd, p, eccsize * eccsteps);
626 static int spinand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
627 uint8_t *buf, int oob_required, int page)
631 int eccsize = chip->ecc.size;
632 int eccsteps = chip->ecc.steps;
633 struct spinand_info *info = (struct spinand_info *)chip->priv;
635 enable_read_hw_ecc = 1;
637 chip->read_buf(mtd, p, eccsize * eccsteps);
639 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
642 retval = spinand_read_status(info->spi, &status);
643 if ((status & STATUS_OIP_MASK) == STATUS_READY) {
644 if ((status & STATUS_ECC_MASK) == STATUS_ECC_ERROR) {
645 pr_info("spinand: ECC error\n");
646 mtd->ecc_stats.failed++;
647 } else if ((status & STATUS_ECC_MASK) ==
648 STATUS_ECC_1BIT_CORRECTED)
649 mtd->ecc_stats.corrected++;
658 static void spinand_select_chip(struct mtd_info *mtd, int dev)
662 static uint8_t spinand_read_byte(struct mtd_info *mtd)
664 struct spinand_state *state = mtd_to_state(mtd);
667 data = state->buf[state->buf_ptr];
673 static int spinand_wait(struct mtd_info *mtd, struct nand_chip *chip)
675 struct spinand_info *info = (struct spinand_info *)chip->priv;
677 unsigned long timeo = jiffies;
678 int retval, state = chip->state;
681 if (state == FL_ERASING)
682 timeo += (HZ * 400) / 1000;
684 timeo += (HZ * 20) / 1000;
686 while (time_before(jiffies, timeo)) {
687 retval = spinand_read_status(info->spi, &status);
688 if ((status & STATUS_OIP_MASK) == STATUS_READY)
696 static void spinand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
699 struct spinand_state *state = mtd_to_state(mtd);
701 memcpy(state->buf + state->buf_ptr, buf, len);
702 state->buf_ptr += len;
705 static void spinand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
707 struct spinand_state *state = mtd_to_state(mtd);
709 memcpy(buf, state->buf + state->buf_ptr, len);
710 state->buf_ptr += len;
714 * spinand_reset- send RESET command "0xff" to the Nand device.
716 static void spinand_reset(struct spi_device *spi_nand)
718 struct spinand_cmd cmd = {0};
722 if (spinand_cmd(spi_nand, &cmd) < 0)
723 pr_info("spinand reset failed!\n");
725 /* elapse 1ms before issuing any other command */
728 if (wait_till_ready(spi_nand))
729 dev_err(&spi_nand->dev, "wait timedout!\n");
732 static void spinand_cmdfunc(struct mtd_info *mtd, unsigned int command,
733 int column, int page)
735 struct nand_chip *chip = (struct nand_chip *)mtd->priv;
736 struct spinand_info *info = (struct spinand_info *)chip->priv;
737 struct spinand_state *state = (struct spinand_state *)info->priv;
741 * READ0 - read in first 0x800 bytes
746 spinand_read_page(info->spi, page, 0x0, 0x840, state->buf);
748 /* READOOB reads only the OOB because no ECC is performed. */
749 case NAND_CMD_READOOB:
751 spinand_read_page(info->spi, page, 0x800, 0x40, state->buf);
753 case NAND_CMD_RNDOUT:
754 state->buf_ptr = column;
756 case NAND_CMD_READID:
758 spinand_read_id(info->spi, (u8 *)state->buf);
763 /* ERASE1 stores the block and page address */
764 case NAND_CMD_ERASE1:
765 spinand_erase_block(info->spi, page);
767 /* ERASE2 uses the block and page address from ERASE1 */
768 case NAND_CMD_ERASE2:
770 /* SEQIN sets up the addr buffer and all registers except the length */
776 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
777 case NAND_CMD_PAGEPROG:
778 spinand_program_page(info->spi, state->row, state->col,
779 state->buf_ptr, state->buf);
781 case NAND_CMD_STATUS:
782 spinand_get_otp(info->spi, state->buf);
783 if (!(state->buf[0] & 0x80))
784 state->buf[0] = 0x80;
789 if (wait_till_ready(info->spi))
790 dev_err(&info->spi->dev, "WAIT timedout!!!\n");
791 /* a minimum of 250us must elapse before issuing RESET cmd*/
793 spinand_reset(info->spi);
796 dev_err(&mtd->dev, "Unknown CMD: 0x%x\n", command);
801 * spinand_lock_block- send write register 0x1f command to the Nand device
804 * After power up, all the Nand blocks are locked. This function allows
805 * one to unlock the blocks, and so it can be written or erased.
807 static int spinand_lock_block(struct spi_device *spi_nand, u8 lock)
809 struct spinand_cmd cmd = {0};
813 ret = spinand_get_otp(spi_nand, &otp);
815 cmd.cmd = CMD_WRITE_REG;
817 cmd.addr[0] = REG_BLOCK_LOCK;
821 ret = spinand_cmd(spi_nand, &cmd);
823 dev_err(&spi_nand->dev, "error %d lock block\n", ret);
828 * spinand_probe - [spinand Interface]
829 * @spi_nand: registered device driver.
832 * To set up the device driver parameters to make the device available.
834 static int spinand_probe(struct spi_device *spi_nand)
836 struct mtd_info *mtd;
837 struct nand_chip *chip;
838 struct spinand_info *info;
839 struct spinand_state *state;
840 struct mtd_part_parser_data ppdata;
842 info = devm_kzalloc(&spi_nand->dev, sizeof(struct spinand_info),
847 info->spi = spi_nand;
849 spinand_lock_block(spi_nand, BL_ALL_UNLOCKED);
851 state = devm_kzalloc(&spi_nand->dev, sizeof(struct spinand_state),
858 state->buf = devm_kzalloc(&spi_nand->dev, BUFSIZE, GFP_KERNEL);
862 chip = devm_kzalloc(&spi_nand->dev, sizeof(struct nand_chip),
867 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
868 chip->ecc.mode = NAND_ECC_HW;
869 chip->ecc.size = 0x200;
870 chip->ecc.bytes = 0x6;
871 chip->ecc.steps = 0x4;
873 chip->ecc.strength = 1;
874 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
875 chip->ecc.layout = &spinand_oob_64;
876 chip->ecc.read_page = spinand_read_page_hwecc;
877 chip->ecc.write_page = spinand_write_page_hwecc;
879 chip->ecc.mode = NAND_ECC_SOFT;
880 if (spinand_disable_ecc(spi_nand) < 0)
881 pr_info("%s: disable ecc failed!\n", __func__);
885 chip->read_buf = spinand_read_buf;
886 chip->write_buf = spinand_write_buf;
887 chip->read_byte = spinand_read_byte;
888 chip->cmdfunc = spinand_cmdfunc;
889 chip->waitfunc = spinand_wait;
890 chip->options |= NAND_CACHEPRG;
891 chip->select_chip = spinand_select_chip;
893 mtd = devm_kzalloc(&spi_nand->dev, sizeof(struct mtd_info), GFP_KERNEL);
897 dev_set_drvdata(&spi_nand->dev, mtd);
900 mtd->name = dev_name(&spi_nand->dev);
901 mtd->owner = THIS_MODULE;
904 if (nand_scan(mtd, 1))
907 ppdata.of_node = spi_nand->dev.of_node;
908 return mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
912 * spinand_remove: Remove the device driver
913 * @spi: the spi device.
916 * To remove the device driver parameters and free up allocated memories.
918 static int spinand_remove(struct spi_device *spi)
920 mtd_device_unregister(dev_get_drvdata(&spi->dev));
925 static const struct of_device_id spinand_dt[] = {
926 { .compatible = "spinand,mt29f", },
931 * Device name structure description
933 static struct spi_driver spinand_driver = {
936 .bus = &spi_bus_type,
937 .owner = THIS_MODULE,
938 .of_match_table = spinand_dt,
940 .probe = spinand_probe,
941 .remove = spinand_remove,
944 module_spi_driver(spinand_driver);
946 MODULE_DESCRIPTION("SPI NAND driver for Micron");
947 MODULE_AUTHOR("Henry Pan <hspan@micron.com>, Kamlakant Patel <kamlakant.patel@broadcom.com>");
948 MODULE_LICENSE("GPL v2");