1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018 Intel Corporation.
4 * Copyright 2018 Google LLC.
6 * Author: Tuukka Toivonen <tuukka.toivonen@intel.com>
7 * Author: Sakari Ailus <sakari.ailus@linux.intel.com>
8 * Author: Samu Onkalo <samu.onkalo@intel.com>
9 * Author: Tomasz Figa <tfiga@chromium.org>
13 #include <linux/dma-mapping.h>
14 #include <linux/iopoll.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/slab.h>
17 #include <linux/vmalloc.h>
19 #include <asm/set_memory.h>
23 #define IPU3_PT_BITS 10
24 #define IPU3_PT_PTES (1UL << IPU3_PT_BITS)
25 #define IPU3_PT_SIZE (IPU3_PT_PTES << 2)
26 #define IPU3_PT_ORDER (IPU3_PT_SIZE >> PAGE_SHIFT)
28 #define IPU3_ADDR2PTE(addr) ((addr) >> IPU3_PAGE_SHIFT)
29 #define IPU3_PTE2ADDR(pte) ((phys_addr_t)(pte) << IPU3_PAGE_SHIFT)
31 #define IPU3_L2PT_SHIFT IPU3_PT_BITS
32 #define IPU3_L2PT_MASK ((1UL << IPU3_L2PT_SHIFT) - 1)
34 #define IPU3_L1PT_SHIFT IPU3_PT_BITS
35 #define IPU3_L1PT_MASK ((1UL << IPU3_L1PT_SHIFT) - 1)
37 #define IPU3_MMU_ADDRESS_BITS (IPU3_PAGE_SHIFT + \
41 #define IMGU_REG_BASE 0x4000
42 #define REG_TLB_INVALIDATE (IMGU_REG_BASE + 0x300)
43 #define TLB_INVALIDATE 1
44 #define REG_L1_PHYS (IMGU_REG_BASE + 0x304) /* 27-bit pfn */
45 #define REG_GP_HALT (IMGU_REG_BASE + 0x5dc)
46 #define REG_GP_HALTED (IMGU_REG_BASE + 0x5e0)
51 /* protect access to l2pts, l1pt */
55 u32 dummy_page_pteval;
58 u32 dummy_l2pt_pteval;
63 struct imgu_mmu_info geometry;
66 static inline struct imgu_mmu *to_imgu_mmu(struct imgu_mmu_info *info)
68 return container_of(info, struct imgu_mmu, geometry);
72 * imgu_mmu_tlb_invalidate - invalidate translation look-aside buffer
73 * @mmu: MMU to perform the invalidate operation on
75 * This function invalidates the whole TLB. Must be called when the hardware
78 static void imgu_mmu_tlb_invalidate(struct imgu_mmu *mmu)
80 writel(TLB_INVALIDATE, mmu->base + REG_TLB_INVALIDATE);
83 static void call_if_imgu_is_powered(struct imgu_mmu *mmu,
84 void (*func)(struct imgu_mmu *mmu))
86 if (!pm_runtime_get_if_in_use(mmu->dev))
90 pm_runtime_put(mmu->dev);
94 * imgu_mmu_set_halt - set CIO gate halt bit
95 * @mmu: MMU to set the CIO gate bit in.
96 * @halt: Desired state of the gate bit.
98 * This function sets the CIO gate bit that controls whether external memory
99 * accesses are allowed. Must be called when the hardware is powered on.
101 static void imgu_mmu_set_halt(struct imgu_mmu *mmu, bool halt)
106 writel(halt, mmu->base + REG_GP_HALT);
107 ret = readl_poll_timeout(mmu->base + REG_GP_HALTED,
108 val, (val & 1) == halt, 1000, 100000);
111 dev_err(mmu->dev, "failed to %s CIO gate halt\n",
112 halt ? "set" : "clear");
116 * imgu_mmu_alloc_page_table - allocate a pre-filled page table
117 * @pteval: Value to initialize for page table entries with.
119 * Return: Pointer to allocated page table or NULL on failure.
121 static u32 *imgu_mmu_alloc_page_table(u32 pteval)
126 pt = (u32 *)__get_free_page(GFP_KERNEL);
130 for (pte = 0; pte < IPU3_PT_PTES; pte++)
133 set_memory_uc((unsigned long int)pt, IPU3_PT_ORDER);
139 * imgu_mmu_free_page_table - free page table
140 * @pt: Page table to free.
142 static void imgu_mmu_free_page_table(u32 *pt)
144 set_memory_wb((unsigned long int)pt, IPU3_PT_ORDER);
145 free_page((unsigned long)pt);
149 * address_to_pte_idx - split IOVA into L1 and L2 page table indices
150 * @iova: IOVA to split.
151 * @l1pt_idx: Output for the L1 page table index.
152 * @l2pt_idx: Output for the L2 page index.
154 static inline void address_to_pte_idx(unsigned long iova, u32 *l1pt_idx,
157 iova >>= IPU3_PAGE_SHIFT;
160 *l2pt_idx = iova & IPU3_L2PT_MASK;
162 iova >>= IPU3_L2PT_SHIFT;
165 *l1pt_idx = iova & IPU3_L1PT_MASK;
168 static u32 *imgu_mmu_get_l2pt(struct imgu_mmu *mmu, u32 l1pt_idx)
171 u32 *l2pt, *new_l2pt;
174 spin_lock_irqsave(&mmu->lock, flags);
176 l2pt = mmu->l2pts[l1pt_idx];
178 spin_unlock_irqrestore(&mmu->lock, flags);
182 spin_unlock_irqrestore(&mmu->lock, flags);
184 new_l2pt = imgu_mmu_alloc_page_table(mmu->dummy_page_pteval);
188 spin_lock_irqsave(&mmu->lock, flags);
190 dev_dbg(mmu->dev, "allocated page table %p for l1pt_idx %u\n",
193 l2pt = mmu->l2pts[l1pt_idx];
195 spin_unlock_irqrestore(&mmu->lock, flags);
196 imgu_mmu_free_page_table(new_l2pt);
201 mmu->l2pts[l1pt_idx] = new_l2pt;
203 pteval = IPU3_ADDR2PTE(virt_to_phys(new_l2pt));
204 mmu->l1pt[l1pt_idx] = pteval;
206 spin_unlock_irqrestore(&mmu->lock, flags);
210 static int __imgu_mmu_map(struct imgu_mmu *mmu, unsigned long iova,
213 u32 l1pt_idx, l2pt_idx;
220 address_to_pte_idx(iova, &l1pt_idx, &l2pt_idx);
222 l2pt = imgu_mmu_get_l2pt(mmu, l1pt_idx);
226 spin_lock_irqsave(&mmu->lock, flags);
228 if (l2pt[l2pt_idx] != mmu->dummy_page_pteval) {
229 spin_unlock_irqrestore(&mmu->lock, flags);
233 l2pt[l2pt_idx] = IPU3_ADDR2PTE(paddr);
235 spin_unlock_irqrestore(&mmu->lock, flags);
241 * imgu_mmu_map - map a buffer to a physical address
243 * @info: MMU mappable range
244 * @iova: the virtual address
245 * @paddr: the physical address
246 * @size: length of the mappable area
248 * The function has been adapted from iommu_map() in
249 * drivers/iommu/iommu.c .
251 int imgu_mmu_map(struct imgu_mmu_info *info, unsigned long iova,
252 phys_addr_t paddr, size_t size)
254 struct imgu_mmu *mmu = to_imgu_mmu(info);
258 * both the virtual address and the physical one, as well as
259 * the size of the mapping, must be aligned (at least) to the
260 * size of the smallest page supported by the hardware
262 if (!IS_ALIGNED(iova | paddr | size, IPU3_PAGE_SIZE)) {
263 dev_err(mmu->dev, "unaligned: iova 0x%lx pa %pa size 0x%zx\n",
268 dev_dbg(mmu->dev, "map: iova 0x%lx pa %pa size 0x%zx\n",
272 dev_dbg(mmu->dev, "mapping: iova 0x%lx pa %pa\n", iova, &paddr);
274 ret = __imgu_mmu_map(mmu, iova, paddr);
278 iova += IPU3_PAGE_SIZE;
279 paddr += IPU3_PAGE_SIZE;
280 size -= IPU3_PAGE_SIZE;
283 call_if_imgu_is_powered(mmu, imgu_mmu_tlb_invalidate);
289 * imgu_mmu_map_sg - Map a scatterlist
291 * @info: MMU mappable range
292 * @iova: the virtual address
293 * @sg: the scatterlist to map
294 * @nents: number of entries in the scatterlist
296 * The function has been adapted from default_iommu_map_sg() in
297 * drivers/iommu/iommu.c .
299 size_t imgu_mmu_map_sg(struct imgu_mmu_info *info, unsigned long iova,
300 struct scatterlist *sg, unsigned int nents)
302 struct imgu_mmu *mmu = to_imgu_mmu(info);
303 struct scatterlist *s;
304 size_t s_length, mapped = 0;
308 for_each_sg(sg, s, nents, i) {
309 phys_addr_t phys = page_to_phys(sg_page(s)) + s->offset;
311 s_length = s->length;
313 if (!IS_ALIGNED(s->offset, IPU3_PAGE_SIZE))
316 /* must be IPU3_PAGE_SIZE aligned to be mapped singlely */
317 if (i == nents - 1 && !IS_ALIGNED(s->length, IPU3_PAGE_SIZE))
318 s_length = PAGE_ALIGN(s->length);
320 ret = imgu_mmu_map(info, iova + mapped, phys, s_length);
327 call_if_imgu_is_powered(mmu, imgu_mmu_tlb_invalidate);
332 /* undo mappings already done */
333 imgu_mmu_unmap(info, iova, mapped);
338 static size_t __imgu_mmu_unmap(struct imgu_mmu *mmu,
339 unsigned long iova, size_t size)
341 u32 l1pt_idx, l2pt_idx;
349 address_to_pte_idx(iova, &l1pt_idx, &l2pt_idx);
351 spin_lock_irqsave(&mmu->lock, flags);
353 l2pt = mmu->l2pts[l1pt_idx];
355 spin_unlock_irqrestore(&mmu->lock, flags);
359 if (l2pt[l2pt_idx] == mmu->dummy_page_pteval)
362 l2pt[l2pt_idx] = mmu->dummy_page_pteval;
364 spin_unlock_irqrestore(&mmu->lock, flags);
370 * imgu_mmu_unmap - Unmap a buffer
372 * @info: MMU mappable range
373 * @iova: the virtual address
374 * @size: the length of the buffer
376 * The function has been adapted from iommu_unmap() in
377 * drivers/iommu/iommu.c .
379 size_t imgu_mmu_unmap(struct imgu_mmu_info *info, unsigned long iova,
382 struct imgu_mmu *mmu = to_imgu_mmu(info);
383 size_t unmapped_page, unmapped = 0;
386 * The virtual address, as well as the size of the mapping, must be
387 * aligned (at least) to the size of the smallest page supported
390 if (!IS_ALIGNED(iova | size, IPU3_PAGE_SIZE)) {
391 dev_err(mmu->dev, "unaligned: iova 0x%lx size 0x%zx\n",
396 dev_dbg(mmu->dev, "unmap this: iova 0x%lx size 0x%zx\n", iova, size);
399 * Keep iterating until we either unmap 'size' bytes (or more)
400 * or we hit an area that isn't mapped.
402 while (unmapped < size) {
403 unmapped_page = __imgu_mmu_unmap(mmu, iova, IPU3_PAGE_SIZE);
407 dev_dbg(mmu->dev, "unmapped: iova 0x%lx size 0x%zx\n",
408 iova, unmapped_page);
410 iova += unmapped_page;
411 unmapped += unmapped_page;
414 call_if_imgu_is_powered(mmu, imgu_mmu_tlb_invalidate);
420 * imgu_mmu_init() - initialize IPU3 MMU block
422 * @parent: struct device parent
423 * @base: IOMEM base of hardware registers.
425 * Return: Pointer to IPU3 MMU private data pointer or ERR_PTR() on error.
427 struct imgu_mmu_info *imgu_mmu_init(struct device *parent, void __iomem *base)
429 struct imgu_mmu *mmu;
432 mmu = kzalloc(sizeof(*mmu), GFP_KERNEL);
434 return ERR_PTR(-ENOMEM);
438 spin_lock_init(&mmu->lock);
440 /* Disallow external memory access when having no valid page tables. */
441 imgu_mmu_set_halt(mmu, true);
444 * The MMU does not have a "valid" bit, so we have to use a dummy
445 * page for invalid entries.
447 mmu->dummy_page = (void *)__get_free_page(GFP_KERNEL);
448 if (!mmu->dummy_page)
450 pteval = IPU3_ADDR2PTE(virt_to_phys(mmu->dummy_page));
451 mmu->dummy_page_pteval = pteval;
454 * Allocate a dummy L2 page table with all entries pointing to
457 mmu->dummy_l2pt = imgu_mmu_alloc_page_table(pteval);
458 if (!mmu->dummy_l2pt)
459 goto fail_dummy_page;
460 pteval = IPU3_ADDR2PTE(virt_to_phys(mmu->dummy_l2pt));
461 mmu->dummy_l2pt_pteval = pteval;
464 * Allocate the array of L2PT CPU pointers, initialized to zero,
465 * which means the dummy L2PT allocated above.
467 mmu->l2pts = vzalloc(IPU3_PT_PTES * sizeof(*mmu->l2pts));
471 /* Allocate the L1 page table. */
472 mmu->l1pt = imgu_mmu_alloc_page_table(mmu->dummy_l2pt_pteval);
476 pteval = IPU3_ADDR2PTE(virt_to_phys(mmu->l1pt));
477 writel(pteval, mmu->base + REG_L1_PHYS);
478 imgu_mmu_tlb_invalidate(mmu);
479 imgu_mmu_set_halt(mmu, false);
481 mmu->geometry.aperture_start = 0;
482 mmu->geometry.aperture_end = DMA_BIT_MASK(IPU3_MMU_ADDRESS_BITS);
484 return &mmu->geometry;
489 imgu_mmu_free_page_table(mmu->dummy_l2pt);
491 free_page((unsigned long)mmu->dummy_page);
495 return ERR_PTR(-ENOMEM);
499 * imgu_mmu_exit() - clean up IPU3 MMU block
501 * @info: MMU mappable range
503 void imgu_mmu_exit(struct imgu_mmu_info *info)
505 struct imgu_mmu *mmu = to_imgu_mmu(info);
507 /* We are going to free our page tables, no more memory access. */
508 imgu_mmu_set_halt(mmu, true);
509 imgu_mmu_tlb_invalidate(mmu);
511 imgu_mmu_free_page_table(mmu->l1pt);
513 imgu_mmu_free_page_table(mmu->dummy_l2pt);
514 free_page((unsigned long)mmu->dummy_page);
518 void imgu_mmu_suspend(struct imgu_mmu_info *info)
520 struct imgu_mmu *mmu = to_imgu_mmu(info);
522 imgu_mmu_set_halt(mmu, true);
525 void imgu_mmu_resume(struct imgu_mmu_info *info)
527 struct imgu_mmu *mmu = to_imgu_mmu(info);
530 imgu_mmu_set_halt(mmu, true);
532 pteval = IPU3_ADDR2PTE(virt_to_phys(mmu->l1pt));
533 writel(pteval, mmu->base + REG_L1_PHYS);
535 imgu_mmu_tlb_invalidate(mmu);
536 imgu_mmu_set_halt(mmu, false);