drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_system_ctrl_defs.h

   1 /*
   2  * Support for Intel Camera Imaging ISP subsystem.
   3  * Copyright (c) 2015, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #ifndef _input_system_ctrl_defs_h
  16 #define _input_system_ctrl_defs_h
  17
  18 #define _INPUT_SYSTEM_CTRL_REG_ALIGN                    4  /* assuming 32 bit control bus width */
  19
  20 /* --------------------------------------------------*/
  21
  22 /* --------------------------------------------------*/
  23 /* REGISTER INFO */
  24 /* --------------------------------------------------*/
  25
  26 // Number of registers
  27 #define ISYS_CTRL_NOF_REGS                              23
  28
  29 // Register id's of MMIO slave accesible registers
  30 #define ISYS_CTRL_CAPT_START_ADDR_A_REG_ID              0
  31 #define ISYS_CTRL_CAPT_START_ADDR_B_REG_ID              1
  32 #define ISYS_CTRL_CAPT_START_ADDR_C_REG_ID              2
  33 #define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_ID         3
  34 #define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_ID         4
  35 #define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_ID         5
  36 #define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_ID         6
  37 #define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_ID         7
  38 #define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_ID         8
  39 #define ISYS_CTRL_ACQ_START_ADDR_REG_ID                 9
  40 #define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_ID            10
  41 #define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_ID            11
  42 #define ISYS_CTRL_INIT_REG_ID                           12
  43 #define ISYS_CTRL_LAST_COMMAND_REG_ID                   13
  44 #define ISYS_CTRL_NEXT_COMMAND_REG_ID                   14
  45 #define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_ID               15
  46 #define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_ID               16
  47 #define ISYS_CTRL_FSM_STATE_INFO_REG_ID                 17
  48 #define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_ID          18
  49 #define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_ID          19
  50 #define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_ID          20
  51 #define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_ID             21
  52 #define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_ID    22
  53
  54
  55 /* register reset value */
  56 #define ISYS_CTRL_CAPT_START_ADDR_A_REG_RSTVAL           0
  57 #define ISYS_CTRL_CAPT_START_ADDR_B_REG_RSTVAL           0
  58 #define ISYS_CTRL_CAPT_START_ADDR_C_REG_RSTVAL           0
  59 #define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_RSTVAL      128
  60 #define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_RSTVAL      128
  61 #define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_RSTVAL      128
  62 #define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_RSTVAL      3
  63 #define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_RSTVAL      3
  64 #define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_RSTVAL      3
  65 #define ISYS_CTRL_ACQ_START_ADDR_REG_RSTVAL              0
  66 #define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_RSTVAL         128
  67 #define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_RSTVAL         3
  68 #define ISYS_CTRL_INIT_REG_RSTVAL                        0
  69 #define ISYS_CTRL_LAST_COMMAND_REG_RSTVAL                15    //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
  70 #define ISYS_CTRL_NEXT_COMMAND_REG_RSTVAL                15    //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
  71 #define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_RSTVAL            15    //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
  72 #define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_RSTVAL            15    //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset)
  73 #define ISYS_CTRL_FSM_STATE_INFO_REG_RSTVAL              0
  74 #define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_RSTVAL       0
  75 #define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_RSTVAL       0
  76 #define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_RSTVAL       0
  77 #define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_RSTVAL          0
  78 #define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_RSTVAL 0
  79
  80 /* register width value */
  81 #define ISYS_CTRL_CAPT_START_ADDR_A_REG_WIDTH            9
  82 #define ISYS_CTRL_CAPT_START_ADDR_B_REG_WIDTH            9
  83 #define ISYS_CTRL_CAPT_START_ADDR_C_REG_WIDTH            9
  84 #define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_WIDTH       9
  85 #define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_WIDTH       9
  86 #define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_WIDTH       9
  87 #define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_WIDTH       9
  88 #define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_WIDTH       9
  89 #define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_WIDTH       9
  90 #define ISYS_CTRL_ACQ_START_ADDR_REG_WIDTH               9
  91 #define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_WIDTH          9
  92 #define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_WIDTH          9
  93 #define ISYS_CTRL_INIT_REG_WIDTH                         3
  94 #define ISYS_CTRL_LAST_COMMAND_REG_WIDTH                 32    /* slave data width */
  95 #define ISYS_CTRL_NEXT_COMMAND_REG_WIDTH                 32
  96 #define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_WIDTH             32
  97 #define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_WIDTH             32
  98 #define ISYS_CTRL_FSM_STATE_INFO_REG_WIDTH               32
  99 #define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_WIDTH        32
 100 #define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_WIDTH        32
 101 #define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_WIDTH        32
 102 #define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_WIDTH           32
 103 #define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_WIDTH  1
 104
 105 /* bit definitions */
 106
 107 /* --------------------------------------------------*/
 108 /* TOKEN INFO */
 109 /* --------------------------------------------------*/
 110
 111 /*
 112 InpSysCaptFramesAcq  1/0  [3:0] - 'b0000
 113 [7:4] - CaptPortId,
 114            CaptA-'b0000
 115            CaptB-'b0001
 116            CaptC-'b0010
 117 [31:16] - NOF_frames
 118 InpSysCaptFrameExt  2/0  [3:0] - 'b0001'
 119 [7:4] - CaptPortId,
 120            'b0000 - CaptA
 121            'b0001 - CaptB
 122            'b0010 - CaptC
 123
 124   2/1  [31:0] - external capture address
 125 InpSysAcqFrame  2/0  [3:0] - 'b0010,
 126 [31:4] - NOF_ext_mem_words
 127   2/1  [31:0] - external memory read start address
 128 InpSysOverruleON  1/0  [3:0] - 'b0011,
 129 [7:4] - overrule port id (opid)
 130            'b0000 - CaptA
 131            'b0001 - CaptB
 132            'b0010 - CaptC
 133            'b0011 - Acq
 134            'b0100 - DMA
 135
 136
 137 InpSysOverruleOFF  1/0  [3:0] - 'b0100,
 138 [7:4] - overrule port id (opid)
 139            'b0000 - CaptA
 140            'b0001 - CaptB
 141            'b0010 - CaptC
 142            'b0011 - Acq
 143            'b0100 - DMA
 144
 145
 146 InpSysOverruleCmd  2/0  [3:0] - 'b0101,
 147 [7:4] - overrule port id (opid)
 148            'b0000 - CaptA
 149            'b0001 - CaptB
 150            'b0010 - CaptC
 151            'b0011 - Acq
 152            'b0100 - DMA
 153
 154
 155   2/1  [31:0] - command token value for port opid
 156
 157
 158 acknowledge tokens:
 159
 160 InpSysAckCFA  1/0   [3:0] - 'b0000
 161  [7:4] - CaptPortId,
 162            CaptA-'b0000
 163            CaptB- 'b0001
 164            CaptC-'b0010
 165  [31:16] - NOF_frames
 166 InpSysAckCFE  1/0  [3:0] - 'b0001'
 167 [7:4] - CaptPortId,
 168            'b0000 - CaptA
 169            'b0001 - CaptB
 170            'b0010 - CaptC
 171
 172 InpSysAckAF  1/0  [3:0] - 'b0010
 173 InpSysAckOverruleON  1/0  [3:0] - 'b0011,
 174 [7:4] - overrule port id (opid)
 175            'b0000 - CaptA
 176            'b0001 - CaptB
 177            'b0010 - CaptC
 178            'b0011 - Acq
 179            'b0100 - DMA
 180
 181
 182 InpSysAckOverruleOFF  1/0  [3:0] - 'b0100,
 183 [7:4] - overrule port id (opid)
 184            'b0000 - CaptA
 185            'b0001 - CaptB
 186            'b0010 - CaptC
 187            'b0011 - Acq
 188            'b0100 - DMA
 189
 190
 191 InpSysAckOverrule  2/0  [3:0] - 'b0101,
 192 [7:4] - overrule port id (opid)
 193            'b0000 - CaptA
 194            'b0001 - CaptB
 195            'b0010 - CaptC
 196            'b0011 - Acq
 197            'b0100 - DMA
 198
 199
 200   2/1  [31:0] - acknowledge token value from port opid
 201
 202
 203
 204 */
 205
 206
 207 /* Command and acknowledge tokens IDs */
 208 #define ISYS_CTRL_CAPT_FRAMES_ACQ_TOKEN_ID        0 /* 0000b */
 209 #define ISYS_CTRL_CAPT_FRAME_EXT_TOKEN_ID         1 /* 0001b */
 210 #define ISYS_CTRL_ACQ_FRAME_TOKEN_ID              2 /* 0010b */
 211 #define ISYS_CTRL_OVERRULE_ON_TOKEN_ID            3 /* 0011b */
 212 #define ISYS_CTRL_OVERRULE_OFF_TOKEN_ID           4 /* 0100b */
 213 #define ISYS_CTRL_OVERRULE_TOKEN_ID               5 /* 0101b */
 214
 215 #define ISYS_CTRL_ACK_CFA_TOKEN_ID                0
 216 #define ISYS_CTRL_ACK_CFE_TOKEN_ID                1
 217 #define ISYS_CTRL_ACK_AF_TOKEN_ID                 2
 218 #define ISYS_CTRL_ACK_OVERRULE_ON_TOKEN_ID        3
 219 #define ISYS_CTRL_ACK_OVERRULE_OFF_TOKEN_ID       4
 220 #define ISYS_CTRL_ACK_OVERRULE_TOKEN_ID           5
 221 #define ISYS_CTRL_ACK_DEVICE_ERROR_TOKEN_ID       6
 222
 223 #define ISYS_CTRL_TOKEN_ID_MSB                    3
 224 #define ISYS_CTRL_TOKEN_ID_LSB                    0
 225 #define ISYS_CTRL_PORT_ID_TOKEN_MSB               7
 226 #define ISYS_CTRL_PORT_ID_TOKEN_LSB               4
 227 #define ISYS_CTRL_NOF_CAPT_TOKEN_MSB              31
 228 #define ISYS_CTRL_NOF_CAPT_TOKEN_LSB              16
 229 #define ISYS_CTRL_NOF_EXT_TOKEN_MSB               31
 230 #define ISYS_CTRL_NOF_EXT_TOKEN_LSB               8
 231
 232 #define ISYS_CTRL_TOKEN_ID_IDX                    0
 233 #define ISYS_CTRL_TOKEN_ID_BITS                   (ISYS_CTRL_TOKEN_ID_MSB - ISYS_CTRL_TOKEN_ID_LSB + 1)
 234 #define ISYS_CTRL_PORT_ID_IDX                     (ISYS_CTRL_TOKEN_ID_IDX + ISYS_CTRL_TOKEN_ID_BITS)
 235 #define ISYS_CTRL_PORT_ID_BITS                    (ISYS_CTRL_PORT_ID_TOKEN_MSB - ISYS_CTRL_PORT_ID_TOKEN_LSB +1)
 236 #define ISYS_CTRL_NOF_CAPT_IDX                    ISYS_CTRL_NOF_CAPT_TOKEN_LSB
 237 #define ISYS_CTRL_NOF_CAPT_BITS                   (ISYS_CTRL_NOF_CAPT_TOKEN_MSB - ISYS_CTRL_NOF_CAPT_TOKEN_LSB + 1)
 238 #define ISYS_CTRL_NOF_EXT_IDX                     ISYS_CTRL_NOF_EXT_TOKEN_LSB
 239 #define ISYS_CTRL_NOF_EXT_BITS                    (ISYS_CTRL_NOF_EXT_TOKEN_MSB - ISYS_CTRL_NOF_EXT_TOKEN_LSB + 1)
 240
 241 #define ISYS_CTRL_PORT_ID_CAPT_A                  0 /* device ID for capture unit A      */
 242 #define ISYS_CTRL_PORT_ID_CAPT_B                  1 /* device ID for capture unit B      */
 243 #define ISYS_CTRL_PORT_ID_CAPT_C                  2 /* device ID for capture unit C      */
 244 #define ISYS_CTRL_PORT_ID_ACQUISITION             3 /* device ID for acquistion unit     */
 245 #define ISYS_CTRL_PORT_ID_DMA_CAPT_A              4 /* device ID for dma unit            */
 246 #define ISYS_CTRL_PORT_ID_DMA_CAPT_B              5 /* device ID for dma unit            */
 247 #define ISYS_CTRL_PORT_ID_DMA_CAPT_C              6 /* device ID for dma unit            */
 248 #define ISYS_CTRL_PORT_ID_DMA_ACQ                 7 /* device ID for dma unit            */
 249
 250 #define ISYS_CTRL_NO_ACQ_ACK                      16 /* no ack from acquisition unit */
 251 #define ISYS_CTRL_NO_DMA_ACK                      0
 252 #define ISYS_CTRL_NO_CAPT_ACK                     16
 253
 254 #endif /* _input_system_ctrl_defs_h */