drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/dma_v2_defs.h

   1 /*
   2  * Support for Intel Camera Imaging ISP subsystem.
   3  * Copyright (c) 2015, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #ifndef _dma_v2_defs_h
  16 #define _dma_v2_defs_h
  17
  18 #define _DMA_V2_NUM_CHANNELS_ID               MaxNumChannels
  19 #define _DMA_V2_CONNECTIONS_ID                Connections
  20 #define _DMA_V2_DEV_ELEM_WIDTHS_ID            DevElemWidths
  21 #define _DMA_V2_DEV_FIFO_DEPTH_ID             DevFifoDepth
  22 #define _DMA_V2_DEV_FIFO_RD_LAT_ID            DevFifoRdLat
  23 #define _DMA_V2_DEV_FIFO_LAT_BYPASS_ID        DevFifoRdLatBypass
  24 #define _DMA_V2_DEV_NO_BURST_ID               DevNoBurst
  25 #define _DMA_V2_DEV_RD_ACCEPT_ID              DevRdAccept
  26 #define _DMA_V2_DEV_SRMD_ID                   DevSRMD
  27 #define _DMA_V2_DEV_HAS_CRUN_ID               CRunMasters
  28 #define _DMA_V2_CTRL_ACK_FIFO_DEPTH_ID        CtrlAckFifoDepth
  29 #define _DMA_V2_CMD_FIFO_DEPTH_ID             CommandFifoDepth
  30 #define _DMA_V2_CMD_FIFO_RD_LAT_ID            CommandFifoRdLat
  31 #define _DMA_V2_CMD_FIFO_LAT_BYPASS_ID        CommandFifoRdLatBypass
  32 #define _DMA_V2_NO_PACK_ID                    has_no_pack
  33
  34 #define _DMA_V2_REG_ALIGN                4
  35 #define _DMA_V2_REG_ADDR_BITS            2
  36
  37 /* Command word */
  38 #define _DMA_V2_CMD_IDX            0
  39 #define _DMA_V2_CMD_BITS           6
  40 #define _DMA_V2_CHANNEL_IDX        (_DMA_V2_CMD_IDX + _DMA_V2_CMD_BITS)
  41 #define _DMA_V2_CHANNEL_BITS       5
  42
  43 /* The command to set a parameter contains the PARAM field next */
  44 #define _DMA_V2_PARAM_IDX          (_DMA_V2_CHANNEL_IDX + _DMA_V2_CHANNEL_BITS)
  45 #define _DMA_V2_PARAM_BITS         4
  46
  47 /* Commands to read, write or init specific blocks contain these
  48    three values */
  49 #define _DMA_V2_SPEC_DEV_A_XB_IDX  (_DMA_V2_CHANNEL_IDX + _DMA_V2_CHANNEL_BITS)
  50 #define _DMA_V2_SPEC_DEV_A_XB_BITS 8
  51 #define _DMA_V2_SPEC_DEV_B_XB_IDX  (_DMA_V2_SPEC_DEV_A_XB_IDX + _DMA_V2_SPEC_DEV_A_XB_BITS)
  52 #define _DMA_V2_SPEC_DEV_B_XB_BITS 8
  53 #define _DMA_V2_SPEC_YB_IDX        (_DMA_V2_SPEC_DEV_B_XB_IDX + _DMA_V2_SPEC_DEV_B_XB_BITS)
  54 #define _DMA_V2_SPEC_YB_BITS       (32-_DMA_V2_SPEC_DEV_B_XB_BITS-_DMA_V2_SPEC_DEV_A_XB_BITS-_DMA_V2_CMD_BITS-_DMA_V2_CHANNEL_BITS)
  55
  56 /* */
  57 #define _DMA_V2_CMD_CTRL_IDX       4
  58 #define _DMA_V2_CMD_CTRL_BITS      4
  59
  60 /* Packing setup word */
  61 #define _DMA_V2_CONNECTION_IDX     0
  62 #define _DMA_V2_CONNECTION_BITS    4
  63 #define _DMA_V2_EXTENSION_IDX      (_DMA_V2_CONNECTION_IDX + _DMA_V2_CONNECTION_BITS)
  64 #define _DMA_V2_EXTENSION_BITS     1
  65
  66 /* Elements packing word */
  67 #define _DMA_V2_ELEMENTS_IDX        0
  68 #define _DMA_V2_ELEMENTS_BITS       8
  69 #define _DMA_V2_LEFT_CROPPING_IDX  (_DMA_V2_ELEMENTS_IDX + _DMA_V2_ELEMENTS_BITS)
  70 #define _DMA_V2_LEFT_CROPPING_BITS  8
  71
  72 #define _DMA_V2_WIDTH_IDX           0
  73 #define _DMA_V2_WIDTH_BITS         16
  74
  75 #define _DMA_V2_HEIGHT_IDX          0
  76 #define _DMA_V2_HEIGHT_BITS        16
  77
  78 #define _DMA_V2_STRIDE_IDX          0
  79 #define _DMA_V2_STRIDE_BITS        32
  80
  81 /* Command IDs */
  82 #define _DMA_V2_MOVE_B2A_COMMAND                             0
  83 #define _DMA_V2_MOVE_B2A_BLOCK_COMMAND                       1
  84 #define _DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND                 2
  85 #define _DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND           3
  86 #define _DMA_V2_MOVE_A2B_COMMAND                             4
  87 #define _DMA_V2_MOVE_A2B_BLOCK_COMMAND                       5
  88 #define _DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND                 6
  89 #define _DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND           7
  90 #define _DMA_V2_INIT_A_COMMAND                               8
  91 #define _DMA_V2_INIT_A_BLOCK_COMMAND                         9
  92 #define _DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND                  10
  93 #define _DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND            11
  94 #define _DMA_V2_INIT_B_COMMAND                              12
  95 #define _DMA_V2_INIT_B_BLOCK_COMMAND                        13
  96 #define _DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND                  14
  97 #define _DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND            15
  98 #define _DMA_V2_NO_ACK_MOVE_B2A_NO_SYNC_CHK_COMMAND         (_DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND       + 16)
  99 #define _DMA_V2_NO_ACK_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND   (_DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND + 16)
 100 #define _DMA_V2_NO_ACK_MOVE_A2B_NO_SYNC_CHK_COMMAND         (_DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND       + 16)
 101 #define _DMA_V2_NO_ACK_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND   (_DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND + 16)
 102 #define _DMA_V2_NO_ACK_INIT_A_NO_SYNC_CHK_COMMAND           (_DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND         + 16)
 103 #define _DMA_V2_NO_ACK_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND     (_DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND   + 16)
 104 #define _DMA_V2_NO_ACK_INIT_B_NO_SYNC_CHK_COMMAND           (_DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND         + 16)
 105 #define _DMA_V2_NO_ACK_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND     (_DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND   + 16)
 106 #define _DMA_V2_CONFIG_CHANNEL_COMMAND                      32
 107 #define _DMA_V2_SET_CHANNEL_PARAM_COMMAND                   33
 108 #define _DMA_V2_SET_CRUN_COMMAND                            62
 109
 110 /* Channel Parameter IDs */
 111 #define _DMA_V2_PACKING_SETUP_PARAM                     0
 112 #define _DMA_V2_STRIDE_A_PARAM                          1
 113 #define _DMA_V2_ELEM_CROPPING_A_PARAM                   2
 114 #define _DMA_V2_WIDTH_A_PARAM                           3
 115 #define _DMA_V2_STRIDE_B_PARAM                          4
 116 #define _DMA_V2_ELEM_CROPPING_B_PARAM                   5
 117 #define _DMA_V2_WIDTH_B_PARAM                           6
 118 #define _DMA_V2_HEIGHT_PARAM                            7
 119 #define _DMA_V2_QUEUED_CMDS                             8
 120
 121 /* Parameter Constants */
 122 #define _DMA_V2_ZERO_EXTEND                             0
 123 #define _DMA_V2_SIGN_EXTEND                             1
 124
 125   /* SLAVE address map */
 126 #define _DMA_V2_SEL_FSM_CMD                             0
 127 #define _DMA_V2_SEL_CH_REG                              1
 128 #define _DMA_V2_SEL_CONN_GROUP                          2
 129 #define _DMA_V2_SEL_DEV_INTERF                          3
 130
 131 #define _DMA_V2_ADDR_SEL_COMP_IDX                      12
 132 #define _DMA_V2_ADDR_SEL_COMP_BITS                      4
 133 #define _DMA_V2_ADDR_SEL_CH_REG_IDX                     2
 134 #define _DMA_V2_ADDR_SEL_CH_REG_BITS                    6
 135 #define _DMA_V2_ADDR_SEL_PARAM_IDX                      (_DMA_V2_ADDR_SEL_CH_REG_BITS+_DMA_V2_ADDR_SEL_CH_REG_IDX)
 136 #define _DMA_V2_ADDR_SEL_PARAM_BITS                     4
 137
 138 #define _DMA_V2_ADDR_SEL_GROUP_COMP_IDX                 2
 139 #define _DMA_V2_ADDR_SEL_GROUP_COMP_BITS                6
 140 #define _DMA_V2_ADDR_SEL_GROUP_COMP_INFO_IDX            (_DMA_V2_ADDR_SEL_GROUP_COMP_BITS + _DMA_V2_ADDR_SEL_GROUP_COMP_IDX)
 141 #define _DMA_V2_ADDR_SEL_GROUP_COMP_INFO_BITS           4
 142
 143 #define _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX             2
 144 #define _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS            6
 145 #define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_IDX            (_DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX+_DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS)
 146 #define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_BITS           4
 147
 148 #define _DMA_V2_FSM_GROUP_CMD_IDX                       0
 149 #define _DMA_V2_FSM_GROUP_ADDR_SRC_IDX                  1
 150 #define _DMA_V2_FSM_GROUP_ADDR_DEST_IDX                 2
 151 #define _DMA_V2_FSM_GROUP_CMD_CTRL_IDX                  3
 152 #define _DMA_V2_FSM_GROUP_FSM_CTRL_IDX                  4
 153 #define _DMA_V2_FSM_GROUP_FSM_PACK_IDX                  5
 154 #define _DMA_V2_FSM_GROUP_FSM_REQ_IDX                   6
 155 #define _DMA_V2_FSM_GROUP_FSM_WR_IDX                    7
 156
 157 #define _DMA_V2_FSM_GROUP_FSM_CTRL_STATE_IDX            0
 158 #define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_DEV_IDX          1
 159 #define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_ADDR_IDX         2
 160 #define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_STRIDE_IDX       3
 161 #define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_XB_IDX           4
 162 #define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_YB_IDX           5
 163 #define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_REQ_DEV_IDX     6
 164 #define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_DEV_IDX      7
 165 #define _DMA_V2_FSM_GROUP_FSM_CTRL_WR_ADDR_IDX          8
 166 #define _DMA_V2_FSM_GROUP_FSM_CTRL_WR_STRIDE_IDX        9
 167 #define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_REQ_XB_IDX     10
 168 #define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_YB_IDX      11
 169 #define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_XB_IDX      12
 170 #define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_ELEM_REQ_IDX   13
 171 #define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_ELEM_WR_IDX    14
 172 #define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_S_Z_IDX        15
 173 #define _DMA_V2_FSM_GROUP_FSM_CTRL_CMD_CTRL_IDX        15
 174
 175 #define _DMA_V2_FSM_GROUP_FSM_PACK_STATE_IDX            0
 176 #define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_YB_IDX           1
 177 #define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_XB_REQ_IDX       2
 178 #define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_XB_WR_IDX        3
 179
 180 #define _DMA_V2_FSM_GROUP_FSM_REQ_STATE_IDX             0
 181 #define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_YB_IDX            1
 182 #define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_XB_IDX            2
 183 #define _DMA_V2_FSM_GROUP_FSM_REQ_XB_REMAINING_IDX      3
 184 #define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_BURST_IDX         4
 185
 186 #define _DMA_V2_FSM_GROUP_FSM_WR_STATE_IDX              0
 187 #define _DMA_V2_FSM_GROUP_FSM_WR_CNT_YB_IDX             1
 188 #define _DMA_V2_FSM_GROUP_FSM_WR_CNT_XB_IDX             2
 189 #define _DMA_V2_FSM_GROUP_FSM_WR_XB_REMAINING_IDX       3
 190 #define _DMA_V2_FSM_GROUP_FSM_WR_CNT_BURST_IDX          4
 191
 192 #define _DMA_V2_DEV_INTERF_REQ_SIDE_STATUS_IDX          0
 193 #define _DMA_V2_DEV_INTERF_SEND_SIDE_STATUS_IDX         1
 194 #define _DMA_V2_DEV_INTERF_FIFO_STATUS_IDX              2
 195 #define _DMA_V2_DEV_INTERF_REQ_ONLY_COMPLETE_BURST_IDX  3
 196 #define _DMA_V2_DEV_INTERF_MAX_BURST_IDX                4
 197 #define _DMA_V2_DEV_INTERF_CHK_ADDR_ALIGN               5
 198
 199 #endif /* _dma_v2_defs_h */