drivers/staging/crystalhd/crystalhd_hw.h

   1 /***************************************************************************
   2  * Copyright (c) 2005-2009, Broadcom Corporation.
   3  *
   4  *  Name: crystalhd_hw . h
   5  *
   6  *  Description:
   7  *              BCM70012 Linux driver hardware layer.
   8  *
   9  *  HISTORY:
  10  *
  11  **********************************************************************
  12  * This file is part of the crystalhd device driver.
  13  *
  14  * This driver is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation, version 2 of the License.
  17  *
  18  * This driver is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this driver.  If not, see <http://www.gnu.org/licenses/>.
  25  **********************************************************************/
  26
  27 #ifndef _CRYSTALHD_HW_H_
  28 #define _CRYSTALHD_HW_H_
  29
  30 #include "crystalhd.h"
  31
  32 /* HW constants..*/
  33 #define DMA_ENGINE_CNT          2
  34 #define MAX_PIB_Q_DEPTH         64
  35 #define MIN_PIB_Q_DEPTH         2
  36 #define WR_POINTER_OFF          4
  37
  38 #define ASPM_L1_ENABLE          (BC_BIT(27))
  39
  40 /*************************************************
  41   7412 Decoder  Registers.
  42 **************************************************/
  43 #define FW_CMD_BUFF_SZ          64
  44 #define TS_Host2CpuSnd          0x00000100
  45 #define Hst2CpuMbx1             0x00100F00
  46 #define Cpu2HstMbx1             0x00100F04
  47 #define MbxStat1                0x00100F08
  48 #define Stream2Host_Intr_Sts    0x00100F24
  49 #define C011_RET_SUCCESS        0x0 /* Return status of firmware command. */
  50
  51 /* TS input status register */
  52 #define TS_StreamAFIFOStatus    0x0010044C
  53 #define TS_StreamBFIFOStatus    0x0010084C
  54
  55 /*UART Selection definitions*/
  56 #define UartSelectA             0x00100300
  57 #define UartSelectB             0x00100304
  58
  59 #define BSVS_UART_DEC_NONE      0x00
  60 #define BSVS_UART_DEC_OUTER     0x01
  61 #define BSVS_UART_DEC_INNER     0x02
  62 #define BSVS_UART_STREAM        0x03
  63
  64 /* Code-In fifo */
  65 #define REG_DecCA_RegCinCTL     0xa00
  66 #define REG_DecCA_RegCinBase    0xa0c
  67 #define REG_DecCA_RegCinEnd     0xa10
  68 #define REG_DecCA_RegCinWrPtr   0xa04
  69 #define REG_DecCA_RegCinRdPtr   0xa08
  70
  71 #define REG_Dec_TsUser0Base     0x100864
  72 #define REG_Dec_TsUser0Rdptr    0x100868
  73 #define REG_Dec_TsUser0Wrptr    0x10086C
  74 #define REG_Dec_TsUser0End      0x100874
  75
  76 /* ASF Case ...*/
  77 #define REG_Dec_TsAudCDB2Base   0x10036c
  78 #define REG_Dec_TsAudCDB2Rdptr  0x100378
  79 #define REG_Dec_TsAudCDB2Wrptr  0x100374
  80 #define REG_Dec_TsAudCDB2End    0x100370
  81
  82 /* DRAM bringup Registers */
  83 #define SDRAM_PARAM             0x00040804
  84 #define SDRAM_PRECHARGE         0x000408B0
  85 #define SDRAM_EXT_MODE          0x000408A4
  86 #define SDRAM_MODE              0x000408A0
  87 #define SDRAM_REFRESH           0x00040890
  88 #define SDRAM_REF_PARAM         0x00040808
  89
  90 #define DecHt_PllACtl           0x34000C
  91 #define DecHt_PllBCtl           0x340010
  92 #define DecHt_PllCCtl           0x340014
  93 #define DecHt_PllDCtl           0x340034
  94 #define DecHt_PllECtl           0x340038
  95 #define AUD_DSP_MISC_SOFT_RESET 0x00240104
  96 #define AIO_MISC_PLL_RESET      0x0026000C
  97 #define PCIE_CLK_REQ_REG        0xDC
  98 #define PCI_CLK_REQ_ENABLE      (BC_BIT(8))
  99
 100 /*************************************************
 101   F/W Copy engine definitions..
 102 **************************************************/
 103 #define BC_FWIMG_ST_ADDR        0x00000000
 104 /* FIXME: jarod: there's a kernel function that'll do this for us... */
 105 #define rotr32_1(x, n)          (((x) >> n) | ((x) << (32 - n)))
 106 #define bswap_32_1(x) ((rotr32_1((x), 24) & 0x00ff00ff) | (rotr32_1((x), 8) & 0xff00ff00))
 107
 108 #define DecHt_HostSwReset       0x340000
 109 #define BC_DRAM_FW_CFG_ADDR     0x001c2000
 110
 111 union addr_64 {
 112         struct {
 113                 uint32_t        low_part;
 114                 uint32_t        high_part;
 115         };
 116
 117         uint64_t        full_addr;
 118
 119 };
 120
 121 union intr_mask_reg {
 122         struct {
 123                 uint32_t        mask_tx_done:1;
 124                 uint32_t        mask_tx_err:1;
 125                 uint32_t        mask_rx_done:1;
 126                 uint32_t        mask_rx_err:1;
 127                 uint32_t        mask_pcie_err:1;
 128                 uint32_t        mask_pcie_rbusmast_err:1;
 129                 uint32_t        mask_pcie_rgr_bridge:1;
 130                 uint32_t        reserved:25;
 131         };
 132
 133         uint32_t        whole_reg;
 134
 135 };
 136
 137 union link_misc_perst_deco_ctrl {
 138         struct {
 139                 uint32_t        bcm7412_rst:1;  /* 1 -> BCM7412 is held
 140                                                 in reset. Reset value 1.*/
 141                 uint32_t        reserved0:3;            /* Reserved.No Effect*/
 142                 uint32_t        stop_bcm_7412_clk:1;    /* 1 ->Stops branch of
 143                                                 27MHz clk used to clk BCM7412*/
 144                 uint32_t        reserved1:27;           /* Reserved. No Effect*/
 145         };
 146
 147         uint32_t        whole_reg;
 148
 149 };
 150
 151 union link_misc_perst_clk_ctrl {
 152         struct {
 153                 uint32_t        sel_alt_clk:1;    /* When set, selects a
 154                                  6.75MHz clock as the source of core_clk */
 155                 uint32_t        stop_core_clk:1;  /* When set, stops the branch
 156                  of core_clk that is not needed for low power operation */
 157                 uint32_t        pll_pwr_dn:1;     /* When set, powers down the
 158                          main PLL. The alternate clock bit should be set to
 159                          select an alternate clock before setting this bit.*/
 160                 uint32_t        reserved0:5;      /* Reserved */
 161                 uint32_t        pll_mult:8;       /* This setting controls
 162                                                  the multiplier for the PLL. */
 163                 uint32_t        pll_div:4;        /* This setting controls
 164                                                  the divider for the PLL. */
 165                 uint32_t        reserved1:12;     /* Reserved */
 166         };
 167
 168         uint32_t        whole_reg;
 169
 170 };
 171
 172 union link_misc_perst_decoder_ctrl {
 173         struct {
 174                 uint32_t        bcm_7412_rst:1; /* 1 -> BCM7412 is held
 175                                                  in reset. Reset value 1.*/
 176                 uint32_t        res0:3; /* Reserved.No Effect*/
 177                 uint32_t        stop_7412_clk:1; /* 1 ->Stops branch of 27MHz
 178                                                  clk used to clk BCM7412*/
 179                 uint32_t        res1:27; /* Reserved. No Effect */
 180         };
 181
 182         uint32_t        whole_reg;
 183
 184 };
 185
 186 union desc_low_addr_reg {
 187         struct {
 188                 uint32_t        list_valid:1;
 189                 uint32_t        reserved:4;
 190                 uint32_t        low_addr:27;
 191         };
 192
 193         uint32_t        whole_reg;
 194
 195 };
 196
 197 struct dma_descriptor { /* 8 32-bit values */
 198         /* 0th u32 */
 199         uint32_t sdram_buff_addr:28;    /* bits 0-27:  SDRAM Address */
 200         uint32_t res0:4;                /* bits 28-31: Reserved */
 201
 202         /* 1st u32 */
 203         uint32_t buff_addr_low;         /* 1 buffer address low */
 204         uint32_t buff_addr_high;        /* 2 buffer address high */
 205
 206         /* 3rd u32 */
 207         uint32_t res2:2;                /* 0-1 - Reserved */
 208         uint32_t xfer_size:23;          /* 2-24 = Xfer size in words */
 209         uint32_t res3:6;                /* 25-30 reserved */
 210         uint32_t intr_enable:1;         /* 31 - Interrupt After this desc */
 211
 212         /* 4th u32 */
 213         uint32_t endian_xlat_align:2;   /* 0-1 Endian Translation */
 214         uint32_t next_desc_cont:1;      /* 2 - Next desc is in contig memory */
 215         uint32_t res4:25;               /* 3 - 27 Reserved bits */
 216         uint32_t fill_bytes:2;          /* 28-29 Bits Fill Bytes */
 217         uint32_t dma_dir:1;             /* 30 bit DMA Direction */
 218         uint32_t last_rec_indicator:1;  /* 31 bit Last Record Indicator */
 219
 220         /* 5th u32 */
 221         uint32_t next_desc_addr_low;    /* 32-bits Next Desc Addr lower */
 222
 223         /* 6th u32 */
 224         uint32_t next_desc_addr_high;   /* 32-bits Next Desc Addr Higher */
 225
 226         /* 7th u32 */
 227         uint32_t res8;                  /* Last 32bits reserved */
 228
 229 };
 230
 231 /*
 232  * We will allocate the memory in 4K pages
 233  * the linked list will be a list of 32 byte descriptors.
 234  * The  virtual address will determine what should be freed.
 235  */
 236 struct dma_desc_mem {
 237         struct dma_descriptor   *pdma_desc_start; /* 32-bytes for dma
 238                                  descriptor. should be first element */
 239         dma_addr_t              phy_addr;       /* physical address
 240                                                  of each DMA desc */
 241         uint32_t                sz;
 242         struct _dma_desc_mem_   *Next; /* points to Next Descriptor in chain */
 243
 244 };
 245
 246 enum list_sts {
 247         sts_free = 0,
 248
 249         /* RX-Y Bits 0:7 */
 250         rx_waiting_y_intr       = 0x00000001,
 251         rx_y_error              = 0x00000004,
 252
 253         /* RX-UV Bits 8:16 */
 254         rx_waiting_uv_intr      = 0x0000100,
 255         rx_uv_error             = 0x0000400,
 256
 257         rx_sts_waiting          = (rx_waiting_y_intr|rx_waiting_uv_intr),
 258         rx_sts_error            = (rx_y_error|rx_uv_error),
 259
 260         rx_y_mask               = 0x000000FF,
 261         rx_uv_mask              = 0x0000FF00,
 262 };
 263
 264 struct tx_dma_pkt {
 265         struct dma_desc_mem     desc_mem;
 266         hw_comp_callback        call_back;
 267         struct crystalhd_dio_req        *dio_req;
 268         wait_queue_head_t       *cb_event;
 269         uint32_t                list_tag;
 270 };
 271
 272 struct crystalhd_rx_dma_pkt {
 273         struct dma_desc_mem             desc_mem;
 274         struct crystalhd_dio_req        *dio_req;
 275         uint32_t                        pkt_tag;
 276         uint32_t                        flags;
 277         struct BC_PIC_INFO_BLOCK        pib;
 278         dma_addr_t                      uv_phy_addr;
 279         struct crystalhd_rx_dma_pkt     *next;
 280 };
 281
 282 struct crystalhd_hw_stats {
 283         uint32_t        rx_errors;
 284         uint32_t        tx_errors;
 285         uint32_t        freeq_count;
 286         uint32_t        rdyq_count;
 287         uint32_t        num_interrupts;
 288         uint32_t        dev_interrupts;
 289         uint32_t        cin_busy;
 290         uint32_t        pause_cnt;
 291 };
 292
 293 struct crystalhd_hw {
 294         struct tx_dma_pkt       tx_pkt_pool[DMA_ENGINE_CNT];
 295         spinlock_t              lock;
 296
 297         uint32_t                tx_ioq_tag_seed;
 298         uint32_t                tx_list_post_index;
 299
 300         struct crystalhd_rx_dma_pkt *rx_pkt_pool_head;
 301         uint32_t                rx_pkt_tag_seed;
 302
 303         bool                    dev_started;
 304         void                    *adp;
 305
 306         wait_queue_head_t       *pfw_cmd_event;
 307         int                     fwcmd_evt_sts;
 308
 309         uint32_t                pib_del_Q_addr;
 310         uint32_t                pib_rel_Q_addr;
 311
 312         struct crystalhd_dioq   *tx_freeq;
 313         struct crystalhd_dioq   *tx_actq;
 314
 315         /* Rx DMA Engine Specific Locks */
 316         spinlock_t              rx_lock;
 317         uint32_t                rx_list_post_index;
 318         enum list_sts           rx_list_sts[DMA_ENGINE_CNT];
 319         struct crystalhd_dioq   *rx_rdyq;
 320         struct crystalhd_dioq   *rx_freeq;
 321         struct crystalhd_dioq   *rx_actq;
 322         uint32_t                stop_pending;
 323
 324         /* HW counters.. */
 325         struct crystalhd_hw_stats       stats;
 326
 327         /* Core clock in MHz */
 328         uint32_t                core_clock_mhz;
 329         uint32_t                prev_n;
 330         uint32_t                pwr_lock;
 331 };
 332
 333 /* Clock defines for power control */
 334 #define CLOCK_PRESET 175
 335
 336 /* DMA engine register BIT mask wrappers.. */
 337 #define DMA_START_BIT   MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK
 338
 339 #define GET_RX_INTR_MASK (INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_MASK | \
 340         INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_MASK |  \
 341         INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_MASK |            \
 342         INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_MASK |           \
 343         INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_MASK |           \
 344         INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_MASK |  \
 345         INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_MASK |            \
 346         INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_MASK)
 347
 348 #define GET_Y0_ERR_MSK (MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK | \
 349         MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK |             \
 350         MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK |       \
 351         MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK)
 352
 353 #define GET_UV0_ERR_MSK (MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK | \
 354         MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK |            \
 355         MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK |      \
 356         MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK)
 357
 358 #define GET_Y1_ERR_MSK (MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK | \
 359         MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK |             \
 360         MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK |       \
 361         MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK)
 362
 363 #define GET_UV1_ERR_MSK (MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK | \
 364         MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK |            \
 365         MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK |      \
 366         MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK)
 367
 368
 369 /**** API Exposed to the other layers ****/
 370 enum BC_STATUS crystalhd_download_fw(struct crystalhd_adp *adp,
 371                               void *buffer, uint32_t sz);
 372 enum BC_STATUS crystalhd_do_fw_cmd(struct crystalhd_hw *hw,
 373                                  struct BC_FW_CMD *fw_cmd);
 374 bool crystalhd_hw_interrupt(struct crystalhd_adp *adp,
 375                                  struct crystalhd_hw *hw);
 376 enum BC_STATUS crystalhd_hw_open(struct crystalhd_hw *,
 377                                  struct crystalhd_adp *);
 378 enum BC_STATUS crystalhd_hw_close(struct crystalhd_hw *);
 379 enum BC_STATUS crystalhd_hw_setup_dma_rings(struct crystalhd_hw *);
 380 enum BC_STATUS crystalhd_hw_free_dma_rings(struct crystalhd_hw *);
 381
 382
 383 enum BC_STATUS crystalhd_hw_post_tx(struct crystalhd_hw *hw,
 384                              struct crystalhd_dio_req *ioreq,
 385                              hw_comp_callback call_back,
 386                              wait_queue_head_t *cb_event,
 387                              uint32_t *list_id, uint8_t data_flags);
 388
 389 enum BC_STATUS crystalhd_hw_pause(struct crystalhd_hw *hw);
 390 enum BC_STATUS crystalhd_hw_unpause(struct crystalhd_hw *hw);
 391 enum BC_STATUS crystalhd_hw_suspend(struct crystalhd_hw *hw);
 392 enum BC_STATUS crystalhd_hw_cancel_tx(struct crystalhd_hw *hw,
 393                                  uint32_t list_id);
 394 enum BC_STATUS crystalhd_hw_add_cap_buffer(struct crystalhd_hw *hw,
 395                          struct crystalhd_dio_req *ioreq, bool en_post);
 396 enum BC_STATUS crystalhd_hw_get_cap_buffer(struct crystalhd_hw *hw,
 397                                     struct BC_PIC_INFO_BLOCK *pib,
 398                                     struct crystalhd_dio_req **ioreq);
 399 enum BC_STATUS crystalhd_hw_stop_capture(struct crystalhd_hw *hw);
 400 enum BC_STATUS crystalhd_hw_start_capture(struct crystalhd_hw *hw);
 401 void crystalhd_hw_stats(struct crystalhd_hw *hw,
 402                          struct crystalhd_hw_stats *stats);
 403
 404 /* API to program the core clock on the decoder */
 405 enum BC_STATUS crystalhd_hw_set_core_clock(struct crystalhd_hw *);
 406
 407 #endif