drivers/staging/comedi/drivers/ni_pcidio.c

   1 /*
   2  * Comedi driver for National Instruments PCI-DIO-32HS
   3  *
   4  * COMEDI - Linux Control and Measurement Device Interface
   5  * Copyright (C) 1999,2002 David A. Schleef <ds@schleef.org>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 /*
  19  * Driver: ni_pcidio
  20  * Description: National Instruments PCI-DIO32HS, PCI-6533
  21  * Author: ds
  22  * Status: works
  23  * Devices: [National Instruments] PCI-DIO-32HS (ni_pcidio)
  24  *   [National Instruments] PXI-6533, PCI-6533 (pxi-6533)
  25  *   [National Instruments] PCI-6534 (pci-6534)
  26  * Updated: Mon, 09 Jan 2012 14:27:23 +0000
  27  *
  28  * The DIO32HS board appears as one subdevice, with 32 channels. Each
  29  * channel is individually I/O configurable. The channel order is 0=A0,
  30  * 1=A1, 2=A2, ... 8=B0, 16=C0, 24=D0. The driver only supports simple
  31  * digital I/O; no handshaking is supported.
  32  *
  33  * DMA mostly works for the PCI-DIO32HS, but only in timed input mode.
  34  *
  35  * The PCI-DIO-32HS/PCI-6533 has a configurable external trigger. Setting
  36  * scan_begin_arg to 0 or CR_EDGE triggers on the leading edge. Setting
  37  * scan_begin_arg to CR_INVERT or (CR_EDGE | CR_INVERT) triggers on the
  38  * trailing edge.
  39  *
  40  * This driver could be easily modified to support AT-MIO32HS and AT-MIO96.
  41  *
  42  * The PCI-6534 requires a firmware upload after power-up to work, the
  43  * firmware data and instructions for loading it with comedi_config
  44  * it are contained in the comedi_nonfree_firmware tarball available from
  45  * http://www.comedi.org
  46  */
  47
  48 #define USE_DMA
  49
  50 #include <linux/module.h>
  51 #include <linux/delay.h>
  52 #include <linux/interrupt.h>
  53 #include <linux/sched.h>
  54
  55 #include "../comedi_pci.h"
  56
  57 #include "mite.h"
  58
  59 /* defines for the PCI-DIO-32HS */
  60
  61 #define Window_Address                  4       /* W */
  62 #define Interrupt_And_Window_Status     4       /* R */
  63 #define IntStatus1                              BIT(0)
  64 #define IntStatus2                              BIT(1)
  65 #define WindowAddressStatus_mask                0x7c
  66
  67 #define Master_DMA_And_Interrupt_Control 5      /* W */
  68 #define InterruptLine(x)                        ((x)&3)
  69 #define OpenInt                         BIT(2)
  70 #define Group_Status                    5       /* R */
  71 #define DataLeft                                BIT(0)
  72 #define Req                                     BIT(2)
  73 #define StopTrig                                BIT(3)
  74
  75 #define Group_1_Flags                   6       /* R */
  76 #define Group_2_Flags                   7       /* R */
  77 #define TransferReady                           BIT(0)
  78 #define CountExpired                            BIT(1)
  79 #define Waited                                  BIT(5)
  80 #define PrimaryTC                               BIT(6)
  81 #define SecondaryTC                             BIT(7)
  82   /* #define SerialRose */
  83   /* #define ReqRose */
  84   /* #define Paused */
  85
  86 #define Group_1_First_Clear             6       /* W */
  87 #define Group_2_First_Clear             7       /* W */
  88 #define ClearWaited                             BIT(3)
  89 #define ClearPrimaryTC                          BIT(4)
  90 #define ClearSecondaryTC                        BIT(5)
  91 #define DMAReset                                BIT(6)
  92 #define FIFOReset                               BIT(7)
  93 #define ClearAll                                0xf8
  94
  95 #define Group_1_FIFO                    8       /* W */
  96 #define Group_2_FIFO                    12      /* W */
  97
  98 #define Transfer_Count                  20
  99 #define Chip_ID_D                       24
 100 #define Chip_ID_I                       25
 101 #define Chip_ID_O                       26
 102 #define Chip_Version                    27
 103 #define Port_IO(x)                      (28+(x))
 104 #define Port_Pin_Directions(x)          (32+(x))
 105 #define Port_Pin_Mask(x)                (36+(x))
 106 #define Port_Pin_Polarities(x)          (40+(x))
 107
 108 #define Master_Clock_Routing            45
 109 #define RTSIClocking(x)                 (((x)&3)<<4)
 110
 111 #define Group_1_Second_Clear            46      /* W */
 112 #define Group_2_Second_Clear            47      /* W */
 113 #define ClearExpired                            BIT(0)
 114
 115 #define Port_Pattern(x)                 (48+(x))
 116
 117 #define Data_Path                       64
 118 #define FIFOEnableA             BIT(0)
 119 #define FIFOEnableB             BIT(1)
 120 #define FIFOEnableC             BIT(2)
 121 #define FIFOEnableD             BIT(3)
 122 #define Funneling(x)            (((x)&3)<<4)
 123 #define GroupDirection          BIT(7)
 124
 125 #define Protocol_Register_1             65
 126 #define OpMode                          Protocol_Register_1
 127 #define RunMode(x)              ((x)&7)
 128 #define Numbered                BIT(3)
 129
 130 #define Protocol_Register_2             66
 131 #define ClockReg                        Protocol_Register_2
 132 #define ClockLine(x)            (((x)&3)<<5)
 133 #define InvertStopTrig          BIT(7)
 134 #define DataLatching(x)       (((x)&3)<<5)
 135
 136 #define Protocol_Register_3             67
 137 #define Sequence                        Protocol_Register_3
 138
 139 #define Protocol_Register_14            68      /* 16 bit */
 140 #define ClockSpeed                      Protocol_Register_14
 141
 142 #define Protocol_Register_4             70
 143 #define ReqReg                          Protocol_Register_4
 144 #define ReqConditioning(x)      (((x)&7)<<3)
 145
 146 #define Protocol_Register_5             71
 147 #define BlockMode                       Protocol_Register_5
 148
 149 #define FIFO_Control                    72
 150 #define ReadyLevel(x)           ((x)&7)
 151
 152 #define Protocol_Register_6             73
 153 #define LinePolarities                  Protocol_Register_6
 154 #define InvertAck               BIT(0)
 155 #define InvertReq               BIT(1)
 156 #define InvertClock             BIT(2)
 157 #define InvertSerial            BIT(3)
 158 #define OpenAck         BIT(4)
 159 #define OpenClock               BIT(5)
 160
 161 #define Protocol_Register_7             74
 162 #define AckSer                          Protocol_Register_7
 163 #define AckLine(x)              (((x)&3)<<2)
 164 #define ExchangePins            BIT(7)
 165
 166 #define Interrupt_Control               75
 167   /* bits same as flags */
 168
 169 #define DMA_Line_Control_Group1         76
 170 #define DMA_Line_Control_Group2         108
 171 /* channel zero is none */
 172 static inline unsigned int primary_DMAChannel_bits(unsigned int channel)
 173 {
 174         return channel & 0x3;
 175 }
 176
 177 static inline unsigned int secondary_DMAChannel_bits(unsigned int channel)
 178 {
 179         return (channel << 2) & 0xc;
 180 }
 181
 182 #define Transfer_Size_Control           77
 183 #define TransferWidth(x)        ((x)&3)
 184 #define TransferLength(x)       (((x)&3)<<3)
 185 #define RequireRLevel           BIT(5)
 186
 187 #define Protocol_Register_15            79
 188 #define DAQOptions                      Protocol_Register_15
 189 #define StartSource(x)                  ((x)&0x3)
 190 #define InvertStart                             BIT(2)
 191 #define StopSource(x)                           (((x)&0x3)<<3)
 192 #define ReqStart                                BIT(6)
 193 #define PreStart                                BIT(7)
 194
 195 #define Pattern_Detection               81
 196 #define DetectionMethod                 BIT(0)
 197 #define InvertMatch                             BIT(1)
 198 #define IE_Pattern_Detection                    BIT(2)
 199
 200 #define Protocol_Register_9             82
 201 #define ReqDelay                        Protocol_Register_9
 202
 203 #define Protocol_Register_10            83
 204 #define ReqNotDelay                     Protocol_Register_10
 205
 206 #define Protocol_Register_11            84
 207 #define AckDelay                        Protocol_Register_11
 208
 209 #define Protocol_Register_12            85
 210 #define AckNotDelay                     Protocol_Register_12
 211
 212 #define Protocol_Register_13            86
 213 #define Data1Delay                      Protocol_Register_13
 214
 215 #define Protocol_Register_8             88      /* 32 bit */
 216 #define StartDelay                      Protocol_Register_8
 217
 218 /* Firmware files for PCI-6524 */
 219 #define FW_PCI_6534_MAIN                "/*(DEBLOBBED)*/"
 220 #define FW_PCI_6534_SCARAB_DI           "/*(DEBLOBBED)*/"
 221 #define FW_PCI_6534_SCARAB_DO           "/*(DEBLOBBED)*/"
 222 /*(DEBLOBBED)*/
 223
 224 enum pci_6534_firmware_registers {      /* 16 bit */
 225         Firmware_Control_Register = 0x100,
 226         Firmware_Status_Register = 0x104,
 227         Firmware_Data_Register = 0x108,
 228         Firmware_Mask_Register = 0x10c,
 229         Firmware_Debug_Register = 0x110,
 230 };
 231 /* main fpga registers (32 bit)*/
 232 enum pci_6534_fpga_registers {
 233         FPGA_Control1_Register = 0x200,
 234         FPGA_Control2_Register = 0x204,
 235         FPGA_Irq_Mask_Register = 0x208,
 236         FPGA_Status_Register = 0x20c,
 237         FPGA_Signature_Register = 0x210,
 238         FPGA_SCALS_Counter_Register = 0x280,    /*write-clear */
 239         FPGA_SCAMS_Counter_Register = 0x284,    /*write-clear */
 240         FPGA_SCBLS_Counter_Register = 0x288,    /*write-clear */
 241         FPGA_SCBMS_Counter_Register = 0x28c,    /*write-clear */
 242         FPGA_Temp_Control_Register = 0x2a0,
 243         FPGA_DAR_Register = 0x2a8,
 244         FPGA_ELC_Read_Register = 0x2b8,
 245         FPGA_ELC_Write_Register = 0x2bc,
 246 };
 247 enum FPGA_Control_Bits {
 248         FPGA_Enable_Bit = 0x8000,
 249 };
 250
 251 #define TIMER_BASE 50           /* nanoseconds */
 252
 253 #ifdef USE_DMA
 254 #define IntEn (CountExpired|Waited|PrimaryTC|SecondaryTC)
 255 #else
 256 #define IntEn (TransferReady|CountExpired|Waited|PrimaryTC|SecondaryTC)
 257 #endif
 258
 259 enum nidio_boardid {
 260         BOARD_PCIDIO_32HS,
 261         BOARD_PXI6533,
 262         BOARD_PCI6534,
 263 };
 264
 265 struct nidio_board {
 266         const char *name;
 267         unsigned int uses_firmware:1;
 268 };
 269
 270 static const struct nidio_board nidio_boards[] = {
 271         [BOARD_PCIDIO_32HS] = {
 272                 .name           = "pci-dio-32hs",
 273         },
 274         [BOARD_PXI6533] = {
 275                 .name           = "pxi-6533",
 276         },
 277         [BOARD_PCI6534] = {
 278                 .name           = "pci-6534",
 279                 .uses_firmware  = 1,
 280         },
 281 };
 282
 283 struct nidio96_private {
 284         struct mite *mite;
 285         int boardtype;
 286         int dio;
 287         unsigned short OpModeBits;
 288         struct mite_channel *di_mite_chan;
 289         struct mite_ring *di_mite_ring;
 290         spinlock_t mite_channel_lock;
 291 };
 292
 293 static int ni_pcidio_request_di_mite_channel(struct comedi_device *dev)
 294 {
 295         struct nidio96_private *devpriv = dev->private;
 296         unsigned long flags;
 297
 298         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 299         BUG_ON(devpriv->di_mite_chan);
 300         devpriv->di_mite_chan =
 301             mite_request_channel_in_range(devpriv->mite,
 302                                           devpriv->di_mite_ring, 1, 2);
 303         if (!devpriv->di_mite_chan) {
 304                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 305                 dev_err(dev->class_dev, "failed to reserve mite dma channel\n");
 306                 return -EBUSY;
 307         }
 308         devpriv->di_mite_chan->dir = COMEDI_INPUT;
 309         writeb(primary_DMAChannel_bits(devpriv->di_mite_chan->channel) |
 310                secondary_DMAChannel_bits(devpriv->di_mite_chan->channel),
 311                dev->mmio + DMA_Line_Control_Group1);
 312         mmiowb();
 313         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 314         return 0;
 315 }
 316
 317 static void ni_pcidio_release_di_mite_channel(struct comedi_device *dev)
 318 {
 319         struct nidio96_private *devpriv = dev->private;
 320         unsigned long flags;
 321
 322         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 323         if (devpriv->di_mite_chan) {
 324                 mite_release_channel(devpriv->di_mite_chan);
 325                 devpriv->di_mite_chan = NULL;
 326                 writeb(primary_DMAChannel_bits(0) |
 327                        secondary_DMAChannel_bits(0),
 328                        dev->mmio + DMA_Line_Control_Group1);
 329                 mmiowb();
 330         }
 331         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 332 }
 333
 334 static int setup_mite_dma(struct comedi_device *dev, struct comedi_subdevice *s)
 335 {
 336         struct nidio96_private *devpriv = dev->private;
 337         int retval;
 338         unsigned long flags;
 339
 340         retval = ni_pcidio_request_di_mite_channel(dev);
 341         if (retval)
 342                 return retval;
 343
 344         /* write alloc the entire buffer */
 345         comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
 346
 347         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 348         if (devpriv->di_mite_chan) {
 349                 mite_prep_dma(devpriv->di_mite_chan, 32, 32);
 350                 mite_dma_arm(devpriv->di_mite_chan);
 351         } else {
 352                 retval = -EIO;
 353         }
 354         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 355
 356         return retval;
 357 }
 358
 359 static int ni_pcidio_poll(struct comedi_device *dev, struct comedi_subdevice *s)
 360 {
 361         struct nidio96_private *devpriv = dev->private;
 362         unsigned long irq_flags;
 363         int count;
 364
 365         spin_lock_irqsave(&dev->spinlock, irq_flags);
 366         spin_lock(&devpriv->mite_channel_lock);
 367         if (devpriv->di_mite_chan)
 368                 mite_sync_dma(devpriv->di_mite_chan, s);
 369         spin_unlock(&devpriv->mite_channel_lock);
 370         count = comedi_buf_n_bytes_ready(s);
 371         spin_unlock_irqrestore(&dev->spinlock, irq_flags);
 372         return count;
 373 }
 374
 375 static irqreturn_t nidio_interrupt(int irq, void *d)
 376 {
 377         struct comedi_device *dev = d;
 378         struct nidio96_private *devpriv = dev->private;
 379         struct comedi_subdevice *s = dev->read_subdev;
 380         struct comedi_async *async = s->async;
 381         unsigned int auxdata;
 382         int flags;
 383         int status;
 384         int work = 0;
 385
 386         /* interrupcions parasites */
 387         if (!dev->attached) {
 388                 /* assume it's from another card */
 389                 return IRQ_NONE;
 390         }
 391
 392         /* Lock to avoid race with comedi_poll */
 393         spin_lock(&dev->spinlock);
 394
 395         status = readb(dev->mmio + Interrupt_And_Window_Status);
 396         flags = readb(dev->mmio + Group_1_Flags);
 397
 398         spin_lock(&devpriv->mite_channel_lock);
 399         if (devpriv->di_mite_chan) {
 400                 mite_ack_linkc(devpriv->di_mite_chan, s, false);
 401                 /* XXX need to byteswap sync'ed dma */
 402         }
 403         spin_unlock(&devpriv->mite_channel_lock);
 404
 405         while (status & DataLeft) {
 406                 work++;
 407                 if (work > 20) {
 408                         dev_dbg(dev->class_dev, "too much work in interrupt\n");
 409                         writeb(0x00,
 410                                dev->mmio + Master_DMA_And_Interrupt_Control);
 411                         break;
 412                 }
 413
 414                 flags &= IntEn;
 415
 416                 if (flags & TransferReady) {
 417                         while (flags & TransferReady) {
 418                                 work++;
 419                                 if (work > 100) {
 420                                         dev_dbg(dev->class_dev,
 421                                                 "too much work in interrupt\n");
 422                                         writeb(0x00, dev->mmio +
 423                                                Master_DMA_And_Interrupt_Control
 424                                               );
 425                                         goto out;
 426                                 }
 427                                 auxdata = readl(dev->mmio + Group_1_FIFO);
 428                                 comedi_buf_write_samples(s, &auxdata, 1);
 429                                 flags = readb(dev->mmio + Group_1_Flags);
 430                         }
 431                 }
 432
 433                 if (flags & CountExpired) {
 434                         writeb(ClearExpired, dev->mmio + Group_1_Second_Clear);
 435                         async->events |= COMEDI_CB_EOA;
 436
 437                         writeb(0x00, dev->mmio + OpMode);
 438                         break;
 439                 } else if (flags & Waited) {
 440                         writeb(ClearWaited, dev->mmio + Group_1_First_Clear);
 441                         async->events |= COMEDI_CB_ERROR;
 442                         break;
 443                 } else if (flags & PrimaryTC) {
 444                         writeb(ClearPrimaryTC,
 445                                dev->mmio + Group_1_First_Clear);
 446                         async->events |= COMEDI_CB_EOA;
 447                 } else if (flags & SecondaryTC) {
 448                         writeb(ClearSecondaryTC,
 449                                dev->mmio + Group_1_First_Clear);
 450                         async->events |= COMEDI_CB_EOA;
 451                 }
 452
 453                 flags = readb(dev->mmio + Group_1_Flags);
 454                 status = readb(dev->mmio + Interrupt_And_Window_Status);
 455         }
 456
 457 out:
 458         comedi_handle_events(dev, s);
 459 #if 0
 460         if (!tag)
 461                 writeb(0x03, dev->mmio + Master_DMA_And_Interrupt_Control);
 462 #endif
 463
 464         spin_unlock(&dev->spinlock);
 465         return IRQ_HANDLED;
 466 }
 467
 468 static int ni_pcidio_insn_config(struct comedi_device *dev,
 469                                  struct comedi_subdevice *s,
 470                                  struct comedi_insn *insn,
 471                                  unsigned int *data)
 472 {
 473         int ret;
 474
 475         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
 476         if (ret)
 477                 return ret;
 478
 479         writel(s->io_bits, dev->mmio + Port_Pin_Directions(0));
 480
 481         return insn->n;
 482 }
 483
 484 static int ni_pcidio_insn_bits(struct comedi_device *dev,
 485                                struct comedi_subdevice *s,
 486                                struct comedi_insn *insn,
 487                                unsigned int *data)
 488 {
 489         if (comedi_dio_update_state(s, data))
 490                 writel(s->state, dev->mmio + Port_IO(0));
 491
 492         data[1] = readl(dev->mmio + Port_IO(0));
 493
 494         return insn->n;
 495 }
 496
 497 static int ni_pcidio_ns_to_timer(int *nanosec, unsigned int flags)
 498 {
 499         int divider, base;
 500
 501         base = TIMER_BASE;
 502
 503         switch (flags & CMDF_ROUND_MASK) {
 504         case CMDF_ROUND_NEAREST:
 505         default:
 506                 divider = DIV_ROUND_CLOSEST(*nanosec, base);
 507                 break;
 508         case CMDF_ROUND_DOWN:
 509                 divider = (*nanosec) / base;
 510                 break;
 511         case CMDF_ROUND_UP:
 512                 divider = DIV_ROUND_UP(*nanosec, base);
 513                 break;
 514         }
 515
 516         *nanosec = base * divider;
 517         return divider;
 518 }
 519
 520 static int ni_pcidio_cmdtest(struct comedi_device *dev,
 521                              struct comedi_subdevice *s, struct comedi_cmd *cmd)
 522 {
 523         int err = 0;
 524         unsigned int arg;
 525
 526         /* Step 1 : check if triggers are trivially valid */
 527
 528         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_INT);
 529         err |= comedi_check_trigger_src(&cmd->scan_begin_src,
 530                                         TRIG_TIMER | TRIG_EXT);
 531         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
 532         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
 533         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
 534
 535         if (err)
 536                 return 1;
 537
 538         /* Step 2a : make sure trigger sources are unique */
 539
 540         err |= comedi_check_trigger_is_unique(cmd->start_src);
 541         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
 542         err |= comedi_check_trigger_is_unique(cmd->stop_src);
 543
 544         /* Step 2b : and mutually compatible */
 545
 546         if (err)
 547                 return 2;
 548
 549         /* Step 3: check if arguments are trivially valid */
 550
 551         err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
 552
 553 #define MAX_SPEED       (TIMER_BASE)    /* in nanoseconds */
 554
 555         if (cmd->scan_begin_src == TRIG_TIMER) {
 556                 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
 557                                                     MAX_SPEED);
 558                 /* no minimum speed */
 559         } else {
 560                 /* TRIG_EXT */
 561                 /* should be level/edge, hi/lo specification here */
 562                 if ((cmd->scan_begin_arg & ~(CR_EDGE | CR_INVERT)) != 0) {
 563                         cmd->scan_begin_arg &= (CR_EDGE | CR_INVERT);
 564                         err |= -EINVAL;
 565                 }
 566         }
 567
 568         err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
 569         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
 570                                            cmd->chanlist_len);
 571
 572         if (cmd->stop_src == TRIG_COUNT)
 573                 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
 574         else    /* TRIG_NONE */
 575                 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
 576
 577         if (err)
 578                 return 3;
 579
 580         /* step 4: fix up any arguments */
 581
 582         if (cmd->scan_begin_src == TRIG_TIMER) {
 583                 arg = cmd->scan_begin_arg;
 584                 ni_pcidio_ns_to_timer(&arg, cmd->flags);
 585                 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, arg);
 586         }
 587
 588         if (err)
 589                 return 4;
 590
 591         return 0;
 592 }
 593
 594 static int ni_pcidio_inttrig(struct comedi_device *dev,
 595                              struct comedi_subdevice *s,
 596                              unsigned int trig_num)
 597 {
 598         struct nidio96_private *devpriv = dev->private;
 599         struct comedi_cmd *cmd = &s->async->cmd;
 600
 601         if (trig_num != cmd->start_arg)
 602                 return -EINVAL;
 603
 604         writeb(devpriv->OpModeBits, dev->mmio + OpMode);
 605         s->async->inttrig = NULL;
 606
 607         return 1;
 608 }
 609
 610 static int ni_pcidio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
 611 {
 612         struct nidio96_private *devpriv = dev->private;
 613         struct comedi_cmd *cmd = &s->async->cmd;
 614
 615         /* XXX configure ports for input */
 616         writel(0x0000, dev->mmio + Port_Pin_Directions(0));
 617
 618         if (1) {
 619                 /* enable fifos A B C D */
 620                 writeb(0x0f, dev->mmio + Data_Path);
 621
 622                 /* set transfer width a 32 bits */
 623                 writeb(TransferWidth(0) | TransferLength(0),
 624                        dev->mmio + Transfer_Size_Control);
 625         } else {
 626                 writeb(0x03, dev->mmio + Data_Path);
 627                 writeb(TransferWidth(3) | TransferLength(0),
 628                        dev->mmio + Transfer_Size_Control);
 629         }
 630
 631         /* protocol configuration */
 632         if (cmd->scan_begin_src == TRIG_TIMER) {
 633                 /* page 4-5, "input with internal REQs" */
 634                 writeb(0, dev->mmio + OpMode);
 635                 writeb(0x00, dev->mmio + ClockReg);
 636                 writeb(1, dev->mmio + Sequence);
 637                 writeb(0x04, dev->mmio + ReqReg);
 638                 writeb(4, dev->mmio + BlockMode);
 639                 writeb(3, dev->mmio + LinePolarities);
 640                 writeb(0xc0, dev->mmio + AckSer);
 641                 writel(ni_pcidio_ns_to_timer(&cmd->scan_begin_arg,
 642                                              CMDF_ROUND_NEAREST),
 643                        dev->mmio + StartDelay);
 644                 writeb(1, dev->mmio + ReqDelay);
 645                 writeb(1, dev->mmio + ReqNotDelay);
 646                 writeb(1, dev->mmio + AckDelay);
 647                 writeb(0x0b, dev->mmio + AckNotDelay);
 648                 writeb(0x01, dev->mmio + Data1Delay);
 649                 /*
 650                  * manual, page 4-5:
 651                  * ClockSpeed comment is incorrectly listed on DAQOptions
 652                  */
 653                 writew(0, dev->mmio + ClockSpeed);
 654                 writeb(0, dev->mmio + DAQOptions);
 655         } else {
 656                 /* TRIG_EXT */
 657                 /* page 4-5, "input with external REQs" */
 658                 writeb(0, dev->mmio + OpMode);
 659                 writeb(0x00, dev->mmio + ClockReg);
 660                 writeb(0, dev->mmio + Sequence);
 661                 writeb(0x00, dev->mmio + ReqReg);
 662                 writeb(4, dev->mmio + BlockMode);
 663                 if (!(cmd->scan_begin_arg & CR_INVERT)) /* Leading Edge */
 664                         writeb(0, dev->mmio + LinePolarities);
 665                 else                                    /* Trailing Edge */
 666                         writeb(2, dev->mmio + LinePolarities);
 667                 writeb(0x00, dev->mmio + AckSer);
 668                 writel(1, dev->mmio + StartDelay);
 669                 writeb(1, dev->mmio + ReqDelay);
 670                 writeb(1, dev->mmio + ReqNotDelay);
 671                 writeb(1, dev->mmio + AckDelay);
 672                 writeb(0x0C, dev->mmio + AckNotDelay);
 673                 writeb(0x10, dev->mmio + Data1Delay);
 674                 writew(0, dev->mmio + ClockSpeed);
 675                 writeb(0x60, dev->mmio + DAQOptions);
 676         }
 677
 678         if (cmd->stop_src == TRIG_COUNT) {
 679                 writel(cmd->stop_arg,
 680                        dev->mmio + Transfer_Count);
 681         } else {
 682                 /* XXX */
 683         }
 684
 685 #ifdef USE_DMA
 686         writeb(ClearPrimaryTC | ClearSecondaryTC,
 687                dev->mmio + Group_1_First_Clear);
 688
 689         {
 690                 int retval = setup_mite_dma(dev, s);
 691
 692                 if (retval)
 693                         return retval;
 694         }
 695 #else
 696         writeb(0x00, dev->mmio + DMA_Line_Control_Group1);
 697 #endif
 698         writeb(0x00, dev->mmio + DMA_Line_Control_Group2);
 699
 700         /* clear and enable interrupts */
 701         writeb(0xff, dev->mmio + Group_1_First_Clear);
 702         /* writeb(ClearExpired, dev->mmio+Group_1_Second_Clear); */
 703
 704         writeb(IntEn, dev->mmio + Interrupt_Control);
 705         writeb(0x03, dev->mmio + Master_DMA_And_Interrupt_Control);
 706
 707         if (cmd->stop_src == TRIG_NONE) {
 708                 devpriv->OpModeBits = DataLatching(0) | RunMode(7);
 709         } else {                /* TRIG_TIMER */
 710                 devpriv->OpModeBits = Numbered | RunMode(7);
 711         }
 712         if (cmd->start_src == TRIG_NOW) {
 713                 /* start */
 714                 writeb(devpriv->OpModeBits, dev->mmio + OpMode);
 715                 s->async->inttrig = NULL;
 716         } else {
 717                 /* TRIG_INT */
 718                 s->async->inttrig = ni_pcidio_inttrig;
 719         }
 720
 721         return 0;
 722 }
 723
 724 static int ni_pcidio_cancel(struct comedi_device *dev,
 725                             struct comedi_subdevice *s)
 726 {
 727         writeb(0x00, dev->mmio + Master_DMA_And_Interrupt_Control);
 728         ni_pcidio_release_di_mite_channel(dev);
 729
 730         return 0;
 731 }
 732
 733 static int ni_pcidio_change(struct comedi_device *dev,
 734                             struct comedi_subdevice *s)
 735 {
 736         struct nidio96_private *devpriv = dev->private;
 737         int ret;
 738
 739         ret = mite_buf_change(devpriv->di_mite_ring, s);
 740         if (ret < 0)
 741                 return ret;
 742
 743         memset(s->async->prealloc_buf, 0xaa, s->async->prealloc_bufsz);
 744
 745         return 0;
 746 }
 747
 748 static int pci_6534_load_fpga(struct comedi_device *dev,
 749                               const u8 *data, size_t data_len,
 750                               unsigned long context)
 751 {
 752         static const int timeout = 1000;
 753         int fpga_index = context;
 754         int i;
 755         size_t j;
 756
 757         writew(0x80 | fpga_index, dev->mmio + Firmware_Control_Register);
 758         writew(0xc0 | fpga_index, dev->mmio + Firmware_Control_Register);
 759         for (i = 0;
 760              (readw(dev->mmio + Firmware_Status_Register) & 0x2) == 0 &&
 761              i < timeout; ++i) {
 762                 udelay(1);
 763         }
 764         if (i == timeout) {
 765                 dev_warn(dev->class_dev,
 766                          "ni_pcidio: failed to load fpga %i, waiting for status 0x2\n",
 767                          fpga_index);
 768                 return -EIO;
 769         }
 770         writew(0x80 | fpga_index, dev->mmio + Firmware_Control_Register);
 771         for (i = 0;
 772              readw(dev->mmio + Firmware_Status_Register) != 0x3 &&
 773              i < timeout; ++i) {
 774                 udelay(1);
 775         }
 776         if (i == timeout) {
 777                 dev_warn(dev->class_dev,
 778                          "ni_pcidio: failed to load fpga %i, waiting for status 0x3\n",
 779                          fpga_index);
 780                 return -EIO;
 781         }
 782         for (j = 0; j + 1 < data_len;) {
 783                 unsigned int value = data[j++];
 784
 785                 value |= data[j++] << 8;
 786                 writew(value, dev->mmio + Firmware_Data_Register);
 787                 for (i = 0;
 788                      (readw(dev->mmio + Firmware_Status_Register) & 0x2) == 0
 789                      && i < timeout; ++i) {
 790                         udelay(1);
 791                 }
 792                 if (i == timeout) {
 793                         dev_warn(dev->class_dev,
 794                                  "ni_pcidio: failed to load word into fpga %i\n",
 795                                  fpga_index);
 796                         return -EIO;
 797                 }
 798                 if (need_resched())
 799                         schedule();
 800         }
 801         writew(0x0, dev->mmio + Firmware_Control_Register);
 802         return 0;
 803 }
 804
 805 static int pci_6534_reset_fpga(struct comedi_device *dev, int fpga_index)
 806 {
 807         return pci_6534_load_fpga(dev, NULL, 0, fpga_index);
 808 }
 809
 810 static int pci_6534_reset_fpgas(struct comedi_device *dev)
 811 {
 812         int ret;
 813         int i;
 814
 815         writew(0x0, dev->mmio + Firmware_Control_Register);
 816         for (i = 0; i < 3; ++i) {
 817                 ret = pci_6534_reset_fpga(dev, i);
 818                 if (ret < 0)
 819                         break;
 820         }
 821         writew(0x0, dev->mmio + Firmware_Mask_Register);
 822         return ret;
 823 }
 824
 825 static void pci_6534_init_main_fpga(struct comedi_device *dev)
 826 {
 827         writel(0, dev->mmio + FPGA_Control1_Register);
 828         writel(0, dev->mmio + FPGA_Control2_Register);
 829         writel(0, dev->mmio + FPGA_SCALS_Counter_Register);
 830         writel(0, dev->mmio + FPGA_SCAMS_Counter_Register);
 831         writel(0, dev->mmio + FPGA_SCBLS_Counter_Register);
 832         writel(0, dev->mmio + FPGA_SCBMS_Counter_Register);
 833 }
 834
 835 static int pci_6534_upload_firmware(struct comedi_device *dev)
 836 {
 837         struct nidio96_private *devpriv = dev->private;
 838         static const char *const fw_file[3] = {
 839                 FW_PCI_6534_SCARAB_DI,  /* loaded into scarab A for DI */
 840                 FW_PCI_6534_SCARAB_DO,  /* loaded into scarab B for DO */
 841                 FW_PCI_6534_MAIN,       /* loaded into main FPGA */
 842         };
 843         int ret;
 844         int n;
 845
 846         ret = pci_6534_reset_fpgas(dev);
 847         if (ret < 0)
 848                 return ret;
 849         /* load main FPGA first, then the two scarabs */
 850         for (n = 2; n >= 0; n--) {
 851                 ret = comedi_load_firmware(dev, &devpriv->mite->pcidev->dev,
 852                                            fw_file[n],
 853                                            pci_6534_load_fpga, n);
 854                 if (ret == 0 && n == 2)
 855                         pci_6534_init_main_fpga(dev);
 856                 if (ret < 0)
 857                         break;
 858         }
 859         return ret;
 860 }
 861
 862 static void nidio_reset_board(struct comedi_device *dev)
 863 {
 864         writel(0, dev->mmio + Port_IO(0));
 865         writel(0, dev->mmio + Port_Pin_Directions(0));
 866         writel(0, dev->mmio + Port_Pin_Mask(0));
 867
 868         /* disable interrupts on board */
 869         writeb(0, dev->mmio + Master_DMA_And_Interrupt_Control);
 870 }
 871
 872 static int nidio_auto_attach(struct comedi_device *dev,
 873                              unsigned long context)
 874 {
 875         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
 876         const struct nidio_board *board = NULL;
 877         struct nidio96_private *devpriv;
 878         struct comedi_subdevice *s;
 879         int ret;
 880         unsigned int irq;
 881
 882         if (context < ARRAY_SIZE(nidio_boards))
 883                 board = &nidio_boards[context];
 884         if (!board)
 885                 return -ENODEV;
 886         dev->board_ptr = board;
 887         dev->board_name = board->name;
 888
 889         ret = comedi_pci_enable(dev);
 890         if (ret)
 891                 return ret;
 892
 893         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
 894         if (!devpriv)
 895                 return -ENOMEM;
 896
 897         spin_lock_init(&devpriv->mite_channel_lock);
 898
 899         devpriv->mite = mite_attach(dev, false);        /* use win0 */
 900         if (!devpriv->mite)
 901                 return -ENOMEM;
 902
 903         devpriv->di_mite_ring = mite_alloc_ring(devpriv->mite);
 904         if (!devpriv->di_mite_ring)
 905                 return -ENOMEM;
 906
 907         if (board->uses_firmware) {
 908                 ret = pci_6534_upload_firmware(dev);
 909                 if (ret < 0)
 910                         return ret;
 911         }
 912
 913         nidio_reset_board(dev);
 914
 915         ret = comedi_alloc_subdevices(dev, 1);
 916         if (ret)
 917                 return ret;
 918
 919         dev_info(dev->class_dev, "%s rev=%d\n", dev->board_name,
 920                  readb(dev->mmio + Chip_Version));
 921
 922         s = &dev->subdevices[0];
 923
 924         dev->read_subdev = s;
 925         s->type = COMEDI_SUBD_DIO;
 926         s->subdev_flags =
 927                 SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_PACKED |
 928                 SDF_CMD_READ;
 929         s->n_chan = 32;
 930         s->range_table = &range_digital;
 931         s->maxdata = 1;
 932         s->insn_config = &ni_pcidio_insn_config;
 933         s->insn_bits = &ni_pcidio_insn_bits;
 934         s->do_cmd = &ni_pcidio_cmd;
 935         s->do_cmdtest = &ni_pcidio_cmdtest;
 936         s->cancel = &ni_pcidio_cancel;
 937         s->len_chanlist = 32;   /* XXX */
 938         s->buf_change = &ni_pcidio_change;
 939         s->async_dma_dir = DMA_BIDIRECTIONAL;
 940         s->poll = &ni_pcidio_poll;
 941
 942         irq = pcidev->irq;
 943         if (irq) {
 944                 ret = request_irq(irq, nidio_interrupt, IRQF_SHARED,
 945                                   dev->board_name, dev);
 946                 if (ret == 0)
 947                         dev->irq = irq;
 948         }
 949
 950         return 0;
 951 }
 952
 953 static void nidio_detach(struct comedi_device *dev)
 954 {
 955         struct nidio96_private *devpriv = dev->private;
 956
 957         if (dev->irq)
 958                 free_irq(dev->irq, dev);
 959         if (devpriv) {
 960                 if (devpriv->di_mite_ring) {
 961                         mite_free_ring(devpriv->di_mite_ring);
 962                         devpriv->di_mite_ring = NULL;
 963                 }
 964                 mite_detach(devpriv->mite);
 965         }
 966         if (dev->mmio)
 967                 iounmap(dev->mmio);
 968         comedi_pci_disable(dev);
 969 }
 970
 971 static struct comedi_driver ni_pcidio_driver = {
 972         .driver_name    = "ni_pcidio",
 973         .module         = THIS_MODULE,
 974         .auto_attach    = nidio_auto_attach,
 975         .detach         = nidio_detach,
 976 };
 977
 978 static int ni_pcidio_pci_probe(struct pci_dev *dev,
 979                                const struct pci_device_id *id)
 980 {
 981         return comedi_pci_auto_config(dev, &ni_pcidio_driver, id->driver_data);
 982 }
 983
 984 static const struct pci_device_id ni_pcidio_pci_table[] = {
 985         { PCI_VDEVICE(NI, 0x1150), BOARD_PCIDIO_32HS },
 986         { PCI_VDEVICE(NI, 0x12b0), BOARD_PCI6534 },
 987         { PCI_VDEVICE(NI, 0x1320), BOARD_PXI6533 },
 988         { 0 }
 989 };
 990 MODULE_DEVICE_TABLE(pci, ni_pcidio_pci_table);
 991
 992 static struct pci_driver ni_pcidio_pci_driver = {
 993         .name           = "ni_pcidio",
 994         .id_table       = ni_pcidio_pci_table,
 995         .probe          = ni_pcidio_pci_probe,
 996         .remove         = comedi_pci_auto_unconfig,
 997 };
 998 module_comedi_pci_driver(ni_pcidio_driver, ni_pcidio_pci_driver);
 999
1000 MODULE_AUTHOR("Comedi http://www.comedi.org");
1001 MODULE_DESCRIPTION("Comedi low-level driver");
1002 MODULE_LICENSE("GPL");