2 * Comedi driver for National Instruments AT-A2150 boards
3 * Copyright (C) 2001, 2002 Frank Mori Hess <fmhess@users.sourceforge.net>
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 2000 David A. Schleef <ds@schleef.org>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
21 * Description: National Instruments AT-A2150
22 * Author: Frank Mori Hess
24 * Devices: [National Instruments] AT-A2150C (at_a2150c), AT-2150S (at_a2150s)
26 * Configuration options:
27 * [0] - I/O port base address
28 * [1] - IRQ (optional, required for timed conversions)
29 * [2] - DMA (optional, required for timed conversions)
31 * Yet another driver for obsolete hardware brought to you by Frank Hess.
32 * Testing and debugging help provided by Dave Andruczyk.
34 * If you want to ac couple the board's inputs, use AREF_OTHER.
36 * The only difference in the boards is their master clock frequencies.
38 * References (from ftp://ftp.natinst.com/support/manuals):
39 * 320360.pdf AT-A2150 User Manual
42 * - analog level triggering
46 #include <linux/module.h>
47 #include <linux/delay.h>
48 #include <linux/interrupt.h>
49 #include <linux/slab.h>
52 #include "../comedidev.h"
54 #include "comedi_isadma.h"
55 #include "comedi_8254.h"
57 #define A2150_DMA_BUFFER_SIZE 0xff00 /* size in bytes of dma buffer */
59 /* Registers and bits */
60 #define CONFIG_REG 0x0
61 #define CHANNEL_BITS(x) ((x) & 0x7)
62 #define CHANNEL_MASK 0x7
63 #define CLOCK_SELECT_BITS(x) (((x) & 0x3) << 3)
64 #define CLOCK_DIVISOR_BITS(x) (((x) & 0x3) << 5)
65 #define CLOCK_MASK (0xf << 3)
66 /* enable (don't internally ground) channels 0 and 1 */
67 #define ENABLE0_BIT 0x80
68 /* enable (don't internally ground) channels 2 and 3 */
69 #define ENABLE1_BIT 0x100
70 #define AC0_BIT 0x200 /* ac couple channels 0,1 */
71 #define AC1_BIT 0x400 /* ac couple channels 2,3 */
72 #define APD_BIT 0x800 /* analog power down */
73 #define DPD_BIT 0x1000 /* digital power down */
74 #define TRIGGER_REG 0x2 /* trigger config register */
75 #define POST_TRIGGER_BITS 0x2
76 #define DELAY_TRIGGER_BITS 0x3
77 #define HW_TRIG_EN 0x10 /* enable hardware trigger */
78 #define FIFO_START_REG 0x6 /* software start aquistion trigger */
79 #define FIFO_RESET_REG 0x8 /* clears fifo + fifo flags */
80 #define FIFO_DATA_REG 0xa /* read data */
81 #define DMA_TC_CLEAR_REG 0xe /* clear dma terminal count interrupt */
82 #define STATUS_REG 0x12 /* read only */
83 #define FNE_BIT 0x1 /* fifo not empty */
84 #define OVFL_BIT 0x8 /* fifo overflow */
85 #define EDAQ_BIT 0x10 /* end of acquisition interrupt */
86 #define DCAL_BIT 0x20 /* offset calibration in progress */
87 #define INTR_BIT 0x40 /* interrupt has occurred */
88 /* dma terminal count interrupt has occurred */
89 #define DMA_TC_BIT 0x80
90 #define ID_BITS(x) (((x) >> 8) & 0x3)
91 #define IRQ_DMA_CNTRL_REG 0x12 /* write only */
92 #define DMA_CHAN_BITS(x) ((x) & 0x7) /* sets dma channel */
93 #define DMA_EN_BIT 0x8 /* enables dma */
94 #define IRQ_LVL_BITS(x) (((x) & 0xf) << 4) /* sets irq level */
95 #define FIFO_INTR_EN_BIT 0x100 /* enable fifo interrupts */
96 #define FIFO_INTR_FHF_BIT 0x200 /* interrupt fifo half full */
97 /* enable interrupt on dma terminal count */
98 #define DMA_INTR_EN_BIT 0x800
99 #define DMA_DEM_EN_BIT 0x1000 /* enables demand mode dma */
100 #define I8253_BASE_REG 0x14
104 int clock[4]; /* master clock periods, in nanoseconds */
105 int num_clocks; /* number of available master clock speeds */
106 int ai_speed; /* maximum conversion rate in nanoseconds */
109 /* analog input range */
110 static const struct comedi_lrange range_a2150 = {
116 /* enum must match board indices */
117 enum { a2150_c, a2150_s };
118 static const struct a2150_board a2150_boards[] = {
121 .clock = {31250, 22676, 20833, 19531},
127 .clock = {62500, 50000, 41667, 0},
133 struct a2150_private {
134 struct comedi_isadma *dma;
135 unsigned int count; /* number of data points left to be taken */
136 int irq_dma_bits; /* irq/dma register bits */
137 int config_bits; /* config register bits */
140 /* interrupt service routine */
141 static irqreturn_t a2150_interrupt(int irq, void *d)
143 struct comedi_device *dev = d;
144 struct a2150_private *devpriv = dev->private;
145 struct comedi_isadma *dma = devpriv->dma;
146 struct comedi_isadma_desc *desc = &dma->desc[0];
147 struct comedi_subdevice *s = dev->read_subdev;
148 struct comedi_async *async = s->async;
149 struct comedi_cmd *cmd = &async->cmd;
150 unsigned short *buf = desc->virt_addr;
151 unsigned int max_points, num_points, residue, leftover;
159 status = inw(dev->iobase + STATUS_REG);
160 if ((status & INTR_BIT) == 0)
163 if (status & OVFL_BIT) {
164 async->events |= COMEDI_CB_ERROR;
165 comedi_handle_events(dev, s);
168 if ((status & DMA_TC_BIT) == 0) {
169 async->events |= COMEDI_CB_ERROR;
170 comedi_handle_events(dev, s);
175 * residue is the number of bytes left to be done on the dma
176 * transfer. It should always be zero at this point unless
177 * the stop_src is set to external triggering.
179 residue = comedi_isadma_disable(desc->chan);
181 /* figure out how many points to read */
182 max_points = comedi_bytes_to_samples(s, desc->size);
183 num_points = max_points - comedi_bytes_to_samples(s, residue);
184 if (devpriv->count < num_points && cmd->stop_src == TRIG_COUNT)
185 num_points = devpriv->count;
187 /* figure out how many points will be stored next time */
189 if (cmd->stop_src == TRIG_NONE) {
190 leftover = comedi_bytes_to_samples(s, desc->size);
191 } else if (devpriv->count > max_points) {
192 leftover = devpriv->count - max_points;
193 if (leftover > max_points)
194 leftover = max_points;
197 * There should only be a residue if collection was stopped by having
198 * the stop_src set to an external trigger, in which case there
199 * will be no more data
204 for (i = 0; i < num_points; i++) {
205 /* write data point to comedi buffer */
207 /* convert from 2's complement to unsigned coding */
209 comedi_buf_write_samples(s, &dpnt, 1);
210 if (cmd->stop_src == TRIG_COUNT) {
211 if (--devpriv->count == 0) { /* end of acquisition */
212 async->events |= COMEDI_CB_EOA;
219 desc->size = comedi_samples_to_bytes(s, leftover);
220 comedi_isadma_program(desc);
223 comedi_handle_events(dev, s);
225 /* clear interrupt */
226 outw(0x00, dev->iobase + DMA_TC_CLEAR_REG);
231 static int a2150_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
233 struct a2150_private *devpriv = dev->private;
234 struct comedi_isadma *dma = devpriv->dma;
235 struct comedi_isadma_desc *desc = &dma->desc[0];
237 /* disable dma on card */
238 devpriv->irq_dma_bits &= ~DMA_INTR_EN_BIT & ~DMA_EN_BIT;
239 outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG);
241 /* disable computer's dma */
242 comedi_isadma_disable(desc->chan);
244 /* clear fifo and reset triggering circuitry */
245 outw(0, dev->iobase + FIFO_RESET_REG);
251 * sets bits in devpriv->clock_bits to nearest approximation of requested
252 * period, adjusts requested period to actual timing.
254 static int a2150_get_timing(struct comedi_device *dev, unsigned int *period,
257 const struct a2150_board *board = dev->board_ptr;
258 struct a2150_private *devpriv = dev->private;
260 int lub_divisor_shift, lub_index, glb_divisor_shift, glb_index;
263 /* initialize greatest lower and least upper bounds */
264 lub_divisor_shift = 3;
266 lub = board->clock[lub_index] * (1 << lub_divisor_shift);
267 glb_divisor_shift = 0;
268 glb_index = board->num_clocks - 1;
269 glb = board->clock[glb_index] * (1 << glb_divisor_shift);
271 /* make sure period is in available range */
277 /* we can multiply period by 1, 2, 4, or 8, using (1 << i) */
278 for (i = 0; i < 4; i++) {
279 /* there are a maximum of 4 master clocks */
280 for (j = 0; j < board->num_clocks; j++) {
281 /* temp is the period in nanosec we are evaluating */
282 temp = board->clock[j] * (1 << i);
283 /* if it is the best match yet */
284 if (temp < lub && temp >= *period) {
285 lub_divisor_shift = i;
289 if (temp > glb && temp <= *period) {
290 glb_divisor_shift = i;
296 switch (flags & CMDF_ROUND_MASK) {
297 case CMDF_ROUND_NEAREST:
299 /* if least upper bound is better approximation */
300 if (lub - *period < *period - glb)
308 case CMDF_ROUND_DOWN:
313 /* set clock bits for config register appropriately */
314 devpriv->config_bits &= ~CLOCK_MASK;
315 if (*period == lub) {
316 devpriv->config_bits |=
317 CLOCK_SELECT_BITS(lub_index) |
318 CLOCK_DIVISOR_BITS(lub_divisor_shift);
320 devpriv->config_bits |=
321 CLOCK_SELECT_BITS(glb_index) |
322 CLOCK_DIVISOR_BITS(glb_divisor_shift);
328 static int a2150_set_chanlist(struct comedi_device *dev,
329 unsigned int start_channel,
330 unsigned int num_channels)
332 struct a2150_private *devpriv = dev->private;
334 if (start_channel + num_channels > 4)
337 devpriv->config_bits &= ~CHANNEL_MASK;
339 switch (num_channels) {
341 devpriv->config_bits |= CHANNEL_BITS(0x4 | start_channel);
344 if (start_channel == 0)
345 devpriv->config_bits |= CHANNEL_BITS(0x2);
346 else if (start_channel == 2)
347 devpriv->config_bits |= CHANNEL_BITS(0x3);
352 devpriv->config_bits |= CHANNEL_BITS(0x1);
361 static int a2150_ai_check_chanlist(struct comedi_device *dev,
362 struct comedi_subdevice *s,
363 struct comedi_cmd *cmd)
365 unsigned int chan0 = CR_CHAN(cmd->chanlist[0]);
366 unsigned int aref0 = CR_AREF(cmd->chanlist[0]);
369 if (cmd->chanlist_len == 2 && (chan0 == 1 || chan0 == 3)) {
370 dev_dbg(dev->class_dev,
371 "length 2 chanlist must be channels 0,1 or channels 2,3\n");
375 if (cmd->chanlist_len == 3) {
376 dev_dbg(dev->class_dev,
377 "chanlist must have 1,2 or 4 channels\n");
381 for (i = 1; i < cmd->chanlist_len; i++) {
382 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
383 unsigned int aref = CR_AREF(cmd->chanlist[i]);
385 if (chan != (chan0 + i)) {
386 dev_dbg(dev->class_dev,
387 "entries in chanlist must be consecutive channels, counting upwards\n");
394 dev_dbg(dev->class_dev,
395 "channels 0/1 and 2/3 must have the same analog reference\n");
403 static int a2150_ai_cmdtest(struct comedi_device *dev,
404 struct comedi_subdevice *s, struct comedi_cmd *cmd)
406 const struct a2150_board *board = dev->board_ptr;
410 /* Step 1 : check if triggers are trivially valid */
412 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
413 err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_TIMER);
414 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
415 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
416 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
421 /* Step 2a : make sure trigger sources are unique */
423 err |= comedi_check_trigger_is_unique(cmd->start_src);
424 err |= comedi_check_trigger_is_unique(cmd->stop_src);
426 /* Step 2b : and mutually compatible */
431 /* Step 3: check if arguments are trivially valid */
433 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
435 if (cmd->convert_src == TRIG_TIMER) {
436 err |= comedi_check_trigger_arg_min(&cmd->convert_arg,
440 err |= comedi_check_trigger_arg_min(&cmd->chanlist_len, 1);
441 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
444 if (cmd->stop_src == TRIG_COUNT)
445 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
447 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
452 /* step 4: fix up any arguments */
454 if (cmd->scan_begin_src == TRIG_TIMER) {
455 arg = cmd->scan_begin_arg;
456 a2150_get_timing(dev, &arg, cmd->flags);
457 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, arg);
463 /* Step 5: check channel list if it exists */
464 if (cmd->chanlist && cmd->chanlist_len > 0)
465 err |= a2150_ai_check_chanlist(dev, s, cmd);
473 static int a2150_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
475 struct a2150_private *devpriv = dev->private;
476 struct comedi_isadma *dma = devpriv->dma;
477 struct comedi_isadma_desc *desc = &dma->desc[0];
478 struct comedi_async *async = s->async;
479 struct comedi_cmd *cmd = &async->cmd;
480 unsigned int old_config_bits = devpriv->config_bits;
481 unsigned int trigger_bits;
483 if (cmd->flags & CMDF_PRIORITY) {
484 dev_err(dev->class_dev,
485 "dma incompatible with hard real-time interrupt (CMDF_PRIORITY), aborting\n");
488 /* clear fifo and reset triggering circuitry */
489 outw(0, dev->iobase + FIFO_RESET_REG);
492 if (a2150_set_chanlist(dev, CR_CHAN(cmd->chanlist[0]),
493 cmd->chanlist_len) < 0)
496 /* setup ac/dc coupling */
497 if (CR_AREF(cmd->chanlist[0]) == AREF_OTHER)
498 devpriv->config_bits |= AC0_BIT;
500 devpriv->config_bits &= ~AC0_BIT;
501 if (CR_AREF(cmd->chanlist[2]) == AREF_OTHER)
502 devpriv->config_bits |= AC1_BIT;
504 devpriv->config_bits &= ~AC1_BIT;
507 a2150_get_timing(dev, &cmd->scan_begin_arg, cmd->flags);
509 /* send timing, channel, config bits */
510 outw(devpriv->config_bits, dev->iobase + CONFIG_REG);
512 /* initialize number of samples remaining */
513 devpriv->count = cmd->stop_arg * cmd->chanlist_len;
515 comedi_isadma_disable(desc->chan);
517 /* set size of transfer to fill in 1/3 second */
518 #define ONE_THIRD_SECOND 333333333
519 desc->size = comedi_bytes_per_sample(s) * cmd->chanlist_len *
520 ONE_THIRD_SECOND / cmd->scan_begin_arg;
521 if (desc->size > desc->maxsize)
522 desc->size = desc->maxsize;
523 if (desc->size < comedi_bytes_per_sample(s))
524 desc->size = comedi_bytes_per_sample(s);
525 desc->size -= desc->size % comedi_bytes_per_sample(s);
527 comedi_isadma_program(desc);
530 * Clear dma interrupt before enabling it, to try and get rid of
531 * that one spurious interrupt that has been happening.
533 outw(0x00, dev->iobase + DMA_TC_CLEAR_REG);
535 /* enable dma on card */
536 devpriv->irq_dma_bits |= DMA_INTR_EN_BIT | DMA_EN_BIT;
537 outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG);
539 /* may need to wait 72 sampling periods if timing was changed */
540 comedi_8254_load(dev->pacer, 2, 72, I8254_MODE0 | I8254_BINARY);
542 /* setup start triggering */
544 /* decide if we need to wait 72 periods for valid data */
545 if (cmd->start_src == TRIG_NOW &&
546 (old_config_bits & CLOCK_MASK) !=
547 (devpriv->config_bits & CLOCK_MASK)) {
548 /* set trigger source to delay trigger */
549 trigger_bits |= DELAY_TRIGGER_BITS;
551 /* otherwise no delay */
552 trigger_bits |= POST_TRIGGER_BITS;
554 /* enable external hardware trigger */
555 if (cmd->start_src == TRIG_EXT) {
556 trigger_bits |= HW_TRIG_EN;
557 } else if (cmd->start_src == TRIG_OTHER) {
559 * XXX add support for level/slope start trigger
562 dev_err(dev->class_dev, "you shouldn't see this?\n");
564 /* send trigger config bits */
565 outw(trigger_bits, dev->iobase + TRIGGER_REG);
567 /* start acquisition for soft trigger */
568 if (cmd->start_src == TRIG_NOW)
569 outw(0, dev->iobase + FIFO_START_REG);
574 static int a2150_ai_eoc(struct comedi_device *dev,
575 struct comedi_subdevice *s,
576 struct comedi_insn *insn,
577 unsigned long context)
581 status = inw(dev->iobase + STATUS_REG);
582 if (status & FNE_BIT)
587 static int a2150_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
588 struct comedi_insn *insn, unsigned int *data)
590 struct a2150_private *devpriv = dev->private;
594 /* clear fifo and reset triggering circuitry */
595 outw(0, dev->iobase + FIFO_RESET_REG);
598 if (a2150_set_chanlist(dev, CR_CHAN(insn->chanspec), 1) < 0)
601 /* set dc coupling */
602 devpriv->config_bits &= ~AC0_BIT;
603 devpriv->config_bits &= ~AC1_BIT;
605 /* send timing, channel, config bits */
606 outw(devpriv->config_bits, dev->iobase + CONFIG_REG);
608 /* disable dma on card */
609 devpriv->irq_dma_bits &= ~DMA_INTR_EN_BIT & ~DMA_EN_BIT;
610 outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG);
612 /* setup start triggering */
613 outw(0, dev->iobase + TRIGGER_REG);
615 /* start acquisition for soft trigger */
616 outw(0, dev->iobase + FIFO_START_REG);
619 * there is a 35.6 sample delay for data to get through the
622 for (n = 0; n < 36; n++) {
623 ret = comedi_timeout(dev, s, insn, a2150_ai_eoc, 0);
627 inw(dev->iobase + FIFO_DATA_REG);
631 for (n = 0; n < insn->n; n++) {
632 ret = comedi_timeout(dev, s, insn, a2150_ai_eoc, 0);
636 data[n] = inw(dev->iobase + FIFO_DATA_REG);
640 /* clear fifo and reset triggering circuitry */
641 outw(0, dev->iobase + FIFO_RESET_REG);
646 static void a2150_alloc_irq_and_dma(struct comedi_device *dev,
647 struct comedi_devconfig *it)
649 struct a2150_private *devpriv = dev->private;
650 unsigned int irq_num = it->options[1];
651 unsigned int dma_chan = it->options[2];
654 * Only IRQs 15, 14, 12-9, and 7-3 are valid.
655 * Only DMA channels 7-5 and 3-0 are valid.
657 if (irq_num > 15 || dma_chan > 7 ||
658 !((1 << irq_num) & 0xdef8) || !((1 << dma_chan) & 0xef))
661 if (request_irq(irq_num, a2150_interrupt, 0, dev->board_name, dev))
664 /* DMA uses 1 buffer */
665 devpriv->dma = comedi_isadma_alloc(dev, 1, dma_chan, dma_chan,
666 A2150_DMA_BUFFER_SIZE,
669 free_irq(irq_num, dev);
672 devpriv->irq_dma_bits = IRQ_LVL_BITS(irq_num) |
673 DMA_CHAN_BITS(dma_chan);
677 static void a2150_free_dma(struct comedi_device *dev)
679 struct a2150_private *devpriv = dev->private;
682 comedi_isadma_free(devpriv->dma);
685 static const struct a2150_board *a2150_probe(struct comedi_device *dev)
687 int id = ID_BITS(inw(dev->iobase + STATUS_REG));
689 if (id >= ARRAY_SIZE(a2150_boards))
692 return &a2150_boards[id];
695 static int a2150_attach(struct comedi_device *dev, struct comedi_devconfig *it)
697 const struct a2150_board *board;
698 struct a2150_private *devpriv;
699 struct comedi_subdevice *s;
700 static const int timeout = 2000;
704 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
708 ret = comedi_request_region(dev, it->options[0], 0x1c);
712 board = a2150_probe(dev);
715 dev->board_ptr = board;
716 dev->board_name = board->name;
718 /* an IRQ and DMA are required to support async commands */
719 a2150_alloc_irq_and_dma(dev, it);
721 dev->pacer = comedi_8254_init(dev->iobase + I8253_BASE_REG,
726 ret = comedi_alloc_subdevices(dev, 1);
730 /* analog input subdevice */
731 s = &dev->subdevices[0];
732 s->type = COMEDI_SUBD_AI;
733 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_OTHER;
736 s->range_table = &range_a2150;
737 s->insn_read = a2150_ai_rinsn;
739 dev->read_subdev = s;
740 s->subdev_flags |= SDF_CMD_READ;
741 s->len_chanlist = s->n_chan;
742 s->do_cmd = a2150_ai_cmd;
743 s->do_cmdtest = a2150_ai_cmdtest;
744 s->cancel = a2150_cancel;
747 /* set card's irq and dma levels */
748 outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG);
750 /* reset and sync adc clock circuitry */
751 outw_p(DPD_BIT | APD_BIT, dev->iobase + CONFIG_REG);
752 outw_p(DPD_BIT, dev->iobase + CONFIG_REG);
753 /* initialize configuration register */
754 devpriv->config_bits = 0;
755 outw(devpriv->config_bits, dev->iobase + CONFIG_REG);
756 /* wait until offset calibration is done, then enable analog inputs */
757 for (i = 0; i < timeout; i++) {
758 if ((DCAL_BIT & inw(dev->iobase + STATUS_REG)) == 0)
760 usleep_range(1000, 3000);
763 dev_err(dev->class_dev,
764 "timed out waiting for offset calibration to complete\n");
767 devpriv->config_bits |= ENABLE0_BIT | ENABLE1_BIT;
768 outw(devpriv->config_bits, dev->iobase + CONFIG_REG);
773 static void a2150_detach(struct comedi_device *dev)
776 outw(APD_BIT | DPD_BIT, dev->iobase + CONFIG_REG);
778 comedi_legacy_detach(dev);
781 static struct comedi_driver ni_at_a2150_driver = {
782 .driver_name = "ni_at_a2150",
783 .module = THIS_MODULE,
784 .attach = a2150_attach,
785 .detach = a2150_detach,
787 module_comedi_driver(ni_at_a2150_driver);
789 MODULE_AUTHOR("Comedi http://www.comedi.org");
790 MODULE_DESCRIPTION("Comedi low-level driver");
791 MODULE_LICENSE("GPL");