drivers/spi/spi-orion.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Marvell Orion SPI controller driver
   4  *
   5  * Author: Shadi Ammouri <shadi@marvell.com>
   6  * Copyright (C) 2007-2008 Marvell Ltd.
   7  */
   8
   9 #include <linux/interrupt.h>
  10 #include <linux/delay.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/err.h>
  13 #include <linux/io.h>
  14 #include <linux/spi/spi.h>
  15 #include <linux/module.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/of.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of_device.h>
  20 #include <linux/of_gpio.h>
  21 #include <linux/clk.h>
  22 #include <linux/sizes.h>
  23 #include <linux/gpio.h>
  24 #include <asm/unaligned.h>
  25
  26 #define DRIVER_NAME                     "orion_spi"
  27
  28 /* Runtime PM autosuspend timeout: PM is fairly light on this driver */
  29 #define SPI_AUTOSUSPEND_TIMEOUT         200
  30
  31 /* Some SoCs using this driver support up to 8 chip selects.
  32  * It is up to the implementer to only use the chip selects
  33  * that are available.
  34  */
  35 #define ORION_NUM_CHIPSELECTS           8
  36
  37 #define ORION_SPI_WAIT_RDY_MAX_LOOP     2000 /* in usec */
  38
  39 #define ORION_SPI_IF_CTRL_REG           0x00
  40 #define ORION_SPI_IF_CONFIG_REG         0x04
  41 #define ORION_SPI_IF_RXLSBF             BIT(14)
  42 #define ORION_SPI_IF_TXLSBF             BIT(13)
  43 #define ORION_SPI_DATA_OUT_REG          0x08
  44 #define ORION_SPI_DATA_IN_REG           0x0c
  45 #define ORION_SPI_INT_CAUSE_REG         0x10
  46 #define ORION_SPI_TIMING_PARAMS_REG     0x18
  47
  48 /* Register for the "Direct Mode" */
  49 #define SPI_DIRECT_WRITE_CONFIG_REG     0x20
  50
  51 #define ORION_SPI_TMISO_SAMPLE_MASK     (0x3 << 6)
  52 #define ORION_SPI_TMISO_SAMPLE_1        (1 << 6)
  53 #define ORION_SPI_TMISO_SAMPLE_2        (2 << 6)
  54
  55 #define ORION_SPI_MODE_CPOL             (1 << 11)
  56 #define ORION_SPI_MODE_CPHA             (1 << 12)
  57 #define ORION_SPI_IF_8_16_BIT_MODE      (1 << 5)
  58 #define ORION_SPI_CLK_PRESCALE_MASK     0x1F
  59 #define ARMADA_SPI_CLK_PRESCALE_MASK    0xDF
  60 #define ORION_SPI_MODE_MASK             (ORION_SPI_MODE_CPOL | \
  61                                          ORION_SPI_MODE_CPHA)
  62 #define ORION_SPI_CS_MASK       0x1C
  63 #define ORION_SPI_CS_SHIFT      2
  64 #define ORION_SPI_CS(cs)        ((cs << ORION_SPI_CS_SHIFT) & \
  65                                         ORION_SPI_CS_MASK)
  66
  67 enum orion_spi_type {
  68         ORION_SPI,
  69         ARMADA_SPI,
  70 };
  71
  72 struct orion_spi_dev {
  73         enum orion_spi_type     typ;
  74         /*
  75          * min_divisor and max_hz should be exclusive, the only we can
  76          * have both is for managing the armada-370-spi case with old
  77          * device tree
  78          */
  79         unsigned long           max_hz;
  80         unsigned int            min_divisor;
  81         unsigned int            max_divisor;
  82         u32                     prescale_mask;
  83         bool                    is_errata_50mhz_ac;
  84 };
  85
  86 struct orion_direct_acc {
  87         void __iomem            *vaddr;
  88         u32                     size;
  89 };
  90
  91 struct orion_child_options {
  92         struct orion_direct_acc direct_access;
  93 };
  94
  95 struct orion_spi {
  96         struct spi_master       *master;
  97         void __iomem            *base;
  98         struct clk              *clk;
  99         struct clk              *axi_clk;
 100         const struct orion_spi_dev *devdata;
 101         int                     unused_hw_gpio;
 102
 103         struct orion_child_options      child[ORION_NUM_CHIPSELECTS];
 104 };
 105
 106 static inline void __iomem *spi_reg(struct orion_spi *orion_spi, u32 reg)
 107 {
 108         return orion_spi->base + reg;
 109 }
 110
 111 static inline void
 112 orion_spi_setbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
 113 {
 114         void __iomem *reg_addr = spi_reg(orion_spi, reg);
 115         u32 val;
 116
 117         val = readl(reg_addr);
 118         val |= mask;
 119         writel(val, reg_addr);
 120 }
 121
 122 static inline void
 123 orion_spi_clrbits(struct orion_spi *orion_spi, u32 reg, u32 mask)
 124 {
 125         void __iomem *reg_addr = spi_reg(orion_spi, reg);
 126         u32 val;
 127
 128         val = readl(reg_addr);
 129         val &= ~mask;
 130         writel(val, reg_addr);
 131 }
 132
 133 static int orion_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
 134 {
 135         u32 tclk_hz;
 136         u32 rate;
 137         u32 prescale;
 138         u32 reg;
 139         struct orion_spi *orion_spi;
 140         const struct orion_spi_dev *devdata;
 141
 142         orion_spi = spi_master_get_devdata(spi->master);
 143         devdata = orion_spi->devdata;
 144
 145         tclk_hz = clk_get_rate(orion_spi->clk);
 146
 147         if (devdata->typ == ARMADA_SPI) {
 148                 /*
 149                  * Given the core_clk (tclk_hz) and the target rate (speed) we
 150                  * determine the best values for SPR (in [0 .. 15]) and SPPR (in
 151                  * [0..7]) such that
 152                  *
 153                  *      core_clk / (SPR * 2 ** SPPR)
 154                  *
 155                  * is as big as possible but not bigger than speed.
 156                  */
 157
 158                 /* best integer divider: */
 159                 unsigned divider = DIV_ROUND_UP(tclk_hz, speed);
 160                 unsigned spr, sppr;
 161
 162                 if (divider < 16) {
 163                         /* This is the easy case, divider is less than 16 */
 164                         spr = divider;
 165                         sppr = 0;
 166
 167                 } else {
 168                         unsigned two_pow_sppr;
 169                         /*
 170                          * Find the highest bit set in divider. This and the
 171                          * three next bits define SPR (apart from rounding).
 172                          * SPPR is then the number of zero bits that must be
 173                          * appended:
 174                          */
 175                         sppr = fls(divider) - 4;
 176
 177                         /*
 178                          * As SPR only has 4 bits, we have to round divider up
 179                          * to the next multiple of 2 ** sppr.
 180                          */
 181                         two_pow_sppr = 1 << sppr;
 182                         divider = (divider + two_pow_sppr - 1) & -two_pow_sppr;
 183
 184                         /*
 185                          * recalculate sppr as rounding up divider might have
 186                          * increased it enough to change the position of the
 187                          * highest set bit. In this case the bit that now
 188                          * doesn't make it into SPR is 0, so there is no need to
 189                          * round again.
 190                          */
 191                         sppr = fls(divider) - 4;
 192                         spr = divider >> sppr;
 193
 194                         /*
 195                          * Now do range checking. SPR is constructed to have a
 196                          * width of 4 bits, so this is fine for sure. So we
 197                          * still need to check for sppr to fit into 3 bits:
 198                          */
 199                         if (sppr > 7)
 200                                 return -EINVAL;
 201                 }
 202
 203                 prescale = ((sppr & 0x6) << 5) | ((sppr & 0x1) << 4) | spr;
 204         } else {
 205                 /*
 206                  * the supported rates are: 4,6,8...30
 207                  * round up as we look for equal or less speed
 208                  */
 209                 rate = DIV_ROUND_UP(tclk_hz, speed);
 210                 rate = roundup(rate, 2);
 211
 212                 /* check if requested speed is too small */
 213                 if (rate > 30)
 214                         return -EINVAL;
 215
 216                 if (rate < 4)
 217                         rate = 4;
 218
 219                 /* Convert the rate to SPI clock divisor value. */
 220                 prescale = 0x10 + rate/2;
 221         }
 222
 223         reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
 224         reg = ((reg & ~devdata->prescale_mask) | prescale);
 225         writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
 226
 227         return 0;
 228 }
 229
 230 static void
 231 orion_spi_mode_set(struct spi_device *spi)
 232 {
 233         u32 reg;
 234         struct orion_spi *orion_spi;
 235
 236         orion_spi = spi_master_get_devdata(spi->master);
 237
 238         reg = readl(spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
 239         reg &= ~ORION_SPI_MODE_MASK;
 240         if (spi->mode & SPI_CPOL)
 241                 reg |= ORION_SPI_MODE_CPOL;
 242         if (spi->mode & SPI_CPHA)
 243                 reg |= ORION_SPI_MODE_CPHA;
 244         if (spi->mode & SPI_LSB_FIRST)
 245                 reg |= ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF;
 246         else
 247                 reg &= ~(ORION_SPI_IF_RXLSBF | ORION_SPI_IF_TXLSBF);
 248
 249         writel(reg, spi_reg(orion_spi, ORION_SPI_IF_CONFIG_REG));
 250 }
 251
 252 static void
 253 orion_spi_50mhz_ac_timing_erratum(struct spi_device *spi, unsigned int speed)
 254 {
 255         u32 reg;
 256         struct orion_spi *orion_spi;
 257
 258         orion_spi = spi_master_get_devdata(spi->master);
 259
 260         /*
 261          * Erratum description: (Erratum NO. FE-9144572) The device
 262          * SPI interface supports frequencies of up to 50 MHz.
 263          * However, due to this erratum, when the device core clock is
 264          * 250 MHz and the SPI interfaces is configured for 50MHz SPI
 265          * clock and CPOL=CPHA=1 there might occur data corruption on
 266          * reads from the SPI device.
 267          * Erratum Workaround:
 268          * Work in one of the following configurations:
 269          * 1. Set CPOL=CPHA=0 in "SPI Interface Configuration
 270          * Register".
 271          * 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1
 272          * Register" before setting the interface.
 273          */
 274         reg = readl(spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG));
 275         reg &= ~ORION_SPI_TMISO_SAMPLE_MASK;
 276
 277         if (clk_get_rate(orion_spi->clk) == 250000000 &&
 278                         speed == 50000000 && spi->mode & SPI_CPOL &&
 279                         spi->mode & SPI_CPHA)
 280                 reg |= ORION_SPI_TMISO_SAMPLE_2;
 281         else
 282                 reg |= ORION_SPI_TMISO_SAMPLE_1; /* This is the default value */
 283
 284         writel(reg, spi_reg(orion_spi, ORION_SPI_TIMING_PARAMS_REG));
 285 }
 286
 287 /*
 288  * called only when no transfer is active on the bus
 289  */
 290 static int
 291 orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
 292 {
 293         struct orion_spi *orion_spi;
 294         unsigned int speed = spi->max_speed_hz;
 295         unsigned int bits_per_word = spi->bits_per_word;
 296         int     rc;
 297
 298         orion_spi = spi_master_get_devdata(spi->master);
 299
 300         if ((t != NULL) && t->speed_hz)
 301                 speed = t->speed_hz;
 302
 303         if ((t != NULL) && t->bits_per_word)
 304                 bits_per_word = t->bits_per_word;
 305
 306         orion_spi_mode_set(spi);
 307
 308         if (orion_spi->devdata->is_errata_50mhz_ac)
 309                 orion_spi_50mhz_ac_timing_erratum(spi, speed);
 310
 311         rc = orion_spi_baudrate_set(spi, speed);
 312         if (rc)
 313                 return rc;
 314
 315         if (bits_per_word == 16)
 316                 orion_spi_setbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
 317                                   ORION_SPI_IF_8_16_BIT_MODE);
 318         else
 319                 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CONFIG_REG,
 320                                   ORION_SPI_IF_8_16_BIT_MODE);
 321
 322         return 0;
 323 }
 324
 325 static void orion_spi_set_cs(struct spi_device *spi, bool enable)
 326 {
 327         struct orion_spi *orion_spi;
 328         int cs;
 329
 330         orion_spi = spi_master_get_devdata(spi->master);
 331
 332         if (gpio_is_valid(spi->cs_gpio))
 333                 cs = orion_spi->unused_hw_gpio;
 334         else
 335                 cs = spi->chip_select;
 336
 337         orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, ORION_SPI_CS_MASK);
 338         orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG,
 339                                 ORION_SPI_CS(cs));
 340
 341         /* Chip select logic is inverted from spi_set_cs */
 342         if (!enable)
 343                 orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
 344         else
 345                 orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
 346 }
 347
 348 static inline int orion_spi_wait_till_ready(struct orion_spi *orion_spi)
 349 {
 350         int i;
 351
 352         for (i = 0; i < ORION_SPI_WAIT_RDY_MAX_LOOP; i++) {
 353                 if (readl(spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG)))
 354                         return 1;
 355
 356                 udelay(1);
 357         }
 358
 359         return -1;
 360 }
 361
 362 static inline int
 363 orion_spi_write_read_8bit(struct spi_device *spi,
 364                           const u8 **tx_buf, u8 **rx_buf)
 365 {
 366         void __iomem *tx_reg, *rx_reg, *int_reg;
 367         struct orion_spi *orion_spi;
 368
 369         orion_spi = spi_master_get_devdata(spi->master);
 370         tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
 371         rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
 372         int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
 373
 374         /* clear the interrupt cause register */
 375         writel(0x0, int_reg);
 376
 377         if (tx_buf && *tx_buf)
 378                 writel(*(*tx_buf)++, tx_reg);
 379         else
 380                 writel(0, tx_reg);
 381
 382         if (orion_spi_wait_till_ready(orion_spi) < 0) {
 383                 dev_err(&spi->dev, "TXS timed out\n");
 384                 return -1;
 385         }
 386
 387         if (rx_buf && *rx_buf)
 388                 *(*rx_buf)++ = readl(rx_reg);
 389
 390         return 1;
 391 }
 392
 393 static inline int
 394 orion_spi_write_read_16bit(struct spi_device *spi,
 395                            const u16 **tx_buf, u16 **rx_buf)
 396 {
 397         void __iomem *tx_reg, *rx_reg, *int_reg;
 398         struct orion_spi *orion_spi;
 399
 400         orion_spi = spi_master_get_devdata(spi->master);
 401         tx_reg = spi_reg(orion_spi, ORION_SPI_DATA_OUT_REG);
 402         rx_reg = spi_reg(orion_spi, ORION_SPI_DATA_IN_REG);
 403         int_reg = spi_reg(orion_spi, ORION_SPI_INT_CAUSE_REG);
 404
 405         /* clear the interrupt cause register */
 406         writel(0x0, int_reg);
 407
 408         if (tx_buf && *tx_buf)
 409                 writel(__cpu_to_le16(get_unaligned((*tx_buf)++)), tx_reg);
 410         else
 411                 writel(0, tx_reg);
 412
 413         if (orion_spi_wait_till_ready(orion_spi) < 0) {
 414                 dev_err(&spi->dev, "TXS timed out\n");
 415                 return -1;
 416         }
 417
 418         if (rx_buf && *rx_buf)
 419                 put_unaligned(__le16_to_cpu(readl(rx_reg)), (*rx_buf)++);
 420
 421         return 1;
 422 }
 423
 424 static unsigned int
 425 orion_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
 426 {
 427         unsigned int count;
 428         int word_len;
 429         struct orion_spi *orion_spi;
 430         int cs = spi->chip_select;
 431         void __iomem *vaddr;
 432
 433         word_len = spi->bits_per_word;
 434         count = xfer->len;
 435
 436         orion_spi = spi_master_get_devdata(spi->master);
 437
 438         /*
 439          * Use SPI direct write mode if base address is available. Otherwise
 440          * fall back to PIO mode for this transfer.
 441          */
 442         vaddr = orion_spi->child[cs].direct_access.vaddr;
 443
 444         if (vaddr && xfer->tx_buf && word_len == 8) {
 445                 unsigned int cnt = count / 4;
 446                 unsigned int rem = count % 4;
 447
 448                 /*
 449                  * Send the TX-data to the SPI device via the direct
 450                  * mapped address window
 451                  */
 452                 iowrite32_rep(vaddr, xfer->tx_buf, cnt);
 453                 if (rem) {
 454                         u32 *buf = (u32 *)xfer->tx_buf;
 455
 456                         iowrite8_rep(vaddr, &buf[cnt], rem);
 457                 }
 458
 459                 return count;
 460         }
 461
 462         if (word_len == 8) {
 463                 const u8 *tx = xfer->tx_buf;
 464                 u8 *rx = xfer->rx_buf;
 465
 466                 do {
 467                         if (orion_spi_write_read_8bit(spi, &tx, &rx) < 0)
 468                                 goto out;
 469                         count--;
 470                         if (xfer->word_delay_usecs)
 471                                 udelay(xfer->word_delay_usecs);
 472                 } while (count);
 473         } else if (word_len == 16) {
 474                 const u16 *tx = xfer->tx_buf;
 475                 u16 *rx = xfer->rx_buf;
 476
 477                 do {
 478                         if (orion_spi_write_read_16bit(spi, &tx, &rx) < 0)
 479                                 goto out;
 480                         count -= 2;
 481                         if (xfer->word_delay_usecs)
 482                                 udelay(xfer->word_delay_usecs);
 483                 } while (count);
 484         }
 485
 486 out:
 487         return xfer->len - count;
 488 }
 489
 490 static int orion_spi_transfer_one(struct spi_master *master,
 491                                         struct spi_device *spi,
 492                                         struct spi_transfer *t)
 493 {
 494         int status = 0;
 495
 496         status = orion_spi_setup_transfer(spi, t);
 497         if (status < 0)
 498                 return status;
 499
 500         if (t->len)
 501                 orion_spi_write_read(spi, t);
 502
 503         return status;
 504 }
 505
 506 static int orion_spi_setup(struct spi_device *spi)
 507 {
 508         if (gpio_is_valid(spi->cs_gpio)) {
 509                 gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
 510         }
 511         return orion_spi_setup_transfer(spi, NULL);
 512 }
 513
 514 static int orion_spi_reset(struct orion_spi *orion_spi)
 515 {
 516         /* Verify that the CS is deasserted */
 517         orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
 518
 519         /* Don't deassert CS between the direct mapped SPI transfers */
 520         writel(0, spi_reg(orion_spi, SPI_DIRECT_WRITE_CONFIG_REG));
 521
 522         return 0;
 523 }
 524
 525 static const struct orion_spi_dev orion_spi_dev_data = {
 526         .typ = ORION_SPI,
 527         .min_divisor = 4,
 528         .max_divisor = 30,
 529         .prescale_mask = ORION_SPI_CLK_PRESCALE_MASK,
 530 };
 531
 532 static const struct orion_spi_dev armada_370_spi_dev_data = {
 533         .typ = ARMADA_SPI,
 534         .min_divisor = 4,
 535         .max_divisor = 1920,
 536         .max_hz = 50000000,
 537         .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
 538 };
 539
 540 static const struct orion_spi_dev armada_xp_spi_dev_data = {
 541         .typ = ARMADA_SPI,
 542         .max_hz = 50000000,
 543         .max_divisor = 1920,
 544         .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
 545 };
 546
 547 static const struct orion_spi_dev armada_375_spi_dev_data = {
 548         .typ = ARMADA_SPI,
 549         .min_divisor = 15,
 550         .max_divisor = 1920,
 551         .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
 552 };
 553
 554 static const struct orion_spi_dev armada_380_spi_dev_data = {
 555         .typ = ARMADA_SPI,
 556         .max_hz = 50000000,
 557         .max_divisor = 1920,
 558         .prescale_mask = ARMADA_SPI_CLK_PRESCALE_MASK,
 559         .is_errata_50mhz_ac = true,
 560 };
 561
 562 static const struct of_device_id orion_spi_of_match_table[] = {
 563         {
 564                 .compatible = "marvell,orion-spi",
 565                 .data = &orion_spi_dev_data,
 566         },
 567         {
 568                 .compatible = "marvell,armada-370-spi",
 569                 .data = &armada_370_spi_dev_data,
 570         },
 571         {
 572                 .compatible = "marvell,armada-375-spi",
 573                 .data = &armada_375_spi_dev_data,
 574         },
 575         {
 576                 .compatible = "marvell,armada-380-spi",
 577                 .data = &armada_380_spi_dev_data,
 578         },
 579         {
 580                 .compatible = "marvell,armada-390-spi",
 581                 .data = &armada_xp_spi_dev_data,
 582         },
 583         {
 584                 .compatible = "marvell,armada-xp-spi",
 585                 .data = &armada_xp_spi_dev_data,
 586         },
 587
 588         {}
 589 };
 590 MODULE_DEVICE_TABLE(of, orion_spi_of_match_table);
 591
 592 static int orion_spi_probe(struct platform_device *pdev)
 593 {
 594         const struct of_device_id *of_id;
 595         const struct orion_spi_dev *devdata;
 596         struct spi_master *master;
 597         struct orion_spi *spi;
 598         struct resource *r;
 599         unsigned long tclk_hz;
 600         int status = 0;
 601         struct device_node *np;
 602
 603         master = spi_alloc_master(&pdev->dev, sizeof(*spi));
 604         if (master == NULL) {
 605                 dev_dbg(&pdev->dev, "master allocation failed\n");
 606                 return -ENOMEM;
 607         }
 608
 609         if (pdev->id != -1)
 610                 master->bus_num = pdev->id;
 611         if (pdev->dev.of_node) {
 612                 u32 cell_index;
 613
 614                 if (!of_property_read_u32(pdev->dev.of_node, "cell-index",
 615                                           &cell_index))
 616                         master->bus_num = cell_index;
 617         }
 618
 619         /* we support all 4 SPI modes and LSB first option */
 620         master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_LSB_FIRST;
 621         master->set_cs = orion_spi_set_cs;
 622         master->transfer_one = orion_spi_transfer_one;
 623         master->num_chipselect = ORION_NUM_CHIPSELECTS;
 624         master->setup = orion_spi_setup;
 625         master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
 626         master->auto_runtime_pm = true;
 627         master->flags = SPI_MASTER_GPIO_SS;
 628
 629         platform_set_drvdata(pdev, master);
 630
 631         spi = spi_master_get_devdata(master);
 632         spi->master = master;
 633         spi->unused_hw_gpio = -1;
 634
 635         of_id = of_match_device(orion_spi_of_match_table, &pdev->dev);
 636         devdata = (of_id) ? of_id->data : &orion_spi_dev_data;
 637         spi->devdata = devdata;
 638
 639         spi->clk = devm_clk_get(&pdev->dev, NULL);
 640         if (IS_ERR(spi->clk)) {
 641                 status = PTR_ERR(spi->clk);
 642                 goto out;
 643         }
 644
 645         status = clk_prepare_enable(spi->clk);
 646         if (status)
 647                 goto out;
 648
 649         /* The following clock is only used by some SoCs */
 650         spi->axi_clk = devm_clk_get(&pdev->dev, "axi");
 651         if (IS_ERR(spi->axi_clk) &&
 652             PTR_ERR(spi->axi_clk) == -EPROBE_DEFER) {
 653                 status = -EPROBE_DEFER;
 654                 goto out_rel_clk;
 655         }
 656         if (!IS_ERR(spi->axi_clk))
 657                 clk_prepare_enable(spi->axi_clk);
 658
 659         tclk_hz = clk_get_rate(spi->clk);
 660
 661         /*
 662          * With old device tree, armada-370-spi could be used with
 663          * Armada XP, however for this SoC the maximum frequency is
 664          * 50MHz instead of tclk/4. On Armada 370, tclk cannot be
 665          * higher than 200MHz. So, in order to be able to handle both
 666          * SoCs, we can take the minimum of 50MHz and tclk/4.
 667          */
 668         if (of_device_is_compatible(pdev->dev.of_node,
 669                                         "marvell,armada-370-spi"))
 670                 master->max_speed_hz = min(devdata->max_hz,
 671                                 DIV_ROUND_UP(tclk_hz, devdata->min_divisor));
 672         else if (devdata->min_divisor)
 673                 master->max_speed_hz =
 674                         DIV_ROUND_UP(tclk_hz, devdata->min_divisor);
 675         else
 676                 master->max_speed_hz = devdata->max_hz;
 677         master->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor);
 678
 679         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 680         spi->base = devm_ioremap_resource(&pdev->dev, r);
 681         if (IS_ERR(spi->base)) {
 682                 status = PTR_ERR(spi->base);
 683                 goto out_rel_axi_clk;
 684         }
 685
 686         for_each_available_child_of_node(pdev->dev.of_node, np) {
 687                 struct orion_direct_acc *dir_acc;
 688                 u32 cs;
 689                 int cs_gpio;
 690
 691                 /* Get chip-select number from the "reg" property */
 692                 status = of_property_read_u32(np, "reg", &cs);
 693                 if (status) {
 694                         dev_err(&pdev->dev,
 695                                 "%pOF has no valid 'reg' property (%d)\n",
 696                                 np, status);
 697                         continue;
 698                 }
 699
 700                 /*
 701                  * Initialize the CS GPIO:
 702                  * - properly request the actual GPIO signal
 703                  * - de-assert the logical signal so that all GPIO CS lines
 704                  *   are inactive when probing for slaves
 705                  * - find an unused physical CS which will be driven for any
 706                  *   slave which uses a CS GPIO
 707                  */
 708                 cs_gpio = of_get_named_gpio(pdev->dev.of_node, "cs-gpios", cs);
 709                 if (cs_gpio > 0) {
 710                         char *gpio_name;
 711                         int cs_flags;
 712
 713                         if (spi->unused_hw_gpio == -1) {
 714                                 dev_info(&pdev->dev,
 715                                         "Selected unused HW CS#%d for any GPIO CSes\n",
 716                                         cs);
 717                                 spi->unused_hw_gpio = cs;
 718                         }
 719
 720                         gpio_name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
 721                                         "%s-CS%d", dev_name(&pdev->dev), cs);
 722                         if (!gpio_name) {
 723                                 status = -ENOMEM;
 724                                 goto out_rel_axi_clk;
 725                         }
 726
 727                         cs_flags = of_property_read_bool(np, "spi-cs-high") ?
 728                                 GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH;
 729                         status = devm_gpio_request_one(&pdev->dev, cs_gpio,
 730                                         cs_flags, gpio_name);
 731                         if (status) {
 732                                 dev_err(&pdev->dev,
 733                                         "Can't request GPIO for CS %d\n", cs);
 734                                 goto out_rel_axi_clk;
 735                         }
 736                 }
 737
 738                 /*
 739                  * Check if an address is configured for this SPI device. If
 740                  * not, the MBus mapping via the 'ranges' property in the 'soc'
 741                  * node is not configured and this device should not use the
 742                  * direct mode. In this case, just continue with the next
 743                  * device.
 744                  */
 745                 status = of_address_to_resource(pdev->dev.of_node, cs + 1, r);
 746                 if (status)
 747                         continue;
 748
 749                 /*
 750                  * Only map one page for direct access. This is enough for the
 751                  * simple TX transfer which only writes to the first word.
 752                  * This needs to get extended for the direct SPI-NOR / SPI-NAND
 753                  * support, once this gets implemented.
 754                  */
 755                 dir_acc = &spi->child[cs].direct_access;
 756                 dir_acc->vaddr = devm_ioremap(&pdev->dev, r->start, PAGE_SIZE);
 757                 if (!dir_acc->vaddr) {
 758                         status = -ENOMEM;
 759                         goto out_rel_axi_clk;
 760                 }
 761                 dir_acc->size = PAGE_SIZE;
 762
 763                 dev_info(&pdev->dev, "CS%d configured for direct access\n", cs);
 764         }
 765
 766         pm_runtime_set_active(&pdev->dev);
 767         pm_runtime_use_autosuspend(&pdev->dev);
 768         pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
 769         pm_runtime_enable(&pdev->dev);
 770
 771         status = orion_spi_reset(spi);
 772         if (status < 0)
 773                 goto out_rel_pm;
 774
 775         pm_runtime_mark_last_busy(&pdev->dev);
 776         pm_runtime_put_autosuspend(&pdev->dev);
 777
 778         master->dev.of_node = pdev->dev.of_node;
 779         status = spi_register_master(master);
 780         if (status < 0)
 781                 goto out_rel_pm;
 782
 783         return status;
 784
 785 out_rel_pm:
 786         pm_runtime_disable(&pdev->dev);
 787 out_rel_axi_clk:
 788         clk_disable_unprepare(spi->axi_clk);
 789 out_rel_clk:
 790         clk_disable_unprepare(spi->clk);
 791 out:
 792         spi_master_put(master);
 793         return status;
 794 }
 795
 796
 797 static int orion_spi_remove(struct platform_device *pdev)
 798 {
 799         struct spi_master *master = platform_get_drvdata(pdev);
 800         struct orion_spi *spi = spi_master_get_devdata(master);
 801
 802         pm_runtime_get_sync(&pdev->dev);
 803         clk_disable_unprepare(spi->axi_clk);
 804         clk_disable_unprepare(spi->clk);
 805
 806         spi_unregister_master(master);
 807         pm_runtime_disable(&pdev->dev);
 808
 809         return 0;
 810 }
 811
 812 MODULE_ALIAS("platform:" DRIVER_NAME);
 813
 814 #ifdef CONFIG_PM
 815 static int orion_spi_runtime_suspend(struct device *dev)
 816 {
 817         struct spi_master *master = dev_get_drvdata(dev);
 818         struct orion_spi *spi = spi_master_get_devdata(master);
 819
 820         clk_disable_unprepare(spi->axi_clk);
 821         clk_disable_unprepare(spi->clk);
 822         return 0;
 823 }
 824
 825 static int orion_spi_runtime_resume(struct device *dev)
 826 {
 827         struct spi_master *master = dev_get_drvdata(dev);
 828         struct orion_spi *spi = spi_master_get_devdata(master);
 829
 830         if (!IS_ERR(spi->axi_clk))
 831                 clk_prepare_enable(spi->axi_clk);
 832         return clk_prepare_enable(spi->clk);
 833 }
 834 #endif
 835
 836 static const struct dev_pm_ops orion_spi_pm_ops = {
 837         SET_RUNTIME_PM_OPS(orion_spi_runtime_suspend,
 838                            orion_spi_runtime_resume,
 839                            NULL)
 840 };
 841
 842 static struct platform_driver orion_spi_driver = {
 843         .driver = {
 844                 .name   = DRIVER_NAME,
 845                 .pm     = &orion_spi_pm_ops,
 846                 .of_match_table = of_match_ptr(orion_spi_of_match_table),
 847         },
 848         .probe          = orion_spi_probe,
 849         .remove         = orion_spi_remove,
 850 };
 851
 852 module_platform_driver(orion_spi_driver);
 853
 854 MODULE_DESCRIPTION("Orion SPI driver");
 855 MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>");
 856 MODULE_LICENSE("GPL");