drivers/scsi/mpt2sas/mpi/mpi2_ioc.h

   1 /*
   2  *  Copyright (c) 2000-2011 LSI Corporation.
   3  *
   4  *
   5  *           Name:  mpi2_ioc.h
   6  *          Title:  MPI IOC, Port, Event, FW Download, and FW Upload messages
   7  *  Creation Date:  October 11, 2006
   8  *
   9  *  mpi2_ioc.h Version:  02.00.17
  10  *
  11  *  Version History
  12  *  ---------------
  13  *
  14  *  Date      Version   Description
  15  *  --------  --------  ------------------------------------------------------
  16  *  04-30-07  02.00.00  Corresponds to Fusion-MPT MPI Specification Rev A.
  17  *  06-04-07  02.00.01  In IOCFacts Reply structure, renamed MaxDevices to
  18  *                      MaxTargets.
  19  *                      Added TotalImageSize field to FWDownload Request.
  20  *                      Added reserved words to FWUpload Request.
  21  *  06-26-07  02.00.02  Added IR Configuration Change List Event.
  22  *  08-31-07  02.00.03  Removed SystemReplyQueueDepth field from the IOCInit
  23  *                      request and replaced it with
  24  *                      ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth.
  25  *                      Replaced the MinReplyQueueDepth field of the IOCFacts
  26  *                      reply with MaxReplyDescriptorPostQueueDepth.
  27  *                      Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum
  28  *                      depth for the Reply Descriptor Post Queue.
  29  *                      Added SASAddress field to Initiator Device Table
  30  *                      Overflow Event data.
  31  *  10-31-07  02.00.04  Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING
  32  *                      for SAS Initiator Device Status Change Event data.
  33  *                      Modified Reason Code defines for SAS Topology Change
  34  *                      List Event data, including adding a bit for PHY Vacant
  35  *                      status, and adding a mask for the Reason Code.
  36  *                      Added define for
  37  *                      MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING.
  38  *                      Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID.
  39  *  12-18-07  02.00.05  Added Boot Status defines for the IOCExceptions field of
  40  *                      the IOCFacts Reply.
  41  *                      Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
  42  *                      Moved MPI2_VERSION_UNION to mpi2.h.
  43  *                      Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks
  44  *                      instead of enables, and added SASBroadcastPrimitiveMasks
  45  *                      field.
  46  *                      Added Log Entry Added Event and related structure.
  47  *  02-29-08  02.00.06  Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID.
  48  *                      Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET.
  49  *                      Added MaxVolumes and MaxPersistentEntries fields to
  50  *                      IOCFacts reply.
  51  *                      Added ProtocalFlags and IOCCapabilities fields to
  52  *                      MPI2_FW_IMAGE_HEADER.
  53  *                      Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT.
  54  *  03-03-08  02.00.07  Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to
  55  *                      a U16 (from a U32).
  56  *                      Removed extra 's' from EventMasks name.
  57  *  06-27-08  02.00.08  Fixed an offset in a comment.
  58  *  10-02-08  02.00.09  Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST.
  59  *                      Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and
  60  *                      renamed MinReplyFrameSize to ReplyFrameSize.
  61  *                      Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX.
  62  *                      Added two new RAIDOperation values for Integrated RAID
  63  *                      Operations Status Event data.
  64  *                      Added four new IR Configuration Change List Event data
  65  *                      ReasonCode values.
  66  *                      Added two new ReasonCode defines for SAS Device Status
  67  *                      Change Event data.
  68  *                      Added three new DiscoveryStatus bits for the SAS
  69  *                      Discovery event data.
  70  *                      Added Multiplexing Status Change bit to the PhyStatus
  71  *                      field of the SAS Topology Change List event data.
  72  *                      Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY.
  73  *                      BootFlags are now product-specific.
  74  *                      Added defines for the indivdual signature bytes
  75  *                      for MPI2_INIT_IMAGE_FOOTER.
  76  *  01-19-09  02.00.10  Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define.
  77  *                      Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR
  78  *                      define.
  79  *                      Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE
  80  *                      define.
  81  *                      Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define.
  82  *  05-06-09  02.00.11  Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define.
  83  *                      Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define.
  84  *                      Added two new reason codes for SAS Device Status Change
  85  *                      Event.
  86  *                      Added new event: SAS PHY Counter.
  87  *  07-30-09  02.00.12  Added GPIO Interrupt event define and structure.
  88  *                      Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
  89  *                      Added new product id family for 2208.
  90  *  10-28-09  02.00.13  Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST.
  91  *                      Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY.
  92  *                      Added MinDevHandle field to MPI2_IOC_FACTS_REPLY.
  93  *                      Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY.
  94  *                      Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define.
  95  *                      Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define.
  96  *                      Added Host Based Discovery Phy Event data.
  97  *                      Added defines for ProductID Product field
  98  *                      (MPI2_FW_HEADER_PID_).
  99  *                      Modified values for SAS ProductID Family
 100  *                      (MPI2_FW_HEADER_PID_FAMILY_).
 101  *  02-10-10  02.00.14  Added SAS Quiesce Event structure and defines.
 102  *                      Added PowerManagementControl Request structures and
 103  *                      defines.
 104  *  05-12-10  02.00.15  Marked Task Set Full Event as obsolete.
 105  *                      Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define.
 106  *  11-10-10  02.00.16  Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC.
 107  *  02-23-11  02.00.17  Added SAS NOTIFY Primitive event, and added
 108  *                      SASNotifyPrimitiveMasks field to
 109  *                      MPI2_EVENT_NOTIFICATION_REQUEST.
 110  *                      Added Temperature Threshold Event.
 111  *                      Added Host Message Event.
 112  *                      Added Send Host Message request and reply.
 113  *  --------------------------------------------------------------------------
 114  */
 115
 116 #ifndef MPI2_IOC_H
 117 #define MPI2_IOC_H
 118
 119 /*****************************************************************************
 120 *
 121 *               IOC Messages
 122 *
 123 *****************************************************************************/
 124
 125 /****************************************************************************
 126 *  IOCInit message
 127 ****************************************************************************/
 128
 129 /* IOCInit Request message */
 130 typedef struct _MPI2_IOC_INIT_REQUEST
 131 {
 132     U8                      WhoInit;                        /* 0x00 */
 133     U8                      Reserved1;                      /* 0x01 */
 134     U8                      ChainOffset;                    /* 0x02 */
 135     U8                      Function;                       /* 0x03 */
 136     U16                     Reserved2;                      /* 0x04 */
 137     U8                      Reserved3;                      /* 0x06 */
 138     U8                      MsgFlags;                       /* 0x07 */
 139     U8                      VP_ID;                          /* 0x08 */
 140     U8                      VF_ID;                          /* 0x09 */
 141     U16                     Reserved4;                      /* 0x0A */
 142     U16                     MsgVersion;                     /* 0x0C */
 143     U16                     HeaderVersion;                  /* 0x0E */
 144     U32                     Reserved5;                      /* 0x10 */
 145     U16                     Reserved6;                      /* 0x14 */
 146     U8                      Reserved7;                      /* 0x16 */
 147     U8                      HostMSIxVectors;                /* 0x17 */
 148     U16                     Reserved8;                      /* 0x18 */
 149     U16                     SystemRequestFrameSize;         /* 0x1A */
 150     U16                     ReplyDescriptorPostQueueDepth;  /* 0x1C */
 151     U16                     ReplyFreeQueueDepth;            /* 0x1E */
 152     U32                     SenseBufferAddressHigh;         /* 0x20 */
 153     U32                     SystemReplyAddressHigh;         /* 0x24 */
 154     U64                     SystemRequestFrameBaseAddress;  /* 0x28 */
 155     U64                     ReplyDescriptorPostQueueAddress;/* 0x30 */
 156     U64                     ReplyFreeQueueAddress;          /* 0x38 */
 157     U64                     TimeStamp;                      /* 0x40 */
 158 } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST,
 159   Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t;
 160
 161 /* WhoInit values */
 162 #define MPI2_WHOINIT_NOT_INITIALIZED            (0x00)
 163 #define MPI2_WHOINIT_SYSTEM_BIOS                (0x01)
 164 #define MPI2_WHOINIT_ROM_BIOS                   (0x02)
 165 #define MPI2_WHOINIT_PCI_PEER                   (0x03)
 166 #define MPI2_WHOINIT_HOST_DRIVER                (0x04)
 167 #define MPI2_WHOINIT_MANUFACTURER               (0x05)
 168
 169 /* MsgVersion */
 170 #define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK      (0xFF00)
 171 #define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT     (8)
 172 #define MPI2_IOCINIT_MSGVERSION_MINOR_MASK      (0x00FF)
 173 #define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT     (0)
 174
 175 /* HeaderVersion */
 176 #define MPI2_IOCINIT_HDRVERSION_UNIT_MASK       (0xFF00)
 177 #define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT      (8)
 178 #define MPI2_IOCINIT_HDRVERSION_DEV_MASK        (0x00FF)
 179 #define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT       (0)
 180
 181 /* minimum depth for the Reply Descriptor Post Queue */
 182 #define MPI2_RDPQ_DEPTH_MIN                     (16)
 183
 184
 185 /* IOCInit Reply message */
 186 typedef struct _MPI2_IOC_INIT_REPLY
 187 {
 188     U8                      WhoInit;                        /* 0x00 */
 189     U8                      Reserved1;                      /* 0x01 */
 190     U8                      MsgLength;                      /* 0x02 */
 191     U8                      Function;                       /* 0x03 */
 192     U16                     Reserved2;                      /* 0x04 */
 193     U8                      Reserved3;                      /* 0x06 */
 194     U8                      MsgFlags;                       /* 0x07 */
 195     U8                      VP_ID;                          /* 0x08 */
 196     U8                      VF_ID;                          /* 0x09 */
 197     U16                     Reserved4;                      /* 0x0A */
 198     U16                     Reserved5;                      /* 0x0C */
 199     U16                     IOCStatus;                      /* 0x0E */
 200     U32                     IOCLogInfo;                     /* 0x10 */
 201 } MPI2_IOC_INIT_REPLY, MPI2_POINTER PTR_MPI2_IOC_INIT_REPLY,
 202   Mpi2IOCInitReply_t, MPI2_POINTER pMpi2IOCInitReply_t;
 203
 204
 205 /****************************************************************************
 206 *  IOCFacts message
 207 ****************************************************************************/
 208
 209 /* IOCFacts Request message */
 210 typedef struct _MPI2_IOC_FACTS_REQUEST
 211 {
 212     U16                     Reserved1;                      /* 0x00 */
 213     U8                      ChainOffset;                    /* 0x02 */
 214     U8                      Function;                       /* 0x03 */
 215     U16                     Reserved2;                      /* 0x04 */
 216     U8                      Reserved3;                      /* 0x06 */
 217     U8                      MsgFlags;                       /* 0x07 */
 218     U8                      VP_ID;                          /* 0x08 */
 219     U8                      VF_ID;                          /* 0x09 */
 220     U16                     Reserved4;                      /* 0x0A */
 221 } MPI2_IOC_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_IOC_FACTS_REQUEST,
 222   Mpi2IOCFactsRequest_t, MPI2_POINTER pMpi2IOCFactsRequest_t;
 223
 224
 225 /* IOCFacts Reply message */
 226 typedef struct _MPI2_IOC_FACTS_REPLY
 227 {
 228     U16                     MsgVersion;                     /* 0x00 */
 229     U8                      MsgLength;                      /* 0x02 */
 230     U8                      Function;                       /* 0x03 */
 231     U16                     HeaderVersion;                  /* 0x04 */
 232     U8                      IOCNumber;                      /* 0x06 */
 233     U8                      MsgFlags;                       /* 0x07 */
 234     U8                      VP_ID;                          /* 0x08 */
 235     U8                      VF_ID;                          /* 0x09 */
 236     U16                     Reserved1;                      /* 0x0A */
 237     U16                     IOCExceptions;                  /* 0x0C */
 238     U16                     IOCStatus;                      /* 0x0E */
 239     U32                     IOCLogInfo;                     /* 0x10 */
 240     U8                      MaxChainDepth;                  /* 0x14 */
 241     U8                      WhoInit;                        /* 0x15 */
 242     U8                      NumberOfPorts;                  /* 0x16 */
 243     U8                      MaxMSIxVectors;                 /* 0x17 */
 244     U16                     RequestCredit;                  /* 0x18 */
 245     U16                     ProductID;                      /* 0x1A */
 246     U32                     IOCCapabilities;                /* 0x1C */
 247     MPI2_VERSION_UNION      FWVersion;                      /* 0x20 */
 248     U16                     IOCRequestFrameSize;            /* 0x24 */
 249     U16                     Reserved3;                      /* 0x26 */
 250     U16                     MaxInitiators;                  /* 0x28 */
 251     U16                     MaxTargets;                     /* 0x2A */
 252     U16                     MaxSasExpanders;                /* 0x2C */
 253     U16                     MaxEnclosures;                  /* 0x2E */
 254     U16                     ProtocolFlags;                  /* 0x30 */
 255     U16                     HighPriorityCredit;             /* 0x32 */
 256     U16                     MaxReplyDescriptorPostQueueDepth; /* 0x34 */
 257     U8                      ReplyFrameSize;                 /* 0x36 */
 258     U8                      MaxVolumes;                     /* 0x37 */
 259     U16                     MaxDevHandle;                   /* 0x38 */
 260     U16                     MaxPersistentEntries;           /* 0x3A */
 261     U16                     MinDevHandle;                   /* 0x3C */
 262     U16                     Reserved4;                      /* 0x3E */
 263 } MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY,
 264   Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t;
 265
 266 /* MsgVersion */
 267 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK             (0xFF00)
 268 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT            (8)
 269 #define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK             (0x00FF)
 270 #define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT            (0)
 271
 272 /* HeaderVersion */
 273 #define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK              (0xFF00)
 274 #define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT             (8)
 275 #define MPI2_IOCFACTS_HDRVERSION_DEV_MASK               (0x00FF)
 276 #define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT              (0)
 277
 278 /* IOCExceptions */
 279 #define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX      (0x0100)
 280
 281 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK              (0x00E0)
 282 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD              (0x0000)
 283 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP            (0x0020)
 284 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED          (0x0040)
 285 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP    (0x0060)
 286
 287 #define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED       (0x0010)
 288 #define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL     (0x0008)
 289 #define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL           (0x0004)
 290 #define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID        (0x0002)
 291 #define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL       (0x0001)
 292
 293 /* defines for WhoInit field are after the IOCInit Request */
 294
 295 /* ProductID field uses MPI2_FW_HEADER_PID_ */
 296
 297 /* IOCCapabilities */
 298 #define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY   (0x00010000)
 299 #define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX            (0x00008000)
 300 #define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR       (0x00004000)
 301 #define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY           (0x00002000)
 302 #define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID        (0x00001000)
 303 #define MPI2_IOCFACTS_CAPABILITY_TLR                    (0x00000800)
 304 #define MPI2_IOCFACTS_CAPABILITY_MULTICAST              (0x00000100)
 305 #define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET   (0x00000080)
 306 #define MPI2_IOCFACTS_CAPABILITY_EEDP                   (0x00000040)
 307 #define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER        (0x00000020)
 308 #define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER        (0x00000010)
 309 #define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER      (0x00000008)
 310 #define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
 311
 312 /* ProtocolFlags */
 313 #define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET              (0x0001)
 314 #define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR           (0x0002)
 315
 316
 317 /****************************************************************************
 318 *  PortFacts message
 319 ****************************************************************************/
 320
 321 /* PortFacts Request message */
 322 typedef struct _MPI2_PORT_FACTS_REQUEST
 323 {
 324     U16                     Reserved1;                      /* 0x00 */
 325     U8                      ChainOffset;                    /* 0x02 */
 326     U8                      Function;                       /* 0x03 */
 327     U16                     Reserved2;                      /* 0x04 */
 328     U8                      PortNumber;                     /* 0x06 */
 329     U8                      MsgFlags;                       /* 0x07 */
 330     U8                      VP_ID;                          /* 0x08 */
 331     U8                      VF_ID;                          /* 0x09 */
 332     U16                     Reserved3;                      /* 0x0A */
 333 } MPI2_PORT_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_PORT_FACTS_REQUEST,
 334   Mpi2PortFactsRequest_t, MPI2_POINTER pMpi2PortFactsRequest_t;
 335
 336 /* PortFacts Reply message */
 337 typedef struct _MPI2_PORT_FACTS_REPLY
 338 {
 339     U16                     Reserved1;                      /* 0x00 */
 340     U8                      MsgLength;                      /* 0x02 */
 341     U8                      Function;                       /* 0x03 */
 342     U16                     Reserved2;                      /* 0x04 */
 343     U8                      PortNumber;                     /* 0x06 */
 344     U8                      MsgFlags;                       /* 0x07 */
 345     U8                      VP_ID;                          /* 0x08 */
 346     U8                      VF_ID;                          /* 0x09 */
 347     U16                     Reserved3;                      /* 0x0A */
 348     U16                     Reserved4;                      /* 0x0C */
 349     U16                     IOCStatus;                      /* 0x0E */
 350     U32                     IOCLogInfo;                     /* 0x10 */
 351     U8                      Reserved5;                      /* 0x14 */
 352     U8                      PortType;                       /* 0x15 */
 353     U16                     Reserved6;                      /* 0x16 */
 354     U16                     MaxPostedCmdBuffers;            /* 0x18 */
 355     U16                     Reserved7;                      /* 0x1A */
 356 } MPI2_PORT_FACTS_REPLY, MPI2_POINTER PTR_MPI2_PORT_FACTS_REPLY,
 357   Mpi2PortFactsReply_t, MPI2_POINTER pMpi2PortFactsReply_t;
 358
 359 /* PortType values */
 360 #define MPI2_PORTFACTS_PORTTYPE_INACTIVE            (0x00)
 361 #define MPI2_PORTFACTS_PORTTYPE_FC                  (0x10)
 362 #define MPI2_PORTFACTS_PORTTYPE_ISCSI               (0x20)
 363 #define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL        (0x30)
 364 #define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL         (0x31)
 365
 366
 367 /****************************************************************************
 368 *  PortEnable message
 369 ****************************************************************************/
 370
 371 /* PortEnable Request message */
 372 typedef struct _MPI2_PORT_ENABLE_REQUEST
 373 {
 374     U16                     Reserved1;                      /* 0x00 */
 375     U8                      ChainOffset;                    /* 0x02 */
 376     U8                      Function;                       /* 0x03 */
 377     U8                      Reserved2;                      /* 0x04 */
 378     U8                      PortFlags;                      /* 0x05 */
 379     U8                      Reserved3;                      /* 0x06 */
 380     U8                      MsgFlags;                       /* 0x07 */
 381     U8                      VP_ID;                          /* 0x08 */
 382     U8                      VF_ID;                          /* 0x09 */
 383     U16                     Reserved4;                      /* 0x0A */
 384 } MPI2_PORT_ENABLE_REQUEST, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REQUEST,
 385   Mpi2PortEnableRequest_t, MPI2_POINTER pMpi2PortEnableRequest_t;
 386
 387
 388 /* PortEnable Reply message */
 389 typedef struct _MPI2_PORT_ENABLE_REPLY
 390 {
 391     U16                     Reserved1;                      /* 0x00 */
 392     U8                      MsgLength;                      /* 0x02 */
 393     U8                      Function;                       /* 0x03 */
 394     U8                      Reserved2;                      /* 0x04 */
 395     U8                      PortFlags;                      /* 0x05 */
 396     U8                      Reserved3;                      /* 0x06 */
 397     U8                      MsgFlags;                       /* 0x07 */
 398     U8                      VP_ID;                          /* 0x08 */
 399     U8                      VF_ID;                          /* 0x09 */
 400     U16                     Reserved4;                      /* 0x0A */
 401     U16                     Reserved5;                      /* 0x0C */
 402     U16                     IOCStatus;                      /* 0x0E */
 403     U32                     IOCLogInfo;                     /* 0x10 */
 404 } MPI2_PORT_ENABLE_REPLY, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REPLY,
 405   Mpi2PortEnableReply_t, MPI2_POINTER pMpi2PortEnableReply_t;
 406
 407
 408 /****************************************************************************
 409 *  EventNotification message
 410 ****************************************************************************/
 411
 412 /* EventNotification Request message */
 413 #define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS           (4)
 414
 415 typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST
 416 {
 417     U16                     Reserved1;                      /* 0x00 */
 418     U8                      ChainOffset;                    /* 0x02 */
 419     U8                      Function;                       /* 0x03 */
 420     U16                     Reserved2;                      /* 0x04 */
 421     U8                      Reserved3;                      /* 0x06 */
 422     U8                      MsgFlags;                       /* 0x07 */
 423     U8                      VP_ID;                          /* 0x08 */
 424     U8                      VF_ID;                          /* 0x09 */
 425     U16                     Reserved4;                      /* 0x0A */
 426     U32                     Reserved5;                      /* 0x0C */
 427     U32                     Reserved6;                      /* 0x10 */
 428     U32                     EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];/* 0x14 */
 429     U16                     SASBroadcastPrimitiveMasks;     /* 0x24 */
 430          U16                     SASNotifyPrimitiveMasks;        /* 0x26 */
 431     U32                     Reserved8;                      /* 0x28 */
 432 } MPI2_EVENT_NOTIFICATION_REQUEST,
 433   MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REQUEST,
 434   Mpi2EventNotificationRequest_t, MPI2_POINTER pMpi2EventNotificationRequest_t;
 435
 436
 437 /* EventNotification Reply message */
 438 typedef struct _MPI2_EVENT_NOTIFICATION_REPLY
 439 {
 440     U16                     EventDataLength;                /* 0x00 */
 441     U8                      MsgLength;                      /* 0x02 */
 442     U8                      Function;                       /* 0x03 */
 443     U16                     Reserved1;                      /* 0x04 */
 444     U8                      AckRequired;                    /* 0x06 */
 445     U8                      MsgFlags;                       /* 0x07 */
 446     U8                      VP_ID;                          /* 0x08 */
 447     U8                      VF_ID;                          /* 0x09 */
 448     U16                     Reserved2;                      /* 0x0A */
 449     U16                     Reserved3;                      /* 0x0C */
 450     U16                     IOCStatus;                      /* 0x0E */
 451     U32                     IOCLogInfo;                     /* 0x10 */
 452     U16                     Event;                          /* 0x14 */
 453     U16                     Reserved4;                      /* 0x16 */
 454     U32                     EventContext;                   /* 0x18 */
 455     U32                     EventData[1];                   /* 0x1C */
 456 } MPI2_EVENT_NOTIFICATION_REPLY, MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REPLY,
 457   Mpi2EventNotificationReply_t, MPI2_POINTER pMpi2EventNotificationReply_t;
 458
 459 /* AckRequired */
 460 #define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED    (0x00)
 461 #define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED        (0x01)
 462
 463 /* Event */
 464 #define MPI2_EVENT_LOG_DATA                         (0x0001)
 465 #define MPI2_EVENT_STATE_CHANGE                     (0x0002)
 466 #define MPI2_EVENT_HARD_RESET_RECEIVED              (0x0005)
 467 #define MPI2_EVENT_EVENT_CHANGE                     (0x000A)
 468 #define MPI2_EVENT_TASK_SET_FULL                    (0x000E) /* obsolete */
 469 #define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE         (0x000F)
 470 #define MPI2_EVENT_IR_OPERATION_STATUS              (0x0014)
 471 #define MPI2_EVENT_SAS_DISCOVERY                    (0x0016)
 472 #define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE          (0x0017)
 473 #define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE    (0x0018)
 474 #define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW          (0x0019)
 475 #define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST         (0x001C)
 476 #define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE    (0x001D)
 477 #define MPI2_EVENT_IR_VOLUME                        (0x001E)
 478 #define MPI2_EVENT_IR_PHYSICAL_DISK                 (0x001F)
 479 #define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST     (0x0020)
 480 #define MPI2_EVENT_LOG_ENTRY_ADDED                  (0x0021)
 481 #define MPI2_EVENT_SAS_PHY_COUNTER                  (0x0022)
 482 #define MPI2_EVENT_GPIO_INTERRUPT                   (0x0023)
 483 #define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY         (0x0024)
 484 #define MPI2_EVENT_SAS_QUIESCE                      (0x0025)
 485 #define MPI2_EVENT_SAS_NOTIFY_PRIMITIVE             (0x0026)
 486 #define MPI2_EVENT_TEMP_THRESHOLD                   (0x0027)
 487 #define MPI2_EVENT_HOST_MESSAGE                     (0x0028)
 488
 489
 490 /* Log Entry Added Event data */
 491
 492 /* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */
 493 #define MPI2_EVENT_DATA_LOG_DATA_LENGTH             (0x1C)
 494
 495 typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED
 496 {
 497     U64         TimeStamp;                          /* 0x00 */
 498     U32         Reserved1;                          /* 0x08 */
 499     U16         LogSequence;                        /* 0x0C */
 500     U16         LogEntryQualifier;                  /* 0x0E */
 501     U8          VP_ID;                              /* 0x10 */
 502     U8          VF_ID;                              /* 0x11 */
 503     U16         Reserved2;                          /* 0x12 */
 504     U8          LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];/* 0x14 */
 505 } MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
 506   MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
 507   Mpi2EventDataLogEntryAdded_t, MPI2_POINTER pMpi2EventDataLogEntryAdded_t;
 508
 509 /* GPIO Interrupt Event data */
 510
 511 typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT {
 512     U8          GPIONum;                            /* 0x00 */
 513     U8          Reserved1;                          /* 0x01 */
 514     U16         Reserved2;                          /* 0x02 */
 515 } MPI2_EVENT_DATA_GPIO_INTERRUPT,
 516   MPI2_POINTER PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT,
 517   Mpi2EventDataGpioInterrupt_t, MPI2_POINTER pMpi2EventDataGpioInterrupt_t;
 518
 519 /* Temperature Threshold Event data */
 520
 521 typedef struct _MPI2_EVENT_DATA_TEMPERATURE {
 522         U16         Status;                             /* 0x00 */
 523         U8          SensorNum;                          /* 0x02 */
 524         U8          Reserved1;                          /* 0x03 */
 525         U16         CurrentTemperature;                 /* 0x04 */
 526         U16         Reserved2;                          /* 0x06 */
 527         U32         Reserved3;                          /* 0x08 */
 528         U32         Reserved4;                          /* 0x0C */
 529 } MPI2_EVENT_DATA_TEMPERATURE,
 530 MPI2_POINTER PTR_MPI2_EVENT_DATA_TEMPERATURE,
 531 Mpi2EventDataTemperature_t, MPI2_POINTER pMpi2EventDataTemperature_t;
 532
 533 /* Temperature Threshold Event data Status bits */
 534 #define MPI2_EVENT_TEMPERATURE3_EXCEEDED            (0x0008)
 535 #define MPI2_EVENT_TEMPERATURE2_EXCEEDED            (0x0004)
 536 #define MPI2_EVENT_TEMPERATURE1_EXCEEDED            (0x0002)
 537 #define MPI2_EVENT_TEMPERATURE0_EXCEEDED            (0x0001)
 538
 539
 540 /* Host Message Event data */
 541
 542 typedef struct _MPI2_EVENT_DATA_HOST_MESSAGE {
 543         U8          SourceVF_ID;                        /* 0x00 */
 544         U8          Reserved1;                          /* 0x01 */
 545         U16         Reserved2;                          /* 0x02 */
 546         U32         Reserved3;                          /* 0x04 */
 547         U32         HostData[1];                        /* 0x08 */
 548 } MPI2_EVENT_DATA_HOST_MESSAGE, MPI2_POINTER PTR_MPI2_EVENT_DATA_HOST_MESSAGE,
 549 Mpi2EventDataHostMessage_t, MPI2_POINTER pMpi2EventDataHostMessage_t;
 550
 551
 552 /* Hard Reset Received Event data */
 553
 554 typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED
 555 {
 556     U8                      Reserved1;                      /* 0x00 */
 557     U8                      Port;                           /* 0x01 */
 558     U16                     Reserved2;                      /* 0x02 */
 559 } MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
 560   MPI2_POINTER PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
 561   Mpi2EventDataHardResetReceived_t,
 562   MPI2_POINTER pMpi2EventDataHardResetReceived_t;
 563
 564 /* Task Set Full Event data */
 565 /*   this event is obsolete */
 566
 567 typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL
 568 {
 569     U16                     DevHandle;                      /* 0x00 */
 570     U16                     CurrentDepth;                   /* 0x02 */
 571 } MPI2_EVENT_DATA_TASK_SET_FULL, MPI2_POINTER PTR_MPI2_EVENT_DATA_TASK_SET_FULL,
 572   Mpi2EventDataTaskSetFull_t, MPI2_POINTER pMpi2EventDataTaskSetFull_t;
 573
 574
 575 /* SAS Device Status Change Event data */
 576
 577 typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE
 578 {
 579     U16                     TaskTag;                        /* 0x00 */
 580     U8                      ReasonCode;                     /* 0x02 */
 581     U8                      Reserved1;                      /* 0x03 */
 582     U8                      ASC;                            /* 0x04 */
 583     U8                      ASCQ;                           /* 0x05 */
 584     U16                     DevHandle;                      /* 0x06 */
 585     U32                     Reserved2;                      /* 0x08 */
 586     U64                     SASAddress;                     /* 0x0C */
 587     U8                      LUN[8];                         /* 0x14 */
 588 } MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
 589   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
 590   Mpi2EventDataSasDeviceStatusChange_t,
 591   MPI2_POINTER pMpi2EventDataSasDeviceStatusChange_t;
 592
 593 /* SAS Device Status Change Event data ReasonCode values */
 594 #define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA                           (0x05)
 595 #define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED                          (0x07)
 596 #define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET                (0x08)
 597 #define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL                  (0x09)
 598 #define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL              (0x0A)
 599 #define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL              (0x0B)
 600 #define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL                  (0x0C)
 601 #define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION                   (0x0D)
 602 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET               (0x0E)
 603 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL              (0x0F)
 604 #define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE                    (0x10)
 605 #define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY       (0x11)
 606 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY   (0x12)
 607
 608
 609 /* Integrated RAID Operation Status Event data */
 610
 611 typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS
 612 {
 613     U16                     VolDevHandle;               /* 0x00 */
 614     U16                     Reserved1;                  /* 0x02 */
 615     U8                      RAIDOperation;              /* 0x04 */
 616     U8                      PercentComplete;            /* 0x05 */
 617     U16                     Reserved2;                  /* 0x06 */
 618     U32                     Resereved3;                 /* 0x08 */
 619 } MPI2_EVENT_DATA_IR_OPERATION_STATUS,
 620   MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS,
 621   Mpi2EventDataIrOperationStatus_t,
 622   MPI2_POINTER pMpi2EventDataIrOperationStatus_t;
 623
 624 /* Integrated RAID Operation Status Event data RAIDOperation values */
 625 #define MPI2_EVENT_IR_RAIDOP_RESYNC                     (0x00)
 626 #define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION       (0x01)
 627 #define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK          (0x02)
 628 #define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT            (0x03)
 629 #define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT       (0x04)
 630
 631
 632 /* Integrated RAID Volume Event data */
 633
 634 typedef struct _MPI2_EVENT_DATA_IR_VOLUME
 635 {
 636     U16                     VolDevHandle;               /* 0x00 */
 637     U8                      ReasonCode;                 /* 0x02 */
 638     U8                      Reserved1;                  /* 0x03 */
 639     U32                     NewValue;                   /* 0x04 */
 640     U32                     PreviousValue;              /* 0x08 */
 641 } MPI2_EVENT_DATA_IR_VOLUME, MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_VOLUME,
 642   Mpi2EventDataIrVolume_t, MPI2_POINTER pMpi2EventDataIrVolume_t;
 643
 644 /* Integrated RAID Volume Event data ReasonCode values */
 645 #define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED        (0x01)
 646 #define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED    (0x02)
 647 #define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED           (0x03)
 648
 649
 650 /* Integrated RAID Physical Disk Event data */
 651
 652 typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK
 653 {
 654     U16                     Reserved1;                  /* 0x00 */
 655     U8                      ReasonCode;                 /* 0x02 */
 656     U8                      PhysDiskNum;                /* 0x03 */
 657     U16                     PhysDiskDevHandle;          /* 0x04 */
 658     U16                     Reserved2;                  /* 0x06 */
 659     U16                     Slot;                       /* 0x08 */
 660     U16                     EnclosureHandle;            /* 0x0A */
 661     U32                     NewValue;                   /* 0x0C */
 662     U32                     PreviousValue;              /* 0x10 */
 663 } MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
 664   MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
 665   Mpi2EventDataIrPhysicalDisk_t, MPI2_POINTER pMpi2EventDataIrPhysicalDisk_t;
 666
 667 /* Integrated RAID Physical Disk Event data ReasonCode values */
 668 #define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED      (0x01)
 669 #define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED  (0x02)
 670 #define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED         (0x03)
 671
 672
 673 /* Integrated RAID Configuration Change List Event data */
 674
 675 /*
 676  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 677  * one and check NumElements at runtime.
 678  */
 679 #ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT
 680 #define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT          (1)
 681 #endif
 682
 683 typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT
 684 {
 685     U16                     ElementFlags;               /* 0x00 */
 686     U16                     VolDevHandle;               /* 0x02 */
 687     U8                      ReasonCode;                 /* 0x04 */
 688     U8                      PhysDiskNum;                /* 0x05 */
 689     U16                     PhysDiskDevHandle;          /* 0x06 */
 690 } MPI2_EVENT_IR_CONFIG_ELEMENT, MPI2_POINTER PTR_MPI2_EVENT_IR_CONFIG_ELEMENT,
 691   Mpi2EventIrConfigElement_t, MPI2_POINTER pMpi2EventIrConfigElement_t;
 692
 693 /* IR Configuration Change List Event data ElementFlags values */
 694 #define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK   (0x000F)
 695 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT      (0x0000)
 696 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001)
 697 #define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT    (0x0002)
 698
 699 /* IR Configuration Change List Event data ReasonCode values */
 700 #define MPI2_EVENT_IR_CHANGE_RC_ADDED                   (0x01)
 701 #define MPI2_EVENT_IR_CHANGE_RC_REMOVED                 (0x02)
 702 #define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE               (0x03)
 703 #define MPI2_EVENT_IR_CHANGE_RC_HIDE                    (0x04)
 704 #define MPI2_EVENT_IR_CHANGE_RC_UNHIDE                  (0x05)
 705 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED          (0x06)
 706 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED          (0x07)
 707 #define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED              (0x08)
 708 #define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED              (0x09)
 709
 710 typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST
 711 {
 712     U8                              NumElements;        /* 0x00 */
 713     U8                              Reserved1;          /* 0x01 */
 714     U8                              Reserved2;          /* 0x02 */
 715     U8                              ConfigNum;          /* 0x03 */
 716     U32                             Flags;              /* 0x04 */
 717     MPI2_EVENT_IR_CONFIG_ELEMENT    ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT];    /* 0x08 */
 718 } MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
 719   MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
 720   Mpi2EventDataIrConfigChangeList_t,
 721   MPI2_POINTER pMpi2EventDataIrConfigChangeList_t;
 722
 723 /* IR Configuration Change List Event data Flags values */
 724 #define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG   (0x00000001)
 725
 726
 727 /* SAS Discovery Event data */
 728
 729 typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY
 730 {
 731     U8                      Flags;                      /* 0x00 */
 732     U8                      ReasonCode;                 /* 0x01 */
 733     U8                      PhysicalPort;               /* 0x02 */
 734     U8                      Reserved1;                  /* 0x03 */
 735     U32                     DiscoveryStatus;            /* 0x04 */
 736 } MPI2_EVENT_DATA_SAS_DISCOVERY,
 737   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DISCOVERY,
 738   Mpi2EventDataSasDiscovery_t, MPI2_POINTER pMpi2EventDataSasDiscovery_t;
 739
 740 /* SAS Discovery Event data Flags values */
 741 #define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE                   (0x02)
 742 #define MPI2_EVENT_SAS_DISC_IN_PROGRESS                     (0x01)
 743
 744 /* SAS Discovery Event data ReasonCode values */
 745 #define MPI2_EVENT_SAS_DISC_RC_STARTED                      (0x01)
 746 #define MPI2_EVENT_SAS_DISC_RC_COMPLETED                    (0x02)
 747
 748 /* SAS Discovery Event data DiscoveryStatus values */
 749 #define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED            (0x80000000)
 750 #define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED             (0x40000000)
 751 #define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED               (0x20000000)
 752 #define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED             (0x10000000)
 753 #define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR             (0x08000000)
 754 #define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE    (0x00008000)
 755 #define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE            (0x00004000)
 756 #define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN                (0x00002000)
 757 #define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK        (0x00001000)
 758 #define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE               (0x00000800)
 759 #define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK                       (0x00000400)
 760 #define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK                 (0x00000200)
 761 #define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR                    (0x00000100)
 762 #define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED              (0x00000080)
 763 #define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST                  (0x00000040)
 764 #define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES                (0x00000020)
 765 #define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT                      (0x00000010)
 766 #define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS                   (0x00000004)
 767 #define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE             (0x00000002)
 768 #define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED                    (0x00000001)
 769
 770
 771 /* SAS Broadcast Primitive Event data */
 772
 773 typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE
 774 {
 775     U8                      PhyNum;                     /* 0x00 */
 776     U8                      Port;                       /* 0x01 */
 777     U8                      PortWidth;                  /* 0x02 */
 778     U8                      Primitive;                  /* 0x03 */
 779 } MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
 780   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
 781   Mpi2EventDataSasBroadcastPrimitive_t,
 782   MPI2_POINTER pMpi2EventDataSasBroadcastPrimitive_t;
 783
 784 /* defines for the Primitive field */
 785 #define MPI2_EVENT_PRIMITIVE_CHANGE                         (0x01)
 786 #define MPI2_EVENT_PRIMITIVE_SES                            (0x02)
 787 #define MPI2_EVENT_PRIMITIVE_EXPANDER                       (0x03)
 788 #define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT             (0x04)
 789 #define MPI2_EVENT_PRIMITIVE_RESERVED3                      (0x05)
 790 #define MPI2_EVENT_PRIMITIVE_RESERVED4                      (0x06)
 791 #define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED               (0x07)
 792 #define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED               (0x08)
 793
 794 /* SAS Notify Primitive Event data */
 795
 796 typedef struct _MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE {
 797         U8                      PhyNum;                     /* 0x00 */
 798         U8                      Port;                       /* 0x01 */
 799         U8                      Reserved1;                  /* 0x02 */
 800         U8                      Primitive;                  /* 0x03 */
 801 } MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
 802 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
 803 Mpi2EventDataSasNotifyPrimitive_t,
 804 MPI2_POINTER pMpi2EventDataSasNotifyPrimitive_t;
 805
 806 /* defines for the Primitive field */
 807 #define MPI2_EVENT_NOTIFY_ENABLE_SPINUP                     (0x01)
 808 #define MPI2_EVENT_NOTIFY_POWER_LOSS_EXPECTED               (0x02)
 809 #define MPI2_EVENT_NOTIFY_RESERVED1                         (0x03)
 810 #define MPI2_EVENT_NOTIFY_RESERVED2                         (0x04)
 811
 812
 813 /* SAS Initiator Device Status Change Event data */
 814
 815 typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE
 816 {
 817     U8                      ReasonCode;                 /* 0x00 */
 818     U8                      PhysicalPort;               /* 0x01 */
 819     U16                     DevHandle;                  /* 0x02 */
 820     U64                     SASAddress;                 /* 0x04 */
 821 } MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
 822   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
 823   Mpi2EventDataSasInitDevStatusChange_t,
 824   MPI2_POINTER pMpi2EventDataSasInitDevStatusChange_t;
 825
 826 /* SAS Initiator Device Status Change event ReasonCode values */
 827 #define MPI2_EVENT_SAS_INIT_RC_ADDED                (0x01)
 828 #define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING       (0x02)
 829
 830
 831 /* SAS Initiator Device Table Overflow Event data */
 832
 833 typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW
 834 {
 835     U16                     MaxInit;                    /* 0x00 */
 836     U16                     CurrentInit;                /* 0x02 */
 837     U64                     SASAddress;                 /* 0x04 */
 838 } MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
 839   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
 840   Mpi2EventDataSasInitTableOverflow_t,
 841   MPI2_POINTER pMpi2EventDataSasInitTableOverflow_t;
 842
 843
 844 /* SAS Topology Change List Event data */
 845
 846 /*
 847  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
 848  * one and check NumEntries at runtime.
 849  */
 850 #ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT
 851 #define MPI2_EVENT_SAS_TOPO_PHY_COUNT           (1)
 852 #endif
 853
 854 typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY
 855 {
 856     U16                     AttachedDevHandle;          /* 0x00 */
 857     U8                      LinkRate;                   /* 0x02 */
 858     U8                      PhyStatus;                  /* 0x03 */
 859 } MPI2_EVENT_SAS_TOPO_PHY_ENTRY, MPI2_POINTER PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY,
 860   Mpi2EventSasTopoPhyEntry_t, MPI2_POINTER pMpi2EventSasTopoPhyEntry_t;
 861
 862 typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST
 863 {
 864     U16                             EnclosureHandle;            /* 0x00 */
 865     U16                             ExpanderDevHandle;          /* 0x02 */
 866     U8                              NumPhys;                    /* 0x04 */
 867     U8                              Reserved1;                  /* 0x05 */
 868     U16                             Reserved2;                  /* 0x06 */
 869     U8                              NumEntries;                 /* 0x08 */
 870     U8                              StartPhyNum;                /* 0x09 */
 871     U8                              ExpStatus;                  /* 0x0A */
 872     U8                              PhysicalPort;               /* 0x0B */
 873     MPI2_EVENT_SAS_TOPO_PHY_ENTRY   PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C*/
 874 } MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
 875   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
 876   Mpi2EventDataSasTopologyChangeList_t,
 877   MPI2_POINTER pMpi2EventDataSasTopologyChangeList_t;
 878
 879 /* values for the ExpStatus field */
 880 #define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER                  (0x00)
 881 #define MPI2_EVENT_SAS_TOPO_ES_ADDED                        (0x01)
 882 #define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING               (0x02)
 883 #define MPI2_EVENT_SAS_TOPO_ES_RESPONDING                   (0x03)
 884 #define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING         (0x04)
 885
 886 /* defines for the LinkRate field */
 887 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK                 (0xF0)
 888 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT                (4)
 889 #define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK                    (0x0F)
 890 #define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT                   (0)
 891
 892 #define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE            (0x00)
 893 #define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED                 (0x01)
 894 #define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED           (0x02)
 895 #define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE            (0x03)
 896 #define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR                (0x04)
 897 #define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS        (0x05)
 898 #define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY              (0x06)
 899 #define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5                     (0x08)
 900 #define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0                     (0x09)
 901 #define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0                     (0x0A)
 902
 903 /* values for the PhyStatus field */
 904 #define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT                (0x80)
 905 #define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE             (0x10)
 906 /* values for the PhyStatus ReasonCode sub-field */
 907 #define MPI2_EVENT_SAS_TOPO_RC_MASK                         (0x0F)
 908 #define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED                   (0x01)
 909 #define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING          (0x02)
 910 #define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED                  (0x03)
 911 #define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE                    (0x04)
 912 #define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING         (0x05)
 913
 914
 915 /* SAS Enclosure Device Status Change Event data */
 916
 917 typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE
 918 {
 919     U16                     EnclosureHandle;            /* 0x00 */
 920     U8                      ReasonCode;                 /* 0x02 */
 921     U8                      PhysicalPort;               /* 0x03 */
 922     U64                     EnclosureLogicalID;         /* 0x04 */
 923     U16                     NumSlots;                   /* 0x0C */
 924     U16                     StartSlot;                  /* 0x0E */
 925     U32                     PhyBits;                    /* 0x10 */
 926 } MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
 927   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
 928   Mpi2EventDataSasEnclDevStatusChange_t,
 929   MPI2_POINTER pMpi2EventDataSasEnclDevStatusChange_t;
 930
 931 /* SAS Enclosure Device Status Change event ReasonCode values */
 932 #define MPI2_EVENT_SAS_ENCL_RC_ADDED                (0x01)
 933 #define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING       (0x02)
 934
 935
 936 /* SAS PHY Counter Event data */
 937
 938 typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER {
 939     U64         TimeStamp;          /* 0x00 */
 940     U32         Reserved1;          /* 0x08 */
 941     U8          PhyEventCode;       /* 0x0C */
 942     U8          PhyNum;             /* 0x0D */
 943     U16         Reserved2;          /* 0x0E */
 944     U32         PhyEventInfo;       /* 0x10 */
 945     U8          CounterType;        /* 0x14 */
 946     U8          ThresholdWindow;    /* 0x15 */
 947     U8          TimeUnits;          /* 0x16 */
 948     U8          Reserved3;          /* 0x17 */
 949     U32         EventThreshold;     /* 0x18 */
 950     U16         ThresholdFlags;     /* 0x1C */
 951     U16         Reserved4;          /* 0x1E */
 952 } MPI2_EVENT_DATA_SAS_PHY_COUNTER,
 953   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER,
 954   Mpi2EventDataSasPhyCounter_t, MPI2_POINTER pMpi2EventDataSasPhyCounter_t;
 955
 956 /* use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h for the
 957  * PhyEventCode field
 958  * use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h for the
 959  * CounterType field
 960  * use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h for the
 961  * TimeUnits field
 962  * use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h for the
 963  * ThresholdFlags field
 964  * */
 965
 966
 967 /* SAS Quiesce Event data */
 968
 969 typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE {
 970     U8                      ReasonCode;                 /* 0x00 */
 971     U8                      Reserved1;                  /* 0x01 */
 972     U16                     Reserved2;                  /* 0x02 */
 973     U32                     Reserved3;                  /* 0x04 */
 974 } MPI2_EVENT_DATA_SAS_QUIESCE,
 975   MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_QUIESCE,
 976   Mpi2EventDataSasQuiesce_t, MPI2_POINTER pMpi2EventDataSasQuiesce_t;
 977
 978 /* SAS Quiesce Event data ReasonCode values */
 979 #define MPI2_EVENT_SAS_QUIESCE_RC_STARTED                   (0x01)
 980 #define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED                 (0x02)
 981
 982
 983 /* Host Based Discovery Phy Event data */
 984
 985 typedef struct _MPI2_EVENT_HBD_PHY_SAS {
 986     U8          Flags;                      /* 0x00 */
 987     U8          NegotiatedLinkRate;         /* 0x01 */
 988     U8          PhyNum;                     /* 0x02 */
 989     U8          PhysicalPort;               /* 0x03 */
 990     U32         Reserved1;                  /* 0x04 */
 991     U8          InitialFrame[28];           /* 0x08 */
 992 } MPI2_EVENT_HBD_PHY_SAS, MPI2_POINTER PTR_MPI2_EVENT_HBD_PHY_SAS,
 993   Mpi2EventHbdPhySas_t, MPI2_POINTER pMpi2EventHbdPhySas_t;
 994
 995 /* values for the Flags field */
 996 #define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID        (0x02)
 997 #define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME         (0x01)
 998
 999 /* use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h for
1000  * the NegotiatedLinkRate field */
1001
1002 typedef union _MPI2_EVENT_HBD_DESCRIPTOR {
1003     MPI2_EVENT_HBD_PHY_SAS      Sas;
1004 } MPI2_EVENT_HBD_DESCRIPTOR, MPI2_POINTER PTR_MPI2_EVENT_HBD_DESCRIPTOR,
1005   Mpi2EventHbdDescriptor_t, MPI2_POINTER pMpi2EventHbdDescriptor_t;
1006
1007 typedef struct _MPI2_EVENT_DATA_HBD_PHY {
1008     U8                          DescriptorType;     /* 0x00 */
1009     U8                          Reserved1;          /* 0x01 */
1010     U16                         Reserved2;          /* 0x02 */
1011     U32                         Reserved3;          /* 0x04 */
1012     MPI2_EVENT_HBD_DESCRIPTOR   Descriptor;         /* 0x08 */
1013 } MPI2_EVENT_DATA_HBD_PHY, MPI2_POINTER PTR_MPI2_EVENT_DATA_HBD_PHY,
1014   Mpi2EventDataHbdPhy_t, MPI2_POINTER pMpi2EventDataMpi2EventDataHbdPhy_t;
1015
1016 /* values for the DescriptorType field */
1017 #define MPI2_EVENT_HBD_DT_SAS               (0x01)
1018
1019
1020
1021 /****************************************************************************
1022 *  EventAck message
1023 ****************************************************************************/
1024
1025 /* EventAck Request message */
1026 typedef struct _MPI2_EVENT_ACK_REQUEST
1027 {
1028     U16                     Reserved1;                      /* 0x00 */
1029     U8                      ChainOffset;                    /* 0x02 */
1030     U8                      Function;                       /* 0x03 */
1031     U16                     Reserved2;                      /* 0x04 */
1032     U8                      Reserved3;                      /* 0x06 */
1033     U8                      MsgFlags;                       /* 0x07 */
1034     U8                      VP_ID;                          /* 0x08 */
1035     U8                      VF_ID;                          /* 0x09 */
1036     U16                     Reserved4;                      /* 0x0A */
1037     U16                     Event;                          /* 0x0C */
1038     U16                     Reserved5;                      /* 0x0E */
1039     U32                     EventContext;                   /* 0x10 */
1040 } MPI2_EVENT_ACK_REQUEST, MPI2_POINTER PTR_MPI2_EVENT_ACK_REQUEST,
1041   Mpi2EventAckRequest_t, MPI2_POINTER pMpi2EventAckRequest_t;
1042
1043
1044 /* EventAck Reply message */
1045 typedef struct _MPI2_EVENT_ACK_REPLY
1046 {
1047     U16                     Reserved1;                      /* 0x00 */
1048     U8                      MsgLength;                      /* 0x02 */
1049     U8                      Function;                       /* 0x03 */
1050     U16                     Reserved2;                      /* 0x04 */
1051     U8                      Reserved3;                      /* 0x06 */
1052     U8                      MsgFlags;                       /* 0x07 */
1053     U8                      VP_ID;                          /* 0x08 */
1054     U8                      VF_ID;                          /* 0x09 */
1055     U16                     Reserved4;                      /* 0x0A */
1056     U16                     Reserved5;                      /* 0x0C */
1057     U16                     IOCStatus;                      /* 0x0E */
1058     U32                     IOCLogInfo;                     /* 0x10 */
1059 } MPI2_EVENT_ACK_REPLY, MPI2_POINTER PTR_MPI2_EVENT_ACK_REPLY,
1060   Mpi2EventAckReply_t, MPI2_POINTER pMpi2EventAckReply_t;
1061
1062
1063 /****************************************************************************
1064 *  SendHostMessage message
1065 ****************************************************************************/
1066
1067 /* SendHostMessage Request message */
1068 typedef struct _MPI2_SEND_HOST_MESSAGE_REQUEST {
1069         U16                     HostDataLength;                 /* 0x00 */
1070         U8                      ChainOffset;                    /* 0x02 */
1071         U8                      Function;                       /* 0x03 */
1072         U16                     Reserved1;                      /* 0x04 */
1073         U8                      Reserved2;                      /* 0x06 */
1074         U8                      MsgFlags;                       /* 0x07 */
1075         U8                      VP_ID;                          /* 0x08 */
1076         U8                      VF_ID;                          /* 0x09 */
1077         U16                     Reserved3;                      /* 0x0A */
1078         U8                      Reserved4;                      /* 0x0C */
1079         U8                      DestVF_ID;                      /* 0x0D */
1080         U16                     Reserved5;                      /* 0x0E */
1081         U32                     Reserved6;                      /* 0x10 */
1082         U32                     Reserved7;                      /* 0x14 */
1083         U32                     Reserved8;                      /* 0x18 */
1084         U32                     Reserved9;                      /* 0x1C */
1085         U32                     Reserved10;                     /* 0x20 */
1086         U32                     HostData[1];                    /* 0x24 */
1087 } MPI2_SEND_HOST_MESSAGE_REQUEST,
1088 MPI2_POINTER PTR_MPI2_SEND_HOST_MESSAGE_REQUEST,
1089 Mpi2SendHostMessageRequest_t, MPI2_POINTER pMpi2SendHostMessageRequest_t;
1090
1091
1092 /* SendHostMessage Reply message */
1093 typedef struct _MPI2_SEND_HOST_MESSAGE_REPLY {
1094         U16                     HostDataLength;                 /* 0x00 */
1095         U8                      MsgLength;                      /* 0x02 */
1096         U8                      Function;                       /* 0x03 */
1097         U16                     Reserved1;                      /* 0x04 */
1098         U8                      Reserved2;                      /* 0x06 */
1099         U8                      MsgFlags;                       /* 0x07 */
1100         U8                      VP_ID;                          /* 0x08 */
1101         U8                      VF_ID;                          /* 0x09 */
1102         U16                     Reserved3;                      /* 0x0A */
1103         U16                     Reserved4;                      /* 0x0C */
1104         U16                     IOCStatus;                      /* 0x0E */
1105         U32                     IOCLogInfo;                     /* 0x10 */
1106 } MPI2_SEND_HOST_MESSAGE_REPLY, MPI2_POINTER PTR_MPI2_SEND_HOST_MESSAGE_REPLY,
1107 Mpi2SendHostMessageReply_t, MPI2_POINTER pMpi2SendHostMessageReply_t;
1108
1109
1110 /****************************************************************************
1111 *  FWDownload message
1112 ****************************************************************************/
1113
1114 /* FWDownload Request message */
1115 typedef struct _MPI2_FW_DOWNLOAD_REQUEST
1116 {
1117     U8                      ImageType;                  /* 0x00 */
1118     U8                      Reserved1;                  /* 0x01 */
1119     U8                      ChainOffset;                /* 0x02 */
1120     U8                      Function;                   /* 0x03 */
1121     U16                     Reserved2;                  /* 0x04 */
1122     U8                      Reserved3;                  /* 0x06 */
1123     U8                      MsgFlags;                   /* 0x07 */
1124     U8                      VP_ID;                      /* 0x08 */
1125     U8                      VF_ID;                      /* 0x09 */
1126     U16                     Reserved4;                  /* 0x0A */
1127     U32                     TotalImageSize;             /* 0x0C */
1128     U32                     Reserved5;                  /* 0x10 */
1129     MPI2_MPI_SGE_UNION      SGL;                        /* 0x14 */
1130 } MPI2_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REQUEST,
1131   Mpi2FWDownloadRequest, MPI2_POINTER pMpi2FWDownloadRequest;
1132
1133 #define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT   (0x01)
1134
1135 #define MPI2_FW_DOWNLOAD_ITYPE_FW                   (0x01)
1136 #define MPI2_FW_DOWNLOAD_ITYPE_BIOS                 (0x02)
1137 #define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING        (0x06)
1138 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1             (0x07)
1139 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2             (0x08)
1140 #define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID             (0x09)
1141 #define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE             (0x0A)
1142 #define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK    (0x0B)
1143 #define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0)
1144
1145 /* FWDownload TransactionContext Element */
1146 typedef struct _MPI2_FW_DOWNLOAD_TCSGE
1147 {
1148     U8                      Reserved1;                  /* 0x00 */
1149     U8                      ContextSize;                /* 0x01 */
1150     U8                      DetailsLength;              /* 0x02 */
1151     U8                      Flags;                      /* 0x03 */
1152     U32                     Reserved2;                  /* 0x04 */
1153     U32                     ImageOffset;                /* 0x08 */
1154     U32                     ImageSize;                  /* 0x0C */
1155 } MPI2_FW_DOWNLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_TCSGE,
1156   Mpi2FWDownloadTCSGE_t, MPI2_POINTER pMpi2FWDownloadTCSGE_t;
1157
1158 /* FWDownload Reply message */
1159 typedef struct _MPI2_FW_DOWNLOAD_REPLY
1160 {
1161     U8                      ImageType;                  /* 0x00 */
1162     U8                      Reserved1;                  /* 0x01 */
1163     U8                      MsgLength;                  /* 0x02 */
1164     U8                      Function;                   /* 0x03 */
1165     U16                     Reserved2;                  /* 0x04 */
1166     U8                      Reserved3;                  /* 0x06 */
1167     U8                      MsgFlags;                   /* 0x07 */
1168     U8                      VP_ID;                      /* 0x08 */
1169     U8                      VF_ID;                      /* 0x09 */
1170     U16                     Reserved4;                  /* 0x0A */
1171     U16                     Reserved5;                  /* 0x0C */
1172     U16                     IOCStatus;                  /* 0x0E */
1173     U32                     IOCLogInfo;                 /* 0x10 */
1174 } MPI2_FW_DOWNLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REPLY,
1175   Mpi2FWDownloadReply_t, MPI2_POINTER pMpi2FWDownloadReply_t;
1176
1177
1178 /****************************************************************************
1179 *  FWUpload message
1180 ****************************************************************************/
1181
1182 /* FWUpload Request message */
1183 typedef struct _MPI2_FW_UPLOAD_REQUEST
1184 {
1185     U8                      ImageType;                  /* 0x00 */
1186     U8                      Reserved1;                  /* 0x01 */
1187     U8                      ChainOffset;                /* 0x02 */
1188     U8                      Function;                   /* 0x03 */
1189     U16                     Reserved2;                  /* 0x04 */
1190     U8                      Reserved3;                  /* 0x06 */
1191     U8                      MsgFlags;                   /* 0x07 */
1192     U8                      VP_ID;                      /* 0x08 */
1193     U8                      VF_ID;                      /* 0x09 */
1194     U16                     Reserved4;                  /* 0x0A */
1195     U32                     Reserved5;                  /* 0x0C */
1196     U32                     Reserved6;                  /* 0x10 */
1197     MPI2_MPI_SGE_UNION      SGL;                        /* 0x14 */
1198 } MPI2_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REQUEST,
1199   Mpi2FWUploadRequest_t, MPI2_POINTER pMpi2FWUploadRequest_t;
1200
1201 #define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT         (0x00)
1202 #define MPI2_FW_UPLOAD_ITYPE_FW_FLASH           (0x01)
1203 #define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH         (0x02)
1204 #define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP          (0x05)
1205 #define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING      (0x06)
1206 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_1           (0x07)
1207 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_2           (0x08)
1208 #define MPI2_FW_UPLOAD_ITYPE_MEGARAID           (0x09)
1209 #define MPI2_FW_UPLOAD_ITYPE_COMPLETE           (0x0A)
1210 #define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK  (0x0B)
1211
1212 typedef struct _MPI2_FW_UPLOAD_TCSGE
1213 {
1214     U8                      Reserved1;                  /* 0x00 */
1215     U8                      ContextSize;                /* 0x01 */
1216     U8                      DetailsLength;              /* 0x02 */
1217     U8                      Flags;                      /* 0x03 */
1218     U32                     Reserved2;                  /* 0x04 */
1219     U32                     ImageOffset;                /* 0x08 */
1220     U32                     ImageSize;                  /* 0x0C */
1221 } MPI2_FW_UPLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_UPLOAD_TCSGE,
1222   Mpi2FWUploadTCSGE_t, MPI2_POINTER pMpi2FWUploadTCSGE_t;
1223
1224 /* FWUpload Reply message */
1225 typedef struct _MPI2_FW_UPLOAD_REPLY
1226 {
1227     U8                      ImageType;                  /* 0x00 */
1228     U8                      Reserved1;                  /* 0x01 */
1229     U8                      MsgLength;                  /* 0x02 */
1230     U8                      Function;                   /* 0x03 */
1231     U16                     Reserved2;                  /* 0x04 */
1232     U8                      Reserved3;                  /* 0x06 */
1233     U8                      MsgFlags;                   /* 0x07 */
1234     U8                      VP_ID;                      /* 0x08 */
1235     U8                      VF_ID;                      /* 0x09 */
1236     U16                     Reserved4;                  /* 0x0A */
1237     U16                     Reserved5;                  /* 0x0C */
1238     U16                     IOCStatus;                  /* 0x0E */
1239     U32                     IOCLogInfo;                 /* 0x10 */
1240     U32                     ActualImageSize;            /* 0x14 */
1241 } MPI2_FW_UPLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REPLY,
1242   Mpi2FWUploadReply_t, MPI2_POINTER pMPi2FWUploadReply_t;
1243
1244
1245 /* FW Image Header */
1246 typedef struct _MPI2_FW_IMAGE_HEADER
1247 {
1248     U32                     Signature;                  /* 0x00 */
1249     U32                     Signature0;                 /* 0x04 */
1250     U32                     Signature1;                 /* 0x08 */
1251     U32                     Signature2;                 /* 0x0C */
1252     MPI2_VERSION_UNION      MPIVersion;                 /* 0x10 */
1253     MPI2_VERSION_UNION      FWVersion;                  /* 0x14 */
1254     MPI2_VERSION_UNION      NVDATAVersion;              /* 0x18 */
1255     MPI2_VERSION_UNION      PackageVersion;             /* 0x1C */
1256     U16                     VendorID;                   /* 0x20 */
1257     U16                     ProductID;                  /* 0x22 */
1258     U16                     ProtocolFlags;              /* 0x24 */
1259     U16                     Reserved26;                 /* 0x26 */
1260     U32                     IOCCapabilities;            /* 0x28 */
1261     U32                     ImageSize;                  /* 0x2C */
1262     U32                     NextImageHeaderOffset;      /* 0x30 */
1263     U32                     Checksum;                   /* 0x34 */
1264     U32                     Reserved38;                 /* 0x38 */
1265     U32                     Reserved3C;                 /* 0x3C */
1266     U32                     Reserved40;                 /* 0x40 */
1267     U32                     Reserved44;                 /* 0x44 */
1268     U32                     Reserved48;                 /* 0x48 */
1269     U32                     Reserved4C;                 /* 0x4C */
1270     U32                     Reserved50;                 /* 0x50 */
1271     U32                     Reserved54;                 /* 0x54 */
1272     U32                     Reserved58;                 /* 0x58 */
1273     U32                     Reserved5C;                 /* 0x5C */
1274     U32                     Reserved60;                 /* 0x60 */
1275     U32                     FirmwareVersionNameWhat;    /* 0x64 */
1276     U8                      FirmwareVersionName[32];    /* 0x68 */
1277     U32                     VendorNameWhat;             /* 0x88 */
1278     U8                      VendorName[32];             /* 0x8C */
1279     U32                     PackageNameWhat;            /* 0x88 */
1280     U8                      PackageName[32];            /* 0x8C */
1281     U32                     ReservedD0;                 /* 0xD0 */
1282     U32                     ReservedD4;                 /* 0xD4 */
1283     U32                     ReservedD8;                 /* 0xD8 */
1284     U32                     ReservedDC;                 /* 0xDC */
1285     U32                     ReservedE0;                 /* 0xE0 */
1286     U32                     ReservedE4;                 /* 0xE4 */
1287     U32                     ReservedE8;                 /* 0xE8 */
1288     U32                     ReservedEC;                 /* 0xEC */
1289     U32                     ReservedF0;                 /* 0xF0 */
1290     U32                     ReservedF4;                 /* 0xF4 */
1291     U32                     ReservedF8;                 /* 0xF8 */
1292     U32                     ReservedFC;                 /* 0xFC */
1293 } MPI2_FW_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_FW_IMAGE_HEADER,
1294   Mpi2FWImageHeader_t, MPI2_POINTER pMpi2FWImageHeader_t;
1295
1296 /* Signature field */
1297 #define MPI2_FW_HEADER_SIGNATURE_OFFSET         (0x00)
1298 #define MPI2_FW_HEADER_SIGNATURE_MASK           (0xFF000000)
1299 #define MPI2_FW_HEADER_SIGNATURE                (0xEA000000)
1300
1301 /* Signature0 field */
1302 #define MPI2_FW_HEADER_SIGNATURE0_OFFSET        (0x04)
1303 #define MPI2_FW_HEADER_SIGNATURE0               (0x5AFAA55A)
1304
1305 /* Signature1 field */
1306 #define MPI2_FW_HEADER_SIGNATURE1_OFFSET        (0x08)
1307 #define MPI2_FW_HEADER_SIGNATURE1               (0xA55AFAA5)
1308
1309 /* Signature2 field */
1310 #define MPI2_FW_HEADER_SIGNATURE2_OFFSET        (0x0C)
1311 #define MPI2_FW_HEADER_SIGNATURE2               (0x5AA55AFA)
1312
1313
1314 /* defines for using the ProductID field */
1315 #define MPI2_FW_HEADER_PID_TYPE_MASK            (0xF000)
1316 #define MPI2_FW_HEADER_PID_TYPE_SAS             (0x2000)
1317
1318 #define MPI2_FW_HEADER_PID_PROD_MASK                    (0x0F00)
1319 #define MPI2_FW_HEADER_PID_PROD_A                       (0x0000)
1320 #define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI   (0x0200)
1321 #define MPI2_FW_HEADER_PID_PROD_IR_SCSI                 (0x0700)
1322
1323
1324 #define MPI2_FW_HEADER_PID_FAMILY_MASK          (0x00FF)
1325 /* SAS */
1326 #define MPI2_FW_HEADER_PID_FAMILY_2108_SAS      (0x0013)
1327 #define MPI2_FW_HEADER_PID_FAMILY_2208_SAS      (0x0014)
1328
1329 /* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */
1330
1331 /* use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */
1332
1333
1334 #define MPI2_FW_HEADER_IMAGESIZE_OFFSET         (0x2C)
1335 #define MPI2_FW_HEADER_NEXTIMAGE_OFFSET         (0x30)
1336 #define MPI2_FW_HEADER_VERNMHWAT_OFFSET         (0x64)
1337
1338 #define MPI2_FW_HEADER_WHAT_SIGNATURE           (0x29232840)
1339
1340 #define MPI2_FW_HEADER_SIZE                     (0x100)
1341
1342
1343 /* Extended Image Header */
1344 typedef struct _MPI2_EXT_IMAGE_HEADER
1345
1346 {
1347     U8                      ImageType;                  /* 0x00 */
1348     U8                      Reserved1;                  /* 0x01 */
1349     U16                     Reserved2;                  /* 0x02 */
1350     U32                     Checksum;                   /* 0x04 */
1351     U32                     ImageSize;                  /* 0x08 */
1352     U32                     NextImageHeaderOffset;      /* 0x0C */
1353     U32                     PackageVersion;             /* 0x10 */
1354     U32                     Reserved3;                  /* 0x14 */
1355     U32                     Reserved4;                  /* 0x18 */
1356     U32                     Reserved5;                  /* 0x1C */
1357     U8                      IdentifyString[32];         /* 0x20 */
1358 } MPI2_EXT_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_EXT_IMAGE_HEADER,
1359   Mpi2ExtImageHeader_t, MPI2_POINTER pMpi2ExtImageHeader_t;
1360
1361 /* useful offsets */
1362 #define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET         (0x00)
1363 #define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET         (0x08)
1364 #define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET         (0x0C)
1365
1366 #define MPI2_EXT_IMAGE_HEADER_SIZE              (0x40)
1367
1368 /* defines for the ImageType field */
1369 #define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED         (0x00)
1370 #define MPI2_EXT_IMAGE_TYPE_FW                  (0x01)
1371 #define MPI2_EXT_IMAGE_TYPE_NVDATA              (0x03)
1372 #define MPI2_EXT_IMAGE_TYPE_BOOTLOADER          (0x04)
1373 #define MPI2_EXT_IMAGE_TYPE_INITIALIZATION      (0x05)
1374 #define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT        (0x06)
1375 #define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES   (0x07)
1376 #define MPI2_EXT_IMAGE_TYPE_MEGARAID            (0x08)
1377
1378 #define MPI2_EXT_IMAGE_TYPE_MAX                 (MPI2_EXT_IMAGE_TYPE_MEGARAID)
1379
1380
1381
1382 /* FLASH Layout Extended Image Data */
1383
1384 /*
1385  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1386  * one and check RegionsPerLayout at runtime.
1387  */
1388 #ifndef MPI2_FLASH_NUMBER_OF_REGIONS
1389 #define MPI2_FLASH_NUMBER_OF_REGIONS        (1)
1390 #endif
1391
1392 /*
1393  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1394  * one and check NumberOfLayouts at runtime.
1395  */
1396 #ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS
1397 #define MPI2_FLASH_NUMBER_OF_LAYOUTS        (1)
1398 #endif
1399
1400 typedef struct _MPI2_FLASH_REGION
1401 {
1402     U8                      RegionType;                 /* 0x00 */
1403     U8                      Reserved1;                  /* 0x01 */
1404     U16                     Reserved2;                  /* 0x02 */
1405     U32                     RegionOffset;               /* 0x04 */
1406     U32                     RegionSize;                 /* 0x08 */
1407     U32                     Reserved3;                  /* 0x0C */
1408 } MPI2_FLASH_REGION, MPI2_POINTER PTR_MPI2_FLASH_REGION,
1409   Mpi2FlashRegion_t, MPI2_POINTER pMpi2FlashRegion_t;
1410
1411 typedef struct _MPI2_FLASH_LAYOUT
1412 {
1413     U32                     FlashSize;                  /* 0x00 */
1414     U32                     Reserved1;                  /* 0x04 */
1415     U32                     Reserved2;                  /* 0x08 */
1416     U32                     Reserved3;                  /* 0x0C */
1417     MPI2_FLASH_REGION       Region[MPI2_FLASH_NUMBER_OF_REGIONS];/* 0x10 */
1418 } MPI2_FLASH_LAYOUT, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT,
1419   Mpi2FlashLayout_t, MPI2_POINTER pMpi2FlashLayout_t;
1420
1421 typedef struct _MPI2_FLASH_LAYOUT_DATA
1422 {
1423     U8                      ImageRevision;              /* 0x00 */
1424     U8                      Reserved1;                  /* 0x01 */
1425     U8                      SizeOfRegion;               /* 0x02 */
1426     U8                      Reserved2;                  /* 0x03 */
1427     U16                     NumberOfLayouts;            /* 0x04 */
1428     U16                     RegionsPerLayout;           /* 0x06 */
1429     U16                     MinimumSectorAlignment;     /* 0x08 */
1430     U16                     Reserved3;                  /* 0x0A */
1431     U32                     Reserved4;                  /* 0x0C */
1432     MPI2_FLASH_LAYOUT       Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS];/* 0x10 */
1433 } MPI2_FLASH_LAYOUT_DATA, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT_DATA,
1434   Mpi2FlashLayoutData_t, MPI2_POINTER pMpi2FlashLayoutData_t;
1435
1436 /* defines for the RegionType field */
1437 #define MPI2_FLASH_REGION_UNUSED                (0x00)
1438 #define MPI2_FLASH_REGION_FIRMWARE              (0x01)
1439 #define MPI2_FLASH_REGION_BIOS                  (0x02)
1440 #define MPI2_FLASH_REGION_NVDATA                (0x03)
1441 #define MPI2_FLASH_REGION_FIRMWARE_BACKUP       (0x05)
1442 #define MPI2_FLASH_REGION_MFG_INFORMATION       (0x06)
1443 #define MPI2_FLASH_REGION_CONFIG_1              (0x07)
1444 #define MPI2_FLASH_REGION_CONFIG_2              (0x08)
1445 #define MPI2_FLASH_REGION_MEGARAID              (0x09)
1446 #define MPI2_FLASH_REGION_INIT                  (0x0A)
1447
1448 /* ImageRevision */
1449 #define MPI2_FLASH_LAYOUT_IMAGE_REVISION        (0x00)
1450
1451
1452
1453 /* Supported Devices Extended Image Data */
1454
1455 /*
1456  * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1457  * one and check NumberOfDevices at runtime.
1458  */
1459 #ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES
1460 #define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES    (1)
1461 #endif
1462
1463 typedef struct _MPI2_SUPPORTED_DEVICE
1464 {
1465     U16                     DeviceID;                   /* 0x00 */
1466     U16                     VendorID;                   /* 0x02 */
1467     U16                     DeviceIDMask;               /* 0x04 */
1468     U16                     Reserved1;                  /* 0x06 */
1469     U8                      LowPCIRev;                  /* 0x08 */
1470     U8                      HighPCIRev;                 /* 0x09 */
1471     U16                     Reserved2;                  /* 0x0A */
1472     U32                     Reserved3;                  /* 0x0C */
1473 } MPI2_SUPPORTED_DEVICE, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICE,
1474   Mpi2SupportedDevice_t, MPI2_POINTER pMpi2SupportedDevice_t;
1475
1476 typedef struct _MPI2_SUPPORTED_DEVICES_DATA
1477 {
1478     U8                      ImageRevision;              /* 0x00 */
1479     U8                      Reserved1;                  /* 0x01 */
1480     U8                      NumberOfDevices;            /* 0x02 */
1481     U8                      Reserved2;                  /* 0x03 */
1482     U32                     Reserved3;                  /* 0x04 */
1483     MPI2_SUPPORTED_DEVICE   SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES]; /* 0x08 */
1484 } MPI2_SUPPORTED_DEVICES_DATA, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICES_DATA,
1485   Mpi2SupportedDevicesData_t, MPI2_POINTER pMpi2SupportedDevicesData_t;
1486
1487 /* ImageRevision */
1488 #define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION   (0x00)
1489
1490
1491 /* Init Extended Image Data */
1492
1493 typedef struct _MPI2_INIT_IMAGE_FOOTER
1494
1495 {
1496     U32                     BootFlags;                  /* 0x00 */
1497     U32                     ImageSize;                  /* 0x04 */
1498     U32                     Signature0;                 /* 0x08 */
1499     U32                     Signature1;                 /* 0x0C */
1500     U32                     Signature2;                 /* 0x10 */
1501     U32                     ResetVector;                /* 0x14 */
1502 } MPI2_INIT_IMAGE_FOOTER, MPI2_POINTER PTR_MPI2_INIT_IMAGE_FOOTER,
1503   Mpi2InitImageFooter_t, MPI2_POINTER pMpi2InitImageFooter_t;
1504
1505 /* defines for the BootFlags field */
1506 #define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET        (0x00)
1507
1508 /* defines for the ImageSize field */
1509 #define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET        (0x04)
1510
1511 /* defines for the Signature0 field */
1512 #define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET       (0x08)
1513 #define MPI2_INIT_IMAGE_SIGNATURE0              (0x5AA55AEA)
1514
1515 /* defines for the Signature1 field */
1516 #define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET       (0x0C)
1517 #define MPI2_INIT_IMAGE_SIGNATURE1              (0xA55AEAA5)
1518
1519 /* defines for the Signature2 field */
1520 #define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET       (0x10)
1521 #define MPI2_INIT_IMAGE_SIGNATURE2              (0x5AEAA55A)
1522
1523 /* Signature fields as individual bytes */
1524 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0        (0xEA)
1525 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1        (0x5A)
1526 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2        (0xA5)
1527 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3        (0x5A)
1528
1529 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4        (0xA5)
1530 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5        (0xEA)
1531 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6        (0x5A)
1532 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7        (0xA5)
1533
1534 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8        (0x5A)
1535 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9        (0xA5)
1536 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A        (0xEA)
1537 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B        (0x5A)
1538
1539 /* defines for the ResetVector field */
1540 #define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET      (0x14)
1541
1542
1543 /****************************************************************************
1544 *  PowerManagementControl message
1545 ****************************************************************************/
1546
1547 /* PowerManagementControl Request message */
1548 typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST {
1549     U8                      Feature;                    /* 0x00 */
1550     U8                      Reserved1;                  /* 0x01 */
1551     U8                      ChainOffset;                /* 0x02 */
1552     U8                      Function;                   /* 0x03 */
1553     U16                     Reserved2;                  /* 0x04 */
1554     U8                      Reserved3;                  /* 0x06 */
1555     U8                      MsgFlags;                   /* 0x07 */
1556     U8                      VP_ID;                      /* 0x08 */
1557     U8                      VF_ID;                      /* 0x09 */
1558     U16                     Reserved4;                  /* 0x0A */
1559     U8                      Parameter1;                 /* 0x0C */
1560     U8                      Parameter2;                 /* 0x0D */
1561     U8                      Parameter3;                 /* 0x0E */
1562     U8                      Parameter4;                 /* 0x0F */
1563     U32                     Reserved5;                  /* 0x10 */
1564     U32                     Reserved6;                  /* 0x14 */
1565 } MPI2_PWR_MGMT_CONTROL_REQUEST, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REQUEST,
1566   Mpi2PwrMgmtControlRequest_t, MPI2_POINTER pMpi2PwrMgmtControlRequest_t;
1567
1568 /* defines for the Feature field */
1569 #define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND       (0x01)
1570 #define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION   (0x02)
1571 #define MPI2_PM_CONTROL_FEATURE_PCIE_LINK               (0x03)
1572 #define MPI2_PM_CONTROL_FEATURE_IOC_SPEED               (0x04)
1573 #define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC    (0x80)
1574 #define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC    (0xFF)
1575
1576 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */
1577 /* Parameter1 contains a PHY number */
1578 /* Parameter2 indicates power condition action using these defines */
1579 #define MPI2_PM_CONTROL_PARAM2_PARTIAL                  (0x01)
1580 #define MPI2_PM_CONTROL_PARAM2_SLUMBER                  (0x02)
1581 #define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT            (0x03)
1582 /* Parameter3 and Parameter4 are reserved */
1583
1584 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION
1585  *  Feature */
1586 /* Parameter1 contains SAS port width modulation group number */
1587 /* Parameter2 indicates IOC action using these defines */
1588 #define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP        (0x01)
1589 #define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION        (0x02)
1590 #define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP     (0x03)
1591 /* Parameter3 indicates desired modulation level using these defines */
1592 #define MPI2_PM_CONTROL_PARAM3_25_PERCENT               (0x00)
1593 #define MPI2_PM_CONTROL_PARAM3_50_PERCENT               (0x01)
1594 #define MPI2_PM_CONTROL_PARAM3_75_PERCENT               (0x02)
1595 #define MPI2_PM_CONTROL_PARAM3_100_PERCENT              (0x03)
1596 /* Parameter4 is reserved */
1597
1598 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */
1599 /* Parameter1 indicates desired PCIe link speed using these defines */
1600 #define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS            (0x00)
1601 #define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS            (0x01)
1602 #define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS            (0x02)
1603 /* Parameter2 indicates desired PCIe link width using these defines */
1604 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X1                 (0x01)
1605 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X2                 (0x02)
1606 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X4                 (0x04)
1607 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X8                 (0x08)
1608 /* Parameter3 and Parameter4 are reserved */
1609
1610 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */
1611 /* Parameter1 indicates desired IOC hardware clock speed using these defines */
1612 #define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED           (0x01)
1613 #define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED           (0x02)
1614 #define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED        (0x04)
1615 #define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED         (0x08)
1616 /* Parameter2, Parameter3, and Parameter4 are reserved */
1617
1618
1619 /* PowerManagementControl Reply message */
1620 typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY {
1621     U8                      Feature;                    /* 0x00 */
1622     U8                      Reserved1;                  /* 0x01 */
1623     U8                      MsgLength;                  /* 0x02 */
1624     U8                      Function;                   /* 0x03 */
1625     U16                     Reserved2;                  /* 0x04 */
1626     U8                      Reserved3;                  /* 0x06 */
1627     U8                      MsgFlags;                   /* 0x07 */
1628     U8                      VP_ID;                      /* 0x08 */
1629     U8                      VF_ID;                      /* 0x09 */
1630     U16                     Reserved4;                  /* 0x0A */
1631     U16                     Reserved5;                  /* 0x0C */
1632     U16                     IOCStatus;                  /* 0x0E */
1633     U32                     IOCLogInfo;                 /* 0x10 */
1634 } MPI2_PWR_MGMT_CONTROL_REPLY, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REPLY,
1635   Mpi2PwrMgmtControlReply_t, MPI2_POINTER pMpi2PwrMgmtControlReply_t;
1636
1637
1638 #endif
1639