2 * Linux MegaRAID driver for SAS based RAID controllers
4 * Copyright (c) 2009-2012 LSI Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 * FILE: megaraid_sas_fusion.h
22 * Authors: LSI Corporation
26 * Send feedback to: <megaraidlinux@lsi.com>
28 * Mail to: LSI Corporation, 1621 Barber Lane, Milpitas, CA 95035
32 #ifndef _MEGARAID_SAS_FUSION_H_
33 #define _MEGARAID_SAS_FUSION_H_
36 #define MEGASAS_MAX_SZ_CHAIN_FRAME 1024
37 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009)
38 #define MEGA_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256
39 #define MEGASAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0
40 #define MEGASAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1
41 #define MEGASAS_LOAD_BALANCE_FLAG 0x1
42 #define MEGASAS_DCMD_MBOX_PEND_FLAG 0x1
43 #define HOST_DIAG_WRITE_ENABLE 0x80
44 #define HOST_DIAG_RESET_ADAPTER 0x4
45 #define MEGASAS_FUSION_MAX_RESET_TRIES 3
46 #define MAX_MSIX_QUEUES_FUSION 128
49 #define MPI2_TYPE_CUDA 0x2
50 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000
51 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00
52 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10
53 #define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80
54 #define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8
57 #define MR_PROT_INFO_TYPE_CONTROLLER 0x8
58 #define MEGASAS_SCSI_VARIABLE_LENGTH_CMD 0x7f
59 #define MEGASAS_SCSI_SERVICE_ACTION_READ32 0x9
60 #define MEGASAS_SCSI_SERVICE_ACTION_WRITE32 0xB
61 #define MEGASAS_SCSI_ADDL_CDB_LEN 0x18
62 #define MEGASAS_RD_WR_PROTECT_CHECK_ALL 0x20
63 #define MEGASAS_RD_WR_PROTECT_CHECK_NONE 0x60
65 #define MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C)
66 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
72 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4
73 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30
74 enum MR_RAID_FLAGS_IO_SUB_TYPE {
75 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0,
76 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1,
80 * Request descriptor types
82 #define MEGASAS_REQ_DESCRIPT_FLAGS_LD_IO 0x7
83 #define MEGASAS_REQ_DESCRIPT_FLAGS_MFA 0x1
84 #define MEGASAS_REQ_DESCRIPT_FLAGS_NO_LOCK 0x2
85 #define MEGASAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 1
87 #define MEGASAS_FP_CMD_LEN 16
88 #define MEGASAS_FUSION_IN_RESET 0
89 #define THRESHOLD_REPLY_COUNT 50
92 * Raid Context structure which describes MegaRAID specific IO Parameters
93 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames
97 #if defined(__BIG_ENDIAN_BITFIELD)
108 u16 VirtualDiskTgtId;
121 #define RAID_CTX_SPANARM_ARM_SHIFT (0)
122 #define RAID_CTX_SPANARM_ARM_MASK (0x1f)
124 #define RAID_CTX_SPANARM_SPAN_SHIFT (5)
125 #define RAID_CTX_SPANARM_SPAN_MASK (0xE0)
128 * define region lock types
131 REGION_TYPE_UNUSED = 0,
132 REGION_TYPE_SHARED_READ = 1,
133 REGION_TYPE_SHARED_WRITE = 2,
134 REGION_TYPE_EXCLUSIVE = 3,
138 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
139 #define MPI2_WHOINIT_HOST_DRIVER (0x04)
140 #define MPI2_VERSION_MAJOR (0x02)
141 #define MPI2_VERSION_MINOR (0x00)
142 #define MPI2_VERSION_MAJOR_MASK (0xFF00)
143 #define MPI2_VERSION_MAJOR_SHIFT (8)
144 #define MPI2_VERSION_MINOR_MASK (0x00FF)
145 #define MPI2_VERSION_MINOR_SHIFT (0)
146 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
148 #define MPI2_HEADER_VERSION_UNIT (0x10)
149 #define MPI2_HEADER_VERSION_DEV (0x00)
150 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
151 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
152 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
153 #define MPI2_HEADER_VERSION_DEV_SHIFT (0)
154 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \
155 MPI2_HEADER_VERSION_DEV)
156 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
157 #define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000)
158 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400)
159 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003)
160 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200)
161 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100)
162 #define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004)
163 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
164 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
165 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
166 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
167 #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000)
168 #define MPI2_SCSIIO_CONTROL_READ (0x02000000)
169 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
170 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
171 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
172 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
173 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
174 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
175 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
176 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
177 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
178 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
179 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
180 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
182 struct MPI25_IEEE_SGE_CHAIN64 {
190 struct MPI2_SGE_SIMPLE_UNION {
198 struct MPI2_SCSI_IO_CDB_EEDP32 {
199 u8 CDB[20]; /* 0x00 */
200 u32 PrimaryReferenceTag; /* 0x14 */
201 u16 PrimaryApplicationTag; /* 0x18 */
202 u16 PrimaryApplicationTagMask; /* 0x1A */
203 u32 TransferLength; /* 0x1C */
206 struct MPI2_SGE_CHAIN_UNION {
216 struct MPI2_IEEE_SGE_SIMPLE32 {
221 struct MPI2_IEEE_SGE_CHAIN32 {
226 struct MPI2_IEEE_SGE_SIMPLE64 {
234 struct MPI2_IEEE_SGE_CHAIN64 {
242 union MPI2_IEEE_SGE_SIMPLE_UNION {
243 struct MPI2_IEEE_SGE_SIMPLE32 Simple32;
244 struct MPI2_IEEE_SGE_SIMPLE64 Simple64;
247 union MPI2_IEEE_SGE_CHAIN_UNION {
248 struct MPI2_IEEE_SGE_CHAIN32 Chain32;
249 struct MPI2_IEEE_SGE_CHAIN64 Chain64;
252 union MPI2_SGE_IO_UNION {
253 struct MPI2_SGE_SIMPLE_UNION MpiSimple;
254 struct MPI2_SGE_CHAIN_UNION MpiChain;
255 union MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
256 union MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
259 union MPI2_SCSI_IO_CDB_UNION {
261 struct MPI2_SCSI_IO_CDB_EEDP32 EEDP32;
262 struct MPI2_SGE_SIMPLE_UNION SGE;
266 * RAID SCSI IO Request Message
267 * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST
269 struct MPI2_RAID_SCSI_IO_REQUEST {
270 u16 DevHandle; /* 0x00 */
271 u8 ChainOffset; /* 0x02 */
272 u8 Function; /* 0x03 */
273 u16 Reserved1; /* 0x04 */
274 u8 Reserved2; /* 0x06 */
275 u8 MsgFlags; /* 0x07 */
278 u16 Reserved3; /* 0x0A */
279 u32 SenseBufferLowAddress; /* 0x0C */
280 u16 SGLFlags; /* 0x10 */
281 u8 SenseBufferLength; /* 0x12 */
282 u8 Reserved4; /* 0x13 */
283 u8 SGLOffset0; /* 0x14 */
284 u8 SGLOffset1; /* 0x15 */
285 u8 SGLOffset2; /* 0x16 */
286 u8 SGLOffset3; /* 0x17 */
287 u32 SkipCount; /* 0x18 */
288 u32 DataLength; /* 0x1C */
289 u32 BidirectionalDataLength; /* 0x20 */
290 u16 IoFlags; /* 0x24 */
291 u16 EEDPFlags; /* 0x26 */
292 u32 EEDPBlockSize; /* 0x28 */
293 u32 SecondaryReferenceTag; /* 0x2C */
294 u16 SecondaryApplicationTag; /* 0x30 */
295 u16 ApplicationTagTranslationMask; /* 0x32 */
296 u8 LUN[8]; /* 0x34 */
297 u32 Control; /* 0x3C */
298 union MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */
299 struct RAID_CONTEXT RaidContext; /* 0x60 */
300 union MPI2_SGE_IO_UNION SGL; /* 0x80 */
304 * MPT RAID MFA IO Descriptor.
306 struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR {
308 u32 MessageAddress1:24;
312 /* Default Request Descriptor */
313 struct MPI2_DEFAULT_REQUEST_DESCRIPTOR {
314 u8 RequestFlags; /* 0x00 */
315 u8 MSIxIndex; /* 0x01 */
318 u16 DescriptorTypeDependent; /* 0x06 */
321 /* High Priority Request Descriptor */
322 struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR {
323 u8 RequestFlags; /* 0x00 */
324 u8 MSIxIndex; /* 0x01 */
327 u16 Reserved1; /* 0x06 */
330 /* SCSI IO Request Descriptor */
331 struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR {
332 u8 RequestFlags; /* 0x00 */
333 u8 MSIxIndex; /* 0x01 */
336 u16 DevHandle; /* 0x06 */
339 /* SCSI Target Request Descriptor */
340 struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR {
341 u8 RequestFlags; /* 0x00 */
342 u8 MSIxIndex; /* 0x01 */
345 u16 IoIndex; /* 0x06 */
348 /* RAID Accelerator Request Descriptor */
349 struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
350 u8 RequestFlags; /* 0x00 */
351 u8 MSIxIndex; /* 0x01 */
354 u16 Reserved; /* 0x06 */
357 /* union of Request Descriptors */
358 union MEGASAS_REQUEST_DESCRIPTOR_UNION {
359 struct MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
360 struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
361 struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
362 struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
363 struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
364 struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo;
374 /* Default Reply Descriptor */
375 struct MPI2_DEFAULT_REPLY_DESCRIPTOR {
376 u8 ReplyFlags; /* 0x00 */
377 u8 MSIxIndex; /* 0x01 */
378 u16 DescriptorTypeDependent1; /* 0x02 */
379 u32 DescriptorTypeDependent2; /* 0x04 */
382 /* Address Reply Descriptor */
383 struct MPI2_ADDRESS_REPLY_DESCRIPTOR {
384 u8 ReplyFlags; /* 0x00 */
385 u8 MSIxIndex; /* 0x01 */
387 u32 ReplyFrameAddress; /* 0x04 */
390 /* SCSI IO Success Reply Descriptor */
391 struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR {
392 u8 ReplyFlags; /* 0x00 */
393 u8 MSIxIndex; /* 0x01 */
395 u16 TaskTag; /* 0x04 */
396 u16 Reserved1; /* 0x06 */
399 /* TargetAssist Success Reply Descriptor */
400 struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR {
401 u8 ReplyFlags; /* 0x00 */
402 u8 MSIxIndex; /* 0x01 */
404 u8 SequenceNumber; /* 0x04 */
405 u8 Reserved1; /* 0x05 */
406 u16 IoIndex; /* 0x06 */
409 /* Target Command Buffer Reply Descriptor */
410 struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR {
411 u8 ReplyFlags; /* 0x00 */
412 u8 MSIxIndex; /* 0x01 */
415 u16 InitiatorDevHandle; /* 0x04 */
416 u16 IoIndex; /* 0x06 */
419 /* RAID Accelerator Success Reply Descriptor */
420 struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
421 u8 ReplyFlags; /* 0x00 */
422 u8 MSIxIndex; /* 0x01 */
424 u32 Reserved; /* 0x04 */
427 /* union of Reply Descriptors */
428 union MPI2_REPLY_DESCRIPTORS_UNION {
429 struct MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
430 struct MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
431 struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
432 struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
433 struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
434 struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR
435 RAIDAcceleratorSuccess;
439 /* IOCInit Request message */
440 struct MPI2_IOC_INIT_REQUEST {
441 u8 WhoInit; /* 0x00 */
442 u8 Reserved1; /* 0x01 */
443 u8 ChainOffset; /* 0x02 */
444 u8 Function; /* 0x03 */
445 u16 Reserved2; /* 0x04 */
446 u8 Reserved3; /* 0x06 */
447 u8 MsgFlags; /* 0x07 */
450 u16 Reserved4; /* 0x0A */
451 u16 MsgVersion; /* 0x0C */
452 u16 HeaderVersion; /* 0x0E */
453 u32 Reserved5; /* 0x10 */
454 u16 Reserved6; /* 0x14 */
455 u8 Reserved7; /* 0x16 */
456 u8 HostMSIxVectors; /* 0x17 */
457 u16 Reserved8; /* 0x18 */
458 u16 SystemRequestFrameSize; /* 0x1A */
459 u16 ReplyDescriptorPostQueueDepth; /* 0x1C */
460 u16 ReplyFreeQueueDepth; /* 0x1E */
461 u32 SenseBufferAddressHigh; /* 0x20 */
462 u32 SystemReplyAddressHigh; /* 0x24 */
463 u64 SystemRequestFrameBaseAddress; /* 0x28 */
464 u64 ReplyDescriptorPostQueueAddress;/* 0x30 */
465 u64 ReplyFreeQueueAddress; /* 0x38 */
466 u64 TimeStamp; /* 0x40 */
470 #define MR_PD_INVALID 0xFFFF
471 #define MAX_SPAN_DEPTH 8
472 #define MAX_QUAD_DEPTH MAX_SPAN_DEPTH
473 #define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH)
474 #define MAX_ROW_SIZE 32
475 #define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE)
476 #define MAX_LOGICAL_DRIVES 64
477 #define MAX_LOGICAL_DRIVES_EXT 256
478 #define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES)
479 #define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES)
480 #define MAX_ARRAYS 128
481 #define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS)
482 #define MAX_ARRAYS_EXT 256
483 #define MAX_API_ARRAYS_EXT (MAX_ARRAYS_EXT)
484 #define MAX_PHYSICAL_DEVICES 256
485 #define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES)
486 #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101
487 #define MR_DCMD_CTRL_SHARED_HOST_MEM_ALLOC 0x010e8485 /* SR-IOV HB alloc*/
488 #define MR_DCMD_LD_VF_MAP_GET_ALL_LDS_111 0x03200200
489 #define MR_DCMD_LD_VF_MAP_GET_ALL_LDS 0x03150200
491 struct MR_DEV_HANDLE_INFO {
498 struct MR_ARRAY_INFO {
499 u16 pd[MAX_RAIDMAP_ROW_SIZE];
502 struct MR_QUAD_ELEMENT {
510 struct MR_SPAN_INFO {
513 struct MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH];
525 struct MR_SPAN_BLOCK_INFO {
527 struct MR_LD_SPAN span;
528 struct MR_SPAN_INFO block_span_info;
533 #if defined(__BIG_ENDIAN_BITFIELD)
535 u32 fpNonRWCapable:1;
536 u32 fpReadAcrossStripe:1;
537 u32 fpWriteAcrossStripe:1;
539 u32 fpWriteCapable:1;
540 u32 encryptionType:8;
550 u32 encryptionType:8;
551 u32 fpWriteCapable:1;
553 u32 fpWriteAcrossStripe:1;
554 u32 fpReadAcrossStripe:1;
555 u32 fpNonRWCapable:1;
571 u8 regTypeReqOnWrite;
577 u32 ldSyncRequired:1;
581 u8 LUN[8]; /* 0x24 8 byte LUN field used for SCSI IO's */
582 u8 fpIoTimeoutForLd;/*0x2C timeout value used by driver in FP IO*/
583 u8 reserved3[0x80-0x2D]; /* 0x2D */
586 struct MR_LD_SPAN_MAP {
587 struct MR_LD_RAID ldRaid;
588 u8 dataArmMap[MAX_RAIDMAP_ROW_SIZE];
589 struct MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH];
592 struct MR_FW_RAID_MAP {
607 u8 ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES+
611 struct MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS];
612 struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
613 struct MR_LD_SPAN_MAP ldSpanMap[1];
616 struct IO_REQUEST_INFO {
628 u8 span_arm; /* span[7:5], arm[4:0] */
632 struct MR_LD_TARGET_SYNC {
638 #define IEEE_SGE_FLAGS_ADDR_MASK (0x03)
639 #define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
640 #define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
641 #define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
642 #define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
643 #define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
644 #define IEEE_SGE_FLAGS_END_OF_LIST (0x40)
646 struct megasas_register_set;
647 struct megasas_instance;
657 struct megasas_cmd_fusion {
658 struct MPI2_RAID_SCSI_IO_REQUEST *io_request;
659 dma_addr_t io_request_phys_addr;
661 union MPI2_SGE_IO_UNION *sg_frame;
662 dma_addr_t sg_frame_phys_addr;
665 dma_addr_t sense_phys_addr;
667 struct list_head list;
668 struct scsi_cmnd *scmd;
669 struct megasas_instance *instance;
671 u8 retry_for_fw_reset;
672 union MEGASAS_REQUEST_DESCRIPTOR_UNION *request_desc;
675 * Context for a MFI frame.
676 * Used to get the mfi cmd from list when a MFI cmd is completed
684 struct LD_LOAD_BALANCE_INFO {
687 atomic_t scsi_pending_cmds[MAX_PHYSICAL_DEVICES];
688 u64 last_accessed_block[MAX_PHYSICAL_DEVICES];
691 /* SPAN_SET is info caclulated from span info from Raid map per LD */
692 typedef struct _LD_SPAN_SET {
697 u64 data_strip_start;
701 u8 strip_offset[MAX_SPAN_DEPTH];
702 u32 span_row_data_width;
705 } LD_SPAN_SET, *PLD_SPAN_SET;
707 typedef struct LOG_BLOCK_SPAN_INFO {
708 LD_SPAN_SET span_set[MAX_SPAN_DEPTH];
709 } LD_SPAN_INFO, *PLD_SPAN_INFO;
711 struct MR_FW_RAID_MAP_ALL {
712 struct MR_FW_RAID_MAP raidMap;
713 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1];
714 } __attribute__ ((packed));
716 struct MR_DRV_RAID_MAP {
717 /* total size of this structure, including this field.
718 * This feild will be manupulated by driver for ext raid map,
719 * else pick the value from firmware raid map.
734 /* timeout value used by driver in FP IOs*/
743 struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
744 u8 ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT];
745 struct MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT];
746 struct MR_LD_SPAN_MAP ldSpanMap[1];
750 /* Driver raid map size is same as raid map ext
751 * MR_DRV_RAID_MAP_ALL is created to sync with old raid.
752 * And it is mainly for code re-use purpose.
754 struct MR_DRV_RAID_MAP_ALL {
756 struct MR_DRV_RAID_MAP raidMap;
757 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT - 1];
762 struct MR_FW_RAID_MAP_EXT {
763 /* Not usred in new map */
785 struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
786 u8 ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT];
787 struct MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT];
788 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT];
791 struct fusion_context {
792 struct megasas_cmd_fusion **cmd_list;
793 struct list_head cmd_pool;
795 spinlock_t mpt_pool_lock;
797 dma_addr_t req_frames_desc_phys;
800 struct dma_pool *io_request_frames_pool;
801 dma_addr_t io_request_frames_phys;
802 u8 *io_request_frames;
804 struct dma_pool *sg_dma_pool;
805 struct dma_pool *sense_dma_pool;
807 dma_addr_t reply_frames_desc_phys;
808 union MPI2_REPLY_DESCRIPTORS_UNION *reply_frames_desc;
809 struct dma_pool *reply_frames_desc_pool;
811 u16 last_reply_idx[MAX_MSIX_QUEUES_FUSION];
814 u32 request_alloc_sz;
816 u32 io_frames_alloc_sz;
818 u16 max_sge_in_main_msg;
819 u16 max_sge_in_chain;
821 u8 chain_offset_io_request;
822 u8 chain_offset_mfi_pthru;
824 struct MR_FW_RAID_MAP_ALL *ld_map[2];
825 dma_addr_t ld_map_phys[2];
827 /*Non dma-able memory. Driver local copy.*/
828 struct MR_DRV_RAID_MAP_ALL *ld_drv_map[2];
837 struct LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES_EXT];
838 LD_SPAN_INFO log_to_span[MAX_LOGICAL_DRIVES_EXT];
850 #endif /* _MEGARAID_SAS_FUSION_H_ */