drivers/scsi/lpfc/lpfc_hw4.h

   1 /*******************************************************************
   2  * This file is part of the Emulex Linux Device Driver for         *
   3  * Fibre Channel Host Bus Adapters.                                *
   4  * Copyright (C) 2009-2015 Emulex.  All rights reserved.                *
   5  * EMULEX and SLI are trademarks of Emulex.                        *
   6  * www.emulex.com                                                  *
   7  *                                                                 *
   8  * This program is free software; you can redistribute it and/or   *
   9  * modify it under the terms of version 2 of the GNU General       *
  10  * Public License as published by the Free Software Foundation.    *
  11  * This program is distributed in the hope that it will be useful. *
  12  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
  13  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
  14  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
  15  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  16  * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
  17  * more details, a copy of which can be found in the file COPYING  *
  18  * included with this package.                                     *
  19  *******************************************************************/
  20
  21 /* Macros to deal with bit fields. Each bit field must have 3 #defines
  22  * associated with it (_SHIFT, _MASK, and _WORD).
  23  * EG. For a bit field that is in the 7th bit of the "field4" field of a
  24  * structure and is 2 bits in size the following #defines must exist:
  25  *      struct temp {
  26  *              uint32_t        field1;
  27  *              uint32_t        field2;
  28  *              uint32_t        field3;
  29  *              uint32_t        field4;
  30  *      #define example_bit_field_SHIFT         7
  31  *      #define example_bit_field_MASK          0x03
  32  *      #define example_bit_field_WORD          field4
  33  *              uint32_t        field5;
  34  *      };
  35  * Then the macros below may be used to get or set the value of that field.
  36  * EG. To get the value of the bit field from the above example:
  37  *      struct temp t1;
  38  *      value = bf_get(example_bit_field, &t1);
  39  * And then to set that bit field:
  40  *      bf_set(example_bit_field, &t1, 2);
  41  * Or clear that bit field:
  42  *      bf_set(example_bit_field, &t1, 0);
  43  */
  44 #define bf_get_be32(name, ptr) \
  45         ((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK)
  46 #define bf_get_le32(name, ptr) \
  47         ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK)
  48 #define bf_get(name, ptr) \
  49         (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK)
  50 #define bf_set_le32(name, ptr, value) \
  51         ((ptr)->name##_WORD = cpu_to_le32(((((value) & \
  52         name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \
  53         ~(name##_MASK << name##_SHIFT)))))
  54 #define bf_set(name, ptr, value) \
  55         ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \
  56                  ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT))))
  57
  58 struct dma_address {
  59         uint32_t addr_lo;
  60         uint32_t addr_hi;
  61 };
  62
  63 struct lpfc_sli_intf {
  64         uint32_t word0;
  65 #define lpfc_sli_intf_valid_SHIFT               29
  66 #define lpfc_sli_intf_valid_MASK                0x00000007
  67 #define lpfc_sli_intf_valid_WORD                word0
  68 #define LPFC_SLI_INTF_VALID             6
  69 #define lpfc_sli_intf_sli_hint2_SHIFT           24
  70 #define lpfc_sli_intf_sli_hint2_MASK            0x0000001F
  71 #define lpfc_sli_intf_sli_hint2_WORD            word0
  72 #define LPFC_SLI_INTF_SLI_HINT2_NONE    0
  73 #define lpfc_sli_intf_sli_hint1_SHIFT           16
  74 #define lpfc_sli_intf_sli_hint1_MASK            0x000000FF
  75 #define lpfc_sli_intf_sli_hint1_WORD            word0
  76 #define LPFC_SLI_INTF_SLI_HINT1_NONE    0
  77 #define LPFC_SLI_INTF_SLI_HINT1_1       1
  78 #define LPFC_SLI_INTF_SLI_HINT1_2       2
  79 #define lpfc_sli_intf_if_type_SHIFT             12
  80 #define lpfc_sli_intf_if_type_MASK              0x0000000F
  81 #define lpfc_sli_intf_if_type_WORD              word0
  82 #define LPFC_SLI_INTF_IF_TYPE_0         0
  83 #define LPFC_SLI_INTF_IF_TYPE_1         1
  84 #define LPFC_SLI_INTF_IF_TYPE_2         2
  85 #define lpfc_sli_intf_sli_family_SHIFT          8
  86 #define lpfc_sli_intf_sli_family_MASK           0x0000000F
  87 #define lpfc_sli_intf_sli_family_WORD           word0
  88 #define LPFC_SLI_INTF_FAMILY_BE2        0x0
  89 #define LPFC_SLI_INTF_FAMILY_BE3        0x1
  90 #define LPFC_SLI_INTF_FAMILY_LNCR_A0    0xa
  91 #define LPFC_SLI_INTF_FAMILY_LNCR_B0    0xb
  92 #define lpfc_sli_intf_slirev_SHIFT              4
  93 #define lpfc_sli_intf_slirev_MASK               0x0000000F
  94 #define lpfc_sli_intf_slirev_WORD               word0
  95 #define LPFC_SLI_INTF_REV_SLI3          3
  96 #define LPFC_SLI_INTF_REV_SLI4          4
  97 #define lpfc_sli_intf_func_type_SHIFT           0
  98 #define lpfc_sli_intf_func_type_MASK            0x00000001
  99 #define lpfc_sli_intf_func_type_WORD            word0
 100 #define LPFC_SLI_INTF_IF_TYPE_PHYS      0
 101 #define LPFC_SLI_INTF_IF_TYPE_VIRT      1
 102 };
 103
 104 #define LPFC_SLI4_MBX_EMBED     true
 105 #define LPFC_SLI4_MBX_NEMBED    false
 106
 107 #define LPFC_SLI4_MB_WORD_COUNT         64
 108 #define LPFC_MAX_MQ_PAGE                8
 109 #define LPFC_MAX_WQ_PAGE_V0             4
 110 #define LPFC_MAX_WQ_PAGE                8
 111 #define LPFC_MAX_CQ_PAGE                4
 112 #define LPFC_MAX_EQ_PAGE                8
 113
 114 #define LPFC_VIR_FUNC_MAX       32 /* Maximum number of virtual functions */
 115 #define LPFC_PCI_FUNC_MAX        5 /* Maximum number of PCI functions */
 116 #define LPFC_VFR_PAGE_SIZE      0x1000 /* 4KB BAR2 per-VF register page size */
 117
 118 /* Define SLI4 Alignment requirements. */
 119 #define LPFC_ALIGN_16_BYTE      16
 120 #define LPFC_ALIGN_64_BYTE      64
 121
 122 /* Define SLI4 specific definitions. */
 123 #define LPFC_MQ_CQE_BYTE_OFFSET 256
 124 #define LPFC_MBX_CMD_HDR_LENGTH 16
 125 #define LPFC_MBX_ERROR_RANGE    0x4000
 126 #define LPFC_BMBX_BIT1_ADDR_HI  0x2
 127 #define LPFC_BMBX_BIT1_ADDR_LO  0
 128 #define LPFC_RPI_HDR_COUNT      64
 129 #define LPFC_HDR_TEMPLATE_SIZE  4096
 130 #define LPFC_RPI_ALLOC_ERROR    0xFFFF
 131 #define LPFC_FCF_RECORD_WD_CNT  132
 132 #define LPFC_ENTIRE_FCF_DATABASE 0
 133 #define LPFC_DFLT_FCF_INDEX      0
 134
 135 /* Virtual function numbers */
 136 #define LPFC_VF0                0
 137 #define LPFC_VF1                1
 138 #define LPFC_VF2                2
 139 #define LPFC_VF3                3
 140 #define LPFC_VF4                4
 141 #define LPFC_VF5                5
 142 #define LPFC_VF6                6
 143 #define LPFC_VF7                7
 144 #define LPFC_VF8                8
 145 #define LPFC_VF9                9
 146 #define LPFC_VF10               10
 147 #define LPFC_VF11               11
 148 #define LPFC_VF12               12
 149 #define LPFC_VF13               13
 150 #define LPFC_VF14               14
 151 #define LPFC_VF15               15
 152 #define LPFC_VF16               16
 153 #define LPFC_VF17               17
 154 #define LPFC_VF18               18
 155 #define LPFC_VF19               19
 156 #define LPFC_VF20               20
 157 #define LPFC_VF21               21
 158 #define LPFC_VF22               22
 159 #define LPFC_VF23               23
 160 #define LPFC_VF24               24
 161 #define LPFC_VF25               25
 162 #define LPFC_VF26               26
 163 #define LPFC_VF27               27
 164 #define LPFC_VF28               28
 165 #define LPFC_VF29               29
 166 #define LPFC_VF30               30
 167 #define LPFC_VF31               31
 168
 169 /* PCI function numbers */
 170 #define LPFC_PCI_FUNC0          0
 171 #define LPFC_PCI_FUNC1          1
 172 #define LPFC_PCI_FUNC2          2
 173 #define LPFC_PCI_FUNC3          3
 174 #define LPFC_PCI_FUNC4          4
 175
 176 /* SLI4 interface type-2 PDEV_CTL register */
 177 #define LPFC_CTL_PDEV_CTL_OFFSET        0x414
 178 #define LPFC_CTL_PDEV_CTL_DRST          0x00000001
 179 #define LPFC_CTL_PDEV_CTL_FRST          0x00000002
 180 #define LPFC_CTL_PDEV_CTL_DD            0x00000004
 181 #define LPFC_CTL_PDEV_CTL_LC            0x00000008
 182 #define LPFC_CTL_PDEV_CTL_FRL_ALL       0x00
 183 #define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE   0x10
 184 #define LPFC_CTL_PDEV_CTL_FRL_NIC       0x20
 185
 186 #define LPFC_FW_DUMP_REQUEST    (LPFC_CTL_PDEV_CTL_DD | LPFC_CTL_PDEV_CTL_FRST)
 187
 188 /* Active interrupt test count */
 189 #define LPFC_ACT_INTR_CNT       4
 190
 191 /* Algrithmns for scheduling FCP commands to WQs */
 192 #define LPFC_FCP_SCHED_ROUND_ROBIN      0
 193 #define LPFC_FCP_SCHED_BY_CPU           1
 194
 195 /* Delay Multiplier constant */
 196 #define LPFC_DMULT_CONST       651042
 197
 198 /* Configuration of Interrupts / sec for entire HBA port */
 199 #define LPFC_MIN_IMAX          5000
 200 #define LPFC_MAX_IMAX          5000000
 201 #define LPFC_DEF_IMAX          50000
 202
 203 #define LPFC_MIN_CPU_MAP       0
 204 #define LPFC_MAX_CPU_MAP       2
 205 #define LPFC_HBA_CPU_MAP       1
 206 #define LPFC_DRIVER_CPU_MAP    2  /* Default */
 207
 208 /* PORT_CAPABILITIES constants. */
 209 #define LPFC_MAX_SUPPORTED_PAGES        8
 210
 211 struct ulp_bde64 {
 212         union ULP_BDE_TUS {
 213                 uint32_t w;
 214                 struct {
 215 #ifdef __BIG_ENDIAN_BITFIELD
 216                         uint32_t bdeFlags:8;    /* BDE Flags 0 IS A SUPPORTED
 217                                                    VALUE !! */
 218                         uint32_t bdeSize:24;    /* Size of buffer (in bytes) */
 219 #else   /*  __LITTLE_ENDIAN_BITFIELD */
 220                         uint32_t bdeSize:24;    /* Size of buffer (in bytes) */
 221                         uint32_t bdeFlags:8;    /* BDE Flags 0 IS A SUPPORTED
 222                                                    VALUE !! */
 223 #endif
 224 #define BUFF_TYPE_BDE_64    0x00        /* BDE (Host_resident) */
 225 #define BUFF_TYPE_BDE_IMMED 0x01        /* Immediate Data BDE */
 226 #define BUFF_TYPE_BDE_64P   0x02        /* BDE (Port-resident) */
 227 #define BUFF_TYPE_BDE_64I   0x08        /* Input BDE (Host-resident) */
 228 #define BUFF_TYPE_BDE_64IP  0x0A        /* Input BDE (Port-resident) */
 229 #define BUFF_TYPE_BLP_64    0x40        /* BLP (Host-resident) */
 230 #define BUFF_TYPE_BLP_64P   0x42        /* BLP (Port-resident) */
 231                 } f;
 232         } tus;
 233         uint32_t addrLow;
 234         uint32_t addrHigh;
 235 };
 236
 237 /* Maximun size of immediate data that can fit into a 128 byte WQE */
 238 #define LPFC_MAX_BDE_IMM_SIZE   64
 239
 240 struct lpfc_sli4_flags {
 241         uint32_t word0;
 242 #define lpfc_idx_rsrc_rdy_SHIFT         0
 243 #define lpfc_idx_rsrc_rdy_MASK          0x00000001
 244 #define lpfc_idx_rsrc_rdy_WORD          word0
 245 #define LPFC_IDX_RSRC_RDY               1
 246 #define lpfc_rpi_rsrc_rdy_SHIFT         1
 247 #define lpfc_rpi_rsrc_rdy_MASK          0x00000001
 248 #define lpfc_rpi_rsrc_rdy_WORD          word0
 249 #define LPFC_RPI_RSRC_RDY               1
 250 #define lpfc_vpi_rsrc_rdy_SHIFT         2
 251 #define lpfc_vpi_rsrc_rdy_MASK          0x00000001
 252 #define lpfc_vpi_rsrc_rdy_WORD          word0
 253 #define LPFC_VPI_RSRC_RDY               1
 254 #define lpfc_vfi_rsrc_rdy_SHIFT         3
 255 #define lpfc_vfi_rsrc_rdy_MASK          0x00000001
 256 #define lpfc_vfi_rsrc_rdy_WORD          word0
 257 #define LPFC_VFI_RSRC_RDY               1
 258 };
 259
 260 struct sli4_bls_rsp {
 261         uint32_t word0_rsvd;      /* Word0 must be reserved */
 262         uint32_t word1;
 263 #define lpfc_abts_orig_SHIFT      0
 264 #define lpfc_abts_orig_MASK       0x00000001
 265 #define lpfc_abts_orig_WORD       word1
 266 #define LPFC_ABTS_UNSOL_RSP       1
 267 #define LPFC_ABTS_UNSOL_INT       0
 268         uint32_t word2;
 269 #define lpfc_abts_rxid_SHIFT      0
 270 #define lpfc_abts_rxid_MASK       0x0000FFFF
 271 #define lpfc_abts_rxid_WORD       word2
 272 #define lpfc_abts_oxid_SHIFT      16
 273 #define lpfc_abts_oxid_MASK       0x0000FFFF
 274 #define lpfc_abts_oxid_WORD       word2
 275         uint32_t word3;
 276 #define lpfc_vndr_code_SHIFT    0
 277 #define lpfc_vndr_code_MASK     0x000000FF
 278 #define lpfc_vndr_code_WORD     word3
 279 #define lpfc_rsn_expln_SHIFT    8
 280 #define lpfc_rsn_expln_MASK     0x000000FF
 281 #define lpfc_rsn_expln_WORD     word3
 282 #define lpfc_rsn_code_SHIFT     16
 283 #define lpfc_rsn_code_MASK      0x000000FF
 284 #define lpfc_rsn_code_WORD      word3
 285
 286         uint32_t word4;
 287         uint32_t word5_rsvd;    /* Word5 must be reserved */
 288 };
 289
 290 /* event queue entry structure */
 291 struct lpfc_eqe {
 292         uint32_t word0;
 293 #define lpfc_eqe_resource_id_SHIFT      16
 294 #define lpfc_eqe_resource_id_MASK       0x0000FFFF
 295 #define lpfc_eqe_resource_id_WORD       word0
 296 #define lpfc_eqe_minor_code_SHIFT       4
 297 #define lpfc_eqe_minor_code_MASK        0x00000FFF
 298 #define lpfc_eqe_minor_code_WORD        word0
 299 #define lpfc_eqe_major_code_SHIFT       1
 300 #define lpfc_eqe_major_code_MASK        0x00000007
 301 #define lpfc_eqe_major_code_WORD        word0
 302 #define lpfc_eqe_valid_SHIFT            0
 303 #define lpfc_eqe_valid_MASK             0x00000001
 304 #define lpfc_eqe_valid_WORD             word0
 305 };
 306
 307 /* completion queue entry structure (common fields for all cqe types) */
 308 struct lpfc_cqe {
 309         uint32_t reserved0;
 310         uint32_t reserved1;
 311         uint32_t reserved2;
 312         uint32_t word3;
 313 #define lpfc_cqe_valid_SHIFT            31
 314 #define lpfc_cqe_valid_MASK             0x00000001
 315 #define lpfc_cqe_valid_WORD             word3
 316 #define lpfc_cqe_code_SHIFT             16
 317 #define lpfc_cqe_code_MASK              0x000000FF
 318 #define lpfc_cqe_code_WORD              word3
 319 };
 320
 321 /* Completion Queue Entry Status Codes */
 322 #define CQE_STATUS_SUCCESS              0x0
 323 #define CQE_STATUS_FCP_RSP_FAILURE      0x1
 324 #define CQE_STATUS_REMOTE_STOP          0x2
 325 #define CQE_STATUS_LOCAL_REJECT         0x3
 326 #define CQE_STATUS_NPORT_RJT            0x4
 327 #define CQE_STATUS_FABRIC_RJT           0x5
 328 #define CQE_STATUS_NPORT_BSY            0x6
 329 #define CQE_STATUS_FABRIC_BSY           0x7
 330 #define CQE_STATUS_INTERMED_RSP         0x8
 331 #define CQE_STATUS_LS_RJT               0x9
 332 #define CQE_STATUS_CMD_REJECT           0xb
 333 #define CQE_STATUS_FCP_TGT_LENCHECK     0xc
 334 #define CQE_STATUS_NEED_BUFF_ENTRY      0xf
 335 #define CQE_STATUS_DI_ERROR             0x16
 336
 337 /* Used when mapping CQE status to IOCB */
 338 #define LPFC_IOCB_STATUS_MASK           0xf
 339
 340 /* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */
 341 #define CQE_HW_STATUS_NO_ERR            0x0
 342 #define CQE_HW_STATUS_UNDERRUN          0x1
 343 #define CQE_HW_STATUS_OVERRUN           0x2
 344
 345 /* Completion Queue Entry Codes */
 346 #define CQE_CODE_COMPL_WQE              0x1
 347 #define CQE_CODE_RELEASE_WQE            0x2
 348 #define CQE_CODE_RECEIVE                0x4
 349 #define CQE_CODE_XRI_ABORTED            0x5
 350 #define CQE_CODE_RECEIVE_V1             0x9
 351
 352 /*
 353  * Define mask value for xri_aborted and wcqe completed CQE extended status.
 354  * Currently, extended status is limited to 9 bits (0x0 -> 0x103) .
 355  */
 356 #define WCQE_PARAM_MASK         0x1FF
 357
 358 /* completion queue entry for wqe completions */
 359 struct lpfc_wcqe_complete {
 360         uint32_t word0;
 361 #define lpfc_wcqe_c_request_tag_SHIFT   16
 362 #define lpfc_wcqe_c_request_tag_MASK    0x0000FFFF
 363 #define lpfc_wcqe_c_request_tag_WORD    word0
 364 #define lpfc_wcqe_c_status_SHIFT        8
 365 #define lpfc_wcqe_c_status_MASK         0x000000FF
 366 #define lpfc_wcqe_c_status_WORD         word0
 367 #define lpfc_wcqe_c_hw_status_SHIFT     0
 368 #define lpfc_wcqe_c_hw_status_MASK      0x000000FF
 369 #define lpfc_wcqe_c_hw_status_WORD      word0
 370         uint32_t total_data_placed;
 371         uint32_t parameter;
 372 #define lpfc_wcqe_c_bg_edir_SHIFT       5
 373 #define lpfc_wcqe_c_bg_edir_MASK        0x00000001
 374 #define lpfc_wcqe_c_bg_edir_WORD        parameter
 375 #define lpfc_wcqe_c_bg_tdpv_SHIFT       3
 376 #define lpfc_wcqe_c_bg_tdpv_MASK        0x00000001
 377 #define lpfc_wcqe_c_bg_tdpv_WORD        parameter
 378 #define lpfc_wcqe_c_bg_re_SHIFT         2
 379 #define lpfc_wcqe_c_bg_re_MASK          0x00000001
 380 #define lpfc_wcqe_c_bg_re_WORD          parameter
 381 #define lpfc_wcqe_c_bg_ae_SHIFT         1
 382 #define lpfc_wcqe_c_bg_ae_MASK          0x00000001
 383 #define lpfc_wcqe_c_bg_ae_WORD          parameter
 384 #define lpfc_wcqe_c_bg_ge_SHIFT         0
 385 #define lpfc_wcqe_c_bg_ge_MASK          0x00000001
 386 #define lpfc_wcqe_c_bg_ge_WORD          parameter
 387         uint32_t word3;
 388 #define lpfc_wcqe_c_valid_SHIFT         lpfc_cqe_valid_SHIFT
 389 #define lpfc_wcqe_c_valid_MASK          lpfc_cqe_valid_MASK
 390 #define lpfc_wcqe_c_valid_WORD          lpfc_cqe_valid_WORD
 391 #define lpfc_wcqe_c_xb_SHIFT            28
 392 #define lpfc_wcqe_c_xb_MASK             0x00000001
 393 #define lpfc_wcqe_c_xb_WORD             word3
 394 #define lpfc_wcqe_c_pv_SHIFT            27
 395 #define lpfc_wcqe_c_pv_MASK             0x00000001
 396 #define lpfc_wcqe_c_pv_WORD             word3
 397 #define lpfc_wcqe_c_priority_SHIFT      24
 398 #define lpfc_wcqe_c_priority_MASK       0x00000007
 399 #define lpfc_wcqe_c_priority_WORD       word3
 400 #define lpfc_wcqe_c_code_SHIFT          lpfc_cqe_code_SHIFT
 401 #define lpfc_wcqe_c_code_MASK           lpfc_cqe_code_MASK
 402 #define lpfc_wcqe_c_code_WORD           lpfc_cqe_code_WORD
 403 };
 404
 405 /* completion queue entry for wqe release */
 406 struct lpfc_wcqe_release {
 407         uint32_t reserved0;
 408         uint32_t reserved1;
 409         uint32_t word2;
 410 #define lpfc_wcqe_r_wq_id_SHIFT         16
 411 #define lpfc_wcqe_r_wq_id_MASK          0x0000FFFF
 412 #define lpfc_wcqe_r_wq_id_WORD          word2
 413 #define lpfc_wcqe_r_wqe_index_SHIFT     0
 414 #define lpfc_wcqe_r_wqe_index_MASK      0x0000FFFF
 415 #define lpfc_wcqe_r_wqe_index_WORD      word2
 416         uint32_t word3;
 417 #define lpfc_wcqe_r_valid_SHIFT         lpfc_cqe_valid_SHIFT
 418 #define lpfc_wcqe_r_valid_MASK          lpfc_cqe_valid_MASK
 419 #define lpfc_wcqe_r_valid_WORD          lpfc_cqe_valid_WORD
 420 #define lpfc_wcqe_r_code_SHIFT          lpfc_cqe_code_SHIFT
 421 #define lpfc_wcqe_r_code_MASK           lpfc_cqe_code_MASK
 422 #define lpfc_wcqe_r_code_WORD           lpfc_cqe_code_WORD
 423 };
 424
 425 struct sli4_wcqe_xri_aborted {
 426         uint32_t word0;
 427 #define lpfc_wcqe_xa_status_SHIFT               8
 428 #define lpfc_wcqe_xa_status_MASK                0x000000FF
 429 #define lpfc_wcqe_xa_status_WORD                word0
 430         uint32_t parameter;
 431         uint32_t word2;
 432 #define lpfc_wcqe_xa_remote_xid_SHIFT   16
 433 #define lpfc_wcqe_xa_remote_xid_MASK    0x0000FFFF
 434 #define lpfc_wcqe_xa_remote_xid_WORD    word2
 435 #define lpfc_wcqe_xa_xri_SHIFT          0
 436 #define lpfc_wcqe_xa_xri_MASK           0x0000FFFF
 437 #define lpfc_wcqe_xa_xri_WORD           word2
 438         uint32_t word3;
 439 #define lpfc_wcqe_xa_valid_SHIFT        lpfc_cqe_valid_SHIFT
 440 #define lpfc_wcqe_xa_valid_MASK         lpfc_cqe_valid_MASK
 441 #define lpfc_wcqe_xa_valid_WORD         lpfc_cqe_valid_WORD
 442 #define lpfc_wcqe_xa_ia_SHIFT           30
 443 #define lpfc_wcqe_xa_ia_MASK            0x00000001
 444 #define lpfc_wcqe_xa_ia_WORD            word3
 445 #define CQE_XRI_ABORTED_IA_REMOTE       0
 446 #define CQE_XRI_ABORTED_IA_LOCAL        1
 447 #define lpfc_wcqe_xa_br_SHIFT           29
 448 #define lpfc_wcqe_xa_br_MASK            0x00000001
 449 #define lpfc_wcqe_xa_br_WORD            word3
 450 #define CQE_XRI_ABORTED_BR_BA_ACC       0
 451 #define CQE_XRI_ABORTED_BR_BA_RJT       1
 452 #define lpfc_wcqe_xa_eo_SHIFT           28
 453 #define lpfc_wcqe_xa_eo_MASK            0x00000001
 454 #define lpfc_wcqe_xa_eo_WORD            word3
 455 #define CQE_XRI_ABORTED_EO_REMOTE       0
 456 #define CQE_XRI_ABORTED_EO_LOCAL        1
 457 #define lpfc_wcqe_xa_code_SHIFT         lpfc_cqe_code_SHIFT
 458 #define lpfc_wcqe_xa_code_MASK          lpfc_cqe_code_MASK
 459 #define lpfc_wcqe_xa_code_WORD          lpfc_cqe_code_WORD
 460 };
 461
 462 /* completion queue entry structure for rqe completion */
 463 struct lpfc_rcqe {
 464         uint32_t word0;
 465 #define lpfc_rcqe_bindex_SHIFT          16
 466 #define lpfc_rcqe_bindex_MASK           0x0000FFF
 467 #define lpfc_rcqe_bindex_WORD           word0
 468 #define lpfc_rcqe_status_SHIFT          8
 469 #define lpfc_rcqe_status_MASK           0x000000FF
 470 #define lpfc_rcqe_status_WORD           word0
 471 #define FC_STATUS_RQ_SUCCESS            0x10 /* Async receive successful */
 472 #define FC_STATUS_RQ_BUF_LEN_EXCEEDED   0x11 /* payload truncated */
 473 #define FC_STATUS_INSUFF_BUF_NEED_BUF   0x12 /* Insufficient buffers */
 474 #define FC_STATUS_INSUFF_BUF_FRM_DISC   0x13 /* Frame Discard */
 475         uint32_t word1;
 476 #define lpfc_rcqe_fcf_id_v1_SHIFT       0
 477 #define lpfc_rcqe_fcf_id_v1_MASK        0x0000003F
 478 #define lpfc_rcqe_fcf_id_v1_WORD        word1
 479         uint32_t word2;
 480 #define lpfc_rcqe_length_SHIFT          16
 481 #define lpfc_rcqe_length_MASK           0x0000FFFF
 482 #define lpfc_rcqe_length_WORD           word2
 483 #define lpfc_rcqe_rq_id_SHIFT           6
 484 #define lpfc_rcqe_rq_id_MASK            0x000003FF
 485 #define lpfc_rcqe_rq_id_WORD            word2
 486 #define lpfc_rcqe_fcf_id_SHIFT          0
 487 #define lpfc_rcqe_fcf_id_MASK           0x0000003F
 488 #define lpfc_rcqe_fcf_id_WORD           word2
 489 #define lpfc_rcqe_rq_id_v1_SHIFT        0
 490 #define lpfc_rcqe_rq_id_v1_MASK         0x0000FFFF
 491 #define lpfc_rcqe_rq_id_v1_WORD         word2
 492         uint32_t word3;
 493 #define lpfc_rcqe_valid_SHIFT           lpfc_cqe_valid_SHIFT
 494 #define lpfc_rcqe_valid_MASK            lpfc_cqe_valid_MASK
 495 #define lpfc_rcqe_valid_WORD            lpfc_cqe_valid_WORD
 496 #define lpfc_rcqe_port_SHIFT            30
 497 #define lpfc_rcqe_port_MASK             0x00000001
 498 #define lpfc_rcqe_port_WORD             word3
 499 #define lpfc_rcqe_hdr_length_SHIFT      24
 500 #define lpfc_rcqe_hdr_length_MASK       0x0000001F
 501 #define lpfc_rcqe_hdr_length_WORD       word3
 502 #define lpfc_rcqe_code_SHIFT            lpfc_cqe_code_SHIFT
 503 #define lpfc_rcqe_code_MASK             lpfc_cqe_code_MASK
 504 #define lpfc_rcqe_code_WORD             lpfc_cqe_code_WORD
 505 #define lpfc_rcqe_eof_SHIFT             8
 506 #define lpfc_rcqe_eof_MASK              0x000000FF
 507 #define lpfc_rcqe_eof_WORD              word3
 508 #define FCOE_EOFn       0x41
 509 #define FCOE_EOFt       0x42
 510 #define FCOE_EOFni      0x49
 511 #define FCOE_EOFa       0x50
 512 #define lpfc_rcqe_sof_SHIFT             0
 513 #define lpfc_rcqe_sof_MASK              0x000000FF
 514 #define lpfc_rcqe_sof_WORD              word3
 515 #define FCOE_SOFi2      0x2d
 516 #define FCOE_SOFi3      0x2e
 517 #define FCOE_SOFn2      0x35
 518 #define FCOE_SOFn3      0x36
 519 };
 520
 521 struct lpfc_rqe {
 522         uint32_t address_hi;
 523         uint32_t address_lo;
 524 };
 525
 526 /* buffer descriptors */
 527 struct lpfc_bde4 {
 528         uint32_t addr_hi;
 529         uint32_t addr_lo;
 530         uint32_t word2;
 531 #define lpfc_bde4_last_SHIFT            31
 532 #define lpfc_bde4_last_MASK             0x00000001
 533 #define lpfc_bde4_last_WORD             word2
 534 #define lpfc_bde4_sge_offset_SHIFT      0
 535 #define lpfc_bde4_sge_offset_MASK       0x000003FF
 536 #define lpfc_bde4_sge_offset_WORD       word2
 537         uint32_t word3;
 538 #define lpfc_bde4_length_SHIFT          0
 539 #define lpfc_bde4_length_MASK           0x000000FF
 540 #define lpfc_bde4_length_WORD           word3
 541 };
 542
 543 struct lpfc_register {
 544         uint32_t word0;
 545 };
 546
 547 /* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */
 548 #define LPFC_UERR_STATUS_HI             0x00A4
 549 #define LPFC_UERR_STATUS_LO             0x00A0
 550 #define LPFC_UE_MASK_HI                 0x00AC
 551 #define LPFC_UE_MASK_LO                 0x00A8
 552
 553 /* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */
 554 #define LPFC_SLI_INTF                   0x0058
 555
 556 #define LPFC_CTL_PORT_SEM_OFFSET        0x400
 557 #define lpfc_port_smphr_perr_SHIFT      31
 558 #define lpfc_port_smphr_perr_MASK       0x1
 559 #define lpfc_port_smphr_perr_WORD       word0
 560 #define lpfc_port_smphr_sfi_SHIFT       30
 561 #define lpfc_port_smphr_sfi_MASK        0x1
 562 #define lpfc_port_smphr_sfi_WORD        word0
 563 #define lpfc_port_smphr_nip_SHIFT       29
 564 #define lpfc_port_smphr_nip_MASK        0x1
 565 #define lpfc_port_smphr_nip_WORD        word0
 566 #define lpfc_port_smphr_ipc_SHIFT       28
 567 #define lpfc_port_smphr_ipc_MASK        0x1
 568 #define lpfc_port_smphr_ipc_WORD        word0
 569 #define lpfc_port_smphr_scr1_SHIFT      27
 570 #define lpfc_port_smphr_scr1_MASK       0x1
 571 #define lpfc_port_smphr_scr1_WORD       word0
 572 #define lpfc_port_smphr_scr2_SHIFT      26
 573 #define lpfc_port_smphr_scr2_MASK       0x1
 574 #define lpfc_port_smphr_scr2_WORD       word0
 575 #define lpfc_port_smphr_host_scratch_SHIFT      16
 576 #define lpfc_port_smphr_host_scratch_MASK       0xFF
 577 #define lpfc_port_smphr_host_scratch_WORD       word0
 578 #define lpfc_port_smphr_port_status_SHIFT       0
 579 #define lpfc_port_smphr_port_status_MASK        0xFFFF
 580 #define lpfc_port_smphr_port_status_WORD        word0
 581
 582 #define LPFC_POST_STAGE_POWER_ON_RESET                  0x0000
 583 #define LPFC_POST_STAGE_AWAITING_HOST_RDY               0x0001
 584 #define LPFC_POST_STAGE_HOST_RDY                        0x0002
 585 #define LPFC_POST_STAGE_BE_RESET                        0x0003
 586 #define LPFC_POST_STAGE_SEEPROM_CS_START                0x0100
 587 #define LPFC_POST_STAGE_SEEPROM_CS_DONE                 0x0101
 588 #define LPFC_POST_STAGE_DDR_CONFIG_START                0x0200
 589 #define LPFC_POST_STAGE_DDR_CONFIG_DONE                 0x0201
 590 #define LPFC_POST_STAGE_DDR_CALIBRATE_START             0x0300
 591 #define LPFC_POST_STAGE_DDR_CALIBRATE_DONE              0x0301
 592 #define LPFC_POST_STAGE_DDR_TEST_START                  0x0400
 593 #define LPFC_POST_STAGE_DDR_TEST_DONE                   0x0401
 594 #define LPFC_POST_STAGE_REDBOOT_INIT_START              0x0600
 595 #define LPFC_POST_STAGE_REDBOOT_INIT_DONE               0x0601
 596 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_START             0x0700
 597 #define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE              0x0701
 598 #define LPFC_POST_STAGE_ARMFW_START                     0x0800
 599 #define LPFC_POST_STAGE_DHCP_QUERY_START                0x0900
 600 #define LPFC_POST_STAGE_DHCP_QUERY_DONE                 0x0901
 601 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START     0x0A00
 602 #define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE      0x0A01
 603 #define LPFC_POST_STAGE_RC_OPTION_SET                   0x0B00
 604 #define LPFC_POST_STAGE_SWITCH_LINK                     0x0B01
 605 #define LPFC_POST_STAGE_SEND_ICDS_MESSAGE               0x0B02
 606 #define LPFC_POST_STAGE_PERFROM_TFTP                    0x0B03
 607 #define LPFC_POST_STAGE_PARSE_XML                       0x0B04
 608 #define LPFC_POST_STAGE_DOWNLOAD_IMAGE                  0x0B05
 609 #define LPFC_POST_STAGE_FLASH_IMAGE                     0x0B06
 610 #define LPFC_POST_STAGE_RC_DONE                         0x0B07
 611 #define LPFC_POST_STAGE_REBOOT_SYSTEM                   0x0B08
 612 #define LPFC_POST_STAGE_MAC_ADDRESS                     0x0C00
 613 #define LPFC_POST_STAGE_PORT_READY                      0xC000
 614 #define LPFC_POST_STAGE_PORT_UE                         0xF000
 615
 616 #define LPFC_CTL_PORT_STA_OFFSET        0x404
 617 #define lpfc_sliport_status_err_SHIFT   31
 618 #define lpfc_sliport_status_err_MASK    0x1
 619 #define lpfc_sliport_status_err_WORD    word0
 620 #define lpfc_sliport_status_end_SHIFT   30
 621 #define lpfc_sliport_status_end_MASK    0x1
 622 #define lpfc_sliport_status_end_WORD    word0
 623 #define lpfc_sliport_status_oti_SHIFT   29
 624 #define lpfc_sliport_status_oti_MASK    0x1
 625 #define lpfc_sliport_status_oti_WORD    word0
 626 #define lpfc_sliport_status_rn_SHIFT    24
 627 #define lpfc_sliport_status_rn_MASK     0x1
 628 #define lpfc_sliport_status_rn_WORD     word0
 629 #define lpfc_sliport_status_rdy_SHIFT   23
 630 #define lpfc_sliport_status_rdy_MASK    0x1
 631 #define lpfc_sliport_status_rdy_WORD    word0
 632 #define MAX_IF_TYPE_2_RESETS            6
 633
 634 #define LPFC_CTL_PORT_CTL_OFFSET        0x408
 635 #define lpfc_sliport_ctrl_end_SHIFT     30
 636 #define lpfc_sliport_ctrl_end_MASK      0x1
 637 #define lpfc_sliport_ctrl_end_WORD      word0
 638 #define LPFC_SLIPORT_LITTLE_ENDIAN 0
 639 #define LPFC_SLIPORT_BIG_ENDIAN    1
 640 #define lpfc_sliport_ctrl_ip_SHIFT      27
 641 #define lpfc_sliport_ctrl_ip_MASK       0x1
 642 #define lpfc_sliport_ctrl_ip_WORD       word0
 643 #define LPFC_SLIPORT_INIT_PORT  1
 644
 645 #define LPFC_CTL_PORT_ER1_OFFSET        0x40C
 646 #define LPFC_CTL_PORT_ER2_OFFSET        0x410
 647
 648 /* The following Registers apply to SLI4 if_type 0 UCNAs. They typically
 649  * reside in BAR 2.
 650  */
 651 #define LPFC_SLIPORT_IF0_SMPHR  0x00AC
 652
 653 #define LPFC_IMR_MASK_ALL       0xFFFFFFFF
 654 #define LPFC_ISCR_CLEAR_ALL     0xFFFFFFFF
 655
 656 #define LPFC_HST_ISR0           0x0C18
 657 #define LPFC_HST_ISR1           0x0C1C
 658 #define LPFC_HST_ISR2           0x0C20
 659 #define LPFC_HST_ISR3           0x0C24
 660 #define LPFC_HST_ISR4           0x0C28
 661
 662 #define LPFC_HST_IMR0           0x0C48
 663 #define LPFC_HST_IMR1           0x0C4C
 664 #define LPFC_HST_IMR2           0x0C50
 665 #define LPFC_HST_IMR3           0x0C54
 666 #define LPFC_HST_IMR4           0x0C58
 667
 668 #define LPFC_HST_ISCR0          0x0C78
 669 #define LPFC_HST_ISCR1          0x0C7C
 670 #define LPFC_HST_ISCR2          0x0C80
 671 #define LPFC_HST_ISCR3          0x0C84
 672 #define LPFC_HST_ISCR4          0x0C88
 673
 674 #define LPFC_SLI4_INTR0                 BIT0
 675 #define LPFC_SLI4_INTR1                 BIT1
 676 #define LPFC_SLI4_INTR2                 BIT2
 677 #define LPFC_SLI4_INTR3                 BIT3
 678 #define LPFC_SLI4_INTR4                 BIT4
 679 #define LPFC_SLI4_INTR5                 BIT5
 680 #define LPFC_SLI4_INTR6                 BIT6
 681 #define LPFC_SLI4_INTR7                 BIT7
 682 #define LPFC_SLI4_INTR8                 BIT8
 683 #define LPFC_SLI4_INTR9                 BIT9
 684 #define LPFC_SLI4_INTR10                BIT10
 685 #define LPFC_SLI4_INTR11                BIT11
 686 #define LPFC_SLI4_INTR12                BIT12
 687 #define LPFC_SLI4_INTR13                BIT13
 688 #define LPFC_SLI4_INTR14                BIT14
 689 #define LPFC_SLI4_INTR15                BIT15
 690 #define LPFC_SLI4_INTR16                BIT16
 691 #define LPFC_SLI4_INTR17                BIT17
 692 #define LPFC_SLI4_INTR18                BIT18
 693 #define LPFC_SLI4_INTR19                BIT19
 694 #define LPFC_SLI4_INTR20                BIT20
 695 #define LPFC_SLI4_INTR21                BIT21
 696 #define LPFC_SLI4_INTR22                BIT22
 697 #define LPFC_SLI4_INTR23                BIT23
 698 #define LPFC_SLI4_INTR24                BIT24
 699 #define LPFC_SLI4_INTR25                BIT25
 700 #define LPFC_SLI4_INTR26                BIT26
 701 #define LPFC_SLI4_INTR27                BIT27
 702 #define LPFC_SLI4_INTR28                BIT28
 703 #define LPFC_SLI4_INTR29                BIT29
 704 #define LPFC_SLI4_INTR30                BIT30
 705 #define LPFC_SLI4_INTR31                BIT31
 706
 707 /*
 708  * The Doorbell registers defined here exist in different BAR
 709  * register sets depending on the UCNA Port's reported if_type
 710  * value.  For UCNA ports running SLI4 and if_type 0, they reside in
 711  * BAR4.  For UCNA ports running SLI4 and if_type 2, they reside in
 712  * BAR0.  The offsets are the same so the driver must account for
 713  * any base address difference.
 714  */
 715 #define LPFC_ULP0_RQ_DOORBELL           0x00A0
 716 #define LPFC_ULP1_RQ_DOORBELL           0x00C0
 717 #define lpfc_rq_db_list_fm_num_posted_SHIFT     24
 718 #define lpfc_rq_db_list_fm_num_posted_MASK      0x00FF
 719 #define lpfc_rq_db_list_fm_num_posted_WORD      word0
 720 #define lpfc_rq_db_list_fm_index_SHIFT          16
 721 #define lpfc_rq_db_list_fm_index_MASK           0x00FF
 722 #define lpfc_rq_db_list_fm_index_WORD           word0
 723 #define lpfc_rq_db_list_fm_id_SHIFT             0
 724 #define lpfc_rq_db_list_fm_id_MASK              0xFFFF
 725 #define lpfc_rq_db_list_fm_id_WORD              word0
 726 #define lpfc_rq_db_ring_fm_num_posted_SHIFT     16
 727 #define lpfc_rq_db_ring_fm_num_posted_MASK      0x3FFF
 728 #define lpfc_rq_db_ring_fm_num_posted_WORD      word0
 729 #define lpfc_rq_db_ring_fm_id_SHIFT             0
 730 #define lpfc_rq_db_ring_fm_id_MASK              0xFFFF
 731 #define lpfc_rq_db_ring_fm_id_WORD              word0
 732
 733 #define LPFC_ULP0_WQ_DOORBELL           0x0040
 734 #define LPFC_ULP1_WQ_DOORBELL           0x0060
 735 #define lpfc_wq_db_list_fm_num_posted_SHIFT     24
 736 #define lpfc_wq_db_list_fm_num_posted_MASK      0x00FF
 737 #define lpfc_wq_db_list_fm_num_posted_WORD      word0
 738 #define lpfc_wq_db_list_fm_index_SHIFT          16
 739 #define lpfc_wq_db_list_fm_index_MASK           0x00FF
 740 #define lpfc_wq_db_list_fm_index_WORD           word0
 741 #define lpfc_wq_db_list_fm_id_SHIFT             0
 742 #define lpfc_wq_db_list_fm_id_MASK              0xFFFF
 743 #define lpfc_wq_db_list_fm_id_WORD              word0
 744 #define lpfc_wq_db_ring_fm_num_posted_SHIFT     16
 745 #define lpfc_wq_db_ring_fm_num_posted_MASK      0x3FFF
 746 #define lpfc_wq_db_ring_fm_num_posted_WORD      word0
 747 #define lpfc_wq_db_ring_fm_id_SHIFT             0
 748 #define lpfc_wq_db_ring_fm_id_MASK              0xFFFF
 749 #define lpfc_wq_db_ring_fm_id_WORD              word0
 750
 751 #define LPFC_EQCQ_DOORBELL              0x0120
 752 #define lpfc_eqcq_doorbell_se_SHIFT             31
 753 #define lpfc_eqcq_doorbell_se_MASK              0x0001
 754 #define lpfc_eqcq_doorbell_se_WORD              word0
 755 #define LPFC_EQCQ_SOLICIT_ENABLE_OFF    0
 756 #define LPFC_EQCQ_SOLICIT_ENABLE_ON     1
 757 #define lpfc_eqcq_doorbell_arm_SHIFT            29
 758 #define lpfc_eqcq_doorbell_arm_MASK             0x0001
 759 #define lpfc_eqcq_doorbell_arm_WORD             word0
 760 #define lpfc_eqcq_doorbell_num_released_SHIFT   16
 761 #define lpfc_eqcq_doorbell_num_released_MASK    0x1FFF
 762 #define lpfc_eqcq_doorbell_num_released_WORD    word0
 763 #define lpfc_eqcq_doorbell_qt_SHIFT             10
 764 #define lpfc_eqcq_doorbell_qt_MASK              0x0001
 765 #define lpfc_eqcq_doorbell_qt_WORD              word0
 766 #define LPFC_QUEUE_TYPE_COMPLETION      0
 767 #define LPFC_QUEUE_TYPE_EVENT           1
 768 #define lpfc_eqcq_doorbell_eqci_SHIFT           9
 769 #define lpfc_eqcq_doorbell_eqci_MASK            0x0001
 770 #define lpfc_eqcq_doorbell_eqci_WORD            word0
 771 #define lpfc_eqcq_doorbell_cqid_lo_SHIFT        0
 772 #define lpfc_eqcq_doorbell_cqid_lo_MASK         0x03FF
 773 #define lpfc_eqcq_doorbell_cqid_lo_WORD         word0
 774 #define lpfc_eqcq_doorbell_cqid_hi_SHIFT        11
 775 #define lpfc_eqcq_doorbell_cqid_hi_MASK         0x001F
 776 #define lpfc_eqcq_doorbell_cqid_hi_WORD         word0
 777 #define lpfc_eqcq_doorbell_eqid_lo_SHIFT        0
 778 #define lpfc_eqcq_doorbell_eqid_lo_MASK         0x01FF
 779 #define lpfc_eqcq_doorbell_eqid_lo_WORD         word0
 780 #define lpfc_eqcq_doorbell_eqid_hi_SHIFT        11
 781 #define lpfc_eqcq_doorbell_eqid_hi_MASK         0x001F
 782 #define lpfc_eqcq_doorbell_eqid_hi_WORD         word0
 783 #define LPFC_CQID_HI_FIELD_SHIFT                10
 784 #define LPFC_EQID_HI_FIELD_SHIFT                9
 785
 786 #define LPFC_BMBX                       0x0160
 787 #define lpfc_bmbx_addr_SHIFT            2
 788 #define lpfc_bmbx_addr_MASK             0x3FFFFFFF
 789 #define lpfc_bmbx_addr_WORD             word0
 790 #define lpfc_bmbx_hi_SHIFT              1
 791 #define lpfc_bmbx_hi_MASK               0x0001
 792 #define lpfc_bmbx_hi_WORD               word0
 793 #define lpfc_bmbx_rdy_SHIFT             0
 794 #define lpfc_bmbx_rdy_MASK              0x0001
 795 #define lpfc_bmbx_rdy_WORD              word0
 796
 797 #define LPFC_MQ_DOORBELL                        0x0140
 798 #define lpfc_mq_doorbell_num_posted_SHIFT       16
 799 #define lpfc_mq_doorbell_num_posted_MASK        0x3FFF
 800 #define lpfc_mq_doorbell_num_posted_WORD        word0
 801 #define lpfc_mq_doorbell_id_SHIFT               0
 802 #define lpfc_mq_doorbell_id_MASK                0xFFFF
 803 #define lpfc_mq_doorbell_id_WORD                word0
 804
 805 struct lpfc_sli4_cfg_mhdr {
 806         uint32_t word1;
 807 #define lpfc_mbox_hdr_emb_SHIFT         0
 808 #define lpfc_mbox_hdr_emb_MASK          0x00000001
 809 #define lpfc_mbox_hdr_emb_WORD          word1
 810 #define lpfc_mbox_hdr_sge_cnt_SHIFT     3
 811 #define lpfc_mbox_hdr_sge_cnt_MASK      0x0000001F
 812 #define lpfc_mbox_hdr_sge_cnt_WORD      word1
 813         uint32_t payload_length;
 814         uint32_t tag_lo;
 815         uint32_t tag_hi;
 816         uint32_t reserved5;
 817 };
 818
 819 union lpfc_sli4_cfg_shdr {
 820         struct {
 821                 uint32_t word6;
 822 #define lpfc_mbox_hdr_opcode_SHIFT      0
 823 #define lpfc_mbox_hdr_opcode_MASK       0x000000FF
 824 #define lpfc_mbox_hdr_opcode_WORD       word6
 825 #define lpfc_mbox_hdr_subsystem_SHIFT   8
 826 #define lpfc_mbox_hdr_subsystem_MASK    0x000000FF
 827 #define lpfc_mbox_hdr_subsystem_WORD    word6
 828 #define lpfc_mbox_hdr_port_number_SHIFT 16
 829 #define lpfc_mbox_hdr_port_number_MASK  0x000000FF
 830 #define lpfc_mbox_hdr_port_number_WORD  word6
 831 #define lpfc_mbox_hdr_domain_SHIFT      24
 832 #define lpfc_mbox_hdr_domain_MASK       0x000000FF
 833 #define lpfc_mbox_hdr_domain_WORD       word6
 834                 uint32_t timeout;
 835                 uint32_t request_length;
 836                 uint32_t word9;
 837 #define lpfc_mbox_hdr_version_SHIFT     0
 838 #define lpfc_mbox_hdr_version_MASK      0x000000FF
 839 #define lpfc_mbox_hdr_version_WORD      word9
 840 #define lpfc_mbox_hdr_pf_num_SHIFT      16
 841 #define lpfc_mbox_hdr_pf_num_MASK       0x000000FF
 842 #define lpfc_mbox_hdr_pf_num_WORD       word9
 843 #define lpfc_mbox_hdr_vh_num_SHIFT      24
 844 #define lpfc_mbox_hdr_vh_num_MASK       0x000000FF
 845 #define lpfc_mbox_hdr_vh_num_WORD       word9
 846 #define LPFC_Q_CREATE_VERSION_2 2
 847 #define LPFC_Q_CREATE_VERSION_1 1
 848 #define LPFC_Q_CREATE_VERSION_0 0
 849 #define LPFC_OPCODE_VERSION_0   0
 850 #define LPFC_OPCODE_VERSION_1   1
 851         } request;
 852         struct {
 853                 uint32_t word6;
 854 #define lpfc_mbox_hdr_opcode_SHIFT              0
 855 #define lpfc_mbox_hdr_opcode_MASK               0x000000FF
 856 #define lpfc_mbox_hdr_opcode_WORD               word6
 857 #define lpfc_mbox_hdr_subsystem_SHIFT           8
 858 #define lpfc_mbox_hdr_subsystem_MASK            0x000000FF
 859 #define lpfc_mbox_hdr_subsystem_WORD            word6
 860 #define lpfc_mbox_hdr_domain_SHIFT              24
 861 #define lpfc_mbox_hdr_domain_MASK               0x000000FF
 862 #define lpfc_mbox_hdr_domain_WORD               word6
 863                 uint32_t word7;
 864 #define lpfc_mbox_hdr_status_SHIFT              0
 865 #define lpfc_mbox_hdr_status_MASK               0x000000FF
 866 #define lpfc_mbox_hdr_status_WORD               word7
 867 #define lpfc_mbox_hdr_add_status_SHIFT          8
 868 #define lpfc_mbox_hdr_add_status_MASK           0x000000FF
 869 #define lpfc_mbox_hdr_add_status_WORD           word7
 870                 uint32_t response_length;
 871                 uint32_t actual_response_length;
 872         } response;
 873 };
 874
 875 /* Mailbox Header structures.
 876  * struct mbox_header is defined for first generation SLI4_CFG mailbox
 877  * calls deployed for BE-based ports.
 878  *
 879  * struct sli4_mbox_header is defined for second generation SLI4
 880  * ports that don't deploy the SLI4_CFG mechanism.
 881  */
 882 struct mbox_header {
 883         struct lpfc_sli4_cfg_mhdr cfg_mhdr;
 884         union  lpfc_sli4_cfg_shdr cfg_shdr;
 885 };
 886
 887 #define LPFC_EXTENT_LOCAL               0
 888 #define LPFC_TIMEOUT_DEFAULT            0
 889 #define LPFC_EXTENT_VERSION_DEFAULT     0
 890
 891 /* Subsystem Definitions */
 892 #define LPFC_MBOX_SUBSYSTEM_NA          0x0
 893 #define LPFC_MBOX_SUBSYSTEM_COMMON      0x1
 894 #define LPFC_MBOX_SUBSYSTEM_FCOE        0xC
 895
 896 /* Device Specific Definitions */
 897
 898 /* The HOST ENDIAN defines are in Big Endian format. */
 899 #define HOST_ENDIAN_LOW_WORD0   0xFF3412FF
 900 #define HOST_ENDIAN_HIGH_WORD1  0xFF7856FF
 901
 902 /* Common Opcodes */
 903 #define LPFC_MBOX_OPCODE_NA                             0x00
 904 #define LPFC_MBOX_OPCODE_CQ_CREATE                      0x0C
 905 #define LPFC_MBOX_OPCODE_EQ_CREATE                      0x0D
 906 #define LPFC_MBOX_OPCODE_MQ_CREATE                      0x15
 907 #define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES            0x20
 908 #define LPFC_MBOX_OPCODE_NOP                            0x21
 909 #define LPFC_MBOX_OPCODE_MODIFY_EQ_DELAY                0x29
 910 #define LPFC_MBOX_OPCODE_MQ_DESTROY                     0x35
 911 #define LPFC_MBOX_OPCODE_CQ_DESTROY                     0x36
 912 #define LPFC_MBOX_OPCODE_EQ_DESTROY                     0x37
 913 #define LPFC_MBOX_OPCODE_QUERY_FW_CFG                   0x3A
 914 #define LPFC_MBOX_OPCODE_FUNCTION_RESET                 0x3D
 915 #define LPFC_MBOX_OPCODE_SET_PHYSICAL_LINK_CONFIG       0x3E
 916 #define LPFC_MBOX_OPCODE_SET_BOOT_CONFIG                0x43
 917 #define LPFC_MBOX_OPCODE_SET_BEACON_CONFIG              0x45
 918 #define LPFC_MBOX_OPCODE_GET_BEACON_CONFIG              0x46
 919 #define LPFC_MBOX_OPCODE_GET_PORT_NAME                  0x4D
 920 #define LPFC_MBOX_OPCODE_MQ_CREATE_EXT                  0x5A
 921 #define LPFC_MBOX_OPCODE_GET_VPD_DATA                   0x5B
 922 #define LPFC_MBOX_OPCODE_SEND_ACTIVATION                0x73
 923 #define LPFC_MBOX_OPCODE_RESET_LICENSES                 0x74
 924 #define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO           0x9A
 925 #define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT          0x9B
 926 #define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT              0x9C
 927 #define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT            0x9D
 928 #define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG            0xA0
 929 #define LPFC_MBOX_OPCODE_GET_PROFILE_CAPACITIES         0xA1
 930 #define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG             0xA4
 931 #define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG             0xA5
 932 #define LPFC_MBOX_OPCODE_GET_PROFILE_LIST               0xA6
 933 #define LPFC_MBOX_OPCODE_SET_ACT_PROFILE                0xA8
 934 #define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG     0xA9
 935 #define LPFC_MBOX_OPCODE_READ_OBJECT                    0xAB
 936 #define LPFC_MBOX_OPCODE_WRITE_OBJECT                   0xAC
 937 #define LPFC_MBOX_OPCODE_READ_OBJECT_LIST               0xAD
 938 #define LPFC_MBOX_OPCODE_DELETE_OBJECT                  0xAE
 939 #define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS            0xB5
 940
 941 /* FCoE Opcodes */
 942 #define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE                 0x01
 943 #define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY                0x02
 944 #define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES            0x03
 945 #define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES          0x04
 946 #define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE                 0x05
 947 #define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY                0x06
 948 #define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE            0x08
 949 #define LPFC_MBOX_OPCODE_FCOE_ADD_FCF                   0x09
 950 #define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF                0x0A
 951 #define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE         0x0B
 952 #define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF            0x10
 953 #define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS       0x21
 954 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE           0x22
 955 #define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK        0x23
 956
 957 /* Mailbox command structures */
 958 struct eq_context {
 959         uint32_t word0;
 960 #define lpfc_eq_context_size_SHIFT      31
 961 #define lpfc_eq_context_size_MASK       0x00000001
 962 #define lpfc_eq_context_size_WORD       word0
 963 #define LPFC_EQE_SIZE_4                 0x0
 964 #define LPFC_EQE_SIZE_16                0x1
 965 #define lpfc_eq_context_valid_SHIFT     29
 966 #define lpfc_eq_context_valid_MASK      0x00000001
 967 #define lpfc_eq_context_valid_WORD      word0
 968         uint32_t word1;
 969 #define lpfc_eq_context_count_SHIFT     26
 970 #define lpfc_eq_context_count_MASK      0x00000003
 971 #define lpfc_eq_context_count_WORD      word1
 972 #define LPFC_EQ_CNT_256         0x0
 973 #define LPFC_EQ_CNT_512         0x1
 974 #define LPFC_EQ_CNT_1024        0x2
 975 #define LPFC_EQ_CNT_2048        0x3
 976 #define LPFC_EQ_CNT_4096        0x4
 977         uint32_t word2;
 978 #define lpfc_eq_context_delay_multi_SHIFT       13
 979 #define lpfc_eq_context_delay_multi_MASK        0x000003FF
 980 #define lpfc_eq_context_delay_multi_WORD        word2
 981         uint32_t reserved3;
 982 };
 983
 984 struct eq_delay_info {
 985         uint32_t eq_id;
 986         uint32_t phase;
 987         uint32_t delay_multi;
 988 };
 989 #define LPFC_MAX_EQ_DELAY       8
 990
 991 struct sgl_page_pairs {
 992         uint32_t sgl_pg0_addr_lo;
 993         uint32_t sgl_pg0_addr_hi;
 994         uint32_t sgl_pg1_addr_lo;
 995         uint32_t sgl_pg1_addr_hi;
 996 };
 997
 998 struct lpfc_mbx_post_sgl_pages {
 999         struct mbox_header header;
1000         uint32_t word0;
1001 #define lpfc_post_sgl_pages_xri_SHIFT   0
1002 #define lpfc_post_sgl_pages_xri_MASK    0x0000FFFF
1003 #define lpfc_post_sgl_pages_xri_WORD    word0
1004 #define lpfc_post_sgl_pages_xricnt_SHIFT        16
1005 #define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF
1006 #define lpfc_post_sgl_pages_xricnt_WORD word0
1007         struct sgl_page_pairs  sgl_pg_pairs[1];
1008 };
1009
1010 /* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */
1011 struct lpfc_mbx_post_uembed_sgl_page1 {
1012         union  lpfc_sli4_cfg_shdr cfg_shdr;
1013         uint32_t word0;
1014         struct sgl_page_pairs sgl_pg_pairs;
1015 };
1016
1017 struct lpfc_mbx_sge {
1018         uint32_t pa_lo;
1019         uint32_t pa_hi;
1020         uint32_t length;
1021 };
1022
1023 struct lpfc_mbx_nembed_cmd {
1024         struct lpfc_sli4_cfg_mhdr cfg_mhdr;
1025 #define LPFC_SLI4_MBX_SGE_MAX_PAGES     19
1026         struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES];
1027 };
1028
1029 struct lpfc_mbx_nembed_sge_virt {
1030         void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES];
1031 };
1032
1033 struct lpfc_mbx_eq_create {
1034         struct mbox_header header;
1035         union {
1036                 struct {
1037                         uint32_t word0;
1038 #define lpfc_mbx_eq_create_num_pages_SHIFT      0
1039 #define lpfc_mbx_eq_create_num_pages_MASK       0x0000FFFF
1040 #define lpfc_mbx_eq_create_num_pages_WORD       word0
1041                         struct eq_context context;
1042                         struct dma_address page[LPFC_MAX_EQ_PAGE];
1043                 } request;
1044                 struct {
1045                         uint32_t word0;
1046 #define lpfc_mbx_eq_create_q_id_SHIFT   0
1047 #define lpfc_mbx_eq_create_q_id_MASK    0x0000FFFF
1048 #define lpfc_mbx_eq_create_q_id_WORD    word0
1049                 } response;
1050         } u;
1051 };
1052
1053 struct lpfc_mbx_modify_eq_delay {
1054         struct mbox_header header;
1055         union {
1056                 struct {
1057                         uint32_t num_eq;
1058                         struct eq_delay_info eq[LPFC_MAX_EQ_DELAY];
1059                 } request;
1060                 struct {
1061                         uint32_t word0;
1062                 } response;
1063         } u;
1064 };
1065
1066 struct lpfc_mbx_eq_destroy {
1067         struct mbox_header header;
1068         union {
1069                 struct {
1070                         uint32_t word0;
1071 #define lpfc_mbx_eq_destroy_q_id_SHIFT  0
1072 #define lpfc_mbx_eq_destroy_q_id_MASK   0x0000FFFF
1073 #define lpfc_mbx_eq_destroy_q_id_WORD   word0
1074                 } request;
1075                 struct {
1076                         uint32_t word0;
1077                 } response;
1078         } u;
1079 };
1080
1081 struct lpfc_mbx_nop {
1082         struct mbox_header header;
1083         uint32_t context[2];
1084 };
1085
1086 struct cq_context {
1087         uint32_t word0;
1088 #define lpfc_cq_context_event_SHIFT     31
1089 #define lpfc_cq_context_event_MASK      0x00000001
1090 #define lpfc_cq_context_event_WORD      word0
1091 #define lpfc_cq_context_valid_SHIFT     29
1092 #define lpfc_cq_context_valid_MASK      0x00000001
1093 #define lpfc_cq_context_valid_WORD      word0
1094 #define lpfc_cq_context_count_SHIFT     27
1095 #define lpfc_cq_context_count_MASK      0x00000003
1096 #define lpfc_cq_context_count_WORD      word0
1097 #define LPFC_CQ_CNT_256         0x0
1098 #define LPFC_CQ_CNT_512         0x1
1099 #define LPFC_CQ_CNT_1024        0x2
1100         uint32_t word1;
1101 #define lpfc_cq_eq_id_SHIFT             22      /* Version 0 Only */
1102 #define lpfc_cq_eq_id_MASK              0x000000FF
1103 #define lpfc_cq_eq_id_WORD              word1
1104 #define lpfc_cq_eq_id_2_SHIFT           0       /* Version 2 Only */
1105 #define lpfc_cq_eq_id_2_MASK            0x0000FFFF
1106 #define lpfc_cq_eq_id_2_WORD            word1
1107         uint32_t reserved0;
1108         uint32_t reserved1;
1109 };
1110
1111 struct lpfc_mbx_cq_create {
1112         struct mbox_header header;
1113         union {
1114                 struct {
1115                         uint32_t word0;
1116 #define lpfc_mbx_cq_create_page_size_SHIFT      16      /* Version 2 Only */
1117 #define lpfc_mbx_cq_create_page_size_MASK       0x000000FF
1118 #define lpfc_mbx_cq_create_page_size_WORD       word0
1119 #define lpfc_mbx_cq_create_num_pages_SHIFT      0
1120 #define lpfc_mbx_cq_create_num_pages_MASK       0x0000FFFF
1121 #define lpfc_mbx_cq_create_num_pages_WORD       word0
1122                         struct cq_context context;
1123                         struct dma_address page[LPFC_MAX_CQ_PAGE];
1124                 } request;
1125                 struct {
1126                         uint32_t word0;
1127 #define lpfc_mbx_cq_create_q_id_SHIFT   0
1128 #define lpfc_mbx_cq_create_q_id_MASK    0x0000FFFF
1129 #define lpfc_mbx_cq_create_q_id_WORD    word0
1130                 } response;
1131         } u;
1132 };
1133
1134 struct lpfc_mbx_cq_destroy {
1135         struct mbox_header header;
1136         union {
1137                 struct {
1138                         uint32_t word0;
1139 #define lpfc_mbx_cq_destroy_q_id_SHIFT  0
1140 #define lpfc_mbx_cq_destroy_q_id_MASK   0x0000FFFF
1141 #define lpfc_mbx_cq_destroy_q_id_WORD   word0
1142                 } request;
1143                 struct {
1144                         uint32_t word0;
1145                 } response;
1146         } u;
1147 };
1148
1149 struct wq_context {
1150         uint32_t reserved0;
1151         uint32_t reserved1;
1152         uint32_t reserved2;
1153         uint32_t reserved3;
1154 };
1155
1156 struct lpfc_mbx_wq_create {
1157         struct mbox_header header;
1158         union {
1159                 struct {        /* Version 0 Request */
1160                         uint32_t word0;
1161 #define lpfc_mbx_wq_create_num_pages_SHIFT      0
1162 #define lpfc_mbx_wq_create_num_pages_MASK       0x000000FF
1163 #define lpfc_mbx_wq_create_num_pages_WORD       word0
1164 #define lpfc_mbx_wq_create_dua_SHIFT            8
1165 #define lpfc_mbx_wq_create_dua_MASK             0x00000001
1166 #define lpfc_mbx_wq_create_dua_WORD             word0
1167 #define lpfc_mbx_wq_create_cq_id_SHIFT          16
1168 #define lpfc_mbx_wq_create_cq_id_MASK           0x0000FFFF
1169 #define lpfc_mbx_wq_create_cq_id_WORD           word0
1170                         struct dma_address page[LPFC_MAX_WQ_PAGE_V0];
1171                         uint32_t word9;
1172 #define lpfc_mbx_wq_create_bua_SHIFT            0
1173 #define lpfc_mbx_wq_create_bua_MASK             0x00000001
1174 #define lpfc_mbx_wq_create_bua_WORD             word9
1175 #define lpfc_mbx_wq_create_ulp_num_SHIFT        8
1176 #define lpfc_mbx_wq_create_ulp_num_MASK         0x000000FF
1177 #define lpfc_mbx_wq_create_ulp_num_WORD         word9
1178                 } request;
1179                 struct {        /* Version 1 Request */
1180                         uint32_t word0; /* Word 0 is the same as in v0 */
1181                         uint32_t word1;
1182 #define lpfc_mbx_wq_create_page_size_SHIFT      0
1183 #define lpfc_mbx_wq_create_page_size_MASK       0x000000FF
1184 #define lpfc_mbx_wq_create_page_size_WORD       word1
1185 #define LPFC_WQ_PAGE_SIZE_4096  0x1
1186 #define lpfc_mbx_wq_create_wqe_size_SHIFT       8
1187 #define lpfc_mbx_wq_create_wqe_size_MASK        0x0000000F
1188 #define lpfc_mbx_wq_create_wqe_size_WORD        word1
1189 #define LPFC_WQ_WQE_SIZE_64     0x5
1190 #define LPFC_WQ_WQE_SIZE_128    0x6
1191 #define lpfc_mbx_wq_create_wqe_count_SHIFT      16
1192 #define lpfc_mbx_wq_create_wqe_count_MASK       0x0000FFFF
1193 #define lpfc_mbx_wq_create_wqe_count_WORD       word1
1194                         uint32_t word2;
1195                         struct dma_address page[LPFC_MAX_WQ_PAGE-1];
1196                 } request_1;
1197                 struct {
1198                         uint32_t word0;
1199 #define lpfc_mbx_wq_create_q_id_SHIFT   0
1200 #define lpfc_mbx_wq_create_q_id_MASK    0x0000FFFF
1201 #define lpfc_mbx_wq_create_q_id_WORD    word0
1202                         uint32_t doorbell_offset;
1203                         uint32_t word2;
1204 #define lpfc_mbx_wq_create_bar_set_SHIFT        0
1205 #define lpfc_mbx_wq_create_bar_set_MASK         0x0000FFFF
1206 #define lpfc_mbx_wq_create_bar_set_WORD         word2
1207 #define WQ_PCI_BAR_0_AND_1      0x00
1208 #define WQ_PCI_BAR_2_AND_3      0x01
1209 #define WQ_PCI_BAR_4_AND_5      0x02
1210 #define lpfc_mbx_wq_create_db_format_SHIFT      16
1211 #define lpfc_mbx_wq_create_db_format_MASK       0x0000FFFF
1212 #define lpfc_mbx_wq_create_db_format_WORD       word2
1213                 } response;
1214         } u;
1215 };
1216
1217 struct lpfc_mbx_wq_destroy {
1218         struct mbox_header header;
1219         union {
1220                 struct {
1221                         uint32_t word0;
1222 #define lpfc_mbx_wq_destroy_q_id_SHIFT  0
1223 #define lpfc_mbx_wq_destroy_q_id_MASK   0x0000FFFF
1224 #define lpfc_mbx_wq_destroy_q_id_WORD   word0
1225                 } request;
1226                 struct {
1227                         uint32_t word0;
1228                 } response;
1229         } u;
1230 };
1231
1232 #define LPFC_HDR_BUF_SIZE 128
1233 #define LPFC_DATA_BUF_SIZE 2048
1234 struct rq_context {
1235         uint32_t word0;
1236 #define lpfc_rq_context_rqe_count_SHIFT 16      /* Version 0 Only */
1237 #define lpfc_rq_context_rqe_count_MASK  0x0000000F
1238 #define lpfc_rq_context_rqe_count_WORD  word0
1239 #define LPFC_RQ_RING_SIZE_512           9       /* 512 entries */
1240 #define LPFC_RQ_RING_SIZE_1024          10      /* 1024 entries */
1241 #define LPFC_RQ_RING_SIZE_2048          11      /* 2048 entries */
1242 #define LPFC_RQ_RING_SIZE_4096          12      /* 4096 entries */
1243 #define lpfc_rq_context_rqe_count_1_SHIFT       16      /* Version 1 Only */
1244 #define lpfc_rq_context_rqe_count_1_MASK        0x0000FFFF
1245 #define lpfc_rq_context_rqe_count_1_WORD        word0
1246 #define lpfc_rq_context_rqe_size_SHIFT  8               /* Version 1 Only */
1247 #define lpfc_rq_context_rqe_size_MASK   0x0000000F
1248 #define lpfc_rq_context_rqe_size_WORD   word0
1249 #define LPFC_RQE_SIZE_8         2
1250 #define LPFC_RQE_SIZE_16        3
1251 #define LPFC_RQE_SIZE_32        4
1252 #define LPFC_RQE_SIZE_64        5
1253 #define LPFC_RQE_SIZE_128       6
1254 #define lpfc_rq_context_page_size_SHIFT 0               /* Version 1 Only */
1255 #define lpfc_rq_context_page_size_MASK  0x000000FF
1256 #define lpfc_rq_context_page_size_WORD  word0
1257 #define LPFC_RQ_PAGE_SIZE_4096  0x1
1258         uint32_t reserved1;
1259         uint32_t word2;
1260 #define lpfc_rq_context_cq_id_SHIFT     16
1261 #define lpfc_rq_context_cq_id_MASK      0x000003FF
1262 #define lpfc_rq_context_cq_id_WORD      word2
1263 #define lpfc_rq_context_buf_size_SHIFT  0
1264 #define lpfc_rq_context_buf_size_MASK   0x0000FFFF
1265 #define lpfc_rq_context_buf_size_WORD   word2
1266         uint32_t buffer_size;                           /* Version 1 Only */
1267 };
1268
1269 struct lpfc_mbx_rq_create {
1270         struct mbox_header header;
1271         union {
1272                 struct {
1273                         uint32_t word0;
1274 #define lpfc_mbx_rq_create_num_pages_SHIFT      0
1275 #define lpfc_mbx_rq_create_num_pages_MASK       0x0000FFFF
1276 #define lpfc_mbx_rq_create_num_pages_WORD       word0
1277 #define lpfc_mbx_rq_create_dua_SHIFT            16
1278 #define lpfc_mbx_rq_create_dua_MASK             0x00000001
1279 #define lpfc_mbx_rq_create_dua_WORD             word0
1280 #define lpfc_mbx_rq_create_bqu_SHIFT            17
1281 #define lpfc_mbx_rq_create_bqu_MASK             0x00000001
1282 #define lpfc_mbx_rq_create_bqu_WORD             word0
1283 #define lpfc_mbx_rq_create_ulp_num_SHIFT        24
1284 #define lpfc_mbx_rq_create_ulp_num_MASK         0x000000FF
1285 #define lpfc_mbx_rq_create_ulp_num_WORD         word0
1286                         struct rq_context context;
1287                         struct dma_address page[LPFC_MAX_WQ_PAGE];
1288                 } request;
1289                 struct {
1290                         uint32_t word0;
1291 #define lpfc_mbx_rq_create_q_id_SHIFT           0
1292 #define lpfc_mbx_rq_create_q_id_MASK            0x0000FFFF
1293 #define lpfc_mbx_rq_create_q_id_WORD            word0
1294                         uint32_t doorbell_offset;
1295                         uint32_t word2;
1296 #define lpfc_mbx_rq_create_bar_set_SHIFT        0
1297 #define lpfc_mbx_rq_create_bar_set_MASK         0x0000FFFF
1298 #define lpfc_mbx_rq_create_bar_set_WORD         word2
1299 #define lpfc_mbx_rq_create_db_format_SHIFT      16
1300 #define lpfc_mbx_rq_create_db_format_MASK       0x0000FFFF
1301 #define lpfc_mbx_rq_create_db_format_WORD       word2
1302                 } response;
1303         } u;
1304 };
1305
1306 struct lpfc_mbx_rq_destroy {
1307         struct mbox_header header;
1308         union {
1309                 struct {
1310                         uint32_t word0;
1311 #define lpfc_mbx_rq_destroy_q_id_SHIFT  0
1312 #define lpfc_mbx_rq_destroy_q_id_MASK   0x0000FFFF
1313 #define lpfc_mbx_rq_destroy_q_id_WORD   word0
1314                 } request;
1315                 struct {
1316                         uint32_t word0;
1317                 } response;
1318         } u;
1319 };
1320
1321 struct mq_context {
1322         uint32_t word0;
1323 #define lpfc_mq_context_cq_id_SHIFT     22      /* Version 0 Only */
1324 #define lpfc_mq_context_cq_id_MASK      0x000003FF
1325 #define lpfc_mq_context_cq_id_WORD      word0
1326 #define lpfc_mq_context_ring_size_SHIFT 16
1327 #define lpfc_mq_context_ring_size_MASK  0x0000000F
1328 #define lpfc_mq_context_ring_size_WORD  word0
1329 #define LPFC_MQ_RING_SIZE_16            0x5
1330 #define LPFC_MQ_RING_SIZE_32            0x6
1331 #define LPFC_MQ_RING_SIZE_64            0x7
1332 #define LPFC_MQ_RING_SIZE_128           0x8
1333         uint32_t word1;
1334 #define lpfc_mq_context_valid_SHIFT     31
1335 #define lpfc_mq_context_valid_MASK      0x00000001
1336 #define lpfc_mq_context_valid_WORD      word1
1337         uint32_t reserved2;
1338         uint32_t reserved3;
1339 };
1340
1341 struct lpfc_mbx_mq_create {
1342         struct mbox_header header;
1343         union {
1344                 struct {
1345                         uint32_t word0;
1346 #define lpfc_mbx_mq_create_num_pages_SHIFT      0
1347 #define lpfc_mbx_mq_create_num_pages_MASK       0x0000FFFF
1348 #define lpfc_mbx_mq_create_num_pages_WORD       word0
1349                         struct mq_context context;
1350                         struct dma_address page[LPFC_MAX_MQ_PAGE];
1351                 } request;
1352                 struct {
1353                         uint32_t word0;
1354 #define lpfc_mbx_mq_create_q_id_SHIFT   0
1355 #define lpfc_mbx_mq_create_q_id_MASK    0x0000FFFF
1356 #define lpfc_mbx_mq_create_q_id_WORD    word0
1357                 } response;
1358         } u;
1359 };
1360
1361 struct lpfc_mbx_mq_create_ext {
1362         struct mbox_header header;
1363         union {
1364                 struct {
1365                         uint32_t word0;
1366 #define lpfc_mbx_mq_create_ext_num_pages_SHIFT  0
1367 #define lpfc_mbx_mq_create_ext_num_pages_MASK   0x0000FFFF
1368 #define lpfc_mbx_mq_create_ext_num_pages_WORD   word0
1369 #define lpfc_mbx_mq_create_ext_cq_id_SHIFT      16      /* Version 1 Only */
1370 #define lpfc_mbx_mq_create_ext_cq_id_MASK       0x0000FFFF
1371 #define lpfc_mbx_mq_create_ext_cq_id_WORD       word0
1372                         uint32_t async_evt_bmap;
1373 #define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT     LPFC_TRAILER_CODE_LINK
1374 #define lpfc_mbx_mq_create_ext_async_evt_link_MASK      0x00000001
1375 #define lpfc_mbx_mq_create_ext_async_evt_link_WORD      async_evt_bmap
1376 #define LPFC_EVT_CODE_LINK_NO_LINK      0x0
1377 #define LPFC_EVT_CODE_LINK_10_MBIT      0x1
1378 #define LPFC_EVT_CODE_LINK_100_MBIT     0x2
1379 #define LPFC_EVT_CODE_LINK_1_GBIT       0x3
1380 #define LPFC_EVT_CODE_LINK_10_GBIT      0x4
1381 #define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT      LPFC_TRAILER_CODE_FCOE
1382 #define lpfc_mbx_mq_create_ext_async_evt_fip_MASK       0x00000001
1383 #define lpfc_mbx_mq_create_ext_async_evt_fip_WORD       async_evt_bmap
1384 #define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT   LPFC_TRAILER_CODE_GRP5
1385 #define lpfc_mbx_mq_create_ext_async_evt_group5_MASK    0x00000001
1386 #define lpfc_mbx_mq_create_ext_async_evt_group5_WORD    async_evt_bmap
1387 #define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT       LPFC_TRAILER_CODE_FC
1388 #define lpfc_mbx_mq_create_ext_async_evt_fc_MASK        0x00000001
1389 #define lpfc_mbx_mq_create_ext_async_evt_fc_WORD        async_evt_bmap
1390 #define LPFC_EVT_CODE_FC_NO_LINK        0x0
1391 #define LPFC_EVT_CODE_FC_1_GBAUD        0x1
1392 #define LPFC_EVT_CODE_FC_2_GBAUD        0x2
1393 #define LPFC_EVT_CODE_FC_4_GBAUD        0x4
1394 #define LPFC_EVT_CODE_FC_8_GBAUD        0x8
1395 #define LPFC_EVT_CODE_FC_10_GBAUD       0xA
1396 #define LPFC_EVT_CODE_FC_16_GBAUD       0x10
1397 #define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT      LPFC_TRAILER_CODE_SLI
1398 #define lpfc_mbx_mq_create_ext_async_evt_sli_MASK       0x00000001
1399 #define lpfc_mbx_mq_create_ext_async_evt_sli_WORD       async_evt_bmap
1400                         struct mq_context context;
1401                         struct dma_address page[LPFC_MAX_MQ_PAGE];
1402                 } request;
1403                 struct {
1404                         uint32_t word0;
1405 #define lpfc_mbx_mq_create_q_id_SHIFT   0
1406 #define lpfc_mbx_mq_create_q_id_MASK    0x0000FFFF
1407 #define lpfc_mbx_mq_create_q_id_WORD    word0
1408                 } response;
1409         } u;
1410 #define LPFC_ASYNC_EVENT_LINK_STATE     0x2
1411 #define LPFC_ASYNC_EVENT_FCF_STATE      0x4
1412 #define LPFC_ASYNC_EVENT_GROUP5         0x20
1413 };
1414
1415 struct lpfc_mbx_mq_destroy {
1416         struct mbox_header header;
1417         union {
1418                 struct {
1419                         uint32_t word0;
1420 #define lpfc_mbx_mq_destroy_q_id_SHIFT  0
1421 #define lpfc_mbx_mq_destroy_q_id_MASK   0x0000FFFF
1422 #define lpfc_mbx_mq_destroy_q_id_WORD   word0
1423                 } request;
1424                 struct {
1425                         uint32_t word0;
1426                 } response;
1427         } u;
1428 };
1429
1430 /* Start Gen 2 SLI4 Mailbox definitions: */
1431
1432 /* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */
1433 #define LPFC_RSC_TYPE_FCOE_VFI  0x20
1434 #define LPFC_RSC_TYPE_FCOE_VPI  0x21
1435 #define LPFC_RSC_TYPE_FCOE_RPI  0x22
1436 #define LPFC_RSC_TYPE_FCOE_XRI  0x23
1437
1438 struct lpfc_mbx_get_rsrc_extent_info {
1439         struct mbox_header header;
1440         union {
1441                 struct {
1442                         uint32_t word4;
1443 #define lpfc_mbx_get_rsrc_extent_info_type_SHIFT        0
1444 #define lpfc_mbx_get_rsrc_extent_info_type_MASK         0x0000FFFF
1445 #define lpfc_mbx_get_rsrc_extent_info_type_WORD         word4
1446                 } req;
1447                 struct {
1448                         uint32_t word4;
1449 #define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT         0
1450 #define lpfc_mbx_get_rsrc_extent_info_cnt_MASK          0x0000FFFF
1451 #define lpfc_mbx_get_rsrc_extent_info_cnt_WORD          word4
1452 #define lpfc_mbx_get_rsrc_extent_info_size_SHIFT        16
1453 #define lpfc_mbx_get_rsrc_extent_info_size_MASK         0x0000FFFF
1454 #define lpfc_mbx_get_rsrc_extent_info_size_WORD         word4
1455                 } rsp;
1456         } u;
1457 };
1458
1459 struct lpfc_mbx_query_fw_config {
1460         struct mbox_header header;
1461         struct {
1462                 uint32_t config_number;
1463 #define LPFC_FC_FCOE            0x00000007
1464                 uint32_t asic_revision;
1465                 uint32_t physical_port;
1466                 uint32_t function_mode;
1467 #define LPFC_FCOE_INI_MODE      0x00000040
1468 #define LPFC_FCOE_TGT_MODE      0x00000080
1469 #define LPFC_DUA_MODE           0x00000800
1470                 uint32_t ulp0_mode;
1471 #define LPFC_ULP_FCOE_INIT_MODE 0x00000040
1472 #define LPFC_ULP_FCOE_TGT_MODE  0x00000080
1473                 uint32_t ulp0_nap_words[12];
1474                 uint32_t ulp1_mode;
1475                 uint32_t ulp1_nap_words[12];
1476                 uint32_t function_capabilities;
1477                 uint32_t cqid_base;
1478                 uint32_t cqid_tot;
1479                 uint32_t eqid_base;
1480                 uint32_t eqid_tot;
1481                 uint32_t ulp0_nap2_words[2];
1482                 uint32_t ulp1_nap2_words[2];
1483         } rsp;
1484 };
1485
1486 struct lpfc_mbx_set_beacon_config {
1487         struct mbox_header header;
1488         uint32_t word4;
1489 #define lpfc_mbx_set_beacon_port_num_SHIFT              0
1490 #define lpfc_mbx_set_beacon_port_num_MASK               0x0000003F
1491 #define lpfc_mbx_set_beacon_port_num_WORD               word4
1492 #define lpfc_mbx_set_beacon_port_type_SHIFT             6
1493 #define lpfc_mbx_set_beacon_port_type_MASK              0x00000003
1494 #define lpfc_mbx_set_beacon_port_type_WORD              word4
1495 #define lpfc_mbx_set_beacon_state_SHIFT                 8
1496 #define lpfc_mbx_set_beacon_state_MASK                  0x000000FF
1497 #define lpfc_mbx_set_beacon_state_WORD                  word4
1498 #define lpfc_mbx_set_beacon_duration_SHIFT              16
1499 #define lpfc_mbx_set_beacon_duration_MASK               0x000000FF
1500 #define lpfc_mbx_set_beacon_duration_WORD               word4
1501 #define lpfc_mbx_set_beacon_status_duration_SHIFT       24
1502 #define lpfc_mbx_set_beacon_status_duration_MASK        0x000000FF
1503 #define lpfc_mbx_set_beacon_status_duration_WORD        word4
1504 };
1505
1506 struct lpfc_id_range {
1507         uint32_t word5;
1508 #define lpfc_mbx_rsrc_id_word4_0_SHIFT  0
1509 #define lpfc_mbx_rsrc_id_word4_0_MASK   0x0000FFFF
1510 #define lpfc_mbx_rsrc_id_word4_0_WORD   word5
1511 #define lpfc_mbx_rsrc_id_word4_1_SHIFT  16
1512 #define lpfc_mbx_rsrc_id_word4_1_MASK   0x0000FFFF
1513 #define lpfc_mbx_rsrc_id_word4_1_WORD   word5
1514 };
1515
1516 struct lpfc_mbx_set_link_diag_state {
1517         struct mbox_header header;
1518         union {
1519                 struct {
1520                         uint32_t word0;
1521 #define lpfc_mbx_set_diag_state_diag_SHIFT      0
1522 #define lpfc_mbx_set_diag_state_diag_MASK       0x00000001
1523 #define lpfc_mbx_set_diag_state_diag_WORD       word0
1524 #define lpfc_mbx_set_diag_state_diag_bit_valid_SHIFT    2
1525 #define lpfc_mbx_set_diag_state_diag_bit_valid_MASK     0x00000001
1526 #define lpfc_mbx_set_diag_state_diag_bit_valid_WORD     word0
1527 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_NO_CHANGE        0
1528 #define LPFC_DIAG_STATE_DIAG_BIT_VALID_CHANGE           1
1529 #define lpfc_mbx_set_diag_state_link_num_SHIFT  16
1530 #define lpfc_mbx_set_diag_state_link_num_MASK   0x0000003F
1531 #define lpfc_mbx_set_diag_state_link_num_WORD   word0
1532 #define lpfc_mbx_set_diag_state_link_type_SHIFT 22
1533 #define lpfc_mbx_set_diag_state_link_type_MASK  0x00000003
1534 #define lpfc_mbx_set_diag_state_link_type_WORD  word0
1535                 } req;
1536                 struct {
1537                         uint32_t word0;
1538                 } rsp;
1539         } u;
1540 };
1541
1542 struct lpfc_mbx_set_link_diag_loopback {
1543         struct mbox_header header;
1544         union {
1545                 struct {
1546                         uint32_t word0;
1547 #define lpfc_mbx_set_diag_lpbk_type_SHIFT       0
1548 #define lpfc_mbx_set_diag_lpbk_type_MASK        0x00000003
1549 #define lpfc_mbx_set_diag_lpbk_type_WORD        word0
1550 #define LPFC_DIAG_LOOPBACK_TYPE_DISABLE         0x0
1551 #define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL        0x1
1552 #define LPFC_DIAG_LOOPBACK_TYPE_SERDES          0x2
1553 #define lpfc_mbx_set_diag_lpbk_link_num_SHIFT   16
1554 #define lpfc_mbx_set_diag_lpbk_link_num_MASK    0x0000003F
1555 #define lpfc_mbx_set_diag_lpbk_link_num_WORD    word0
1556 #define lpfc_mbx_set_diag_lpbk_link_type_SHIFT  22
1557 #define lpfc_mbx_set_diag_lpbk_link_type_MASK   0x00000003
1558 #define lpfc_mbx_set_diag_lpbk_link_type_WORD   word0
1559                 } req;
1560                 struct {
1561                         uint32_t word0;
1562                 } rsp;
1563         } u;
1564 };
1565
1566 struct lpfc_mbx_run_link_diag_test {
1567         struct mbox_header header;
1568         union {
1569                 struct {
1570                         uint32_t word0;
1571 #define lpfc_mbx_run_diag_test_link_num_SHIFT   16
1572 #define lpfc_mbx_run_diag_test_link_num_MASK    0x0000003F
1573 #define lpfc_mbx_run_diag_test_link_num_WORD    word0
1574 #define lpfc_mbx_run_diag_test_link_type_SHIFT  22
1575 #define lpfc_mbx_run_diag_test_link_type_MASK   0x00000003
1576 #define lpfc_mbx_run_diag_test_link_type_WORD   word0
1577                         uint32_t word1;
1578 #define lpfc_mbx_run_diag_test_test_id_SHIFT    0
1579 #define lpfc_mbx_run_diag_test_test_id_MASK     0x0000FFFF
1580 #define lpfc_mbx_run_diag_test_test_id_WORD     word1
1581 #define lpfc_mbx_run_diag_test_loops_SHIFT      16
1582 #define lpfc_mbx_run_diag_test_loops_MASK       0x0000FFFF
1583 #define lpfc_mbx_run_diag_test_loops_WORD       word1
1584                         uint32_t word2;
1585 #define lpfc_mbx_run_diag_test_test_ver_SHIFT   0
1586 #define lpfc_mbx_run_diag_test_test_ver_MASK    0x0000FFFF
1587 #define lpfc_mbx_run_diag_test_test_ver_WORD    word2
1588 #define lpfc_mbx_run_diag_test_err_act_SHIFT    16
1589 #define lpfc_mbx_run_diag_test_err_act_MASK     0x000000FF
1590 #define lpfc_mbx_run_diag_test_err_act_WORD     word2
1591                 } req;
1592                 struct {
1593                         uint32_t word0;
1594                 } rsp;
1595         } u;
1596 };
1597
1598 /*
1599  * struct lpfc_mbx_alloc_rsrc_extents:
1600  * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires
1601  * 6 words of header + 4 words of shared subcommand header +
1602  * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total.
1603  *
1604  * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes
1605  * for extents payload.
1606  *
1607  * 212/2 (bytes per extent) = 106 extents.
1608  * 106/2 (extents per word) = 53 words.
1609  * lpfc_id_range id is statically size to 53.
1610  *
1611  * This mailbox definition is used for ALLOC or GET_ALLOCATED
1612  * extent ranges.  For ALLOC, the type and cnt are required.
1613  * For GET_ALLOCATED, only the type is required.
1614  */
1615 struct lpfc_mbx_alloc_rsrc_extents {
1616         struct mbox_header header;
1617         union {
1618                 struct {
1619                         uint32_t word4;
1620 #define lpfc_mbx_alloc_rsrc_extents_type_SHIFT  0
1621 #define lpfc_mbx_alloc_rsrc_extents_type_MASK   0x0000FFFF
1622 #define lpfc_mbx_alloc_rsrc_extents_type_WORD   word4
1623 #define lpfc_mbx_alloc_rsrc_extents_cnt_SHIFT   16
1624 #define lpfc_mbx_alloc_rsrc_extents_cnt_MASK    0x0000FFFF
1625 #define lpfc_mbx_alloc_rsrc_extents_cnt_WORD    word4
1626                 } req;
1627                 struct {
1628                         uint32_t word4;
1629 #define lpfc_mbx_rsrc_cnt_SHIFT 0
1630 #define lpfc_mbx_rsrc_cnt_MASK  0x0000FFFF
1631 #define lpfc_mbx_rsrc_cnt_WORD  word4
1632                         struct lpfc_id_range id[53];
1633                 } rsp;
1634         } u;
1635 };
1636
1637 /*
1638  * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this
1639  * structure shares the same SHIFT/MASK/WORD defines provided in the
1640  * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in
1641  * the structures defined above.  This non-embedded structure provides for the
1642  * maximum number of extents supported by the port.
1643  */
1644 struct lpfc_mbx_nembed_rsrc_extent {
1645         union  lpfc_sli4_cfg_shdr cfg_shdr;
1646         uint32_t word4;
1647         struct lpfc_id_range id;
1648 };
1649
1650 struct lpfc_mbx_dealloc_rsrc_extents {
1651         struct mbox_header header;
1652         struct {
1653                 uint32_t word4;
1654 #define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT        0
1655 #define lpfc_mbx_dealloc_rsrc_extents_type_MASK         0x0000FFFF
1656 #define lpfc_mbx_dealloc_rsrc_extents_type_WORD         word4
1657         } req;
1658
1659 };
1660
1661 /* Start SLI4 FCoE specific mbox structures. */
1662
1663 struct lpfc_mbx_post_hdr_tmpl {
1664         struct mbox_header header;
1665         uint32_t word10;
1666 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT  0
1667 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK   0x0000FFFF
1668 #define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD   word10
1669 #define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT   16
1670 #define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK    0x0000FFFF
1671 #define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD    word10
1672         uint32_t rpi_paddr_lo;
1673         uint32_t rpi_paddr_hi;
1674 };
1675
1676 struct sli4_sge {       /* SLI-4 */
1677         uint32_t addr_hi;
1678         uint32_t addr_lo;
1679
1680         uint32_t word2;
1681 #define lpfc_sli4_sge_offset_SHIFT      0
1682 #define lpfc_sli4_sge_offset_MASK       0x07FFFFFF
1683 #define lpfc_sli4_sge_offset_WORD       word2
1684 #define lpfc_sli4_sge_type_SHIFT        27
1685 #define lpfc_sli4_sge_type_MASK         0x0000000F
1686 #define lpfc_sli4_sge_type_WORD         word2
1687 #define LPFC_SGE_TYPE_DATA              0x0
1688 #define LPFC_SGE_TYPE_DIF               0x4
1689 #define LPFC_SGE_TYPE_LSP               0x5
1690 #define LPFC_SGE_TYPE_PEDIF             0x6
1691 #define LPFC_SGE_TYPE_PESEED            0x7
1692 #define LPFC_SGE_TYPE_DISEED            0x8
1693 #define LPFC_SGE_TYPE_ENC               0x9
1694 #define LPFC_SGE_TYPE_ATM               0xA
1695 #define LPFC_SGE_TYPE_SKIP              0xC
1696 #define lpfc_sli4_sge_last_SHIFT        31 /* Last SEG in the SGL sets it */
1697 #define lpfc_sli4_sge_last_MASK         0x00000001
1698 #define lpfc_sli4_sge_last_WORD         word2
1699         uint32_t sge_len;
1700 };
1701
1702 struct sli4_sge_diseed {        /* SLI-4 */
1703         uint32_t ref_tag;
1704         uint32_t ref_tag_tran;
1705
1706         uint32_t word2;
1707 #define lpfc_sli4_sge_dif_apptran_SHIFT 0
1708 #define lpfc_sli4_sge_dif_apptran_MASK  0x0000FFFF
1709 #define lpfc_sli4_sge_dif_apptran_WORD  word2
1710 #define lpfc_sli4_sge_dif_af_SHIFT      24
1711 #define lpfc_sli4_sge_dif_af_MASK       0x00000001
1712 #define lpfc_sli4_sge_dif_af_WORD       word2
1713 #define lpfc_sli4_sge_dif_na_SHIFT      25
1714 #define lpfc_sli4_sge_dif_na_MASK       0x00000001
1715 #define lpfc_sli4_sge_dif_na_WORD       word2
1716 #define lpfc_sli4_sge_dif_hi_SHIFT      26
1717 #define lpfc_sli4_sge_dif_hi_MASK       0x00000001
1718 #define lpfc_sli4_sge_dif_hi_WORD       word2
1719 #define lpfc_sli4_sge_dif_type_SHIFT    27
1720 #define lpfc_sli4_sge_dif_type_MASK     0x0000000F
1721 #define lpfc_sli4_sge_dif_type_WORD     word2
1722 #define lpfc_sli4_sge_dif_last_SHIFT    31 /* Last SEG in the SGL sets it */
1723 #define lpfc_sli4_sge_dif_last_MASK     0x00000001
1724 #define lpfc_sli4_sge_dif_last_WORD     word2
1725         uint32_t word3;
1726 #define lpfc_sli4_sge_dif_apptag_SHIFT  0
1727 #define lpfc_sli4_sge_dif_apptag_MASK   0x0000FFFF
1728 #define lpfc_sli4_sge_dif_apptag_WORD   word3
1729 #define lpfc_sli4_sge_dif_bs_SHIFT      16
1730 #define lpfc_sli4_sge_dif_bs_MASK       0x00000007
1731 #define lpfc_sli4_sge_dif_bs_WORD       word3
1732 #define lpfc_sli4_sge_dif_ai_SHIFT      19
1733 #define lpfc_sli4_sge_dif_ai_MASK       0x00000001
1734 #define lpfc_sli4_sge_dif_ai_WORD       word3
1735 #define lpfc_sli4_sge_dif_me_SHIFT      20
1736 #define lpfc_sli4_sge_dif_me_MASK       0x00000001
1737 #define lpfc_sli4_sge_dif_me_WORD       word3
1738 #define lpfc_sli4_sge_dif_re_SHIFT      21
1739 #define lpfc_sli4_sge_dif_re_MASK       0x00000001
1740 #define lpfc_sli4_sge_dif_re_WORD       word3
1741 #define lpfc_sli4_sge_dif_ce_SHIFT      22
1742 #define lpfc_sli4_sge_dif_ce_MASK       0x00000001
1743 #define lpfc_sli4_sge_dif_ce_WORD       word3
1744 #define lpfc_sli4_sge_dif_nr_SHIFT      23
1745 #define lpfc_sli4_sge_dif_nr_MASK       0x00000001
1746 #define lpfc_sli4_sge_dif_nr_WORD       word3
1747 #define lpfc_sli4_sge_dif_oprx_SHIFT    24
1748 #define lpfc_sli4_sge_dif_oprx_MASK     0x0000000F
1749 #define lpfc_sli4_sge_dif_oprx_WORD     word3
1750 #define lpfc_sli4_sge_dif_optx_SHIFT    28
1751 #define lpfc_sli4_sge_dif_optx_MASK     0x0000000F
1752 #define lpfc_sli4_sge_dif_optx_WORD     word3
1753 /* optx and oprx use BG_OP_IN defines in lpfc_hw.h */
1754 };
1755
1756 struct fcf_record {
1757         uint32_t max_rcv_size;
1758         uint32_t fka_adv_period;
1759         uint32_t fip_priority;
1760         uint32_t word3;
1761 #define lpfc_fcf_record_mac_0_SHIFT             0
1762 #define lpfc_fcf_record_mac_0_MASK              0x000000FF
1763 #define lpfc_fcf_record_mac_0_WORD              word3
1764 #define lpfc_fcf_record_mac_1_SHIFT             8
1765 #define lpfc_fcf_record_mac_1_MASK              0x000000FF
1766 #define lpfc_fcf_record_mac_1_WORD              word3
1767 #define lpfc_fcf_record_mac_2_SHIFT             16
1768 #define lpfc_fcf_record_mac_2_MASK              0x000000FF
1769 #define lpfc_fcf_record_mac_2_WORD              word3
1770 #define lpfc_fcf_record_mac_3_SHIFT             24
1771 #define lpfc_fcf_record_mac_3_MASK              0x000000FF
1772 #define lpfc_fcf_record_mac_3_WORD              word3
1773         uint32_t word4;
1774 #define lpfc_fcf_record_mac_4_SHIFT             0
1775 #define lpfc_fcf_record_mac_4_MASK              0x000000FF
1776 #define lpfc_fcf_record_mac_4_WORD              word4
1777 #define lpfc_fcf_record_mac_5_SHIFT             8
1778 #define lpfc_fcf_record_mac_5_MASK              0x000000FF
1779 #define lpfc_fcf_record_mac_5_WORD              word4
1780 #define lpfc_fcf_record_fcf_avail_SHIFT         16
1781 #define lpfc_fcf_record_fcf_avail_MASK          0x000000FF
1782 #define lpfc_fcf_record_fcf_avail_WORD          word4
1783 #define lpfc_fcf_record_mac_addr_prov_SHIFT     24
1784 #define lpfc_fcf_record_mac_addr_prov_MASK      0x000000FF
1785 #define lpfc_fcf_record_mac_addr_prov_WORD      word4
1786 #define LPFC_FCF_FPMA           1       /* Fabric Provided MAC Address */
1787 #define LPFC_FCF_SPMA           2       /* Server Provided MAC Address */
1788         uint32_t word5;
1789 #define lpfc_fcf_record_fab_name_0_SHIFT        0
1790 #define lpfc_fcf_record_fab_name_0_MASK         0x000000FF
1791 #define lpfc_fcf_record_fab_name_0_WORD         word5
1792 #define lpfc_fcf_record_fab_name_1_SHIFT        8
1793 #define lpfc_fcf_record_fab_name_1_MASK         0x000000FF
1794 #define lpfc_fcf_record_fab_name_1_WORD         word5
1795 #define lpfc_fcf_record_fab_name_2_SHIFT        16
1796 #define lpfc_fcf_record_fab_name_2_MASK         0x000000FF
1797 #define lpfc_fcf_record_fab_name_2_WORD         word5
1798 #define lpfc_fcf_record_fab_name_3_SHIFT        24
1799 #define lpfc_fcf_record_fab_name_3_MASK         0x000000FF
1800 #define lpfc_fcf_record_fab_name_3_WORD         word5
1801         uint32_t word6;
1802 #define lpfc_fcf_record_fab_name_4_SHIFT        0
1803 #define lpfc_fcf_record_fab_name_4_MASK         0x000000FF
1804 #define lpfc_fcf_record_fab_name_4_WORD         word6
1805 #define lpfc_fcf_record_fab_name_5_SHIFT        8
1806 #define lpfc_fcf_record_fab_name_5_MASK         0x000000FF
1807 #define lpfc_fcf_record_fab_name_5_WORD         word6
1808 #define lpfc_fcf_record_fab_name_6_SHIFT        16
1809 #define lpfc_fcf_record_fab_name_6_MASK         0x000000FF
1810 #define lpfc_fcf_record_fab_name_6_WORD         word6
1811 #define lpfc_fcf_record_fab_name_7_SHIFT        24
1812 #define lpfc_fcf_record_fab_name_7_MASK         0x000000FF
1813 #define lpfc_fcf_record_fab_name_7_WORD         word6
1814         uint32_t word7;
1815 #define lpfc_fcf_record_fc_map_0_SHIFT          0
1816 #define lpfc_fcf_record_fc_map_0_MASK           0x000000FF
1817 #define lpfc_fcf_record_fc_map_0_WORD           word7
1818 #define lpfc_fcf_record_fc_map_1_SHIFT          8
1819 #define lpfc_fcf_record_fc_map_1_MASK           0x000000FF
1820 #define lpfc_fcf_record_fc_map_1_WORD           word7
1821 #define lpfc_fcf_record_fc_map_2_SHIFT          16
1822 #define lpfc_fcf_record_fc_map_2_MASK           0x000000FF
1823 #define lpfc_fcf_record_fc_map_2_WORD           word7
1824 #define lpfc_fcf_record_fcf_valid_SHIFT         24
1825 #define lpfc_fcf_record_fcf_valid_MASK          0x00000001
1826 #define lpfc_fcf_record_fcf_valid_WORD          word7
1827 #define lpfc_fcf_record_fcf_fc_SHIFT            25
1828 #define lpfc_fcf_record_fcf_fc_MASK             0x00000001
1829 #define lpfc_fcf_record_fcf_fc_WORD             word7
1830 #define lpfc_fcf_record_fcf_sol_SHIFT           31
1831 #define lpfc_fcf_record_fcf_sol_MASK            0x00000001
1832 #define lpfc_fcf_record_fcf_sol_WORD            word7
1833         uint32_t word8;
1834 #define lpfc_fcf_record_fcf_index_SHIFT         0
1835 #define lpfc_fcf_record_fcf_index_MASK          0x0000FFFF
1836 #define lpfc_fcf_record_fcf_index_WORD          word8
1837 #define lpfc_fcf_record_fcf_state_SHIFT         16
1838 #define lpfc_fcf_record_fcf_state_MASK          0x0000FFFF
1839 #define lpfc_fcf_record_fcf_state_WORD          word8
1840         uint8_t vlan_bitmap[512];
1841         uint32_t word137;
1842 #define lpfc_fcf_record_switch_name_0_SHIFT     0
1843 #define lpfc_fcf_record_switch_name_0_MASK      0x000000FF
1844 #define lpfc_fcf_record_switch_name_0_WORD      word137
1845 #define lpfc_fcf_record_switch_name_1_SHIFT     8
1846 #define lpfc_fcf_record_switch_name_1_MASK      0x000000FF
1847 #define lpfc_fcf_record_switch_name_1_WORD      word137
1848 #define lpfc_fcf_record_switch_name_2_SHIFT     16
1849 #define lpfc_fcf_record_switch_name_2_MASK      0x000000FF
1850 #define lpfc_fcf_record_switch_name_2_WORD      word137
1851 #define lpfc_fcf_record_switch_name_3_SHIFT     24
1852 #define lpfc_fcf_record_switch_name_3_MASK      0x000000FF
1853 #define lpfc_fcf_record_switch_name_3_WORD      word137
1854         uint32_t word138;
1855 #define lpfc_fcf_record_switch_name_4_SHIFT     0
1856 #define lpfc_fcf_record_switch_name_4_MASK      0x000000FF
1857 #define lpfc_fcf_record_switch_name_4_WORD      word138
1858 #define lpfc_fcf_record_switch_name_5_SHIFT     8
1859 #define lpfc_fcf_record_switch_name_5_MASK      0x000000FF
1860 #define lpfc_fcf_record_switch_name_5_WORD      word138
1861 #define lpfc_fcf_record_switch_name_6_SHIFT     16
1862 #define lpfc_fcf_record_switch_name_6_MASK      0x000000FF
1863 #define lpfc_fcf_record_switch_name_6_WORD      word138
1864 #define lpfc_fcf_record_switch_name_7_SHIFT     24
1865 #define lpfc_fcf_record_switch_name_7_MASK      0x000000FF
1866 #define lpfc_fcf_record_switch_name_7_WORD      word138
1867 };
1868
1869 struct lpfc_mbx_read_fcf_tbl {
1870         union lpfc_sli4_cfg_shdr cfg_shdr;
1871         union {
1872                 struct {
1873                         uint32_t word10;
1874 #define lpfc_mbx_read_fcf_tbl_indx_SHIFT        0
1875 #define lpfc_mbx_read_fcf_tbl_indx_MASK         0x0000FFFF
1876 #define lpfc_mbx_read_fcf_tbl_indx_WORD         word10
1877                 } request;
1878                 struct {
1879                         uint32_t eventag;
1880                 } response;
1881         } u;
1882         uint32_t word11;
1883 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT   0
1884 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK    0x0000FFFF
1885 #define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD    word11
1886 };
1887
1888 struct lpfc_mbx_add_fcf_tbl_entry {
1889         union lpfc_sli4_cfg_shdr cfg_shdr;
1890         uint32_t word10;
1891 #define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT        0
1892 #define lpfc_mbx_add_fcf_tbl_fcfi_MASK         0x0000FFFF
1893 #define lpfc_mbx_add_fcf_tbl_fcfi_WORD         word10
1894         struct lpfc_mbx_sge fcf_sge;
1895 };
1896
1897 struct lpfc_mbx_del_fcf_tbl_entry {
1898         struct mbox_header header;
1899         uint32_t word10;
1900 #define lpfc_mbx_del_fcf_tbl_count_SHIFT        0
1901 #define lpfc_mbx_del_fcf_tbl_count_MASK         0x0000FFFF
1902 #define lpfc_mbx_del_fcf_tbl_count_WORD         word10
1903 #define lpfc_mbx_del_fcf_tbl_index_SHIFT        16
1904 #define lpfc_mbx_del_fcf_tbl_index_MASK         0x0000FFFF
1905 #define lpfc_mbx_del_fcf_tbl_index_WORD         word10
1906 };
1907
1908 struct lpfc_mbx_redisc_fcf_tbl {
1909         struct mbox_header header;
1910         uint32_t word10;
1911 #define lpfc_mbx_redisc_fcf_count_SHIFT         0
1912 #define lpfc_mbx_redisc_fcf_count_MASK          0x0000FFFF
1913 #define lpfc_mbx_redisc_fcf_count_WORD          word10
1914         uint32_t resvd;
1915         uint32_t word12;
1916 #define lpfc_mbx_redisc_fcf_index_SHIFT         0
1917 #define lpfc_mbx_redisc_fcf_index_MASK          0x0000FFFF
1918 #define lpfc_mbx_redisc_fcf_index_WORD          word12
1919 };
1920
1921 /* Status field for embedded SLI_CONFIG mailbox command */
1922 #define STATUS_SUCCESS                                  0x0
1923 #define STATUS_FAILED                                   0x1
1924 #define STATUS_ILLEGAL_REQUEST                          0x2
1925 #define STATUS_ILLEGAL_FIELD                            0x3
1926 #define STATUS_INSUFFICIENT_BUFFER                      0x4
1927 #define STATUS_UNAUTHORIZED_REQUEST                     0x5
1928 #define STATUS_FLASHROM_SAVE_FAILED                     0x17
1929 #define STATUS_FLASHROM_RESTORE_FAILED                  0x18
1930 #define STATUS_ICCBINDEX_ALLOC_FAILED                   0x1a
1931 #define STATUS_IOCTLHANDLE_ALLOC_FAILED                 0x1b
1932 #define STATUS_INVALID_PHY_ADDR_FROM_OSM                0x1c
1933 #define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM            0x1d
1934 #define STATUS_ASSERT_FAILED                            0x1e
1935 #define STATUS_INVALID_SESSION                          0x1f
1936 #define STATUS_INVALID_CONNECTION                       0x20
1937 #define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT               0x21
1938 #define STATUS_BTL_NO_FREE_SLOT_PATH                    0x24
1939 #define STATUS_BTL_NO_FREE_SLOT_TGTID                   0x25
1940 #define STATUS_OSM_DEVSLOT_NOT_FOUND                    0x26
1941 #define STATUS_FLASHROM_READ_FAILED                     0x27
1942 #define STATUS_POLL_IOCTL_TIMEOUT                       0x28
1943 #define STATUS_ERROR_ACITMAIN                           0x2a
1944 #define STATUS_REBOOT_REQUIRED                          0x2c
1945 #define STATUS_FCF_IN_USE                               0x3a
1946 #define STATUS_FCF_TABLE_EMPTY                          0x43
1947
1948 /*
1949  * Additional status field for embedded SLI_CONFIG mailbox
1950  * command.
1951  */
1952 #define ADD_STATUS_OPERATION_ALREADY_ACTIVE             0x67
1953
1954 struct lpfc_mbx_sli4_config {
1955         struct mbox_header header;
1956 };
1957
1958 struct lpfc_mbx_init_vfi {
1959         uint32_t word1;
1960 #define lpfc_init_vfi_vr_SHIFT          31
1961 #define lpfc_init_vfi_vr_MASK           0x00000001
1962 #define lpfc_init_vfi_vr_WORD           word1
1963 #define lpfc_init_vfi_vt_SHIFT          30
1964 #define lpfc_init_vfi_vt_MASK           0x00000001
1965 #define lpfc_init_vfi_vt_WORD           word1
1966 #define lpfc_init_vfi_vf_SHIFT          29
1967 #define lpfc_init_vfi_vf_MASK           0x00000001
1968 #define lpfc_init_vfi_vf_WORD           word1
1969 #define lpfc_init_vfi_vp_SHIFT          28
1970 #define lpfc_init_vfi_vp_MASK           0x00000001
1971 #define lpfc_init_vfi_vp_WORD           word1
1972 #define lpfc_init_vfi_vfi_SHIFT         0
1973 #define lpfc_init_vfi_vfi_MASK          0x0000FFFF
1974 #define lpfc_init_vfi_vfi_WORD          word1
1975         uint32_t word2;
1976 #define lpfc_init_vfi_vpi_SHIFT         16
1977 #define lpfc_init_vfi_vpi_MASK          0x0000FFFF
1978 #define lpfc_init_vfi_vpi_WORD          word2
1979 #define lpfc_init_vfi_fcfi_SHIFT        0
1980 #define lpfc_init_vfi_fcfi_MASK         0x0000FFFF
1981 #define lpfc_init_vfi_fcfi_WORD         word2
1982         uint32_t word3;
1983 #define lpfc_init_vfi_pri_SHIFT         13
1984 #define lpfc_init_vfi_pri_MASK          0x00000007
1985 #define lpfc_init_vfi_pri_WORD          word3
1986 #define lpfc_init_vfi_vf_id_SHIFT       1
1987 #define lpfc_init_vfi_vf_id_MASK        0x00000FFF
1988 #define lpfc_init_vfi_vf_id_WORD        word3
1989         uint32_t word4;
1990 #define lpfc_init_vfi_hop_count_SHIFT   24
1991 #define lpfc_init_vfi_hop_count_MASK    0x000000FF
1992 #define lpfc_init_vfi_hop_count_WORD    word4
1993 };
1994 #define MBX_VFI_IN_USE                  0x9F02
1995
1996
1997 struct lpfc_mbx_reg_vfi {
1998         uint32_t word1;
1999 #define lpfc_reg_vfi_upd_SHIFT          29
2000 #define lpfc_reg_vfi_upd_MASK           0x00000001
2001 #define lpfc_reg_vfi_upd_WORD           word1
2002 #define lpfc_reg_vfi_vp_SHIFT           28
2003 #define lpfc_reg_vfi_vp_MASK            0x00000001
2004 #define lpfc_reg_vfi_vp_WORD            word1
2005 #define lpfc_reg_vfi_vfi_SHIFT          0
2006 #define lpfc_reg_vfi_vfi_MASK           0x0000FFFF
2007 #define lpfc_reg_vfi_vfi_WORD           word1
2008         uint32_t word2;
2009 #define lpfc_reg_vfi_vpi_SHIFT          16
2010 #define lpfc_reg_vfi_vpi_MASK           0x0000FFFF
2011 #define lpfc_reg_vfi_vpi_WORD           word2
2012 #define lpfc_reg_vfi_fcfi_SHIFT         0
2013 #define lpfc_reg_vfi_fcfi_MASK          0x0000FFFF
2014 #define lpfc_reg_vfi_fcfi_WORD          word2
2015         uint32_t wwn[2];
2016         struct ulp_bde64 bde;
2017         uint32_t e_d_tov;
2018         uint32_t r_a_tov;
2019         uint32_t word10;
2020 #define lpfc_reg_vfi_nport_id_SHIFT             0
2021 #define lpfc_reg_vfi_nport_id_MASK              0x00FFFFFF
2022 #define lpfc_reg_vfi_nport_id_WORD              word10
2023 };
2024
2025 struct lpfc_mbx_init_vpi {
2026         uint32_t word1;
2027 #define lpfc_init_vpi_vfi_SHIFT         16
2028 #define lpfc_init_vpi_vfi_MASK          0x0000FFFF
2029 #define lpfc_init_vpi_vfi_WORD          word1
2030 #define lpfc_init_vpi_vpi_SHIFT         0
2031 #define lpfc_init_vpi_vpi_MASK          0x0000FFFF
2032 #define lpfc_init_vpi_vpi_WORD          word1
2033 };
2034
2035 struct lpfc_mbx_read_vpi {
2036         uint32_t word1_rsvd;
2037         uint32_t word2;
2038 #define lpfc_mbx_read_vpi_vnportid_SHIFT        0
2039 #define lpfc_mbx_read_vpi_vnportid_MASK         0x00FFFFFF
2040 #define lpfc_mbx_read_vpi_vnportid_WORD         word2
2041         uint32_t word3_rsvd;
2042         uint32_t word4;
2043 #define lpfc_mbx_read_vpi_acq_alpa_SHIFT        0
2044 #define lpfc_mbx_read_vpi_acq_alpa_MASK         0x000000FF
2045 #define lpfc_mbx_read_vpi_acq_alpa_WORD         word4
2046 #define lpfc_mbx_read_vpi_pb_SHIFT              15
2047 #define lpfc_mbx_read_vpi_pb_MASK               0x00000001
2048 #define lpfc_mbx_read_vpi_pb_WORD               word4
2049 #define lpfc_mbx_read_vpi_spec_alpa_SHIFT       16
2050 #define lpfc_mbx_read_vpi_spec_alpa_MASK        0x000000FF
2051 #define lpfc_mbx_read_vpi_spec_alpa_WORD        word4
2052 #define lpfc_mbx_read_vpi_ns_SHIFT              30
2053 #define lpfc_mbx_read_vpi_ns_MASK               0x00000001
2054 #define lpfc_mbx_read_vpi_ns_WORD               word4
2055 #define lpfc_mbx_read_vpi_hl_SHIFT              31
2056 #define lpfc_mbx_read_vpi_hl_MASK               0x00000001
2057 #define lpfc_mbx_read_vpi_hl_WORD               word4
2058         uint32_t word5_rsvd;
2059         uint32_t word6;
2060 #define lpfc_mbx_read_vpi_vpi_SHIFT             0
2061 #define lpfc_mbx_read_vpi_vpi_MASK              0x0000FFFF
2062 #define lpfc_mbx_read_vpi_vpi_WORD              word6
2063         uint32_t word7;
2064 #define lpfc_mbx_read_vpi_mac_0_SHIFT           0
2065 #define lpfc_mbx_read_vpi_mac_0_MASK            0x000000FF
2066 #define lpfc_mbx_read_vpi_mac_0_WORD            word7
2067 #define lpfc_mbx_read_vpi_mac_1_SHIFT           8
2068 #define lpfc_mbx_read_vpi_mac_1_MASK            0x000000FF
2069 #define lpfc_mbx_read_vpi_mac_1_WORD            word7
2070 #define lpfc_mbx_read_vpi_mac_2_SHIFT           16
2071 #define lpfc_mbx_read_vpi_mac_2_MASK            0x000000FF
2072 #define lpfc_mbx_read_vpi_mac_2_WORD            word7
2073 #define lpfc_mbx_read_vpi_mac_3_SHIFT           24
2074 #define lpfc_mbx_read_vpi_mac_3_MASK            0x000000FF
2075 #define lpfc_mbx_read_vpi_mac_3_WORD            word7
2076         uint32_t word8;
2077 #define lpfc_mbx_read_vpi_mac_4_SHIFT           0
2078 #define lpfc_mbx_read_vpi_mac_4_MASK            0x000000FF
2079 #define lpfc_mbx_read_vpi_mac_4_WORD            word8
2080 #define lpfc_mbx_read_vpi_mac_5_SHIFT           8
2081 #define lpfc_mbx_read_vpi_mac_5_MASK            0x000000FF
2082 #define lpfc_mbx_read_vpi_mac_5_WORD            word8
2083 #define lpfc_mbx_read_vpi_vlan_tag_SHIFT        16
2084 #define lpfc_mbx_read_vpi_vlan_tag_MASK         0x00000FFF
2085 #define lpfc_mbx_read_vpi_vlan_tag_WORD         word8
2086 #define lpfc_mbx_read_vpi_vv_SHIFT              28
2087 #define lpfc_mbx_read_vpi_vv_MASK               0x0000001
2088 #define lpfc_mbx_read_vpi_vv_WORD               word8
2089 };
2090
2091 struct lpfc_mbx_unreg_vfi {
2092         uint32_t word1_rsvd;
2093         uint32_t word2;
2094 #define lpfc_unreg_vfi_vfi_SHIFT        0
2095 #define lpfc_unreg_vfi_vfi_MASK         0x0000FFFF
2096 #define lpfc_unreg_vfi_vfi_WORD         word2
2097 };
2098
2099 struct lpfc_mbx_resume_rpi {
2100         uint32_t word1;
2101 #define lpfc_resume_rpi_index_SHIFT     0
2102 #define lpfc_resume_rpi_index_MASK      0x0000FFFF
2103 #define lpfc_resume_rpi_index_WORD      word1
2104 #define lpfc_resume_rpi_ii_SHIFT        30
2105 #define lpfc_resume_rpi_ii_MASK         0x00000003
2106 #define lpfc_resume_rpi_ii_WORD         word1
2107 #define RESUME_INDEX_RPI                0
2108 #define RESUME_INDEX_VPI                1
2109 #define RESUME_INDEX_VFI                2
2110 #define RESUME_INDEX_FCFI               3
2111         uint32_t event_tag;
2112 };
2113
2114 #define REG_FCF_INVALID_QID     0xFFFF
2115 struct lpfc_mbx_reg_fcfi {
2116         uint32_t word1;
2117 #define lpfc_reg_fcfi_info_index_SHIFT  0
2118 #define lpfc_reg_fcfi_info_index_MASK   0x0000FFFF
2119 #define lpfc_reg_fcfi_info_index_WORD   word1
2120 #define lpfc_reg_fcfi_fcfi_SHIFT        16
2121 #define lpfc_reg_fcfi_fcfi_MASK         0x0000FFFF
2122 #define lpfc_reg_fcfi_fcfi_WORD         word1
2123         uint32_t word2;
2124 #define lpfc_reg_fcfi_rq_id1_SHIFT      0
2125 #define lpfc_reg_fcfi_rq_id1_MASK       0x0000FFFF
2126 #define lpfc_reg_fcfi_rq_id1_WORD       word2
2127 #define lpfc_reg_fcfi_rq_id0_SHIFT      16
2128 #define lpfc_reg_fcfi_rq_id0_MASK       0x0000FFFF
2129 #define lpfc_reg_fcfi_rq_id0_WORD       word2
2130         uint32_t word3;
2131 #define lpfc_reg_fcfi_rq_id3_SHIFT      0
2132 #define lpfc_reg_fcfi_rq_id3_MASK       0x0000FFFF
2133 #define lpfc_reg_fcfi_rq_id3_WORD       word3
2134 #define lpfc_reg_fcfi_rq_id2_SHIFT      16
2135 #define lpfc_reg_fcfi_rq_id2_MASK       0x0000FFFF
2136 #define lpfc_reg_fcfi_rq_id2_WORD       word3
2137         uint32_t word4;
2138 #define lpfc_reg_fcfi_type_match0_SHIFT 24
2139 #define lpfc_reg_fcfi_type_match0_MASK  0x000000FF
2140 #define lpfc_reg_fcfi_type_match0_WORD  word4
2141 #define lpfc_reg_fcfi_type_mask0_SHIFT  16
2142 #define lpfc_reg_fcfi_type_mask0_MASK   0x000000FF
2143 #define lpfc_reg_fcfi_type_mask0_WORD   word4
2144 #define lpfc_reg_fcfi_rctl_match0_SHIFT 8
2145 #define lpfc_reg_fcfi_rctl_match0_MASK  0x000000FF
2146 #define lpfc_reg_fcfi_rctl_match0_WORD  word4
2147 #define lpfc_reg_fcfi_rctl_mask0_SHIFT  0
2148 #define lpfc_reg_fcfi_rctl_mask0_MASK   0x000000FF
2149 #define lpfc_reg_fcfi_rctl_mask0_WORD   word4
2150         uint32_t word5;
2151 #define lpfc_reg_fcfi_type_match1_SHIFT 24
2152 #define lpfc_reg_fcfi_type_match1_MASK  0x000000FF
2153 #define lpfc_reg_fcfi_type_match1_WORD  word5
2154 #define lpfc_reg_fcfi_type_mask1_SHIFT  16
2155 #define lpfc_reg_fcfi_type_mask1_MASK   0x000000FF
2156 #define lpfc_reg_fcfi_type_mask1_WORD   word5
2157 #define lpfc_reg_fcfi_rctl_match1_SHIFT 8
2158 #define lpfc_reg_fcfi_rctl_match1_MASK  0x000000FF
2159 #define lpfc_reg_fcfi_rctl_match1_WORD  word5
2160 #define lpfc_reg_fcfi_rctl_mask1_SHIFT  0
2161 #define lpfc_reg_fcfi_rctl_mask1_MASK   0x000000FF
2162 #define lpfc_reg_fcfi_rctl_mask1_WORD   word5
2163         uint32_t word6;
2164 #define lpfc_reg_fcfi_type_match2_SHIFT 24
2165 #define lpfc_reg_fcfi_type_match2_MASK  0x000000FF
2166 #define lpfc_reg_fcfi_type_match2_WORD  word6
2167 #define lpfc_reg_fcfi_type_mask2_SHIFT  16
2168 #define lpfc_reg_fcfi_type_mask2_MASK   0x000000FF
2169 #define lpfc_reg_fcfi_type_mask2_WORD   word6
2170 #define lpfc_reg_fcfi_rctl_match2_SHIFT 8
2171 #define lpfc_reg_fcfi_rctl_match2_MASK  0x000000FF
2172 #define lpfc_reg_fcfi_rctl_match2_WORD  word6
2173 #define lpfc_reg_fcfi_rctl_mask2_SHIFT  0
2174 #define lpfc_reg_fcfi_rctl_mask2_MASK   0x000000FF
2175 #define lpfc_reg_fcfi_rctl_mask2_WORD   word6
2176         uint32_t word7;
2177 #define lpfc_reg_fcfi_type_match3_SHIFT 24
2178 #define lpfc_reg_fcfi_type_match3_MASK  0x000000FF
2179 #define lpfc_reg_fcfi_type_match3_WORD  word7
2180 #define lpfc_reg_fcfi_type_mask3_SHIFT  16
2181 #define lpfc_reg_fcfi_type_mask3_MASK   0x000000FF
2182 #define lpfc_reg_fcfi_type_mask3_WORD   word7
2183 #define lpfc_reg_fcfi_rctl_match3_SHIFT 8
2184 #define lpfc_reg_fcfi_rctl_match3_MASK  0x000000FF
2185 #define lpfc_reg_fcfi_rctl_match3_WORD  word7
2186 #define lpfc_reg_fcfi_rctl_mask3_SHIFT  0
2187 #define lpfc_reg_fcfi_rctl_mask3_MASK   0x000000FF
2188 #define lpfc_reg_fcfi_rctl_mask3_WORD   word7
2189         uint32_t word8;
2190 #define lpfc_reg_fcfi_mam_SHIFT         13
2191 #define lpfc_reg_fcfi_mam_MASK          0x00000003
2192 #define lpfc_reg_fcfi_mam_WORD          word8
2193 #define LPFC_MAM_BOTH           0       /* Both SPMA and FPMA */
2194 #define LPFC_MAM_SPMA           1       /* Server Provided MAC Address */
2195 #define LPFC_MAM_FPMA           2       /* Fabric Provided MAC Address */
2196 #define lpfc_reg_fcfi_vv_SHIFT          12
2197 #define lpfc_reg_fcfi_vv_MASK           0x00000001
2198 #define lpfc_reg_fcfi_vv_WORD           word8
2199 #define lpfc_reg_fcfi_vlan_tag_SHIFT    0
2200 #define lpfc_reg_fcfi_vlan_tag_MASK     0x00000FFF
2201 #define lpfc_reg_fcfi_vlan_tag_WORD     word8
2202 };
2203
2204 struct lpfc_mbx_unreg_fcfi {
2205         uint32_t word1_rsv;
2206         uint32_t word2;
2207 #define lpfc_unreg_fcfi_SHIFT           0
2208 #define lpfc_unreg_fcfi_MASK            0x0000FFFF
2209 #define lpfc_unreg_fcfi_WORD            word2
2210 };
2211
2212 struct lpfc_mbx_read_rev {
2213         uint32_t word1;
2214 #define lpfc_mbx_rd_rev_sli_lvl_SHIFT           16
2215 #define lpfc_mbx_rd_rev_sli_lvl_MASK            0x0000000F
2216 #define lpfc_mbx_rd_rev_sli_lvl_WORD            word1
2217 #define lpfc_mbx_rd_rev_fcoe_SHIFT              20
2218 #define lpfc_mbx_rd_rev_fcoe_MASK               0x00000001
2219 #define lpfc_mbx_rd_rev_fcoe_WORD               word1
2220 #define lpfc_mbx_rd_rev_cee_ver_SHIFT           21
2221 #define lpfc_mbx_rd_rev_cee_ver_MASK            0x00000003
2222 #define lpfc_mbx_rd_rev_cee_ver_WORD            word1
2223 #define LPFC_PREDCBX_CEE_MODE   0
2224 #define LPFC_DCBX_CEE_MODE      1
2225 #define lpfc_mbx_rd_rev_vpd_SHIFT               29
2226 #define lpfc_mbx_rd_rev_vpd_MASK                0x00000001
2227 #define lpfc_mbx_rd_rev_vpd_WORD                word1
2228         uint32_t first_hw_rev;
2229         uint32_t second_hw_rev;
2230         uint32_t word4_rsvd;
2231         uint32_t third_hw_rev;
2232         uint32_t word6;
2233 #define lpfc_mbx_rd_rev_fcph_low_SHIFT          0
2234 #define lpfc_mbx_rd_rev_fcph_low_MASK           0x000000FF
2235 #define lpfc_mbx_rd_rev_fcph_low_WORD           word6
2236 #define lpfc_mbx_rd_rev_fcph_high_SHIFT         8
2237 #define lpfc_mbx_rd_rev_fcph_high_MASK          0x000000FF
2238 #define lpfc_mbx_rd_rev_fcph_high_WORD          word6
2239 #define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT       16
2240 #define lpfc_mbx_rd_rev_ftr_lvl_low_MASK        0x000000FF
2241 #define lpfc_mbx_rd_rev_ftr_lvl_low_WORD        word6
2242 #define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT      24
2243 #define lpfc_mbx_rd_rev_ftr_lvl_high_MASK       0x000000FF
2244 #define lpfc_mbx_rd_rev_ftr_lvl_high_WORD       word6
2245         uint32_t word7_rsvd;
2246         uint32_t fw_id_rev;
2247         uint8_t  fw_name[16];
2248         uint32_t ulp_fw_id_rev;
2249         uint8_t  ulp_fw_name[16];
2250         uint32_t word18_47_rsvd[30];
2251         uint32_t word48;
2252 #define lpfc_mbx_rd_rev_avail_len_SHIFT         0
2253 #define lpfc_mbx_rd_rev_avail_len_MASK          0x00FFFFFF
2254 #define lpfc_mbx_rd_rev_avail_len_WORD          word48
2255         uint32_t vpd_paddr_low;
2256         uint32_t vpd_paddr_high;
2257         uint32_t avail_vpd_len;
2258         uint32_t rsvd_52_63[12];
2259 };
2260
2261 struct lpfc_mbx_read_config {
2262         uint32_t word1;
2263 #define lpfc_mbx_rd_conf_extnts_inuse_SHIFT     31
2264 #define lpfc_mbx_rd_conf_extnts_inuse_MASK      0x00000001
2265 #define lpfc_mbx_rd_conf_extnts_inuse_WORD      word1
2266         uint32_t word2;
2267 #define lpfc_mbx_rd_conf_lnk_numb_SHIFT         0
2268 #define lpfc_mbx_rd_conf_lnk_numb_MASK          0x0000003F
2269 #define lpfc_mbx_rd_conf_lnk_numb_WORD          word2
2270 #define lpfc_mbx_rd_conf_lnk_type_SHIFT         6
2271 #define lpfc_mbx_rd_conf_lnk_type_MASK          0x00000003
2272 #define lpfc_mbx_rd_conf_lnk_type_WORD          word2
2273 #define LPFC_LNK_TYPE_GE        0
2274 #define LPFC_LNK_TYPE_FC        1
2275 #define lpfc_mbx_rd_conf_lnk_ldv_SHIFT          8
2276 #define lpfc_mbx_rd_conf_lnk_ldv_MASK           0x00000001
2277 #define lpfc_mbx_rd_conf_lnk_ldv_WORD           word2
2278 #define lpfc_mbx_rd_conf_topology_SHIFT         24
2279 #define lpfc_mbx_rd_conf_topology_MASK          0x000000FF
2280 #define lpfc_mbx_rd_conf_topology_WORD          word2
2281         uint32_t rsvd_3;
2282         uint32_t word4;
2283 #define lpfc_mbx_rd_conf_e_d_tov_SHIFT          0
2284 #define lpfc_mbx_rd_conf_e_d_tov_MASK           0x0000FFFF
2285 #define lpfc_mbx_rd_conf_e_d_tov_WORD           word4
2286         uint32_t rsvd_5;
2287         uint32_t word6;
2288 #define lpfc_mbx_rd_conf_r_a_tov_SHIFT          0
2289 #define lpfc_mbx_rd_conf_r_a_tov_MASK           0x0000FFFF
2290 #define lpfc_mbx_rd_conf_r_a_tov_WORD           word6
2291         uint32_t rsvd_7;
2292         uint32_t rsvd_8;
2293         uint32_t word9;
2294 #define lpfc_mbx_rd_conf_lmt_SHIFT              0
2295 #define lpfc_mbx_rd_conf_lmt_MASK               0x0000FFFF
2296 #define lpfc_mbx_rd_conf_lmt_WORD               word9
2297         uint32_t rsvd_10;
2298         uint32_t rsvd_11;
2299         uint32_t word12;
2300 #define lpfc_mbx_rd_conf_xri_base_SHIFT         0
2301 #define lpfc_mbx_rd_conf_xri_base_MASK          0x0000FFFF
2302 #define lpfc_mbx_rd_conf_xri_base_WORD          word12
2303 #define lpfc_mbx_rd_conf_xri_count_SHIFT        16
2304 #define lpfc_mbx_rd_conf_xri_count_MASK         0x0000FFFF
2305 #define lpfc_mbx_rd_conf_xri_count_WORD         word12
2306         uint32_t word13;
2307 #define lpfc_mbx_rd_conf_rpi_base_SHIFT         0
2308 #define lpfc_mbx_rd_conf_rpi_base_MASK          0x0000FFFF
2309 #define lpfc_mbx_rd_conf_rpi_base_WORD          word13
2310 #define lpfc_mbx_rd_conf_rpi_count_SHIFT        16
2311 #define lpfc_mbx_rd_conf_rpi_count_MASK         0x0000FFFF
2312 #define lpfc_mbx_rd_conf_rpi_count_WORD         word13
2313         uint32_t word14;
2314 #define lpfc_mbx_rd_conf_vpi_base_SHIFT         0
2315 #define lpfc_mbx_rd_conf_vpi_base_MASK          0x0000FFFF
2316 #define lpfc_mbx_rd_conf_vpi_base_WORD          word14
2317 #define lpfc_mbx_rd_conf_vpi_count_SHIFT        16
2318 #define lpfc_mbx_rd_conf_vpi_count_MASK         0x0000FFFF
2319 #define lpfc_mbx_rd_conf_vpi_count_WORD         word14
2320         uint32_t word15;
2321 #define lpfc_mbx_rd_conf_vfi_base_SHIFT         0
2322 #define lpfc_mbx_rd_conf_vfi_base_MASK          0x0000FFFF
2323 #define lpfc_mbx_rd_conf_vfi_base_WORD          word15
2324 #define lpfc_mbx_rd_conf_vfi_count_SHIFT        16
2325 #define lpfc_mbx_rd_conf_vfi_count_MASK         0x0000FFFF
2326 #define lpfc_mbx_rd_conf_vfi_count_WORD         word15
2327         uint32_t word16;
2328 #define lpfc_mbx_rd_conf_fcfi_count_SHIFT       16
2329 #define lpfc_mbx_rd_conf_fcfi_count_MASK        0x0000FFFF
2330 #define lpfc_mbx_rd_conf_fcfi_count_WORD        word16
2331         uint32_t word17;
2332 #define lpfc_mbx_rd_conf_rq_count_SHIFT         0
2333 #define lpfc_mbx_rd_conf_rq_count_MASK          0x0000FFFF
2334 #define lpfc_mbx_rd_conf_rq_count_WORD          word17
2335 #define lpfc_mbx_rd_conf_eq_count_SHIFT         16
2336 #define lpfc_mbx_rd_conf_eq_count_MASK          0x0000FFFF
2337 #define lpfc_mbx_rd_conf_eq_count_WORD          word17
2338         uint32_t word18;
2339 #define lpfc_mbx_rd_conf_wq_count_SHIFT         0
2340 #define lpfc_mbx_rd_conf_wq_count_MASK          0x0000FFFF
2341 #define lpfc_mbx_rd_conf_wq_count_WORD          word18
2342 #define lpfc_mbx_rd_conf_cq_count_SHIFT         16
2343 #define lpfc_mbx_rd_conf_cq_count_MASK          0x0000FFFF
2344 #define lpfc_mbx_rd_conf_cq_count_WORD          word18
2345 };
2346
2347 struct lpfc_mbx_request_features {
2348         uint32_t word1;
2349 #define lpfc_mbx_rq_ftr_qry_SHIFT               0
2350 #define lpfc_mbx_rq_ftr_qry_MASK                0x00000001
2351 #define lpfc_mbx_rq_ftr_qry_WORD                word1
2352         uint32_t word2;
2353 #define lpfc_mbx_rq_ftr_rq_iaab_SHIFT           0
2354 #define lpfc_mbx_rq_ftr_rq_iaab_MASK            0x00000001
2355 #define lpfc_mbx_rq_ftr_rq_iaab_WORD            word2
2356 #define lpfc_mbx_rq_ftr_rq_npiv_SHIFT           1
2357 #define lpfc_mbx_rq_ftr_rq_npiv_MASK            0x00000001
2358 #define lpfc_mbx_rq_ftr_rq_npiv_WORD            word2
2359 #define lpfc_mbx_rq_ftr_rq_dif_SHIFT            2
2360 #define lpfc_mbx_rq_ftr_rq_dif_MASK             0x00000001
2361 #define lpfc_mbx_rq_ftr_rq_dif_WORD             word2
2362 #define lpfc_mbx_rq_ftr_rq_vf_SHIFT             3
2363 #define lpfc_mbx_rq_ftr_rq_vf_MASK              0x00000001
2364 #define lpfc_mbx_rq_ftr_rq_vf_WORD              word2
2365 #define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT           4
2366 #define lpfc_mbx_rq_ftr_rq_fcpi_MASK            0x00000001
2367 #define lpfc_mbx_rq_ftr_rq_fcpi_WORD            word2
2368 #define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT           5
2369 #define lpfc_mbx_rq_ftr_rq_fcpt_MASK            0x00000001
2370 #define lpfc_mbx_rq_ftr_rq_fcpt_WORD            word2
2371 #define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT           6
2372 #define lpfc_mbx_rq_ftr_rq_fcpc_MASK            0x00000001
2373 #define lpfc_mbx_rq_ftr_rq_fcpc_WORD            word2
2374 #define lpfc_mbx_rq_ftr_rq_ifip_SHIFT           7
2375 #define lpfc_mbx_rq_ftr_rq_ifip_MASK            0x00000001
2376 #define lpfc_mbx_rq_ftr_rq_ifip_WORD            word2
2377 #define lpfc_mbx_rq_ftr_rq_perfh_SHIFT          11
2378 #define lpfc_mbx_rq_ftr_rq_perfh_MASK           0x00000001
2379 #define lpfc_mbx_rq_ftr_rq_perfh_WORD           word2
2380         uint32_t word3;
2381 #define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT          0
2382 #define lpfc_mbx_rq_ftr_rsp_iaab_MASK           0x00000001
2383 #define lpfc_mbx_rq_ftr_rsp_iaab_WORD           word3
2384 #define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT          1
2385 #define lpfc_mbx_rq_ftr_rsp_npiv_MASK           0x00000001
2386 #define lpfc_mbx_rq_ftr_rsp_npiv_WORD           word3
2387 #define lpfc_mbx_rq_ftr_rsp_dif_SHIFT           2
2388 #define lpfc_mbx_rq_ftr_rsp_dif_MASK            0x00000001
2389 #define lpfc_mbx_rq_ftr_rsp_dif_WORD            word3
2390 #define lpfc_mbx_rq_ftr_rsp_vf_SHIFT            3
2391 #define lpfc_mbx_rq_ftr_rsp_vf__MASK            0x00000001
2392 #define lpfc_mbx_rq_ftr_rsp_vf_WORD             word3
2393 #define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT          4
2394 #define lpfc_mbx_rq_ftr_rsp_fcpi_MASK           0x00000001
2395 #define lpfc_mbx_rq_ftr_rsp_fcpi_WORD           word3
2396 #define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT          5
2397 #define lpfc_mbx_rq_ftr_rsp_fcpt_MASK           0x00000001
2398 #define lpfc_mbx_rq_ftr_rsp_fcpt_WORD           word3
2399 #define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT          6
2400 #define lpfc_mbx_rq_ftr_rsp_fcpc_MASK           0x00000001
2401 #define lpfc_mbx_rq_ftr_rsp_fcpc_WORD           word3
2402 #define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT          7
2403 #define lpfc_mbx_rq_ftr_rsp_ifip_MASK           0x00000001
2404 #define lpfc_mbx_rq_ftr_rsp_ifip_WORD           word3
2405 #define lpfc_mbx_rq_ftr_rsp_perfh_SHIFT         11
2406 #define lpfc_mbx_rq_ftr_rsp_perfh_MASK          0x00000001
2407 #define lpfc_mbx_rq_ftr_rsp_perfh_WORD          word3
2408 };
2409
2410 struct lpfc_mbx_supp_pages {
2411         uint32_t word1;
2412 #define qs_SHIFT                                0
2413 #define qs_MASK                                 0x00000001
2414 #define qs_WORD                                 word1
2415 #define wr_SHIFT                                1
2416 #define wr_MASK                                 0x00000001
2417 #define wr_WORD                                 word1
2418 #define pf_SHIFT                                8
2419 #define pf_MASK                                 0x000000ff
2420 #define pf_WORD                                 word1
2421 #define cpn_SHIFT                               16
2422 #define cpn_MASK                                0x000000ff
2423 #define cpn_WORD                                word1
2424         uint32_t word2;
2425 #define list_offset_SHIFT                       0
2426 #define list_offset_MASK                        0x000000ff
2427 #define list_offset_WORD                        word2
2428 #define next_offset_SHIFT                       8
2429 #define next_offset_MASK                        0x000000ff
2430 #define next_offset_WORD                        word2
2431 #define elem_cnt_SHIFT                          16
2432 #define elem_cnt_MASK                           0x000000ff
2433 #define elem_cnt_WORD                           word2
2434         uint32_t word3;
2435 #define pn_0_SHIFT                              24
2436 #define pn_0_MASK                               0x000000ff
2437 #define pn_0_WORD                               word3
2438 #define pn_1_SHIFT                              16
2439 #define pn_1_MASK                               0x000000ff
2440 #define pn_1_WORD                               word3
2441 #define pn_2_SHIFT                              8
2442 #define pn_2_MASK                               0x000000ff
2443 #define pn_2_WORD                               word3
2444 #define pn_3_SHIFT                              0
2445 #define pn_3_MASK                               0x000000ff
2446 #define pn_3_WORD                               word3
2447         uint32_t word4;
2448 #define pn_4_SHIFT                              24
2449 #define pn_4_MASK                               0x000000ff
2450 #define pn_4_WORD                               word4
2451 #define pn_5_SHIFT                              16
2452 #define pn_5_MASK                               0x000000ff
2453 #define pn_5_WORD                               word4
2454 #define pn_6_SHIFT                              8
2455 #define pn_6_MASK                               0x000000ff
2456 #define pn_6_WORD                               word4
2457 #define pn_7_SHIFT                              0
2458 #define pn_7_MASK                               0x000000ff
2459 #define pn_7_WORD                               word4
2460         uint32_t rsvd[27];
2461 #define LPFC_SUPP_PAGES                 0
2462 #define LPFC_BLOCK_GUARD_PROFILES       1
2463 #define LPFC_SLI4_PARAMETERS            2
2464 };
2465
2466 struct lpfc_mbx_memory_dump_type3 {
2467         uint32_t word1;
2468 #define lpfc_mbx_memory_dump_type3_type_SHIFT    0
2469 #define lpfc_mbx_memory_dump_type3_type_MASK     0x0000000f
2470 #define lpfc_mbx_memory_dump_type3_type_WORD     word1
2471 #define lpfc_mbx_memory_dump_type3_link_SHIFT    24
2472 #define lpfc_mbx_memory_dump_type3_link_MASK     0x000000ff
2473 #define lpfc_mbx_memory_dump_type3_link_WORD     word1
2474         uint32_t word2;
2475 #define lpfc_mbx_memory_dump_type3_page_no_SHIFT  0
2476 #define lpfc_mbx_memory_dump_type3_page_no_MASK   0x0000ffff
2477 #define lpfc_mbx_memory_dump_type3_page_no_WORD   word2
2478 #define lpfc_mbx_memory_dump_type3_offset_SHIFT   16
2479 #define lpfc_mbx_memory_dump_type3_offset_MASK    0x0000ffff
2480 #define lpfc_mbx_memory_dump_type3_offset_WORD    word2
2481         uint32_t word3;
2482 #define lpfc_mbx_memory_dump_type3_length_SHIFT  0
2483 #define lpfc_mbx_memory_dump_type3_length_MASK   0x00ffffff
2484 #define lpfc_mbx_memory_dump_type3_length_WORD   word3
2485         uint32_t addr_lo;
2486         uint32_t addr_hi;
2487         uint32_t return_len;
2488 };
2489
2490 #define DMP_PAGE_A0             0xa0
2491 #define DMP_PAGE_A2             0xa2
2492 #define DMP_SFF_PAGE_A0_SIZE    256
2493 #define DMP_SFF_PAGE_A2_SIZE    256
2494
2495 #define SFP_WAVELENGTH_LC1310   1310
2496 #define SFP_WAVELENGTH_LL1550   1550
2497
2498
2499 /*
2500  *  * SFF-8472 TABLE 3.4
2501  *   */
2502 #define  SFF_PG0_CONNECTOR_UNKNOWN    0x00   /* Unknown  */
2503 #define  SFF_PG0_CONNECTOR_SC         0x01   /* SC       */
2504 #define  SFF_PG0_CONNECTOR_FC_COPPER1 0x02   /* FC style 1 copper connector */
2505 #define  SFF_PG0_CONNECTOR_FC_COPPER2 0x03   /* FC style 2 copper connector */
2506 #define  SFF_PG0_CONNECTOR_BNC        0x04   /* BNC / TNC */
2507 #define  SFF_PG0_CONNECTOR__FC_COAX   0x05   /* FC coaxial headers */
2508 #define  SFF_PG0_CONNECTOR_FIBERJACK  0x06   /* FiberJack */
2509 #define  SFF_PG0_CONNECTOR_LC         0x07   /* LC        */
2510 #define  SFF_PG0_CONNECTOR_MT         0x08   /* MT - RJ   */
2511 #define  SFF_PG0_CONNECTOR_MU         0x09   /* MU        */
2512 #define  SFF_PG0_CONNECTOR_SF         0x0A   /* SG        */
2513 #define  SFF_PG0_CONNECTOR_OPTICAL_PIGTAIL 0x0B /* Optical pigtail */
2514 #define  SFF_PG0_CONNECTOR_OPTICAL_PARALLEL 0x0C /* MPO Parallel Optic */
2515 #define  SFF_PG0_CONNECTOR_HSSDC_II   0x20   /* HSSDC II */
2516 #define  SFF_PG0_CONNECTOR_COPPER_PIGTAIL 0x21 /* Copper pigtail */
2517 #define  SFF_PG0_CONNECTOR_RJ45       0x22  /* RJ45 */
2518
2519 /* SFF-8472 Table 3.1 Diagnostics: Data Fields Address/Page A0 */
2520
2521 #define SSF_IDENTIFIER                  0
2522 #define SSF_EXT_IDENTIFIER              1
2523 #define SSF_CONNECTOR                   2
2524 #define SSF_TRANSCEIVER_CODE_B0         3
2525 #define SSF_TRANSCEIVER_CODE_B1         4
2526 #define SSF_TRANSCEIVER_CODE_B2         5
2527 #define SSF_TRANSCEIVER_CODE_B3         6
2528 #define SSF_TRANSCEIVER_CODE_B4         7
2529 #define SSF_TRANSCEIVER_CODE_B5         8
2530 #define SSF_TRANSCEIVER_CODE_B6         9
2531 #define SSF_TRANSCEIVER_CODE_B7         10
2532 #define SSF_ENCODING                    11
2533 #define SSF_BR_NOMINAL                  12
2534 #define SSF_RATE_IDENTIFIER             13
2535 #define SSF_LENGTH_9UM_KM               14
2536 #define SSF_LENGTH_9UM                  15
2537 #define SSF_LENGTH_50UM_OM2             16
2538 #define SSF_LENGTH_62UM_OM1             17
2539 #define SFF_LENGTH_COPPER               18
2540 #define SSF_LENGTH_50UM_OM3             19
2541 #define SSF_VENDOR_NAME                 20
2542 #define SSF_VENDOR_OUI                  36
2543 #define SSF_VENDOR_PN                   40
2544 #define SSF_VENDOR_REV                  56
2545 #define SSF_WAVELENGTH_B1               60
2546 #define SSF_WAVELENGTH_B0               61
2547 #define SSF_CC_BASE                     63
2548 #define SSF_OPTIONS_B1                  64
2549 #define SSF_OPTIONS_B0                  65
2550 #define SSF_BR_MAX                      66
2551 #define SSF_BR_MIN                      67
2552 #define SSF_VENDOR_SN                   68
2553 #define SSF_DATE_CODE                   84
2554 #define SSF_MONITORING_TYPEDIAGNOSTIC   92
2555 #define SSF_ENHANCED_OPTIONS            93
2556 #define SFF_8472_COMPLIANCE             94
2557 #define SSF_CC_EXT                      95
2558 #define SSF_A0_VENDOR_SPECIFIC          96
2559
2560 /* SFF-8472 Table 3.1a Diagnostics: Data Fields Address/Page A2 */
2561
2562 #define SSF_AW_THRESHOLDS               0
2563 #define SSF_EXT_CAL_CONSTANTS           56
2564 #define SSF_CC_DMI                      95
2565 #define SFF_TEMPERATURE_B1              96
2566 #define SFF_TEMPERATURE_B0              97
2567 #define SFF_VCC_B1                      98
2568 #define SFF_VCC_B0                      99
2569 #define SFF_TX_BIAS_CURRENT_B1          100
2570 #define SFF_TX_BIAS_CURRENT_B0          101
2571 #define SFF_TXPOWER_B1                  102
2572 #define SFF_TXPOWER_B0                  103
2573 #define SFF_RXPOWER_B1                  104
2574 #define SFF_RXPOWER_B0                  105
2575 #define SSF_STATUS_CONTROL              110
2576 #define SSF_ALARM_FLAGS_B1              112
2577 #define SSF_ALARM_FLAGS_B0              113
2578 #define SSF_WARNING_FLAGS_B1            116
2579 #define SSF_WARNING_FLAGS_B0            117
2580 #define SSF_EXT_TATUS_CONTROL_B1        118
2581 #define SSF_EXT_TATUS_CONTROL_B0        119
2582 #define SSF_A2_VENDOR_SPECIFIC          120
2583 #define SSF_USER_EEPROM                 128
2584 #define SSF_VENDOR_CONTROL              148
2585
2586
2587 /*
2588  * Tranceiver codes Fibre Channel SFF-8472
2589  * Table 3.5.
2590  */
2591
2592 struct sff_trasnceiver_codes_byte0 {
2593         uint8_t inifiband:4;
2594         uint8_t teng_ethernet:4;
2595 };
2596
2597 struct sff_trasnceiver_codes_byte1 {
2598         uint8_t  sonet:6;
2599         uint8_t  escon:2;
2600 };
2601
2602 struct sff_trasnceiver_codes_byte2 {
2603         uint8_t  soNet:8;
2604 };
2605
2606 struct sff_trasnceiver_codes_byte3 {
2607         uint8_t ethernet:8;
2608 };
2609
2610 struct sff_trasnceiver_codes_byte4 {
2611         uint8_t fc_el_lo:1;
2612         uint8_t fc_lw_laser:1;
2613         uint8_t fc_sw_laser:1;
2614         uint8_t fc_md_distance:1;
2615         uint8_t fc_lg_distance:1;
2616         uint8_t fc_int_distance:1;
2617         uint8_t fc_short_distance:1;
2618         uint8_t fc_vld_distance:1;
2619 };
2620
2621 struct sff_trasnceiver_codes_byte5 {
2622         uint8_t reserved1:1;
2623         uint8_t reserved2:1;
2624         uint8_t fc_sfp_active:1;  /* Active cable   */
2625         uint8_t fc_sfp_passive:1; /* Passive cable  */
2626         uint8_t fc_lw_laser:1;     /* Longwave laser */
2627         uint8_t fc_sw_laser_sl:1;
2628         uint8_t fc_sw_laser_sn:1;
2629         uint8_t fc_el_hi:1;        /* Electrical enclosure high bit */
2630 };
2631
2632 struct sff_trasnceiver_codes_byte6 {
2633         uint8_t fc_tm_sm:1;      /* Single Mode */
2634         uint8_t reserved:1;
2635         uint8_t fc_tm_m6:1;       /* Multimode, 62.5um (M6) */
2636         uint8_t fc_tm_tv:1;      /* Video Coax (TV) */
2637         uint8_t fc_tm_mi:1;      /* Miniature Coax (MI) */
2638         uint8_t fc_tm_tp:1;      /* Twisted Pair (TP) */
2639         uint8_t fc_tm_tw:1;      /* Twin Axial Pair  */
2640 };
2641
2642 struct sff_trasnceiver_codes_byte7 {
2643         uint8_t fc_sp_100MB:1;   /*  100 MB/sec */
2644         uint8_t reserve:1;
2645         uint8_t fc_sp_200mb:1;   /*  200 MB/sec */
2646         uint8_t fc_sp_3200MB:1;  /* 3200 MB/sec */
2647         uint8_t fc_sp_400MB:1;   /*  400 MB/sec */
2648         uint8_t fc_sp_1600MB:1;  /* 1600 MB/sec */
2649         uint8_t fc_sp_800MB:1;   /*  800 MB/sec */
2650         uint8_t fc_sp_1200MB:1;  /* 1200 MB/sec */
2651 };
2652
2653 /* User writable non-volatile memory, SFF-8472 Table 3.20 */
2654 struct user_eeprom {
2655         uint8_t vendor_name[16];
2656         uint8_t vendor_oui[3];
2657         uint8_t vendor_pn[816];
2658         uint8_t vendor_rev[4];
2659         uint8_t vendor_sn[16];
2660         uint8_t datecode[6];
2661         uint8_t lot_code[2];
2662         uint8_t reserved191[57];
2663 };
2664
2665 struct lpfc_mbx_pc_sli4_params {
2666         uint32_t word1;
2667 #define qs_SHIFT                                0
2668 #define qs_MASK                                 0x00000001
2669 #define qs_WORD                                 word1
2670 #define wr_SHIFT                                1
2671 #define wr_MASK                                 0x00000001
2672 #define wr_WORD                                 word1
2673 #define pf_SHIFT                                8
2674 #define pf_MASK                                 0x000000ff
2675 #define pf_WORD                                 word1
2676 #define cpn_SHIFT                               16
2677 #define cpn_MASK                                0x000000ff
2678 #define cpn_WORD                                word1
2679         uint32_t word2;
2680 #define if_type_SHIFT                           0
2681 #define if_type_MASK                            0x00000007
2682 #define if_type_WORD                            word2
2683 #define sli_rev_SHIFT                           4
2684 #define sli_rev_MASK                            0x0000000f
2685 #define sli_rev_WORD                            word2
2686 #define sli_family_SHIFT                        8
2687 #define sli_family_MASK                         0x000000ff
2688 #define sli_family_WORD                         word2
2689 #define featurelevel_1_SHIFT                    16
2690 #define featurelevel_1_MASK                     0x000000ff
2691 #define featurelevel_1_WORD                     word2
2692 #define featurelevel_2_SHIFT                    24
2693 #define featurelevel_2_MASK                     0x0000001f
2694 #define featurelevel_2_WORD                     word2
2695         uint32_t word3;
2696 #define fcoe_SHIFT                              0
2697 #define fcoe_MASK                               0x00000001
2698 #define fcoe_WORD                               word3
2699 #define fc_SHIFT                                1
2700 #define fc_MASK                                 0x00000001
2701 #define fc_WORD                                 word3
2702 #define nic_SHIFT                               2
2703 #define nic_MASK                                0x00000001
2704 #define nic_WORD                                word3
2705 #define iscsi_SHIFT                             3
2706 #define iscsi_MASK                              0x00000001
2707 #define iscsi_WORD                              word3
2708 #define rdma_SHIFT                              4
2709 #define rdma_MASK                               0x00000001
2710 #define rdma_WORD                               word3
2711         uint32_t sge_supp_len;
2712 #define SLI4_PAGE_SIZE 4096
2713         uint32_t word5;
2714 #define if_page_sz_SHIFT                        0
2715 #define if_page_sz_MASK                         0x0000ffff
2716 #define if_page_sz_WORD                         word5
2717 #define loopbk_scope_SHIFT                      24
2718 #define loopbk_scope_MASK                       0x0000000f
2719 #define loopbk_scope_WORD                       word5
2720 #define rq_db_window_SHIFT                      28
2721 #define rq_db_window_MASK                       0x0000000f
2722 #define rq_db_window_WORD                       word5
2723         uint32_t word6;
2724 #define eq_pages_SHIFT                          0
2725 #define eq_pages_MASK                           0x0000000f
2726 #define eq_pages_WORD                           word6
2727 #define eqe_size_SHIFT                          8
2728 #define eqe_size_MASK                           0x000000ff
2729 #define eqe_size_WORD                           word6
2730         uint32_t word7;
2731 #define cq_pages_SHIFT                          0
2732 #define cq_pages_MASK                           0x0000000f
2733 #define cq_pages_WORD                           word7
2734 #define cqe_size_SHIFT                          8
2735 #define cqe_size_MASK                           0x000000ff
2736 #define cqe_size_WORD                           word7
2737         uint32_t word8;
2738 #define mq_pages_SHIFT                          0
2739 #define mq_pages_MASK                           0x0000000f
2740 #define mq_pages_WORD                           word8
2741 #define mqe_size_SHIFT                          8
2742 #define mqe_size_MASK                           0x000000ff
2743 #define mqe_size_WORD                           word8
2744 #define mq_elem_cnt_SHIFT                       16
2745 #define mq_elem_cnt_MASK                        0x000000ff
2746 #define mq_elem_cnt_WORD                        word8
2747         uint32_t word9;
2748 #define wq_pages_SHIFT                          0
2749 #define wq_pages_MASK                           0x0000ffff
2750 #define wq_pages_WORD                           word9
2751 #define wqe_size_SHIFT                          8
2752 #define wqe_size_MASK                           0x000000ff
2753 #define wqe_size_WORD                           word9
2754         uint32_t word10;
2755 #define rq_pages_SHIFT                          0
2756 #define rq_pages_MASK                           0x0000ffff
2757 #define rq_pages_WORD                           word10
2758 #define rqe_size_SHIFT                          8
2759 #define rqe_size_MASK                           0x000000ff
2760 #define rqe_size_WORD                           word10
2761         uint32_t word11;
2762 #define hdr_pages_SHIFT                         0
2763 #define hdr_pages_MASK                          0x0000000f
2764 #define hdr_pages_WORD                          word11
2765 #define hdr_size_SHIFT                          8
2766 #define hdr_size_MASK                           0x0000000f
2767 #define hdr_size_WORD                           word11
2768 #define hdr_pp_align_SHIFT                      16
2769 #define hdr_pp_align_MASK                       0x0000ffff
2770 #define hdr_pp_align_WORD                       word11
2771         uint32_t word12;
2772 #define sgl_pages_SHIFT                         0
2773 #define sgl_pages_MASK                          0x0000000f
2774 #define sgl_pages_WORD                          word12
2775 #define sgl_pp_align_SHIFT                      16
2776 #define sgl_pp_align_MASK                       0x0000ffff
2777 #define sgl_pp_align_WORD                       word12
2778         uint32_t rsvd_13_63[51];
2779 };
2780 #define SLI4_PAGE_ALIGN(addr) (((addr)+((SLI4_PAGE_SIZE)-1)) \
2781                                &(~((SLI4_PAGE_SIZE)-1)))
2782
2783 struct lpfc_sli4_parameters {
2784         uint32_t word0;
2785 #define cfg_prot_type_SHIFT                     0
2786 #define cfg_prot_type_MASK                      0x000000FF
2787 #define cfg_prot_type_WORD                      word0
2788         uint32_t word1;
2789 #define cfg_ft_SHIFT                            0
2790 #define cfg_ft_MASK                             0x00000001
2791 #define cfg_ft_WORD                             word1
2792 #define cfg_sli_rev_SHIFT                       4
2793 #define cfg_sli_rev_MASK                        0x0000000f
2794 #define cfg_sli_rev_WORD                        word1
2795 #define cfg_sli_family_SHIFT                    8
2796 #define cfg_sli_family_MASK                     0x0000000f
2797 #define cfg_sli_family_WORD                     word1
2798 #define cfg_if_type_SHIFT                       12
2799 #define cfg_if_type_MASK                        0x0000000f
2800 #define cfg_if_type_WORD                        word1
2801 #define cfg_sli_hint_1_SHIFT                    16
2802 #define cfg_sli_hint_1_MASK                     0x000000ff
2803 #define cfg_sli_hint_1_WORD                     word1
2804 #define cfg_sli_hint_2_SHIFT                    24
2805 #define cfg_sli_hint_2_MASK                     0x0000001f
2806 #define cfg_sli_hint_2_WORD                     word1
2807         uint32_t word2;
2808         uint32_t word3;
2809         uint32_t word4;
2810 #define cfg_cqv_SHIFT                           14
2811 #define cfg_cqv_MASK                            0x00000003
2812 #define cfg_cqv_WORD                            word4
2813         uint32_t word5;
2814         uint32_t word6;
2815 #define cfg_mqv_SHIFT                           14
2816 #define cfg_mqv_MASK                            0x00000003
2817 #define cfg_mqv_WORD                            word6
2818         uint32_t word7;
2819         uint32_t word8;
2820 #define cfg_wqsize_SHIFT                        8
2821 #define cfg_wqsize_MASK                         0x0000000f
2822 #define cfg_wqsize_WORD                         word8
2823 #define cfg_wqv_SHIFT                           14
2824 #define cfg_wqv_MASK                            0x00000003
2825 #define cfg_wqv_WORD                            word8
2826         uint32_t word9;
2827         uint32_t word10;
2828 #define cfg_rqv_SHIFT                           14
2829 #define cfg_rqv_MASK                            0x00000003
2830 #define cfg_rqv_WORD                            word10
2831         uint32_t word11;
2832 #define cfg_rq_db_window_SHIFT                  28
2833 #define cfg_rq_db_window_MASK                   0x0000000f
2834 #define cfg_rq_db_window_WORD                   word11
2835         uint32_t word12;
2836 #define cfg_fcoe_SHIFT                          0
2837 #define cfg_fcoe_MASK                           0x00000001
2838 #define cfg_fcoe_WORD                           word12
2839 #define cfg_ext_SHIFT                           1
2840 #define cfg_ext_MASK                            0x00000001
2841 #define cfg_ext_WORD                            word12
2842 #define cfg_hdrr_SHIFT                          2
2843 #define cfg_hdrr_MASK                           0x00000001
2844 #define cfg_hdrr_WORD                           word12
2845 #define cfg_phwq_SHIFT                          15
2846 #define cfg_phwq_MASK                           0x00000001
2847 #define cfg_phwq_WORD                           word12
2848 #define cfg_oas_SHIFT                           25
2849 #define cfg_oas_MASK                            0x00000001
2850 #define cfg_oas_WORD                            word12
2851 #define cfg_loopbk_scope_SHIFT                  28
2852 #define cfg_loopbk_scope_MASK                   0x0000000f
2853 #define cfg_loopbk_scope_WORD                   word12
2854         uint32_t sge_supp_len;
2855         uint32_t word14;
2856 #define cfg_sgl_page_cnt_SHIFT                  0
2857 #define cfg_sgl_page_cnt_MASK                   0x0000000f
2858 #define cfg_sgl_page_cnt_WORD                   word14
2859 #define cfg_sgl_page_size_SHIFT                 8
2860 #define cfg_sgl_page_size_MASK                  0x000000ff
2861 #define cfg_sgl_page_size_WORD                  word14
2862 #define cfg_sgl_pp_align_SHIFT                  16
2863 #define cfg_sgl_pp_align_MASK                   0x000000ff
2864 #define cfg_sgl_pp_align_WORD                   word14
2865         uint32_t word15;
2866         uint32_t word16;
2867         uint32_t word17;
2868         uint32_t word18;
2869         uint32_t word19;
2870 };
2871
2872 struct lpfc_mbx_get_sli4_parameters {
2873         struct mbox_header header;
2874         struct lpfc_sli4_parameters sli4_parameters;
2875 };
2876
2877 struct lpfc_rscr_desc_generic {
2878 #define LPFC_RSRC_DESC_WSIZE                    22
2879         uint32_t desc[LPFC_RSRC_DESC_WSIZE];
2880 };
2881
2882 struct lpfc_rsrc_desc_pcie {
2883         uint32_t word0;
2884 #define lpfc_rsrc_desc_pcie_type_SHIFT          0
2885 #define lpfc_rsrc_desc_pcie_type_MASK           0x000000ff
2886 #define lpfc_rsrc_desc_pcie_type_WORD           word0
2887 #define LPFC_RSRC_DESC_TYPE_PCIE                0x40
2888 #define lpfc_rsrc_desc_pcie_length_SHIFT        8
2889 #define lpfc_rsrc_desc_pcie_length_MASK         0x000000ff
2890 #define lpfc_rsrc_desc_pcie_length_WORD         word0
2891         uint32_t word1;
2892 #define lpfc_rsrc_desc_pcie_pfnum_SHIFT         0
2893 #define lpfc_rsrc_desc_pcie_pfnum_MASK          0x000000ff
2894 #define lpfc_rsrc_desc_pcie_pfnum_WORD          word1
2895         uint32_t reserved;
2896         uint32_t word3;
2897 #define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT     0
2898 #define lpfc_rsrc_desc_pcie_sriov_sta_MASK      0x000000ff
2899 #define lpfc_rsrc_desc_pcie_sriov_sta_WORD      word3
2900 #define lpfc_rsrc_desc_pcie_pf_sta_SHIFT        8
2901 #define lpfc_rsrc_desc_pcie_pf_sta_MASK         0x000000ff
2902 #define lpfc_rsrc_desc_pcie_pf_sta_WORD         word3
2903 #define lpfc_rsrc_desc_pcie_pf_type_SHIFT       16
2904 #define lpfc_rsrc_desc_pcie_pf_type_MASK        0x000000ff
2905 #define lpfc_rsrc_desc_pcie_pf_type_WORD        word3
2906         uint32_t word4;
2907 #define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT     0
2908 #define lpfc_rsrc_desc_pcie_nr_virtfn_MASK      0x0000ffff
2909 #define lpfc_rsrc_desc_pcie_nr_virtfn_WORD      word4
2910 };
2911
2912 struct lpfc_rsrc_desc_fcfcoe {
2913         uint32_t word0;
2914 #define lpfc_rsrc_desc_fcfcoe_type_SHIFT        0
2915 #define lpfc_rsrc_desc_fcfcoe_type_MASK         0x000000ff
2916 #define lpfc_rsrc_desc_fcfcoe_type_WORD         word0
2917 #define LPFC_RSRC_DESC_TYPE_FCFCOE              0x43
2918 #define lpfc_rsrc_desc_fcfcoe_length_SHIFT      8
2919 #define lpfc_rsrc_desc_fcfcoe_length_MASK       0x000000ff
2920 #define lpfc_rsrc_desc_fcfcoe_length_WORD       word0
2921 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD      0
2922 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH    72
2923 #define LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH    88
2924         uint32_t word1;
2925 #define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT       0
2926 #define lpfc_rsrc_desc_fcfcoe_vfnum_MASK        0x000000ff
2927 #define lpfc_rsrc_desc_fcfcoe_vfnum_WORD        word1
2928 #define lpfc_rsrc_desc_fcfcoe_pfnum_SHIFT       16
2929 #define lpfc_rsrc_desc_fcfcoe_pfnum_MASK        0x000007ff
2930 #define lpfc_rsrc_desc_fcfcoe_pfnum_WORD        word1
2931         uint32_t word2;
2932 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT     0
2933 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK      0x0000ffff
2934 #define lpfc_rsrc_desc_fcfcoe_rpi_cnt_WORD      word2
2935 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_SHIFT     16
2936 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK      0x0000ffff
2937 #define lpfc_rsrc_desc_fcfcoe_xri_cnt_WORD      word2
2938         uint32_t word3;
2939 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT      0
2940 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK       0x0000ffff
2941 #define lpfc_rsrc_desc_fcfcoe_wq_cnt_WORD       word3
2942 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_SHIFT      16
2943 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK       0x0000ffff
2944 #define lpfc_rsrc_desc_fcfcoe_rq_cnt_WORD       word3
2945         uint32_t word4;
2946 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT      0
2947 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK       0x0000ffff
2948 #define lpfc_rsrc_desc_fcfcoe_cq_cnt_WORD       word4
2949 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_SHIFT     16
2950 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK      0x0000ffff
2951 #define lpfc_rsrc_desc_fcfcoe_vpi_cnt_WORD      word4
2952         uint32_t word5;
2953 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT    0
2954 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK     0x0000ffff
2955 #define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_WORD     word5
2956 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_SHIFT     16
2957 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK      0x0000ffff
2958 #define lpfc_rsrc_desc_fcfcoe_vfi_cnt_WORD      word5
2959         uint32_t word6;
2960         uint32_t word7;
2961         uint32_t word8;
2962         uint32_t word9;
2963         uint32_t word10;
2964         uint32_t word11;
2965         uint32_t word12;
2966         uint32_t word13;
2967 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT      0
2968 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK       0x0000003f
2969 #define lpfc_rsrc_desc_fcfcoe_lnk_nr_WORD       word13
2970 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_SHIFT      6
2971 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK       0x00000003
2972 #define lpfc_rsrc_desc_fcfcoe_lnk_tp_WORD       word13
2973 #define lpfc_rsrc_desc_fcfcoe_lmc_SHIFT         8
2974 #define lpfc_rsrc_desc_fcfcoe_lmc_MASK          0x00000001
2975 #define lpfc_rsrc_desc_fcfcoe_lmc_WORD          word13
2976 #define lpfc_rsrc_desc_fcfcoe_lld_SHIFT         9
2977 #define lpfc_rsrc_desc_fcfcoe_lld_MASK          0x00000001
2978 #define lpfc_rsrc_desc_fcfcoe_lld_WORD          word13
2979 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_SHIFT      16
2980 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK       0x0000ffff
2981 #define lpfc_rsrc_desc_fcfcoe_eq_cnt_WORD       word13
2982 /* extended FC/FCoE Resource Descriptor when length = 88 bytes */
2983         uint32_t bw_min;
2984         uint32_t bw_max;
2985         uint32_t iops_min;
2986         uint32_t iops_max;
2987         uint32_t reserved[4];
2988 };
2989
2990 struct lpfc_func_cfg {
2991 #define LPFC_RSRC_DESC_MAX_NUM                  2
2992         uint32_t rsrc_desc_count;
2993         struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM];
2994 };
2995
2996 struct lpfc_mbx_get_func_cfg {
2997         struct mbox_header header;
2998 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE       0x0
2999 #define LPFC_CFG_TYPE_FACTURY_DEFAULT           0x1
3000 #define LPFC_CFG_TYPE_CURRENT_ACTIVE            0x2
3001         struct lpfc_func_cfg func_cfg;
3002 };
3003
3004 struct lpfc_prof_cfg {
3005 #define LPFC_RSRC_DESC_MAX_NUM                  2
3006         uint32_t rsrc_desc_count;
3007         struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM];
3008 };
3009
3010 struct lpfc_mbx_get_prof_cfg {
3011         struct mbox_header header;
3012 #define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE       0x0
3013 #define LPFC_CFG_TYPE_FACTURY_DEFAULT           0x1
3014 #define LPFC_CFG_TYPE_CURRENT_ACTIVE            0x2
3015         union {
3016                 struct {
3017                         uint32_t word10;
3018 #define lpfc_mbx_get_prof_cfg_prof_id_SHIFT     0
3019 #define lpfc_mbx_get_prof_cfg_prof_id_MASK      0x000000ff
3020 #define lpfc_mbx_get_prof_cfg_prof_id_WORD      word10
3021 #define lpfc_mbx_get_prof_cfg_prof_tp_SHIFT     8
3022 #define lpfc_mbx_get_prof_cfg_prof_tp_MASK      0x00000003
3023 #define lpfc_mbx_get_prof_cfg_prof_tp_WORD      word10
3024                 } request;
3025                 struct {
3026                         struct lpfc_prof_cfg prof_cfg;
3027                 } response;
3028         } u;
3029 };
3030
3031 struct lpfc_controller_attribute {
3032         uint32_t version_string[8];
3033         uint32_t manufacturer_name[8];
3034         uint32_t supported_modes;
3035         uint32_t word17;
3036 #define lpfc_cntl_attr_eprom_ver_lo_SHIFT       0
3037 #define lpfc_cntl_attr_eprom_ver_lo_MASK        0x000000ff
3038 #define lpfc_cntl_attr_eprom_ver_lo_WORD        word17
3039 #define lpfc_cntl_attr_eprom_ver_hi_SHIFT       8
3040 #define lpfc_cntl_attr_eprom_ver_hi_MASK        0x000000ff
3041 #define lpfc_cntl_attr_eprom_ver_hi_WORD        word17
3042         uint32_t mbx_da_struct_ver;
3043         uint32_t ep_fw_da_struct_ver;
3044         uint32_t ncsi_ver_str[3];
3045         uint32_t dflt_ext_timeout;
3046         uint32_t model_number[8];
3047         uint32_t description[16];
3048         uint32_t serial_number[8];
3049         uint32_t ip_ver_str[8];
3050         uint32_t fw_ver_str[8];
3051         uint32_t bios_ver_str[8];
3052         uint32_t redboot_ver_str[8];
3053         uint32_t driver_ver_str[8];
3054         uint32_t flash_fw_ver_str[8];
3055         uint32_t functionality;
3056         uint32_t word105;
3057 #define lpfc_cntl_attr_max_cbd_len_SHIFT        0
3058 #define lpfc_cntl_attr_max_cbd_len_MASK         0x0000ffff
3059 #define lpfc_cntl_attr_max_cbd_len_WORD         word105
3060 #define lpfc_cntl_attr_asic_rev_SHIFT           16
3061 #define lpfc_cntl_attr_asic_rev_MASK            0x000000ff
3062 #define lpfc_cntl_attr_asic_rev_WORD            word105
3063 #define lpfc_cntl_attr_gen_guid0_SHIFT          24
3064 #define lpfc_cntl_attr_gen_guid0_MASK           0x000000ff
3065 #define lpfc_cntl_attr_gen_guid0_WORD           word105
3066         uint32_t gen_guid1_12[3];
3067         uint32_t word109;
3068 #define lpfc_cntl_attr_gen_guid13_14_SHIFT      0
3069 #define lpfc_cntl_attr_gen_guid13_14_MASK       0x0000ffff
3070 #define lpfc_cntl_attr_gen_guid13_14_WORD       word109
3071 #define lpfc_cntl_attr_gen_guid15_SHIFT         16
3072 #define lpfc_cntl_attr_gen_guid15_MASK          0x000000ff
3073 #define lpfc_cntl_attr_gen_guid15_WORD          word109
3074 #define lpfc_cntl_attr_hba_port_cnt_SHIFT       24
3075 #define lpfc_cntl_attr_hba_port_cnt_MASK        0x000000ff
3076 #define lpfc_cntl_attr_hba_port_cnt_WORD        word109
3077         uint32_t word110;
3078 #define lpfc_cntl_attr_dflt_lnk_tmo_SHIFT       0
3079 #define lpfc_cntl_attr_dflt_lnk_tmo_MASK        0x0000ffff
3080 #define lpfc_cntl_attr_dflt_lnk_tmo_WORD        word110
3081 #define lpfc_cntl_attr_multi_func_dev_SHIFT     24
3082 #define lpfc_cntl_attr_multi_func_dev_MASK      0x000000ff
3083 #define lpfc_cntl_attr_multi_func_dev_WORD      word110
3084         uint32_t word111;
3085 #define lpfc_cntl_attr_cache_valid_SHIFT        0
3086 #define lpfc_cntl_attr_cache_valid_MASK         0x000000ff
3087 #define lpfc_cntl_attr_cache_valid_WORD         word111
3088 #define lpfc_cntl_attr_hba_status_SHIFT         8
3089 #define lpfc_cntl_attr_hba_status_MASK          0x000000ff
3090 #define lpfc_cntl_attr_hba_status_WORD          word111
3091 #define lpfc_cntl_attr_max_domain_SHIFT         16
3092 #define lpfc_cntl_attr_max_domain_MASK          0x000000ff
3093 #define lpfc_cntl_attr_max_domain_WORD          word111
3094 #define lpfc_cntl_attr_lnk_numb_SHIFT           24
3095 #define lpfc_cntl_attr_lnk_numb_MASK            0x0000003f
3096 #define lpfc_cntl_attr_lnk_numb_WORD            word111
3097 #define lpfc_cntl_attr_lnk_type_SHIFT           30
3098 #define lpfc_cntl_attr_lnk_type_MASK            0x00000003
3099 #define lpfc_cntl_attr_lnk_type_WORD            word111
3100         uint32_t fw_post_status;
3101         uint32_t hba_mtu[8];
3102         uint32_t word121;
3103         uint32_t reserved1[3];
3104         uint32_t word125;
3105 #define lpfc_cntl_attr_pci_vendor_id_SHIFT      0
3106 #define lpfc_cntl_attr_pci_vendor_id_MASK       0x0000ffff
3107 #define lpfc_cntl_attr_pci_vendor_id_WORD       word125
3108 #define lpfc_cntl_attr_pci_device_id_SHIFT      16
3109 #define lpfc_cntl_attr_pci_device_id_MASK       0x0000ffff
3110 #define lpfc_cntl_attr_pci_device_id_WORD       word125
3111         uint32_t word126;
3112 #define lpfc_cntl_attr_pci_subvdr_id_SHIFT      0
3113 #define lpfc_cntl_attr_pci_subvdr_id_MASK       0x0000ffff
3114 #define lpfc_cntl_attr_pci_subvdr_id_WORD       word126
3115 #define lpfc_cntl_attr_pci_subsys_id_SHIFT      16
3116 #define lpfc_cntl_attr_pci_subsys_id_MASK       0x0000ffff
3117 #define lpfc_cntl_attr_pci_subsys_id_WORD       word126
3118         uint32_t word127;
3119 #define lpfc_cntl_attr_pci_bus_num_SHIFT        0
3120 #define lpfc_cntl_attr_pci_bus_num_MASK         0x000000ff
3121 #define lpfc_cntl_attr_pci_bus_num_WORD         word127
3122 #define lpfc_cntl_attr_pci_dev_num_SHIFT        8
3123 #define lpfc_cntl_attr_pci_dev_num_MASK         0x000000ff
3124 #define lpfc_cntl_attr_pci_dev_num_WORD         word127
3125 #define lpfc_cntl_attr_pci_fnc_num_SHIFT        16
3126 #define lpfc_cntl_attr_pci_fnc_num_MASK         0x000000ff
3127 #define lpfc_cntl_attr_pci_fnc_num_WORD         word127
3128 #define lpfc_cntl_attr_inf_type_SHIFT           24
3129 #define lpfc_cntl_attr_inf_type_MASK            0x000000ff
3130 #define lpfc_cntl_attr_inf_type_WORD            word127
3131         uint32_t unique_id[2];
3132         uint32_t word130;
3133 #define lpfc_cntl_attr_num_netfil_SHIFT         0
3134 #define lpfc_cntl_attr_num_netfil_MASK          0x000000ff
3135 #define lpfc_cntl_attr_num_netfil_WORD          word130
3136         uint32_t reserved2[4];
3137 };
3138
3139 struct lpfc_mbx_get_cntl_attributes {
3140         union  lpfc_sli4_cfg_shdr cfg_shdr;
3141         struct lpfc_controller_attribute cntl_attr;
3142 };
3143
3144 struct lpfc_mbx_get_port_name {
3145         struct mbox_header header;
3146         union {
3147                 struct {
3148                         uint32_t word4;
3149 #define lpfc_mbx_get_port_name_lnk_type_SHIFT   0
3150 #define lpfc_mbx_get_port_name_lnk_type_MASK    0x00000003
3151 #define lpfc_mbx_get_port_name_lnk_type_WORD    word4
3152                 } request;
3153                 struct {
3154                         uint32_t word4;
3155 #define lpfc_mbx_get_port_name_name0_SHIFT      0
3156 #define lpfc_mbx_get_port_name_name0_MASK       0x000000FF
3157 #define lpfc_mbx_get_port_name_name0_WORD       word4
3158 #define lpfc_mbx_get_port_name_name1_SHIFT      8
3159 #define lpfc_mbx_get_port_name_name1_MASK       0x000000FF
3160 #define lpfc_mbx_get_port_name_name1_WORD       word4
3161 #define lpfc_mbx_get_port_name_name2_SHIFT      16
3162 #define lpfc_mbx_get_port_name_name2_MASK       0x000000FF
3163 #define lpfc_mbx_get_port_name_name2_WORD       word4
3164 #define lpfc_mbx_get_port_name_name3_SHIFT      24
3165 #define lpfc_mbx_get_port_name_name3_MASK       0x000000FF
3166 #define lpfc_mbx_get_port_name_name3_WORD       word4
3167 #define LPFC_LINK_NUMBER_0                      0
3168 #define LPFC_LINK_NUMBER_1                      1
3169 #define LPFC_LINK_NUMBER_2                      2
3170 #define LPFC_LINK_NUMBER_3                      3
3171                 } response;
3172         } u;
3173 };
3174
3175 /* Mailbox Completion Queue Error Messages */
3176 #define MB_CQE_STATUS_SUCCESS                   0x0
3177 #define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES   0x1
3178 #define MB_CQE_STATUS_INVALID_PARAMETER         0x2
3179 #define MB_CQE_STATUS_INSUFFICIENT_RESOURCES    0x3
3180 #define MB_CEQ_STATUS_QUEUE_FLUSHING            0x4
3181 #define MB_CQE_STATUS_DMA_FAILED                0x5
3182
3183 #define LPFC_MBX_WR_CONFIG_MAX_BDE              1
3184 struct lpfc_mbx_wr_object {
3185         struct mbox_header header;
3186         union {
3187                 struct {
3188                         uint32_t word4;
3189 #define lpfc_wr_object_eof_SHIFT                31
3190 #define lpfc_wr_object_eof_MASK                 0x00000001
3191 #define lpfc_wr_object_eof_WORD                 word4
3192 #define lpfc_wr_object_write_length_SHIFT       0
3193 #define lpfc_wr_object_write_length_MASK        0x00FFFFFF
3194 #define lpfc_wr_object_write_length_WORD        word4
3195                         uint32_t write_offset;
3196                         uint32_t object_name[26];
3197                         uint32_t bde_count;
3198                         struct ulp_bde64 bde[LPFC_MBX_WR_CONFIG_MAX_BDE];
3199                 } request;
3200                 struct {
3201                         uint32_t actual_write_length;
3202                 } response;
3203         } u;
3204 };
3205
3206 /* mailbox queue entry structure */
3207 struct lpfc_mqe {
3208         uint32_t word0;
3209 #define lpfc_mqe_status_SHIFT           16
3210 #define lpfc_mqe_status_MASK            0x0000FFFF
3211 #define lpfc_mqe_status_WORD            word0
3212 #define lpfc_mqe_command_SHIFT          8
3213 #define lpfc_mqe_command_MASK           0x000000FF
3214 #define lpfc_mqe_command_WORD           word0
3215         union {
3216                 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1];
3217                 /* sli4 mailbox commands */
3218                 struct lpfc_mbx_sli4_config sli4_config;
3219                 struct lpfc_mbx_init_vfi init_vfi;
3220                 struct lpfc_mbx_reg_vfi reg_vfi;
3221                 struct lpfc_mbx_reg_vfi unreg_vfi;
3222                 struct lpfc_mbx_init_vpi init_vpi;
3223                 struct lpfc_mbx_resume_rpi resume_rpi;
3224                 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl;
3225                 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry;
3226                 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry;
3227                 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl;
3228                 struct lpfc_mbx_reg_fcfi reg_fcfi;
3229                 struct lpfc_mbx_unreg_fcfi unreg_fcfi;
3230                 struct lpfc_mbx_mq_create mq_create;
3231                 struct lpfc_mbx_mq_create_ext mq_create_ext;
3232                 struct lpfc_mbx_eq_create eq_create;
3233                 struct lpfc_mbx_modify_eq_delay eq_delay;
3234                 struct lpfc_mbx_cq_create cq_create;
3235                 struct lpfc_mbx_wq_create wq_create;
3236                 struct lpfc_mbx_rq_create rq_create;
3237                 struct lpfc_mbx_mq_destroy mq_destroy;
3238                 struct lpfc_mbx_eq_destroy eq_destroy;
3239                 struct lpfc_mbx_cq_destroy cq_destroy;
3240                 struct lpfc_mbx_wq_destroy wq_destroy;
3241                 struct lpfc_mbx_rq_destroy rq_destroy;
3242                 struct lpfc_mbx_get_rsrc_extent_info rsrc_extent_info;
3243                 struct lpfc_mbx_alloc_rsrc_extents alloc_rsrc_extents;
3244                 struct lpfc_mbx_dealloc_rsrc_extents dealloc_rsrc_extents;
3245                 struct lpfc_mbx_post_sgl_pages post_sgl_pages;
3246                 struct lpfc_mbx_nembed_cmd nembed_cmd;
3247                 struct lpfc_mbx_read_rev read_rev;
3248                 struct lpfc_mbx_read_vpi read_vpi;
3249                 struct lpfc_mbx_read_config rd_config;
3250                 struct lpfc_mbx_request_features req_ftrs;
3251                 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl;
3252                 struct lpfc_mbx_query_fw_config query_fw_cfg;
3253                 struct lpfc_mbx_set_beacon_config beacon_config;
3254                 struct lpfc_mbx_supp_pages supp_pages;
3255                 struct lpfc_mbx_pc_sli4_params sli4_params;
3256                 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters;
3257                 struct lpfc_mbx_set_link_diag_state link_diag_state;
3258                 struct lpfc_mbx_set_link_diag_loopback link_diag_loopback;
3259                 struct lpfc_mbx_run_link_diag_test link_diag_test;
3260                 struct lpfc_mbx_get_func_cfg get_func_cfg;
3261                 struct lpfc_mbx_get_prof_cfg get_prof_cfg;
3262                 struct lpfc_mbx_wr_object wr_object;
3263                 struct lpfc_mbx_get_port_name get_port_name;
3264                 struct lpfc_mbx_memory_dump_type3 mem_dump_type3;
3265                 struct lpfc_mbx_nop nop;
3266         } un;
3267 };
3268
3269 struct lpfc_mcqe {
3270         uint32_t word0;
3271 #define lpfc_mcqe_status_SHIFT          0
3272 #define lpfc_mcqe_status_MASK           0x0000FFFF
3273 #define lpfc_mcqe_status_WORD           word0
3274 #define lpfc_mcqe_ext_status_SHIFT      16
3275 #define lpfc_mcqe_ext_status_MASK       0x0000FFFF
3276 #define lpfc_mcqe_ext_status_WORD       word0
3277         uint32_t mcqe_tag0;
3278         uint32_t mcqe_tag1;
3279         uint32_t trailer;
3280 #define lpfc_trailer_valid_SHIFT        31
3281 #define lpfc_trailer_valid_MASK         0x00000001
3282 #define lpfc_trailer_valid_WORD         trailer
3283 #define lpfc_trailer_async_SHIFT        30
3284 #define lpfc_trailer_async_MASK         0x00000001
3285 #define lpfc_trailer_async_WORD         trailer
3286 #define lpfc_trailer_hpi_SHIFT          29
3287 #define lpfc_trailer_hpi_MASK           0x00000001
3288 #define lpfc_trailer_hpi_WORD           trailer
3289 #define lpfc_trailer_completed_SHIFT    28
3290 #define lpfc_trailer_completed_MASK     0x00000001
3291 #define lpfc_trailer_completed_WORD     trailer
3292 #define lpfc_trailer_consumed_SHIFT     27
3293 #define lpfc_trailer_consumed_MASK      0x00000001
3294 #define lpfc_trailer_consumed_WORD      trailer
3295 #define lpfc_trailer_type_SHIFT         16
3296 #define lpfc_trailer_type_MASK          0x000000FF
3297 #define lpfc_trailer_type_WORD          trailer
3298 #define lpfc_trailer_code_SHIFT         8
3299 #define lpfc_trailer_code_MASK          0x000000FF
3300 #define lpfc_trailer_code_WORD          trailer
3301 #define LPFC_TRAILER_CODE_LINK  0x1
3302 #define LPFC_TRAILER_CODE_FCOE  0x2
3303 #define LPFC_TRAILER_CODE_DCBX  0x3
3304 #define LPFC_TRAILER_CODE_GRP5  0x5
3305 #define LPFC_TRAILER_CODE_FC    0x10
3306 #define LPFC_TRAILER_CODE_SLI   0x11
3307 };
3308
3309 struct lpfc_acqe_link {
3310         uint32_t word0;
3311 #define lpfc_acqe_link_speed_SHIFT              24
3312 #define lpfc_acqe_link_speed_MASK               0x000000FF
3313 #define lpfc_acqe_link_speed_WORD               word0
3314 #define LPFC_ASYNC_LINK_SPEED_ZERO              0x0
3315 #define LPFC_ASYNC_LINK_SPEED_10MBPS            0x1
3316 #define LPFC_ASYNC_LINK_SPEED_100MBPS           0x2
3317 #define LPFC_ASYNC_LINK_SPEED_1GBPS             0x3
3318 #define LPFC_ASYNC_LINK_SPEED_10GBPS            0x4
3319 #define LPFC_ASYNC_LINK_SPEED_20GBPS            0x5
3320 #define LPFC_ASYNC_LINK_SPEED_25GBPS            0x6
3321 #define LPFC_ASYNC_LINK_SPEED_40GBPS            0x7
3322 #define lpfc_acqe_link_duplex_SHIFT             16
3323 #define lpfc_acqe_link_duplex_MASK              0x000000FF
3324 #define lpfc_acqe_link_duplex_WORD              word0
3325 #define LPFC_ASYNC_LINK_DUPLEX_NONE             0x0
3326 #define LPFC_ASYNC_LINK_DUPLEX_HALF             0x1
3327 #define LPFC_ASYNC_LINK_DUPLEX_FULL             0x2
3328 #define lpfc_acqe_link_status_SHIFT             8
3329 #define lpfc_acqe_link_status_MASK              0x000000FF
3330 #define lpfc_acqe_link_status_WORD              word0
3331 #define LPFC_ASYNC_LINK_STATUS_DOWN             0x0
3332 #define LPFC_ASYNC_LINK_STATUS_UP               0x1
3333 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN     0x2
3334 #define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP       0x3
3335 #define lpfc_acqe_link_type_SHIFT               6
3336 #define lpfc_acqe_link_type_MASK                0x00000003
3337 #define lpfc_acqe_link_type_WORD                word0
3338 #define lpfc_acqe_link_number_SHIFT             0
3339 #define lpfc_acqe_link_number_MASK              0x0000003F
3340 #define lpfc_acqe_link_number_WORD              word0
3341         uint32_t word1;
3342 #define lpfc_acqe_link_fault_SHIFT      0
3343 #define lpfc_acqe_link_fault_MASK       0x000000FF
3344 #define lpfc_acqe_link_fault_WORD       word1
3345 #define LPFC_ASYNC_LINK_FAULT_NONE      0x0
3346 #define LPFC_ASYNC_LINK_FAULT_LOCAL     0x1
3347 #define LPFC_ASYNC_LINK_FAULT_REMOTE    0x2
3348 #define lpfc_acqe_logical_link_speed_SHIFT      16
3349 #define lpfc_acqe_logical_link_speed_MASK       0x0000FFFF
3350 #define lpfc_acqe_logical_link_speed_WORD       word1
3351         uint32_t event_tag;
3352         uint32_t trailer;
3353 #define LPFC_LINK_EVENT_TYPE_PHYSICAL   0x0
3354 #define LPFC_LINK_EVENT_TYPE_VIRTUAL    0x1
3355 };
3356
3357 struct lpfc_acqe_fip {
3358         uint32_t index;
3359         uint32_t word1;
3360 #define lpfc_acqe_fip_fcf_count_SHIFT           0
3361 #define lpfc_acqe_fip_fcf_count_MASK            0x0000FFFF
3362 #define lpfc_acqe_fip_fcf_count_WORD            word1
3363 #define lpfc_acqe_fip_event_type_SHIFT          16
3364 #define lpfc_acqe_fip_event_type_MASK           0x0000FFFF
3365 #define lpfc_acqe_fip_event_type_WORD           word1
3366         uint32_t event_tag;
3367         uint32_t trailer;
3368 #define LPFC_FIP_EVENT_TYPE_NEW_FCF             0x1
3369 #define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL      0x2
3370 #define LPFC_FIP_EVENT_TYPE_FCF_DEAD            0x3
3371 #define LPFC_FIP_EVENT_TYPE_CVL                 0x4
3372 #define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD       0x5
3373 };
3374
3375 struct lpfc_acqe_dcbx {
3376         uint32_t tlv_ttl;
3377         uint32_t reserved;
3378         uint32_t event_tag;
3379         uint32_t trailer;
3380 };
3381
3382 struct lpfc_acqe_grp5 {
3383         uint32_t word0;
3384 #define lpfc_acqe_grp5_type_SHIFT               6
3385 #define lpfc_acqe_grp5_type_MASK                0x00000003
3386 #define lpfc_acqe_grp5_type_WORD                word0
3387 #define lpfc_acqe_grp5_number_SHIFT             0
3388 #define lpfc_acqe_grp5_number_MASK              0x0000003F
3389 #define lpfc_acqe_grp5_number_WORD              word0
3390         uint32_t word1;
3391 #define lpfc_acqe_grp5_llink_spd_SHIFT  16
3392 #define lpfc_acqe_grp5_llink_spd_MASK   0x0000FFFF
3393 #define lpfc_acqe_grp5_llink_spd_WORD   word1
3394         uint32_t event_tag;
3395         uint32_t trailer;
3396 };
3397
3398 struct lpfc_acqe_fc_la {
3399         uint32_t word0;
3400 #define lpfc_acqe_fc_la_speed_SHIFT             24
3401 #define lpfc_acqe_fc_la_speed_MASK              0x000000FF
3402 #define lpfc_acqe_fc_la_speed_WORD              word0
3403 #define LPFC_FC_LA_SPEED_UNKNOWN                0x0
3404 #define LPFC_FC_LA_SPEED_1G             0x1
3405 #define LPFC_FC_LA_SPEED_2G             0x2
3406 #define LPFC_FC_LA_SPEED_4G             0x4
3407 #define LPFC_FC_LA_SPEED_8G             0x8
3408 #define LPFC_FC_LA_SPEED_10G            0xA
3409 #define LPFC_FC_LA_SPEED_16G            0x10
3410 #define LPFC_FC_LA_SPEED_32G            0x20
3411 #define lpfc_acqe_fc_la_topology_SHIFT          16
3412 #define lpfc_acqe_fc_la_topology_MASK           0x000000FF
3413 #define lpfc_acqe_fc_la_topology_WORD           word0
3414 #define LPFC_FC_LA_TOP_UNKOWN           0x0
3415 #define LPFC_FC_LA_TOP_P2P              0x1
3416 #define LPFC_FC_LA_TOP_FCAL             0x2
3417 #define LPFC_FC_LA_TOP_INTERNAL_LOOP    0x3
3418 #define LPFC_FC_LA_TOP_SERDES_LOOP      0x4
3419 #define lpfc_acqe_fc_la_att_type_SHIFT          8
3420 #define lpfc_acqe_fc_la_att_type_MASK           0x000000FF
3421 #define lpfc_acqe_fc_la_att_type_WORD           word0
3422 #define LPFC_FC_LA_TYPE_LINK_UP         0x1
3423 #define LPFC_FC_LA_TYPE_LINK_DOWN       0x2
3424 #define LPFC_FC_LA_TYPE_NO_HARD_ALPA    0x3
3425 #define lpfc_acqe_fc_la_port_type_SHIFT         6
3426 #define lpfc_acqe_fc_la_port_type_MASK          0x00000003
3427 #define lpfc_acqe_fc_la_port_type_WORD          word0
3428 #define LPFC_LINK_TYPE_ETHERNET         0x0
3429 #define LPFC_LINK_TYPE_FC               0x1
3430 #define lpfc_acqe_fc_la_port_number_SHIFT       0
3431 #define lpfc_acqe_fc_la_port_number_MASK        0x0000003F
3432 #define lpfc_acqe_fc_la_port_number_WORD        word0
3433         uint32_t word1;
3434 #define lpfc_acqe_fc_la_llink_spd_SHIFT         16
3435 #define lpfc_acqe_fc_la_llink_spd_MASK          0x0000FFFF
3436 #define lpfc_acqe_fc_la_llink_spd_WORD          word1
3437 #define lpfc_acqe_fc_la_fault_SHIFT             0
3438 #define lpfc_acqe_fc_la_fault_MASK              0x000000FF
3439 #define lpfc_acqe_fc_la_fault_WORD              word1
3440 #define LPFC_FC_LA_FAULT_NONE           0x0
3441 #define LPFC_FC_LA_FAULT_LOCAL          0x1
3442 #define LPFC_FC_LA_FAULT_REMOTE         0x2
3443         uint32_t event_tag;
3444         uint32_t trailer;
3445 #define LPFC_FC_LA_EVENT_TYPE_FC_LINK           0x1
3446 #define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK       0x2
3447 };
3448
3449 struct lpfc_acqe_misconfigured_event {
3450         struct {
3451         uint32_t word0;
3452 #define lpfc_sli_misconfigured_port0_SHIFT      0
3453 #define lpfc_sli_misconfigured_port0_MASK       0x000000FF
3454 #define lpfc_sli_misconfigured_port0_WORD       word0
3455 #define lpfc_sli_misconfigured_port1_SHIFT      8
3456 #define lpfc_sli_misconfigured_port1_MASK       0x000000FF
3457 #define lpfc_sli_misconfigured_port1_WORD       word0
3458 #define lpfc_sli_misconfigured_port2_SHIFT      16
3459 #define lpfc_sli_misconfigured_port2_MASK       0x000000FF
3460 #define lpfc_sli_misconfigured_port2_WORD       word0
3461 #define lpfc_sli_misconfigured_port3_SHIFT      24
3462 #define lpfc_sli_misconfigured_port3_MASK       0x000000FF
3463 #define lpfc_sli_misconfigured_port3_WORD       word0
3464         } theEvent;
3465 #define LPFC_SLI_EVENT_STATUS_VALID                     0x00
3466 #define LPFC_SLI_EVENT_STATUS_NOT_PRESENT       0x01
3467 #define LPFC_SLI_EVENT_STATUS_WRONG_TYPE        0x02
3468 #define LPFC_SLI_EVENT_STATUS_UNSUPPORTED       0x03
3469 };
3470
3471 struct lpfc_acqe_sli {
3472         uint32_t event_data1;
3473         uint32_t event_data2;
3474         uint32_t reserved;
3475         uint32_t trailer;
3476 #define LPFC_SLI_EVENT_TYPE_PORT_ERROR          0x1
3477 #define LPFC_SLI_EVENT_TYPE_OVER_TEMP           0x2
3478 #define LPFC_SLI_EVENT_TYPE_NORM_TEMP           0x3
3479 #define LPFC_SLI_EVENT_TYPE_NVLOG_POST          0x4
3480 #define LPFC_SLI_EVENT_TYPE_DIAG_DUMP           0x5
3481 #define LPFC_SLI_EVENT_TYPE_MISCONFIGURED       0x9
3482 #define LPFC_SLI_EVENT_TYPE_REMOTE_DPORT        0xA
3483 };
3484
3485 /*
3486  * Define the bootstrap mailbox (bmbx) region used to communicate
3487  * mailbox command between the host and port. The mailbox consists
3488  * of a payload area of 256 bytes and a completion queue of length
3489  * 16 bytes.
3490  */
3491 struct lpfc_bmbx_create {
3492         struct lpfc_mqe mqe;
3493         struct lpfc_mcqe mcqe;
3494 };
3495
3496 #define SGL_ALIGN_SZ 64
3497 #define SGL_PAGE_SIZE 4096
3498 /* align SGL addr on a size boundary - adjust address up */
3499 #define NO_XRI  0xffff
3500
3501 struct wqe_common {
3502         uint32_t word6;
3503 #define wqe_xri_tag_SHIFT     0
3504 #define wqe_xri_tag_MASK      0x0000FFFF
3505 #define wqe_xri_tag_WORD      word6
3506 #define wqe_ctxt_tag_SHIFT    16
3507 #define wqe_ctxt_tag_MASK     0x0000FFFF
3508 #define wqe_ctxt_tag_WORD     word6
3509         uint32_t word7;
3510 #define wqe_dif_SHIFT         0
3511 #define wqe_dif_MASK          0x00000003
3512 #define wqe_dif_WORD          word7
3513 #define LPFC_WQE_DIF_PASSTHRU   1
3514 #define LPFC_WQE_DIF_STRIP      2
3515 #define LPFC_WQE_DIF_INSERT     3
3516 #define wqe_ct_SHIFT          2
3517 #define wqe_ct_MASK           0x00000003
3518 #define wqe_ct_WORD           word7
3519 #define wqe_status_SHIFT      4
3520 #define wqe_status_MASK       0x0000000f
3521 #define wqe_status_WORD       word7
3522 #define wqe_cmnd_SHIFT        8
3523 #define wqe_cmnd_MASK         0x000000ff
3524 #define wqe_cmnd_WORD         word7
3525 #define wqe_class_SHIFT       16
3526 #define wqe_class_MASK        0x00000007
3527 #define wqe_class_WORD        word7
3528 #define wqe_ar_SHIFT          19
3529 #define wqe_ar_MASK           0x00000001
3530 #define wqe_ar_WORD           word7
3531 #define wqe_ag_SHIFT          wqe_ar_SHIFT
3532 #define wqe_ag_MASK           wqe_ar_MASK
3533 #define wqe_ag_WORD           wqe_ar_WORD
3534 #define wqe_pu_SHIFT          20
3535 #define wqe_pu_MASK           0x00000003
3536 #define wqe_pu_WORD           word7
3537 #define wqe_erp_SHIFT         22
3538 #define wqe_erp_MASK          0x00000001
3539 #define wqe_erp_WORD          word7
3540 #define wqe_conf_SHIFT        wqe_erp_SHIFT
3541 #define wqe_conf_MASK         wqe_erp_MASK
3542 #define wqe_conf_WORD         wqe_erp_WORD
3543 #define wqe_lnk_SHIFT         23
3544 #define wqe_lnk_MASK          0x00000001
3545 #define wqe_lnk_WORD          word7
3546 #define wqe_tmo_SHIFT         24
3547 #define wqe_tmo_MASK          0x000000ff
3548 #define wqe_tmo_WORD          word7
3549         uint32_t abort_tag; /* word 8 in WQE */
3550         uint32_t word9;
3551 #define wqe_reqtag_SHIFT      0
3552 #define wqe_reqtag_MASK       0x0000FFFF
3553 #define wqe_reqtag_WORD       word9
3554 #define wqe_temp_rpi_SHIFT    16
3555 #define wqe_temp_rpi_MASK     0x0000FFFF
3556 #define wqe_temp_rpi_WORD     word9
3557 #define wqe_rcvoxid_SHIFT     16
3558 #define wqe_rcvoxid_MASK      0x0000FFFF
3559 #define wqe_rcvoxid_WORD      word9
3560         uint32_t word10;
3561 #define wqe_ebde_cnt_SHIFT    0
3562 #define wqe_ebde_cnt_MASK     0x0000000f
3563 #define wqe_ebde_cnt_WORD     word10
3564 #define wqe_oas_SHIFT         6
3565 #define wqe_oas_MASK          0x00000001
3566 #define wqe_oas_WORD          word10
3567 #define wqe_lenloc_SHIFT      7
3568 #define wqe_lenloc_MASK       0x00000003
3569 #define wqe_lenloc_WORD       word10
3570 #define LPFC_WQE_LENLOC_NONE            0
3571 #define LPFC_WQE_LENLOC_WORD3   1
3572 #define LPFC_WQE_LENLOC_WORD12  2
3573 #define LPFC_WQE_LENLOC_WORD4   3
3574 #define wqe_qosd_SHIFT        9
3575 #define wqe_qosd_MASK         0x00000001
3576 #define wqe_qosd_WORD         word10
3577 #define wqe_xbl_SHIFT         11
3578 #define wqe_xbl_MASK          0x00000001
3579 #define wqe_xbl_WORD          word10
3580 #define wqe_iod_SHIFT         13
3581 #define wqe_iod_MASK          0x00000001
3582 #define wqe_iod_WORD          word10
3583 #define LPFC_WQE_IOD_WRITE      0
3584 #define LPFC_WQE_IOD_READ       1
3585 #define wqe_dbde_SHIFT        14
3586 #define wqe_dbde_MASK         0x00000001
3587 #define wqe_dbde_WORD         word10
3588 #define wqe_wqes_SHIFT        15
3589 #define wqe_wqes_MASK         0x00000001
3590 #define wqe_wqes_WORD         word10
3591 /* Note that this field overlaps above fields */
3592 #define wqe_wqid_SHIFT        1
3593 #define wqe_wqid_MASK         0x00007fff
3594 #define wqe_wqid_WORD         word10
3595 #define wqe_pri_SHIFT         16
3596 #define wqe_pri_MASK          0x00000007
3597 #define wqe_pri_WORD          word10
3598 #define wqe_pv_SHIFT          19
3599 #define wqe_pv_MASK           0x00000001
3600 #define wqe_pv_WORD           word10
3601 #define wqe_xc_SHIFT          21
3602 #define wqe_xc_MASK           0x00000001
3603 #define wqe_xc_WORD           word10
3604 #define wqe_sr_SHIFT          22
3605 #define wqe_sr_MASK           0x00000001
3606 #define wqe_sr_WORD           word10
3607 #define wqe_ccpe_SHIFT        23
3608 #define wqe_ccpe_MASK         0x00000001
3609 #define wqe_ccpe_WORD         word10
3610 #define wqe_ccp_SHIFT         24
3611 #define wqe_ccp_MASK          0x000000ff
3612 #define wqe_ccp_WORD          word10
3613         uint32_t word11;
3614 #define wqe_cmd_type_SHIFT    0
3615 #define wqe_cmd_type_MASK     0x0000000f
3616 #define wqe_cmd_type_WORD     word11
3617 #define wqe_els_id_SHIFT      4
3618 #define wqe_els_id_MASK       0x00000003
3619 #define wqe_els_id_WORD       word11
3620 #define LPFC_ELS_ID_FLOGI       3
3621 #define LPFC_ELS_ID_FDISC       2
3622 #define LPFC_ELS_ID_LOGO        1
3623 #define LPFC_ELS_ID_DEFAULT     0
3624 #define wqe_wqec_SHIFT        7
3625 #define wqe_wqec_MASK         0x00000001
3626 #define wqe_wqec_WORD         word11
3627 #define wqe_cqid_SHIFT        16
3628 #define wqe_cqid_MASK         0x0000ffff
3629 #define wqe_cqid_WORD         word11
3630 #define LPFC_WQE_CQ_ID_DEFAULT  0xffff
3631 };
3632
3633 struct wqe_did {
3634         uint32_t word5;
3635 #define wqe_els_did_SHIFT         0
3636 #define wqe_els_did_MASK          0x00FFFFFF
3637 #define wqe_els_did_WORD          word5
3638 #define wqe_xmit_bls_pt_SHIFT         28
3639 #define wqe_xmit_bls_pt_MASK          0x00000003
3640 #define wqe_xmit_bls_pt_WORD          word5
3641 #define wqe_xmit_bls_ar_SHIFT         30
3642 #define wqe_xmit_bls_ar_MASK          0x00000001
3643 #define wqe_xmit_bls_ar_WORD          word5
3644 #define wqe_xmit_bls_xo_SHIFT         31
3645 #define wqe_xmit_bls_xo_MASK          0x00000001
3646 #define wqe_xmit_bls_xo_WORD          word5
3647 };
3648
3649 struct lpfc_wqe_generic{
3650         struct ulp_bde64 bde;
3651         uint32_t word3;
3652         uint32_t word4;
3653         uint32_t word5;
3654         struct wqe_common wqe_com;
3655         uint32_t payload[4];
3656 };
3657
3658 struct els_request64_wqe {
3659         struct ulp_bde64 bde;
3660         uint32_t payload_len;
3661         uint32_t word4;
3662 #define els_req64_sid_SHIFT         0
3663 #define els_req64_sid_MASK          0x00FFFFFF
3664 #define els_req64_sid_WORD          word4
3665 #define els_req64_sp_SHIFT          24
3666 #define els_req64_sp_MASK           0x00000001
3667 #define els_req64_sp_WORD           word4
3668 #define els_req64_vf_SHIFT          25
3669 #define els_req64_vf_MASK           0x00000001
3670 #define els_req64_vf_WORD           word4
3671         struct wqe_did  wqe_dest;
3672         struct wqe_common wqe_com; /* words 6-11 */
3673         uint32_t word12;
3674 #define els_req64_vfid_SHIFT        1
3675 #define els_req64_vfid_MASK         0x00000FFF
3676 #define els_req64_vfid_WORD         word12
3677 #define els_req64_pri_SHIFT         13
3678 #define els_req64_pri_MASK          0x00000007
3679 #define els_req64_pri_WORD          word12
3680         uint32_t word13;
3681 #define els_req64_hopcnt_SHIFT      24
3682 #define els_req64_hopcnt_MASK       0x000000ff
3683 #define els_req64_hopcnt_WORD       word13
3684         uint32_t word14;
3685         uint32_t max_response_payload_len;
3686 };
3687
3688 struct xmit_els_rsp64_wqe {
3689         struct ulp_bde64 bde;
3690         uint32_t response_payload_len;
3691         uint32_t word4;
3692 #define els_rsp64_sid_SHIFT         0
3693 #define els_rsp64_sid_MASK          0x00FFFFFF
3694 #define els_rsp64_sid_WORD          word4
3695 #define els_rsp64_sp_SHIFT          24
3696 #define els_rsp64_sp_MASK           0x00000001
3697 #define els_rsp64_sp_WORD           word4
3698         struct wqe_did wqe_dest;
3699         struct wqe_common wqe_com; /* words 6-11 */
3700         uint32_t word12;
3701 #define wqe_rsp_temp_rpi_SHIFT    0
3702 #define wqe_rsp_temp_rpi_MASK     0x0000FFFF
3703 #define wqe_rsp_temp_rpi_WORD     word12
3704         uint32_t rsvd_13_15[3];
3705 };
3706
3707 struct xmit_bls_rsp64_wqe {
3708         uint32_t payload0;
3709 /* Payload0 for BA_ACC */
3710 #define xmit_bls_rsp64_acc_seq_id_SHIFT        16
3711 #define xmit_bls_rsp64_acc_seq_id_MASK         0x000000ff
3712 #define xmit_bls_rsp64_acc_seq_id_WORD         payload0
3713 #define xmit_bls_rsp64_acc_seq_id_vald_SHIFT   24
3714 #define xmit_bls_rsp64_acc_seq_id_vald_MASK    0x000000ff
3715 #define xmit_bls_rsp64_acc_seq_id_vald_WORD    payload0
3716 /* Payload0 for BA_RJT */
3717 #define xmit_bls_rsp64_rjt_vspec_SHIFT   0
3718 #define xmit_bls_rsp64_rjt_vspec_MASK    0x000000ff
3719 #define xmit_bls_rsp64_rjt_vspec_WORD    payload0
3720 #define xmit_bls_rsp64_rjt_expc_SHIFT    8
3721 #define xmit_bls_rsp64_rjt_expc_MASK     0x000000ff
3722 #define xmit_bls_rsp64_rjt_expc_WORD     payload0
3723 #define xmit_bls_rsp64_rjt_rsnc_SHIFT    16
3724 #define xmit_bls_rsp64_rjt_rsnc_MASK     0x000000ff
3725 #define xmit_bls_rsp64_rjt_rsnc_WORD     payload0
3726         uint32_t word1;
3727 #define xmit_bls_rsp64_rxid_SHIFT  0
3728 #define xmit_bls_rsp64_rxid_MASK   0x0000ffff
3729 #define xmit_bls_rsp64_rxid_WORD   word1
3730 #define xmit_bls_rsp64_oxid_SHIFT  16
3731 #define xmit_bls_rsp64_oxid_MASK   0x0000ffff
3732 #define xmit_bls_rsp64_oxid_WORD   word1
3733         uint32_t word2;
3734 #define xmit_bls_rsp64_seqcnthi_SHIFT  0
3735 #define xmit_bls_rsp64_seqcnthi_MASK   0x0000ffff
3736 #define xmit_bls_rsp64_seqcnthi_WORD   word2
3737 #define xmit_bls_rsp64_seqcntlo_SHIFT  16
3738 #define xmit_bls_rsp64_seqcntlo_MASK   0x0000ffff
3739 #define xmit_bls_rsp64_seqcntlo_WORD   word2
3740         uint32_t rsrvd3;
3741         uint32_t rsrvd4;
3742         struct wqe_did  wqe_dest;
3743         struct wqe_common wqe_com; /* words 6-11 */
3744         uint32_t word12;
3745 #define xmit_bls_rsp64_temprpi_SHIFT  0
3746 #define xmit_bls_rsp64_temprpi_MASK   0x0000ffff
3747 #define xmit_bls_rsp64_temprpi_WORD   word12
3748         uint32_t rsvd_13_15[3];
3749 };
3750
3751 struct wqe_rctl_dfctl {
3752         uint32_t word5;
3753 #define wqe_si_SHIFT 2
3754 #define wqe_si_MASK  0x000000001
3755 #define wqe_si_WORD  word5
3756 #define wqe_la_SHIFT 3
3757 #define wqe_la_MASK  0x000000001
3758 #define wqe_la_WORD  word5
3759 #define wqe_xo_SHIFT    6
3760 #define wqe_xo_MASK     0x000000001
3761 #define wqe_xo_WORD     word5
3762 #define wqe_ls_SHIFT 7
3763 #define wqe_ls_MASK  0x000000001
3764 #define wqe_ls_WORD  word5
3765 #define wqe_dfctl_SHIFT 8
3766 #define wqe_dfctl_MASK  0x0000000ff
3767 #define wqe_dfctl_WORD  word5
3768 #define wqe_type_SHIFT 16
3769 #define wqe_type_MASK  0x0000000ff
3770 #define wqe_type_WORD  word5
3771 #define wqe_rctl_SHIFT 24
3772 #define wqe_rctl_MASK  0x0000000ff
3773 #define wqe_rctl_WORD  word5
3774 };
3775
3776 struct xmit_seq64_wqe {
3777         struct ulp_bde64 bde;
3778         uint32_t rsvd3;
3779         uint32_t relative_offset;
3780         struct wqe_rctl_dfctl wge_ctl;
3781         struct wqe_common wqe_com; /* words 6-11 */
3782         uint32_t xmit_len;
3783         uint32_t rsvd_12_15[3];
3784 };
3785 struct xmit_bcast64_wqe {
3786         struct ulp_bde64 bde;
3787         uint32_t seq_payload_len;
3788         uint32_t rsvd4;
3789         struct wqe_rctl_dfctl wge_ctl; /* word 5 */
3790         struct wqe_common wqe_com;     /* words 6-11 */
3791         uint32_t rsvd_12_15[4];
3792 };
3793
3794 struct gen_req64_wqe {
3795         struct ulp_bde64 bde;
3796         uint32_t request_payload_len;
3797         uint32_t relative_offset;
3798         struct wqe_rctl_dfctl wge_ctl; /* word 5 */
3799         struct wqe_common wqe_com;     /* words 6-11 */
3800         uint32_t rsvd_12_14[3];
3801         uint32_t max_response_payload_len;
3802 };
3803
3804 struct create_xri_wqe {
3805         uint32_t rsrvd[5];           /* words 0-4 */
3806         struct wqe_did  wqe_dest;  /* word 5 */
3807         struct wqe_common wqe_com; /* words 6-11 */
3808         uint32_t rsvd_12_15[4];         /* word 12-15 */
3809 };
3810
3811 #define T_REQUEST_TAG 3
3812 #define T_XRI_TAG 1
3813
3814 struct abort_cmd_wqe {
3815         uint32_t rsrvd[3];
3816         uint32_t word3;
3817 #define abort_cmd_ia_SHIFT  0
3818 #define abort_cmd_ia_MASK  0x000000001
3819 #define abort_cmd_ia_WORD  word3
3820 #define abort_cmd_criteria_SHIFT  8
3821 #define abort_cmd_criteria_MASK  0x0000000ff
3822 #define abort_cmd_criteria_WORD  word3
3823         uint32_t rsrvd4;
3824         uint32_t rsrvd5;
3825         struct wqe_common wqe_com;     /* words 6-11 */
3826         uint32_t rsvd_12_15[4];         /* word 12-15 */
3827 };
3828
3829 struct fcp_iwrite64_wqe {
3830         struct ulp_bde64 bde;
3831         uint32_t word3;
3832 #define cmd_buff_len_SHIFT  16
3833 #define cmd_buff_len_MASK  0x00000ffff
3834 #define cmd_buff_len_WORD  word3
3835 #define payload_offset_len_SHIFT 0
3836 #define payload_offset_len_MASK 0x0000ffff
3837 #define payload_offset_len_WORD word3
3838         uint32_t total_xfer_len;
3839         uint32_t initial_xfer_len;
3840         struct wqe_common wqe_com;     /* words 6-11 */
3841         uint32_t rsrvd12;
3842         struct ulp_bde64 ph_bde;       /* words 13-15 */
3843 };
3844
3845 struct fcp_iread64_wqe {
3846         struct ulp_bde64 bde;
3847         uint32_t word3;
3848 #define cmd_buff_len_SHIFT  16
3849 #define cmd_buff_len_MASK  0x00000ffff
3850 #define cmd_buff_len_WORD  word3
3851 #define payload_offset_len_SHIFT 0
3852 #define payload_offset_len_MASK 0x0000ffff
3853 #define payload_offset_len_WORD word3
3854         uint32_t total_xfer_len;       /* word 4 */
3855         uint32_t rsrvd5;               /* word 5 */
3856         struct wqe_common wqe_com;     /* words 6-11 */
3857         uint32_t rsrvd12;
3858         struct ulp_bde64 ph_bde;       /* words 13-15 */
3859 };
3860
3861 struct fcp_icmnd64_wqe {
3862         struct ulp_bde64 bde;          /* words 0-2 */
3863         uint32_t word3;
3864 #define cmd_buff_len_SHIFT  16
3865 #define cmd_buff_len_MASK  0x00000ffff
3866 #define cmd_buff_len_WORD  word3
3867 #define payload_offset_len_SHIFT 0
3868 #define payload_offset_len_MASK 0x0000ffff
3869 #define payload_offset_len_WORD word3
3870         uint32_t rsrvd4;               /* word 4 */
3871         uint32_t rsrvd5;               /* word 5 */
3872         struct wqe_common wqe_com;     /* words 6-11 */
3873         uint32_t rsvd_12_15[4];        /* word 12-15 */
3874 };
3875
3876
3877 union lpfc_wqe {
3878         uint32_t words[16];
3879         struct lpfc_wqe_generic generic;
3880         struct fcp_icmnd64_wqe fcp_icmd;
3881         struct fcp_iread64_wqe fcp_iread;
3882         struct fcp_iwrite64_wqe fcp_iwrite;
3883         struct abort_cmd_wqe abort_cmd;
3884         struct create_xri_wqe create_xri;
3885         struct xmit_bcast64_wqe xmit_bcast64;
3886         struct xmit_seq64_wqe xmit_sequence;
3887         struct xmit_bls_rsp64_wqe xmit_bls_rsp;
3888         struct xmit_els_rsp64_wqe xmit_els_rsp;
3889         struct els_request64_wqe els_req;
3890         struct gen_req64_wqe gen_req;
3891 };
3892
3893 union lpfc_wqe128 {
3894         uint32_t words[32];
3895         struct lpfc_wqe_generic generic;
3896         struct xmit_seq64_wqe xmit_sequence;
3897         struct gen_req64_wqe gen_req;
3898 };
3899
3900 #define LPFC_GROUP_OJECT_MAGIC_NUM              0xfeaa0001
3901 #define LPFC_FILE_TYPE_GROUP                    0xf7
3902 #define LPFC_FILE_ID_GROUP                      0xa2
3903 struct lpfc_grp_hdr {
3904         uint32_t size;
3905         uint32_t magic_number;
3906         uint32_t word2;
3907 #define lpfc_grp_hdr_file_type_SHIFT    24
3908 #define lpfc_grp_hdr_file_type_MASK     0x000000FF
3909 #define lpfc_grp_hdr_file_type_WORD     word2
3910 #define lpfc_grp_hdr_id_SHIFT           16
3911 #define lpfc_grp_hdr_id_MASK            0x000000FF
3912 #define lpfc_grp_hdr_id_WORD            word2
3913         uint8_t rev_name[128];
3914         uint8_t date[12];
3915         uint8_t revision[32];
3916 };
3917
3918 #define FCP_COMMAND 0x0
3919 #define FCP_COMMAND_DATA_OUT 0x1
3920 #define ELS_COMMAND_NON_FIP 0xC
3921 #define ELS_COMMAND_FIP 0xD
3922 #define OTHER_COMMAND 0x8
3923
3924 #define LPFC_FW_DUMP    1
3925 #define LPFC_FW_RESET   2
3926 #define LPFC_DV_RESET   3