drivers/rtc/rtc-jz4740.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
   4  *  Copyright (C) 2010, Paul Cercueil <paul@crapouillou.net>
   5  *       JZ4740 SoC RTC driver
   6  */
   7
   8 #include <linux/clk.h>
   9 #include <linux/io.h>
  10 #include <linux/kernel.h>
  11 #include <linux/module.h>
  12 #include <linux/of_device.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/pm_wakeirq.h>
  15 #include <linux/reboot.h>
  16 #include <linux/rtc.h>
  17 #include <linux/slab.h>
  18 #include <linux/spinlock.h>
  19
  20 #define JZ_REG_RTC_CTRL         0x00
  21 #define JZ_REG_RTC_SEC          0x04
  22 #define JZ_REG_RTC_SEC_ALARM    0x08
  23 #define JZ_REG_RTC_REGULATOR    0x0C
  24 #define JZ_REG_RTC_HIBERNATE    0x20
  25 #define JZ_REG_RTC_WAKEUP_FILTER        0x24
  26 #define JZ_REG_RTC_RESET_COUNTER        0x28
  27 #define JZ_REG_RTC_SCRATCHPAD   0x34
  28
  29 /* The following are present on the jz4780 */
  30 #define JZ_REG_RTC_WENR 0x3C
  31 #define JZ_RTC_WENR_WEN BIT(31)
  32
  33 #define JZ_RTC_CTRL_WRDY        BIT(7)
  34 #define JZ_RTC_CTRL_1HZ         BIT(6)
  35 #define JZ_RTC_CTRL_1HZ_IRQ     BIT(5)
  36 #define JZ_RTC_CTRL_AF          BIT(4)
  37 #define JZ_RTC_CTRL_AF_IRQ      BIT(3)
  38 #define JZ_RTC_CTRL_AE          BIT(2)
  39 #define JZ_RTC_CTRL_ENABLE      BIT(0)
  40
  41 /* Magic value to enable writes on jz4780 */
  42 #define JZ_RTC_WENR_MAGIC       0xA55A
  43
  44 #define JZ_RTC_WAKEUP_FILTER_MASK       0x0000FFE0
  45 #define JZ_RTC_RESET_COUNTER_MASK       0x00000FE0
  46
  47 enum jz4740_rtc_type {
  48         ID_JZ4740,
  49         ID_JZ4780,
  50 };
  51
  52 struct jz4740_rtc {
  53         void __iomem *base;
  54         enum jz4740_rtc_type type;
  55
  56         struct rtc_device *rtc;
  57         struct clk *clk;
  58
  59         int irq;
  60
  61         spinlock_t lock;
  62
  63         unsigned int min_wakeup_pin_assert_time;
  64         unsigned int reset_pin_assert_time;
  65 };
  66
  67 static struct device *dev_for_power_off;
  68
  69 static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc *rtc, size_t reg)
  70 {
  71         return readl(rtc->base + reg);
  72 }
  73
  74 static int jz4740_rtc_wait_write_ready(struct jz4740_rtc *rtc)
  75 {
  76         uint32_t ctrl;
  77         int timeout = 10000;
  78
  79         do {
  80                 ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
  81         } while (!(ctrl & JZ_RTC_CTRL_WRDY) && --timeout);
  82
  83         return timeout ? 0 : -EIO;
  84 }
  85
  86 static inline int jz4780_rtc_enable_write(struct jz4740_rtc *rtc)
  87 {
  88         uint32_t ctrl;
  89         int ret, timeout = 10000;
  90
  91         ret = jz4740_rtc_wait_write_ready(rtc);
  92         if (ret != 0)
  93                 return ret;
  94
  95         writel(JZ_RTC_WENR_MAGIC, rtc->base + JZ_REG_RTC_WENR);
  96
  97         do {
  98                 ctrl = readl(rtc->base + JZ_REG_RTC_WENR);
  99         } while (!(ctrl & JZ_RTC_WENR_WEN) && --timeout);
 100
 101         return timeout ? 0 : -EIO;
 102 }
 103
 104 static inline int jz4740_rtc_reg_write(struct jz4740_rtc *rtc, size_t reg,
 105         uint32_t val)
 106 {
 107         int ret = 0;
 108
 109         if (rtc->type >= ID_JZ4780)
 110                 ret = jz4780_rtc_enable_write(rtc);
 111         if (ret == 0)
 112                 ret = jz4740_rtc_wait_write_ready(rtc);
 113         if (ret == 0)
 114                 writel(val, rtc->base + reg);
 115
 116         return ret;
 117 }
 118
 119 static int jz4740_rtc_ctrl_set_bits(struct jz4740_rtc *rtc, uint32_t mask,
 120         bool set)
 121 {
 122         int ret;
 123         unsigned long flags;
 124         uint32_t ctrl;
 125
 126         spin_lock_irqsave(&rtc->lock, flags);
 127
 128         ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
 129
 130         /* Don't clear interrupt flags by accident */
 131         ctrl |= JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF;
 132
 133         if (set)
 134                 ctrl |= mask;
 135         else
 136                 ctrl &= ~mask;
 137
 138         ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CTRL, ctrl);
 139
 140         spin_unlock_irqrestore(&rtc->lock, flags);
 141
 142         return ret;
 143 }
 144
 145 static int jz4740_rtc_read_time(struct device *dev, struct rtc_time *time)
 146 {
 147         struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 148         uint32_t secs, secs2;
 149         int timeout = 5;
 150
 151         if (jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD) != 0x12345678)
 152                 return -EINVAL;
 153
 154         /* If the seconds register is read while it is updated, it can contain a
 155          * bogus value. This can be avoided by making sure that two consecutive
 156          * reads have the same value.
 157          */
 158         secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
 159         secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
 160
 161         while (secs != secs2 && --timeout) {
 162                 secs = secs2;
 163                 secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
 164         }
 165
 166         if (timeout == 0)
 167                 return -EIO;
 168
 169         rtc_time64_to_tm(secs, time);
 170
 171         return 0;
 172 }
 173
 174 static int jz4740_rtc_set_time(struct device *dev, struct rtc_time *time)
 175 {
 176         struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 177         int ret;
 178
 179         ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, rtc_tm_to_time64(time));
 180         if (ret)
 181                 return ret;
 182
 183         return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678);
 184 }
 185
 186 static int jz4740_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 187 {
 188         struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 189         uint32_t secs;
 190         uint32_t ctrl;
 191
 192         secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);
 193
 194         ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
 195
 196         alrm->enabled = !!(ctrl & JZ_RTC_CTRL_AE);
 197         alrm->pending = !!(ctrl & JZ_RTC_CTRL_AF);
 198
 199         rtc_time64_to_tm(secs, &alrm->time);
 200
 201         return 0;
 202 }
 203
 204 static int jz4740_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 205 {
 206         int ret;
 207         struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 208         uint32_t secs = lower_32_bits(rtc_tm_to_time64(&alrm->time));
 209
 210         ret = jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC_ALARM, secs);
 211         if (!ret)
 212                 ret = jz4740_rtc_ctrl_set_bits(rtc,
 213                         JZ_RTC_CTRL_AE | JZ_RTC_CTRL_AF_IRQ, alrm->enabled);
 214
 215         return ret;
 216 }
 217
 218 static int jz4740_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
 219 {
 220         struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 221         return jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ, enable);
 222 }
 223
 224 static const struct rtc_class_ops jz4740_rtc_ops = {
 225         .read_time      = jz4740_rtc_read_time,
 226         .set_time       = jz4740_rtc_set_time,
 227         .read_alarm     = jz4740_rtc_read_alarm,
 228         .set_alarm      = jz4740_rtc_set_alarm,
 229         .alarm_irq_enable = jz4740_rtc_alarm_irq_enable,
 230 };
 231
 232 static irqreturn_t jz4740_rtc_irq(int irq, void *data)
 233 {
 234         struct jz4740_rtc *rtc = data;
 235         uint32_t ctrl;
 236         unsigned long events = 0;
 237
 238         ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
 239
 240         if (ctrl & JZ_RTC_CTRL_1HZ)
 241                 events |= (RTC_UF | RTC_IRQF);
 242
 243         if (ctrl & JZ_RTC_CTRL_AF)
 244                 events |= (RTC_AF | RTC_IRQF);
 245
 246         rtc_update_irq(rtc->rtc, 1, events);
 247
 248         jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF, false);
 249
 250         return IRQ_HANDLED;
 251 }
 252
 253 static void jz4740_rtc_poweroff(struct device *dev)
 254 {
 255         struct jz4740_rtc *rtc = dev_get_drvdata(dev);
 256         jz4740_rtc_reg_write(rtc, JZ_REG_RTC_HIBERNATE, 1);
 257 }
 258
 259 static void jz4740_rtc_power_off(void)
 260 {
 261         struct jz4740_rtc *rtc = dev_get_drvdata(dev_for_power_off);
 262         unsigned long rtc_rate;
 263         unsigned long wakeup_filter_ticks;
 264         unsigned long reset_counter_ticks;
 265
 266         clk_prepare_enable(rtc->clk);
 267
 268         rtc_rate = clk_get_rate(rtc->clk);
 269
 270         /*
 271          * Set minimum wakeup pin assertion time: 100 ms.
 272          * Range is 0 to 2 sec if RTC is clocked at 32 kHz.
 273          */
 274         wakeup_filter_ticks =
 275                 (rtc->min_wakeup_pin_assert_time * rtc_rate) / 1000;
 276         if (wakeup_filter_ticks < JZ_RTC_WAKEUP_FILTER_MASK)
 277                 wakeup_filter_ticks &= JZ_RTC_WAKEUP_FILTER_MASK;
 278         else
 279                 wakeup_filter_ticks = JZ_RTC_WAKEUP_FILTER_MASK;
 280         jz4740_rtc_reg_write(rtc,
 281                              JZ_REG_RTC_WAKEUP_FILTER, wakeup_filter_ticks);
 282
 283         /*
 284          * Set reset pin low-level assertion time after wakeup: 60 ms.
 285          * Range is 0 to 125 ms if RTC is clocked at 32 kHz.
 286          */
 287         reset_counter_ticks = (rtc->reset_pin_assert_time * rtc_rate) / 1000;
 288         if (reset_counter_ticks < JZ_RTC_RESET_COUNTER_MASK)
 289                 reset_counter_ticks &= JZ_RTC_RESET_COUNTER_MASK;
 290         else
 291                 reset_counter_ticks = JZ_RTC_RESET_COUNTER_MASK;
 292         jz4740_rtc_reg_write(rtc,
 293                              JZ_REG_RTC_RESET_COUNTER, reset_counter_ticks);
 294
 295         jz4740_rtc_poweroff(dev_for_power_off);
 296         kernel_halt();
 297 }
 298
 299 static const struct of_device_id jz4740_rtc_of_match[] = {
 300         { .compatible = "ingenic,jz4740-rtc", .data = (void *)ID_JZ4740 },
 301         { .compatible = "ingenic,jz4780-rtc", .data = (void *)ID_JZ4780 },
 302         {},
 303 };
 304 MODULE_DEVICE_TABLE(of, jz4740_rtc_of_match);
 305
 306 static int jz4740_rtc_probe(struct platform_device *pdev)
 307 {
 308         int ret;
 309         struct jz4740_rtc *rtc;
 310         struct resource *mem;
 311         const struct platform_device_id *id = platform_get_device_id(pdev);
 312         const struct of_device_id *of_id = of_match_device(
 313                         jz4740_rtc_of_match, &pdev->dev);
 314         struct device_node *np = pdev->dev.of_node;
 315
 316         rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
 317         if (!rtc)
 318                 return -ENOMEM;
 319
 320         if (of_id)
 321                 rtc->type = (enum jz4740_rtc_type)of_id->data;
 322         else
 323                 rtc->type = id->driver_data;
 324
 325         rtc->irq = platform_get_irq(pdev, 0);
 326         if (rtc->irq < 0)
 327                 return -ENOENT;
 328
 329         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 330         rtc->base = devm_ioremap_resource(&pdev->dev, mem);
 331         if (IS_ERR(rtc->base))
 332                 return PTR_ERR(rtc->base);
 333
 334         rtc->clk = devm_clk_get(&pdev->dev, "rtc");
 335         if (IS_ERR(rtc->clk)) {
 336                 dev_err(&pdev->dev, "Failed to get RTC clock\n");
 337                 return PTR_ERR(rtc->clk);
 338         }
 339
 340         spin_lock_init(&rtc->lock);
 341
 342         platform_set_drvdata(pdev, rtc);
 343
 344         device_init_wakeup(&pdev->dev, 1);
 345
 346         ret = dev_pm_set_wake_irq(&pdev->dev, rtc->irq);
 347         if (ret) {
 348                 dev_err(&pdev->dev, "Failed to set wake irq: %d\n", ret);
 349                 return ret;
 350         }
 351
 352         rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
 353         if (IS_ERR(rtc->rtc)) {
 354                 ret = PTR_ERR(rtc->rtc);
 355                 dev_err(&pdev->dev, "Failed to allocate rtc device: %d\n", ret);
 356                 return ret;
 357         }
 358
 359         rtc->rtc->ops = &jz4740_rtc_ops;
 360         rtc->rtc->range_max = U32_MAX;
 361
 362         ret = rtc_register_device(rtc->rtc);
 363         if (ret)
 364                 return ret;
 365
 366         ret = devm_request_irq(&pdev->dev, rtc->irq, jz4740_rtc_irq, 0,
 367                                 pdev->name, rtc);
 368         if (ret) {
 369                 dev_err(&pdev->dev, "Failed to request rtc irq: %d\n", ret);
 370                 return ret;
 371         }
 372
 373         if (np && of_device_is_system_power_controller(np)) {
 374                 if (!pm_power_off) {
 375                         /* Default: 60ms */
 376                         rtc->reset_pin_assert_time = 60;
 377                         of_property_read_u32(np, "reset-pin-assert-time-ms",
 378                                              &rtc->reset_pin_assert_time);
 379
 380                         /* Default: 100ms */
 381                         rtc->min_wakeup_pin_assert_time = 100;
 382                         of_property_read_u32(np,
 383                                              "min-wakeup-pin-assert-time-ms",
 384                                              &rtc->min_wakeup_pin_assert_time);
 385
 386                         dev_for_power_off = &pdev->dev;
 387                         pm_power_off = jz4740_rtc_power_off;
 388                 } else {
 389                         dev_warn(&pdev->dev,
 390                                  "Poweroff handler already present!\n");
 391                 }
 392         }
 393
 394         return 0;
 395 }
 396
 397 static const struct platform_device_id jz4740_rtc_ids[] = {
 398         { "jz4740-rtc", ID_JZ4740 },
 399         { "jz4780-rtc", ID_JZ4780 },
 400         {}
 401 };
 402 MODULE_DEVICE_TABLE(platform, jz4740_rtc_ids);
 403
 404 static struct platform_driver jz4740_rtc_driver = {
 405         .probe   = jz4740_rtc_probe,
 406         .driver  = {
 407                 .name  = "jz4740-rtc",
 408                 .of_match_table = of_match_ptr(jz4740_rtc_of_match),
 409         },
 410         .id_table = jz4740_rtc_ids,
 411 };
 412
 413 module_platform_driver(jz4740_rtc_driver);
 414
 415 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
 416 MODULE_LICENSE("GPL");
 417 MODULE_DESCRIPTION("RTC driver for the JZ4740 SoC\n");
 418 MODULE_ALIAS("platform:jz4740-rtc");