2 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/export.h>
16 #include <linux/mfd/syscon.h>
18 #include <linux/pinctrl/pinconf.h>
19 #include <linux/pinctrl/pinconf-generic.h>
20 #include <linux/pinctrl/pinctrl.h>
21 #include <linux/pinctrl/pinmux.h>
22 #include <linux/platform_device.h>
23 #include <linux/regmap.h>
26 #include "../pinctrl-utils.h"
27 #include "pinctrl-uniphier.h"
29 struct uniphier_pinctrl_priv {
30 struct pinctrl_desc pctldesc;
31 struct pinctrl_dev *pctldev;
32 struct regmap *regmap;
34 struct uniphier_pinctrl_socdata *socdata;
37 static int uniphier_pctl_get_groups_count(struct pinctrl_dev *pctldev)
39 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
41 return priv->socdata->groups_count;
44 static const char *uniphier_pctl_get_group_name(struct pinctrl_dev *pctldev,
47 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
49 return priv->socdata->groups[selector].name;
52 static int uniphier_pctl_get_group_pins(struct pinctrl_dev *pctldev,
54 const unsigned **pins,
57 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
59 *pins = priv->socdata->groups[selector].pins;
60 *num_pins = priv->socdata->groups[selector].num_pins;
65 #ifdef CONFIG_DEBUG_FS
66 static void uniphier_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
67 struct seq_file *s, unsigned offset)
69 const struct pin_desc *desc = pin_desc_get(pctldev, offset);
70 const char *pull_dir, *drv_type;
72 switch (uniphier_pin_get_pull_dir(desc->drv_data)) {
73 case UNIPHIER_PIN_PULL_UP:
76 case UNIPHIER_PIN_PULL_DOWN:
79 case UNIPHIER_PIN_PULL_UP_FIXED:
80 pull_dir = "UP(FIXED)";
82 case UNIPHIER_PIN_PULL_DOWN_FIXED:
83 pull_dir = "DOWN(FIXED)";
85 case UNIPHIER_PIN_PULL_NONE:
92 switch (uniphier_pin_get_drv_type(desc->drv_data)) {
93 case UNIPHIER_PIN_DRV_1BIT:
96 case UNIPHIER_PIN_DRV_2BIT:
97 drv_type = "8/12/16/20(mA)";
99 case UNIPHIER_PIN_DRV_3BIT:
100 drv_type = "4/5/7/9/11/12/14/16(mA)";
102 case UNIPHIER_PIN_DRV_FIXED4:
105 case UNIPHIER_PIN_DRV_FIXED5:
108 case UNIPHIER_PIN_DRV_FIXED8:
111 case UNIPHIER_PIN_DRV_NONE:
118 seq_printf(s, " PULL_DIR=%s DRV_TYPE=%s", pull_dir, drv_type);
122 static const struct pinctrl_ops uniphier_pctlops = {
123 .get_groups_count = uniphier_pctl_get_groups_count,
124 .get_group_name = uniphier_pctl_get_group_name,
125 .get_group_pins = uniphier_pctl_get_group_pins,
126 #ifdef CONFIG_DEBUG_FS
127 .pin_dbg_show = uniphier_pctl_pin_dbg_show,
129 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
130 .dt_free_map = pinctrl_utils_free_map,
133 static int uniphier_conf_pin_bias_get(struct pinctrl_dev *pctldev,
134 const struct pin_desc *desc,
135 enum pin_config_param param)
137 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
138 enum uniphier_pin_pull_dir pull_dir =
139 uniphier_pin_get_pull_dir(desc->drv_data);
140 unsigned int pupdctrl, reg, shift, val;
141 unsigned int expected = 1;
145 case PIN_CONFIG_BIAS_DISABLE:
146 if (pull_dir == UNIPHIER_PIN_PULL_NONE)
148 if (pull_dir == UNIPHIER_PIN_PULL_UP_FIXED ||
149 pull_dir == UNIPHIER_PIN_PULL_DOWN_FIXED)
153 case PIN_CONFIG_BIAS_PULL_UP:
154 if (pull_dir == UNIPHIER_PIN_PULL_UP_FIXED)
156 if (pull_dir != UNIPHIER_PIN_PULL_UP)
159 case PIN_CONFIG_BIAS_PULL_DOWN:
160 if (pull_dir == UNIPHIER_PIN_PULL_DOWN_FIXED)
162 if (pull_dir != UNIPHIER_PIN_PULL_DOWN)
169 pupdctrl = uniphier_pin_get_pupdctrl(desc->drv_data);
171 reg = UNIPHIER_PINCTRL_PUPDCTRL_BASE + pupdctrl / 32 * 4;
172 shift = pupdctrl % 32;
174 ret = regmap_read(priv->regmap, priv->regbase + reg, &val);
178 val = (val >> shift) & 1;
180 return (val == expected) ? 0 : -EINVAL;
183 static int uniphier_conf_pin_drive_get(struct pinctrl_dev *pctldev,
184 const struct pin_desc *desc,
187 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
188 enum uniphier_pin_drv_type type =
189 uniphier_pin_get_drv_type(desc->drv_data);
190 const unsigned int strength_1bit[] = {4, 8};
191 const unsigned int strength_2bit[] = {8, 12, 16, 20};
192 const unsigned int strength_3bit[] = {4, 5, 7, 9, 11, 12, 14, 16};
193 const unsigned int *supported_strength;
194 unsigned int drvctrl, reg, shift, mask, width, val;
198 case UNIPHIER_PIN_DRV_1BIT:
199 supported_strength = strength_1bit;
200 reg = UNIPHIER_PINCTRL_DRVCTRL_BASE;
203 case UNIPHIER_PIN_DRV_2BIT:
204 supported_strength = strength_2bit;
205 reg = UNIPHIER_PINCTRL_DRV2CTRL_BASE;
208 case UNIPHIER_PIN_DRV_3BIT:
209 supported_strength = strength_3bit;
210 reg = UNIPHIER_PINCTRL_DRV3CTRL_BASE;
213 case UNIPHIER_PIN_DRV_FIXED4:
216 case UNIPHIER_PIN_DRV_FIXED5:
219 case UNIPHIER_PIN_DRV_FIXED8:
223 /* drive strength control is not supported for this pin */
227 drvctrl = uniphier_pin_get_drvctrl(desc->drv_data);
230 reg += drvctrl / 32 * 4;
231 shift = drvctrl % 32;
232 mask = (1U << width) - 1;
234 ret = regmap_read(priv->regmap, priv->regbase + reg, &val);
238 *strength = supported_strength[(val >> shift) & mask];
243 static int uniphier_conf_pin_input_enable_get(struct pinctrl_dev *pctldev,
244 const struct pin_desc *desc)
246 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
247 unsigned int iectrl = uniphier_pin_get_iectrl(desc->drv_data);
251 if (iectrl == UNIPHIER_PIN_IECTRL_NONE)
252 /* This pin is always input-enabled. */
255 ret = regmap_read(priv->regmap,
256 priv->regbase + UNIPHIER_PINCTRL_IECTRL, &val);
260 return val & BIT(iectrl) ? 0 : -EINVAL;
263 static int uniphier_conf_pin_config_get(struct pinctrl_dev *pctldev,
265 unsigned long *configs)
267 const struct pin_desc *desc = pin_desc_get(pctldev, pin);
268 enum pin_config_param param = pinconf_to_config_param(*configs);
269 bool has_arg = false;
274 case PIN_CONFIG_BIAS_DISABLE:
275 case PIN_CONFIG_BIAS_PULL_UP:
276 case PIN_CONFIG_BIAS_PULL_DOWN:
277 ret = uniphier_conf_pin_bias_get(pctldev, desc, param);
279 case PIN_CONFIG_DRIVE_STRENGTH:
280 ret = uniphier_conf_pin_drive_get(pctldev, desc, &arg);
283 case PIN_CONFIG_INPUT_ENABLE:
284 ret = uniphier_conf_pin_input_enable_get(pctldev, desc);
287 /* unsupported parameter */
292 if (ret == 0 && has_arg)
293 *configs = pinconf_to_config_packed(param, arg);
298 static int uniphier_conf_pin_bias_set(struct pinctrl_dev *pctldev,
299 const struct pin_desc *desc,
300 enum pin_config_param param, u16 arg)
302 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
303 enum uniphier_pin_pull_dir pull_dir =
304 uniphier_pin_get_pull_dir(desc->drv_data);
305 unsigned int pupdctrl, reg, shift;
306 unsigned int val = 1;
309 case PIN_CONFIG_BIAS_DISABLE:
310 if (pull_dir == UNIPHIER_PIN_PULL_NONE)
312 if (pull_dir == UNIPHIER_PIN_PULL_UP_FIXED ||
313 pull_dir == UNIPHIER_PIN_PULL_DOWN_FIXED) {
314 dev_err(pctldev->dev,
315 "can not disable pull register for pin %s\n",
321 case PIN_CONFIG_BIAS_PULL_UP:
322 if (pull_dir == UNIPHIER_PIN_PULL_UP_FIXED && arg != 0)
324 if (pull_dir != UNIPHIER_PIN_PULL_UP) {
325 dev_err(pctldev->dev,
326 "pull-up is unsupported for pin %s\n",
331 dev_err(pctldev->dev, "pull-up can not be total\n");
335 case PIN_CONFIG_BIAS_PULL_DOWN:
336 if (pull_dir == UNIPHIER_PIN_PULL_DOWN_FIXED && arg != 0)
338 if (pull_dir != UNIPHIER_PIN_PULL_DOWN) {
339 dev_err(pctldev->dev,
340 "pull-down is unsupported for pin %s\n",
345 dev_err(pctldev->dev, "pull-down can not be total\n");
349 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
350 if (pull_dir == UNIPHIER_PIN_PULL_NONE) {
351 dev_err(pctldev->dev,
352 "pull-up/down is unsupported for pin %s\n",
358 return 0; /* configuration ingored */
364 pupdctrl = uniphier_pin_get_pupdctrl(desc->drv_data);
366 reg = UNIPHIER_PINCTRL_PUPDCTRL_BASE + pupdctrl / 32 * 4;
367 shift = pupdctrl % 32;
369 return regmap_update_bits(priv->regmap, priv->regbase + reg,
370 1 << shift, val << shift);
373 static int uniphier_conf_pin_drive_set(struct pinctrl_dev *pctldev,
374 const struct pin_desc *desc,
377 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
378 enum uniphier_pin_drv_type type =
379 uniphier_pin_get_drv_type(desc->drv_data);
380 const unsigned int strength_1bit[] = {4, 8, -1};
381 const unsigned int strength_2bit[] = {8, 12, 16, 20, -1};
382 const unsigned int strength_3bit[] = {4, 5, 7, 9, 11, 12, 14, 16, -1};
383 const unsigned int *supported_strength;
384 unsigned int drvctrl, reg, shift, mask, width, val;
387 case UNIPHIER_PIN_DRV_1BIT:
388 supported_strength = strength_1bit;
389 reg = UNIPHIER_PINCTRL_DRVCTRL_BASE;
392 case UNIPHIER_PIN_DRV_2BIT:
393 supported_strength = strength_2bit;
394 reg = UNIPHIER_PINCTRL_DRV2CTRL_BASE;
397 case UNIPHIER_PIN_DRV_3BIT:
398 supported_strength = strength_3bit;
399 reg = UNIPHIER_PINCTRL_DRV3CTRL_BASE;
403 dev_err(pctldev->dev,
404 "cannot change drive strength for pin %s\n",
409 for (val = 0; supported_strength[val] > 0; val++) {
410 if (supported_strength[val] > strength)
415 dev_err(pctldev->dev,
416 "unsupported drive strength %u mA for pin %s\n",
417 strength, desc->name);
423 drvctrl = uniphier_pin_get_drvctrl(desc->drv_data);
426 reg += drvctrl / 32 * 4;
427 shift = drvctrl % 32;
428 mask = (1U << width) - 1;
430 return regmap_update_bits(priv->regmap, priv->regbase + reg,
431 mask << shift, val << shift);
434 static int uniphier_conf_pin_input_enable(struct pinctrl_dev *pctldev,
435 const struct pin_desc *desc,
438 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
439 unsigned int iectrl = uniphier_pin_get_iectrl(desc->drv_data);
440 unsigned int reg, mask;
443 * Multiple pins share one input enable, per-pin disabling is
446 if (!(priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL) &&
450 /* UNIPHIER_PIN_IECTRL_NONE means the pin is always input-enabled */
451 if (iectrl == UNIPHIER_PIN_IECTRL_NONE)
452 return enable ? 0 : -EINVAL;
454 reg = priv->regbase + UNIPHIER_PINCTRL_IECTRL + iectrl / 32 * 4;
455 mask = BIT(iectrl % 32);
457 return regmap_update_bits(priv->regmap, reg, mask, enable ? mask : 0);
460 static int uniphier_conf_pin_config_set(struct pinctrl_dev *pctldev,
462 unsigned long *configs,
463 unsigned num_configs)
465 const struct pin_desc *desc = pin_desc_get(pctldev, pin);
468 for (i = 0; i < num_configs; i++) {
469 enum pin_config_param param =
470 pinconf_to_config_param(configs[i]);
471 u16 arg = pinconf_to_config_argument(configs[i]);
474 case PIN_CONFIG_BIAS_DISABLE:
475 case PIN_CONFIG_BIAS_PULL_UP:
476 case PIN_CONFIG_BIAS_PULL_DOWN:
477 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
478 ret = uniphier_conf_pin_bias_set(pctldev, desc,
481 case PIN_CONFIG_DRIVE_STRENGTH:
482 ret = uniphier_conf_pin_drive_set(pctldev, desc, arg);
484 case PIN_CONFIG_INPUT_ENABLE:
485 ret = uniphier_conf_pin_input_enable(pctldev, desc,
489 dev_err(pctldev->dev,
490 "unsupported configuration parameter %u\n",
502 static int uniphier_conf_pin_config_group_set(struct pinctrl_dev *pctldev,
504 unsigned long *configs,
505 unsigned num_configs)
507 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
508 const unsigned *pins = priv->socdata->groups[selector].pins;
509 unsigned num_pins = priv->socdata->groups[selector].num_pins;
512 for (i = 0; i < num_pins; i++) {
513 ret = uniphier_conf_pin_config_set(pctldev, pins[i],
514 configs, num_configs);
522 static const struct pinconf_ops uniphier_confops = {
524 .pin_config_get = uniphier_conf_pin_config_get,
525 .pin_config_set = uniphier_conf_pin_config_set,
526 .pin_config_group_set = uniphier_conf_pin_config_group_set,
529 static int uniphier_pmx_get_functions_count(struct pinctrl_dev *pctldev)
531 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
533 return priv->socdata->functions_count;
536 static const char *uniphier_pmx_get_function_name(struct pinctrl_dev *pctldev,
539 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
541 return priv->socdata->functions[selector].name;
544 static int uniphier_pmx_get_function_groups(struct pinctrl_dev *pctldev,
546 const char * const **groups,
547 unsigned *num_groups)
549 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
551 *groups = priv->socdata->functions[selector].groups;
552 *num_groups = priv->socdata->functions[selector].num_groups;
557 static int uniphier_pmx_set_one_mux(struct pinctrl_dev *pctldev, unsigned pin,
560 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
561 unsigned int mux_bits, reg_stride, reg, reg_end, shift, mask;
565 /* some pins need input-enabling */
566 ret = uniphier_conf_pin_input_enable(pctldev,
567 pin_desc_get(pctldev, pin), 1);
572 return 0; /* dedicated pin; nothing to do for pin-mux */
574 if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE) {
576 * Mode reg_offset bit_position
577 * Normal 4 * n shift+3:shift
578 * Debug 4 * n shift+7:shift+4
585 * Mode reg_offset bit_position
586 * Normal 8 * n shift+3:shift
587 * Debug 8 * n + 4 shift+3:shift
591 load_pinctrl = false;
594 reg = UNIPHIER_PINCTRL_PINMUX_BASE + pin * mux_bits / 32 * reg_stride;
595 reg_end = reg + reg_stride;
596 shift = pin * mux_bits % 32;
597 mask = (1U << mux_bits) - 1;
600 * If reg_stride is greater than 4, the MSB of each pinsel shall be
601 * stored in the offset+4.
603 for (; reg < reg_end; reg += 4) {
604 ret = regmap_update_bits(priv->regmap, priv->regbase + reg,
605 mask << shift, muxval << shift);
612 ret = regmap_write(priv->regmap,
613 priv->regbase + UNIPHIER_PINCTRL_LOAD_PINMUX,
622 static int uniphier_pmx_set_mux(struct pinctrl_dev *pctldev,
623 unsigned func_selector,
624 unsigned group_selector)
626 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
627 const struct uniphier_pinctrl_group *grp =
628 &priv->socdata->groups[group_selector];
632 for (i = 0; i < grp->num_pins; i++) {
633 ret = uniphier_pmx_set_one_mux(pctldev, grp->pins[i],
642 static int uniphier_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
643 struct pinctrl_gpio_range *range,
646 struct uniphier_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
647 const struct uniphier_pinctrl_group *groups = priv->socdata->groups;
648 int groups_count = priv->socdata->groups_count;
649 enum uniphier_pinmux_gpio_range_type range_type;
652 if (strstr(range->name, "irq"))
653 range_type = UNIPHIER_PINMUX_GPIO_RANGE_IRQ;
655 range_type = UNIPHIER_PINMUX_GPIO_RANGE_PORT;
657 for (i = 0; i < groups_count; i++) {
658 if (groups[i].range_type != range_type)
661 for (j = 0; j < groups[i].num_pins; j++)
662 if (groups[i].pins[j] == offset)
666 dev_err(pctldev->dev, "pin %u does not support GPIO\n", offset);
670 return uniphier_pmx_set_one_mux(pctldev, offset, groups[i].muxvals[j]);
673 static const struct pinmux_ops uniphier_pmxops = {
674 .get_functions_count = uniphier_pmx_get_functions_count,
675 .get_function_name = uniphier_pmx_get_function_name,
676 .get_function_groups = uniphier_pmx_get_function_groups,
677 .set_mux = uniphier_pmx_set_mux,
678 .gpio_request_enable = uniphier_pmx_gpio_request_enable,
682 int uniphier_pinctrl_probe(struct platform_device *pdev,
683 struct uniphier_pinctrl_socdata *socdata)
685 struct device *dev = &pdev->dev;
686 struct uniphier_pinctrl_priv *priv;
687 struct device_node *parent;
690 !socdata->pins || !socdata->npins ||
691 !socdata->groups || !socdata->groups_count ||
692 !socdata->functions || !socdata->functions_count) {
693 dev_err(dev, "pinctrl socdata lacks necessary members\n");
697 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
701 if (of_device_is_compatible(dev->of_node, "socionext,ph1-ld4-pinctrl") ||
702 of_device_is_compatible(dev->of_node, "socionext,ph1-pro4-pinctrl") ||
703 of_device_is_compatible(dev->of_node, "socionext,ph1-sld8-pinctrl") ||
704 of_device_is_compatible(dev->of_node, "socionext,ph1-pro5-pinctrl") ||
705 of_device_is_compatible(dev->of_node, "socionext,proxstream2-pinctrl") ||
706 of_device_is_compatible(dev->of_node, "socionext,ph1-ld6b-pinctrl")) {
708 priv->regmap = syscon_node_to_regmap(dev->of_node);
710 priv->regbase = 0x1000;
711 parent = of_get_parent(dev->of_node);
712 priv->regmap = syscon_node_to_regmap(parent);
716 if (IS_ERR(priv->regmap)) {
717 dev_err(dev, "failed to get regmap\n");
718 return PTR_ERR(priv->regmap);
721 priv->socdata = socdata;
722 priv->pctldesc.name = dev->driver->name;
723 priv->pctldesc.pins = socdata->pins;
724 priv->pctldesc.npins = socdata->npins;
725 priv->pctldesc.pctlops = &uniphier_pctlops;
726 priv->pctldesc.pmxops = &uniphier_pmxops;
727 priv->pctldesc.confops = &uniphier_confops;
728 priv->pctldesc.owner = dev->driver->owner;
730 priv->pctldev = devm_pinctrl_register(dev, &priv->pctldesc, priv);
731 if (IS_ERR(priv->pctldev)) {
732 dev_err(dev, "failed to register UniPhier pinctrl driver\n");
733 return PTR_ERR(priv->pctldev);
736 platform_set_drvdata(pdev, priv);
740 EXPORT_SYMBOL_GPL(uniphier_pinctrl_probe);