drivers/pinctrl/tegra/pinctrl-tegra.c

   1 /*
   2  * Driver for the NVIDIA Tegra pinmux
   3  *
   4  * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * Derived from code:
   7  * Copyright (C) 2010 Google, Inc.
   8  * Copyright (C) 2010 NVIDIA Corporation
   9  * Copyright (C) 2009-2011 ST-Ericsson AB
  10  *
  11  * This program is free software; you can redistribute it and/or modify it
  12  * under the terms and conditions of the GNU General Public License,
  13  * version 2, as published by the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope it will be useful, but WITHOUT
  16  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  18  * more details.
  19  */
  20
  21 #include <linux/err.h>
  22 #include <linux/init.h>
  23 #include <linux/io.h>
  24 #include <linux/module.h>
  25 #include <linux/of.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/pinctrl/machine.h>
  28 #include <linux/pinctrl/pinctrl.h>
  29 #include <linux/pinctrl/pinmux.h>
  30 #include <linux/pinctrl/pinconf.h>
  31 #include <linux/slab.h>
  32
  33 #include "../core.h"
  34 #include "../pinctrl-utils.h"
  35 #include "pinctrl-tegra.h"
  36
  37 struct tegra_pmx {
  38         struct device *dev;
  39         struct pinctrl_dev *pctl;
  40
  41         const struct tegra_pinctrl_soc_data *soc;
  42         const char **group_pins;
  43
  44         int nbanks;
  45         void __iomem **regs;
  46 };
  47
  48 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
  49 {
  50         return readl(pmx->regs[bank] + reg);
  51 }
  52
  53 static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
  54 {
  55         writel(val, pmx->regs[bank] + reg);
  56 }
  57
  58 static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
  59 {
  60         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  61
  62         return pmx->soc->ngroups;
  63 }
  64
  65 static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
  66                                                 unsigned group)
  67 {
  68         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  69
  70         return pmx->soc->groups[group].name;
  71 }
  72
  73 static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
  74                                         unsigned group,
  75                                         const unsigned **pins,
  76                                         unsigned *num_pins)
  77 {
  78         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
  79
  80         *pins = pmx->soc->groups[group].pins;
  81         *num_pins = pmx->soc->groups[group].npins;
  82
  83         return 0;
  84 }
  85
  86 #ifdef CONFIG_DEBUG_FS
  87 static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
  88                                        struct seq_file *s,
  89                                        unsigned offset)
  90 {
  91         seq_printf(s, " %s", dev_name(pctldev->dev));
  92 }
  93 #endif
  94
  95 static const struct cfg_param {
  96         const char *property;
  97         enum tegra_pinconf_param param;
  98 } cfg_params[] = {
  99         {"nvidia,pull",                 TEGRA_PINCONF_PARAM_PULL},
 100         {"nvidia,tristate",             TEGRA_PINCONF_PARAM_TRISTATE},
 101         {"nvidia,enable-input",         TEGRA_PINCONF_PARAM_ENABLE_INPUT},
 102         {"nvidia,open-drain",           TEGRA_PINCONF_PARAM_OPEN_DRAIN},
 103         {"nvidia,lock",                 TEGRA_PINCONF_PARAM_LOCK},
 104         {"nvidia,io-reset",             TEGRA_PINCONF_PARAM_IORESET},
 105         {"nvidia,rcv-sel",              TEGRA_PINCONF_PARAM_RCV_SEL},
 106         {"nvidia,io-hv",                TEGRA_PINCONF_PARAM_RCV_SEL},
 107         {"nvidia,high-speed-mode",      TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
 108         {"nvidia,schmitt",              TEGRA_PINCONF_PARAM_SCHMITT},
 109         {"nvidia,low-power-mode",       TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
 110         {"nvidia,pull-down-strength",   TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
 111         {"nvidia,pull-up-strength",     TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
 112         {"nvidia,slew-rate-falling",    TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
 113         {"nvidia,slew-rate-rising",     TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
 114         {"nvidia,drive-type",           TEGRA_PINCONF_PARAM_DRIVE_TYPE},
 115 };
 116
 117 static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
 118                                            struct device_node *np,
 119                                            struct pinctrl_map **map,
 120                                            unsigned *reserved_maps,
 121                                            unsigned *num_maps)
 122 {
 123         struct device *dev = pctldev->dev;
 124         int ret, i;
 125         const char *function;
 126         u32 val;
 127         unsigned long config;
 128         unsigned long *configs = NULL;
 129         unsigned num_configs = 0;
 130         unsigned reserve;
 131         struct property *prop;
 132         const char *group;
 133
 134         ret = of_property_read_string(np, "nvidia,function", &function);
 135         if (ret < 0) {
 136                 /* EINVAL=missing, which is fine since it's optional */
 137                 if (ret != -EINVAL)
 138                         dev_err(dev,
 139                                 "could not parse property nvidia,function\n");
 140                 function = NULL;
 141         }
 142
 143         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 144                 ret = of_property_read_u32(np, cfg_params[i].property, &val);
 145                 if (!ret) {
 146                         config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
 147                         ret = pinctrl_utils_add_config(pctldev, &configs,
 148                                         &num_configs, config);
 149                         if (ret < 0)
 150                                 goto exit;
 151                 /* EINVAL=missing, which is fine since it's optional */
 152                 } else if (ret != -EINVAL) {
 153                         dev_err(dev, "could not parse property %s\n",
 154                                 cfg_params[i].property);
 155                 }
 156         }
 157
 158         reserve = 0;
 159         if (function != NULL)
 160                 reserve++;
 161         if (num_configs)
 162                 reserve++;
 163         ret = of_property_count_strings(np, "nvidia,pins");
 164         if (ret < 0) {
 165                 dev_err(dev, "could not parse property nvidia,pins\n");
 166                 goto exit;
 167         }
 168         reserve *= ret;
 169
 170         ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
 171                                         num_maps, reserve);
 172         if (ret < 0)
 173                 goto exit;
 174
 175         of_property_for_each_string(np, "nvidia,pins", prop, group) {
 176                 if (function) {
 177                         ret = pinctrl_utils_add_map_mux(pctldev, map,
 178                                         reserved_maps, num_maps, group,
 179                                         function);
 180                         if (ret < 0)
 181                                 goto exit;
 182                 }
 183
 184                 if (num_configs) {
 185                         ret = pinctrl_utils_add_map_configs(pctldev, map,
 186                                         reserved_maps, num_maps, group,
 187                                         configs, num_configs,
 188                                         PIN_MAP_TYPE_CONFIGS_GROUP);
 189                         if (ret < 0)
 190                                 goto exit;
 191                 }
 192         }
 193
 194         ret = 0;
 195
 196 exit:
 197         kfree(configs);
 198         return ret;
 199 }
 200
 201 static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
 202                                         struct device_node *np_config,
 203                                         struct pinctrl_map **map,
 204                                         unsigned *num_maps)
 205 {
 206         unsigned reserved_maps;
 207         struct device_node *np;
 208         int ret;
 209
 210         reserved_maps = 0;
 211         *map = NULL;
 212         *num_maps = 0;
 213
 214         for_each_child_of_node(np_config, np) {
 215                 ret = tegra_pinctrl_dt_subnode_to_map(pctldev, np, map,
 216                                                       &reserved_maps, num_maps);
 217                 if (ret < 0) {
 218                         pinctrl_utils_free_map(pctldev, *map,
 219                                 *num_maps);
 220                         of_node_put(np);
 221                         return ret;
 222                 }
 223         }
 224
 225         return 0;
 226 }
 227
 228 static const struct pinctrl_ops tegra_pinctrl_ops = {
 229         .get_groups_count = tegra_pinctrl_get_groups_count,
 230         .get_group_name = tegra_pinctrl_get_group_name,
 231         .get_group_pins = tegra_pinctrl_get_group_pins,
 232 #ifdef CONFIG_DEBUG_FS
 233         .pin_dbg_show = tegra_pinctrl_pin_dbg_show,
 234 #endif
 235         .dt_node_to_map = tegra_pinctrl_dt_node_to_map,
 236         .dt_free_map = pinctrl_utils_free_map,
 237 };
 238
 239 static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
 240 {
 241         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 242
 243         return pmx->soc->nfunctions;
 244 }
 245
 246 static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
 247                                                unsigned function)
 248 {
 249         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 250
 251         return pmx->soc->functions[function].name;
 252 }
 253
 254 static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
 255                                          unsigned function,
 256                                          const char * const **groups,
 257                                          unsigned * const num_groups)
 258 {
 259         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 260
 261         *groups = pmx->soc->functions[function].groups;
 262         *num_groups = pmx->soc->functions[function].ngroups;
 263
 264         return 0;
 265 }
 266
 267 static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev,
 268                                  unsigned function,
 269                                  unsigned group)
 270 {
 271         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 272         const struct tegra_pingroup *g;
 273         int i;
 274         u32 val;
 275
 276         g = &pmx->soc->groups[group];
 277
 278         if (WARN_ON(g->mux_reg < 0))
 279                 return -EINVAL;
 280
 281         for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
 282                 if (g->funcs[i] == function)
 283                         break;
 284         }
 285         if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
 286                 return -EINVAL;
 287
 288         val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
 289         val &= ~(0x3 << g->mux_bit);
 290         val |= i << g->mux_bit;
 291         pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
 292
 293         return 0;
 294 }
 295
 296 static const struct pinmux_ops tegra_pinmux_ops = {
 297         .get_functions_count = tegra_pinctrl_get_funcs_count,
 298         .get_function_name = tegra_pinctrl_get_func_name,
 299         .get_function_groups = tegra_pinctrl_get_func_groups,
 300         .set_mux = tegra_pinctrl_set_mux,
 301 };
 302
 303 static int tegra_pinconf_reg(struct tegra_pmx *pmx,
 304                              const struct tegra_pingroup *g,
 305                              enum tegra_pinconf_param param,
 306                              bool report_err,
 307                              s8 *bank, s16 *reg, s8 *bit, s8 *width)
 308 {
 309         switch (param) {
 310         case TEGRA_PINCONF_PARAM_PULL:
 311                 *bank = g->pupd_bank;
 312                 *reg = g->pupd_reg;
 313                 *bit = g->pupd_bit;
 314                 *width = 2;
 315                 break;
 316         case TEGRA_PINCONF_PARAM_TRISTATE:
 317                 *bank = g->tri_bank;
 318                 *reg = g->tri_reg;
 319                 *bit = g->tri_bit;
 320                 *width = 1;
 321                 break;
 322         case TEGRA_PINCONF_PARAM_ENABLE_INPUT:
 323                 *bank = g->mux_bank;
 324                 *reg = g->mux_reg;
 325                 *bit = g->einput_bit;
 326                 *width = 1;
 327                 break;
 328         case TEGRA_PINCONF_PARAM_OPEN_DRAIN:
 329                 *bank = g->mux_bank;
 330                 *reg = g->mux_reg;
 331                 *bit = g->odrain_bit;
 332                 *width = 1;
 333                 break;
 334         case TEGRA_PINCONF_PARAM_LOCK:
 335                 *bank = g->mux_bank;
 336                 *reg = g->mux_reg;
 337                 *bit = g->lock_bit;
 338                 *width = 1;
 339                 break;
 340         case TEGRA_PINCONF_PARAM_IORESET:
 341                 *bank = g->mux_bank;
 342                 *reg = g->mux_reg;
 343                 *bit = g->ioreset_bit;
 344                 *width = 1;
 345                 break;
 346         case TEGRA_PINCONF_PARAM_RCV_SEL:
 347                 *bank = g->mux_bank;
 348                 *reg = g->mux_reg;
 349                 *bit = g->rcv_sel_bit;
 350                 *width = 1;
 351                 break;
 352         case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
 353                 if (pmx->soc->hsm_in_mux) {
 354                         *bank = g->mux_bank;
 355                         *reg = g->mux_reg;
 356                 } else {
 357                         *bank = g->drv_bank;
 358                         *reg = g->drv_reg;
 359                 }
 360                 *bit = g->hsm_bit;
 361                 *width = 1;
 362                 break;
 363         case TEGRA_PINCONF_PARAM_SCHMITT:
 364                 if (pmx->soc->schmitt_in_mux) {
 365                         *bank = g->mux_bank;
 366                         *reg = g->mux_reg;
 367                 } else {
 368                         *bank = g->drv_bank;
 369                         *reg = g->drv_reg;
 370                 }
 371                 *bit = g->schmitt_bit;
 372                 *width = 1;
 373                 break;
 374         case TEGRA_PINCONF_PARAM_LOW_POWER_MODE:
 375                 *bank = g->drv_bank;
 376                 *reg = g->drv_reg;
 377                 *bit = g->lpmd_bit;
 378                 *width = 2;
 379                 break;
 380         case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH:
 381                 *bank = g->drv_bank;
 382                 *reg = g->drv_reg;
 383                 *bit = g->drvdn_bit;
 384                 *width = g->drvdn_width;
 385                 break;
 386         case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH:
 387                 *bank = g->drv_bank;
 388                 *reg = g->drv_reg;
 389                 *bit = g->drvup_bit;
 390                 *width = g->drvup_width;
 391                 break;
 392         case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING:
 393                 *bank = g->drv_bank;
 394                 *reg = g->drv_reg;
 395                 *bit = g->slwf_bit;
 396                 *width = g->slwf_width;
 397                 break;
 398         case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING:
 399                 *bank = g->drv_bank;
 400                 *reg = g->drv_reg;
 401                 *bit = g->slwr_bit;
 402                 *width = g->slwr_width;
 403                 break;
 404         case TEGRA_PINCONF_PARAM_DRIVE_TYPE:
 405                 if (pmx->soc->drvtype_in_mux) {
 406                         *bank = g->mux_bank;
 407                         *reg = g->mux_reg;
 408                 } else {
 409                         *bank = g->drv_bank;
 410                         *reg = g->drv_reg;
 411                 }
 412                 *bit = g->drvtype_bit;
 413                 *width = 2;
 414                 break;
 415         default:
 416                 dev_err(pmx->dev, "Invalid config param %04x\n", param);
 417                 return -ENOTSUPP;
 418         }
 419
 420         if (*reg < 0 || *bit < 0)  {
 421                 if (report_err) {
 422                         const char *prop = "unknown";
 423                         int i;
 424
 425                         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 426                                 if (cfg_params[i].param == param) {
 427                                         prop = cfg_params[i].property;
 428                                         break;
 429                                 }
 430                         }
 431
 432                         dev_err(pmx->dev,
 433                                 "Config param %04x (%s) not supported on group %s\n",
 434                                 param, prop, g->name);
 435                 }
 436                 return -ENOTSUPP;
 437         }
 438
 439         return 0;
 440 }
 441
 442 static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
 443                              unsigned pin, unsigned long *config)
 444 {
 445         dev_err(pctldev->dev, "pin_config_get op not supported\n");
 446         return -ENOTSUPP;
 447 }
 448
 449 static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
 450                              unsigned pin, unsigned long *configs,
 451                              unsigned num_configs)
 452 {
 453         dev_err(pctldev->dev, "pin_config_set op not supported\n");
 454         return -ENOTSUPP;
 455 }
 456
 457 static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
 458                                    unsigned group, unsigned long *config)
 459 {
 460         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 461         enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config);
 462         u16 arg;
 463         const struct tegra_pingroup *g;
 464         int ret;
 465         s8 bank, bit, width;
 466         s16 reg;
 467         u32 val, mask;
 468
 469         g = &pmx->soc->groups[group];
 470
 471         ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
 472                                 &width);
 473         if (ret < 0)
 474                 return ret;
 475
 476         val = pmx_readl(pmx, bank, reg);
 477         mask = (1 << width) - 1;
 478         arg = (val >> bit) & mask;
 479
 480         *config = TEGRA_PINCONF_PACK(param, arg);
 481
 482         return 0;
 483 }
 484
 485 static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
 486                                    unsigned group, unsigned long *configs,
 487                                    unsigned num_configs)
 488 {
 489         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 490         enum tegra_pinconf_param param;
 491         u16 arg;
 492         const struct tegra_pingroup *g;
 493         int ret, i;
 494         s8 bank, bit, width;
 495         s16 reg;
 496         u32 val, mask;
 497
 498         g = &pmx->soc->groups[group];
 499
 500         for (i = 0; i < num_configs; i++) {
 501                 param = TEGRA_PINCONF_UNPACK_PARAM(configs[i]);
 502                 arg = TEGRA_PINCONF_UNPACK_ARG(configs[i]);
 503
 504                 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
 505                                         &width);
 506                 if (ret < 0)
 507                         return ret;
 508
 509                 val = pmx_readl(pmx, bank, reg);
 510
 511                 /* LOCK can't be cleared */
 512                 if (param == TEGRA_PINCONF_PARAM_LOCK) {
 513                         if ((val & BIT(bit)) && !arg) {
 514                                 dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
 515                                 return -EINVAL;
 516                         }
 517                 }
 518
 519                 /* Special-case Boolean values; allow any non-zero as true */
 520                 if (width == 1)
 521                         arg = !!arg;
 522
 523                 /* Range-check user-supplied value */
 524                 mask = (1 << width) - 1;
 525                 if (arg & ~mask) {
 526                         dev_err(pctldev->dev,
 527                                 "config %lx: %x too big for %d bit register\n",
 528                                 configs[i], arg, width);
 529                         return -EINVAL;
 530                 }
 531
 532                 /* Update register */
 533                 val &= ~(mask << bit);
 534                 val |= arg << bit;
 535                 pmx_writel(pmx, val, bank, reg);
 536         } /* for each config */
 537
 538         return 0;
 539 }
 540
 541 #ifdef CONFIG_DEBUG_FS
 542 static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
 543                                    struct seq_file *s, unsigned offset)
 544 {
 545 }
 546
 547 static const char *strip_prefix(const char *s)
 548 {
 549         const char *comma = strchr(s, ',');
 550         if (!comma)
 551                 return s;
 552
 553         return comma + 1;
 554 }
 555
 556 static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
 557                                          struct seq_file *s, unsigned group)
 558 {
 559         struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
 560         const struct tegra_pingroup *g;
 561         int i, ret;
 562         s8 bank, bit, width;
 563         s16 reg;
 564         u32 val;
 565
 566         g = &pmx->soc->groups[group];
 567
 568         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 569                 ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
 570                                         &bank, &reg, &bit, &width);
 571                 if (ret < 0)
 572                         continue;
 573
 574                 val = pmx_readl(pmx, bank, reg);
 575                 val >>= bit;
 576                 val &= (1 << width) - 1;
 577
 578                 seq_printf(s, "\n\t%s=%u",
 579                            strip_prefix(cfg_params[i].property), val);
 580         }
 581 }
 582
 583 static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
 584                                           struct seq_file *s,
 585                                           unsigned long config)
 586 {
 587         enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
 588         u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
 589         const char *pname = "unknown";
 590         int i;
 591
 592         for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
 593                 if (cfg_params[i].param == param) {
 594                         pname = cfg_params[i].property;
 595                         break;
 596                 }
 597         }
 598
 599         seq_printf(s, "%s=%d", strip_prefix(pname), arg);
 600 }
 601 #endif
 602
 603 static const struct pinconf_ops tegra_pinconf_ops = {
 604         .pin_config_get = tegra_pinconf_get,
 605         .pin_config_set = tegra_pinconf_set,
 606         .pin_config_group_get = tegra_pinconf_group_get,
 607         .pin_config_group_set = tegra_pinconf_group_set,
 608 #ifdef CONFIG_DEBUG_FS
 609         .pin_config_dbg_show = tegra_pinconf_dbg_show,
 610         .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
 611         .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show,
 612 #endif
 613 };
 614
 615 static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
 616         .name = "Tegra GPIOs",
 617         .id = 0,
 618         .base = 0,
 619 };
 620
 621 static struct pinctrl_desc tegra_pinctrl_desc = {
 622         .pctlops = &tegra_pinctrl_ops,
 623         .pmxops = &tegra_pinmux_ops,
 624         .confops = &tegra_pinconf_ops,
 625         .owner = THIS_MODULE,
 626 };
 627
 628 static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)
 629 {
 630         int i = 0;
 631         const struct tegra_pingroup *g;
 632         u32 val;
 633
 634         for (i = 0; i < pmx->soc->ngroups; ++i) {
 635                 g = &pmx->soc->groups[i];
 636                 if (g->parked_bit >= 0) {
 637                         val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
 638                         val &= ~(1 << g->parked_bit);
 639                         pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
 640                 }
 641         }
 642 }
 643
 644 static bool gpio_node_has_range(void)
 645 {
 646         struct device_node *np;
 647         bool has_prop = false;
 648
 649         np = of_find_compatible_node(NULL, NULL, "nvidia,tegra30-gpio");
 650         if (!np)
 651                 return has_prop;
 652
 653         has_prop = of_find_property(np, "gpio-ranges", NULL);
 654
 655         of_node_put(np);
 656
 657         return has_prop;
 658 }
 659
 660 int tegra_pinctrl_probe(struct platform_device *pdev,
 661                         const struct tegra_pinctrl_soc_data *soc_data)
 662 {
 663         struct tegra_pmx *pmx;
 664         struct resource *res;
 665         int i;
 666         const char **group_pins;
 667         int fn, gn, gfn;
 668
 669         pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
 670         if (!pmx) {
 671                 dev_err(&pdev->dev, "Can't alloc tegra_pmx\n");
 672                 return -ENOMEM;
 673         }
 674         pmx->dev = &pdev->dev;
 675         pmx->soc = soc_data;
 676
 677         /*
 678          * Each mux group will appear in 4 functions' list of groups.
 679          * This over-allocates slightly, since not all groups are mux groups.
 680          */
 681         pmx->group_pins = devm_kzalloc(&pdev->dev,
 682                 soc_data->ngroups * 4 * sizeof(*pmx->group_pins),
 683                 GFP_KERNEL);
 684         if (!pmx->group_pins)
 685                 return -ENOMEM;
 686
 687         group_pins = pmx->group_pins;
 688         for (fn = 0; fn < soc_data->nfunctions; fn++) {
 689                 struct tegra_function *func = &soc_data->functions[fn];
 690
 691                 func->groups = group_pins;
 692
 693                 for (gn = 0; gn < soc_data->ngroups; gn++) {
 694                         const struct tegra_pingroup *g = &soc_data->groups[gn];
 695
 696                         if (g->mux_reg == -1)
 697                                 continue;
 698
 699                         for (gfn = 0; gfn < 4; gfn++)
 700                                 if (g->funcs[gfn] == fn)
 701                                         break;
 702                         if (gfn == 4)
 703                                 continue;
 704
 705                         BUG_ON(group_pins - pmx->group_pins >=
 706                                 soc_data->ngroups * 4);
 707                         *group_pins++ = g->name;
 708                         func->ngroups++;
 709                 }
 710         }
 711
 712         tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
 713         tegra_pinctrl_desc.name = dev_name(&pdev->dev);
 714         tegra_pinctrl_desc.pins = pmx->soc->pins;
 715         tegra_pinctrl_desc.npins = pmx->soc->npins;
 716
 717         for (i = 0; ; i++) {
 718                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
 719                 if (!res)
 720                         break;
 721         }
 722         pmx->nbanks = i;
 723
 724         pmx->regs = devm_kzalloc(&pdev->dev, pmx->nbanks * sizeof(*pmx->regs),
 725                                  GFP_KERNEL);
 726         if (!pmx->regs) {
 727                 dev_err(&pdev->dev, "Can't alloc regs pointer\n");
 728                 return -ENOMEM;
 729         }
 730
 731         for (i = 0; i < pmx->nbanks; i++) {
 732                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
 733                 pmx->regs[i] = devm_ioremap_resource(&pdev->dev, res);
 734                 if (IS_ERR(pmx->regs[i]))
 735                         return PTR_ERR(pmx->regs[i]);
 736         }
 737
 738         pmx->pctl = devm_pinctrl_register(&pdev->dev, &tegra_pinctrl_desc, pmx);
 739         if (IS_ERR(pmx->pctl)) {
 740                 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
 741                 return PTR_ERR(pmx->pctl);
 742         }
 743
 744         tegra_pinctrl_clear_parked_bits(pmx);
 745
 746         if (!gpio_node_has_range())
 747                 pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
 748
 749         platform_set_drvdata(pdev, pmx);
 750
 751         dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n");
 752
 753         return 0;
 754 }
 755 EXPORT_SYMBOL_GPL(tegra_pinctrl_probe);