drivers/pinctrl/sirf/pinctrl-prima2.c

   1 /*
   2  * pinctrl pads, groups, functions for CSR SiRFprimaII
   3  *
   4  * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 #include <linux/pinctrl/pinctrl.h>
  10 #include <linux/bitops.h>
  11
  12 #include "pinctrl-sirf.h"
  13
  14 /*
  15  * pad list for the pinmux subsystem
  16  * refer to CS-131858-DC-6A.xls
  17  */
  18 static const struct pinctrl_pin_desc sirfsoc_pads[] = {
  19         PINCTRL_PIN(0, "gpio0-0"),
  20         PINCTRL_PIN(1, "gpio0-1"),
  21         PINCTRL_PIN(2, "gpio0-2"),
  22         PINCTRL_PIN(3, "gpio0-3"),
  23         PINCTRL_PIN(4, "pwm0"),
  24         PINCTRL_PIN(5, "pwm1"),
  25         PINCTRL_PIN(6, "pwm2"),
  26         PINCTRL_PIN(7, "pwm3"),
  27         PINCTRL_PIN(8, "warm_rst_b"),
  28         PINCTRL_PIN(9, "odo_0"),
  29         PINCTRL_PIN(10, "odo_1"),
  30         PINCTRL_PIN(11, "dr_dir"),
  31         PINCTRL_PIN(12, "viprom_fa"),
  32         PINCTRL_PIN(13, "scl_1"),
  33         PINCTRL_PIN(14, "ntrst"),
  34         PINCTRL_PIN(15, "sda_1"),
  35         PINCTRL_PIN(16, "x_ldd[16]"),
  36         PINCTRL_PIN(17, "x_ldd[17]"),
  37         PINCTRL_PIN(18, "x_ldd[18]"),
  38         PINCTRL_PIN(19, "x_ldd[19]"),
  39         PINCTRL_PIN(20, "x_ldd[20]"),
  40         PINCTRL_PIN(21, "x_ldd[21]"),
  41         PINCTRL_PIN(22, "x_ldd[22]"),
  42         PINCTRL_PIN(23, "x_ldd[23], lcdrom_frdy"),
  43         PINCTRL_PIN(24, "gps_sgn"),
  44         PINCTRL_PIN(25, "gps_mag"),
  45         PINCTRL_PIN(26, "gps_clk"),
  46         PINCTRL_PIN(27, "sd_cd_b_1"),
  47         PINCTRL_PIN(28, "sd_vcc_on_1"),
  48         PINCTRL_PIN(29, "sd_wp_b_1"),
  49         PINCTRL_PIN(30, "sd_clk_3"),
  50         PINCTRL_PIN(31, "sd_cmd_3"),
  51
  52         PINCTRL_PIN(32, "x_sd_dat_3[0]"),
  53         PINCTRL_PIN(33, "x_sd_dat_3[1]"),
  54         PINCTRL_PIN(34, "x_sd_dat_3[2]"),
  55         PINCTRL_PIN(35, "x_sd_dat_3[3]"),
  56         PINCTRL_PIN(36, "x_sd_clk_4"),
  57         PINCTRL_PIN(37, "x_sd_cmd_4"),
  58         PINCTRL_PIN(38, "x_sd_dat_4[0]"),
  59         PINCTRL_PIN(39, "x_sd_dat_4[1]"),
  60         PINCTRL_PIN(40, "x_sd_dat_4[2]"),
  61         PINCTRL_PIN(41, "x_sd_dat_4[3]"),
  62         PINCTRL_PIN(42, "x_cko_1"),
  63         PINCTRL_PIN(43, "x_ac97_bit_clk"),
  64         PINCTRL_PIN(44, "x_ac97_dout"),
  65         PINCTRL_PIN(45, "x_ac97_din"),
  66         PINCTRL_PIN(46, "x_ac97_sync"),
  67         PINCTRL_PIN(47, "x_txd_1"),
  68         PINCTRL_PIN(48, "x_txd_2"),
  69         PINCTRL_PIN(49, "x_rxd_1"),
  70         PINCTRL_PIN(50, "x_rxd_2"),
  71         PINCTRL_PIN(51, "x_usclk_0"),
  72         PINCTRL_PIN(52, "x_utxd_0"),
  73         PINCTRL_PIN(53, "x_urxd_0"),
  74         PINCTRL_PIN(54, "x_utfs_0"),
  75         PINCTRL_PIN(55, "x_urfs_0"),
  76         PINCTRL_PIN(56, "x_usclk_1"),
  77         PINCTRL_PIN(57, "x_utxd_1"),
  78         PINCTRL_PIN(58, "x_urxd_1"),
  79         PINCTRL_PIN(59, "x_utfs_1"),
  80         PINCTRL_PIN(60, "x_urfs_1"),
  81         PINCTRL_PIN(61, "x_usclk_2"),
  82         PINCTRL_PIN(62, "x_utxd_2"),
  83         PINCTRL_PIN(63, "x_urxd_2"),
  84
  85         PINCTRL_PIN(64, "x_utfs_2"),
  86         PINCTRL_PIN(65, "x_urfs_2"),
  87         PINCTRL_PIN(66, "x_df_we_b"),
  88         PINCTRL_PIN(67, "x_df_re_b"),
  89         PINCTRL_PIN(68, "x_txd_0"),
  90         PINCTRL_PIN(69, "x_rxd_0"),
  91         PINCTRL_PIN(78, "x_cko_0"),
  92         PINCTRL_PIN(79, "x_vip_pxd[7]"),
  93         PINCTRL_PIN(80, "x_vip_pxd[6]"),
  94         PINCTRL_PIN(81, "x_vip_pxd[5]"),
  95         PINCTRL_PIN(82, "x_vip_pxd[4]"),
  96         PINCTRL_PIN(83, "x_vip_pxd[3]"),
  97         PINCTRL_PIN(84, "x_vip_pxd[2]"),
  98         PINCTRL_PIN(85, "x_vip_pxd[1]"),
  99         PINCTRL_PIN(86, "x_vip_pxd[0]"),
 100         PINCTRL_PIN(87, "x_vip_vsync"),
 101         PINCTRL_PIN(88, "x_vip_hsync"),
 102         PINCTRL_PIN(89, "x_vip_pxclk"),
 103         PINCTRL_PIN(90, "x_sda_0"),
 104         PINCTRL_PIN(91, "x_scl_0"),
 105         PINCTRL_PIN(92, "x_df_ry_by"),
 106         PINCTRL_PIN(93, "x_df_cs_b[1]"),
 107         PINCTRL_PIN(94, "x_df_cs_b[0]"),
 108         PINCTRL_PIN(95, "x_l_pclk"),
 109
 110         PINCTRL_PIN(96, "x_l_lck"),
 111         PINCTRL_PIN(97, "x_l_fck"),
 112         PINCTRL_PIN(98, "x_l_de"),
 113         PINCTRL_PIN(99, "x_ldd[0]"),
 114         PINCTRL_PIN(100, "x_ldd[1]"),
 115         PINCTRL_PIN(101, "x_ldd[2]"),
 116         PINCTRL_PIN(102, "x_ldd[3]"),
 117         PINCTRL_PIN(103, "x_ldd[4]"),
 118         PINCTRL_PIN(104, "x_ldd[5]"),
 119         PINCTRL_PIN(105, "x_ldd[6]"),
 120         PINCTRL_PIN(106, "x_ldd[7]"),
 121         PINCTRL_PIN(107, "x_ldd[8]"),
 122         PINCTRL_PIN(108, "x_ldd[9]"),
 123         PINCTRL_PIN(109, "x_ldd[10]"),
 124         PINCTRL_PIN(110, "x_ldd[11]"),
 125         PINCTRL_PIN(111, "x_ldd[12]"),
 126         PINCTRL_PIN(112, "x_ldd[13]"),
 127         PINCTRL_PIN(113, "x_ldd[14]"),
 128         PINCTRL_PIN(114, "x_ldd[15]"),
 129 };
 130
 131 static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
 132         {
 133                 .group = 3,
 134                 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
 135                         BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
 136                         BIT(17) | BIT(18),
 137         }, {
 138                 .group = 2,
 139                 .mask = BIT(31),
 140         },
 141 };
 142
 143 static const struct sirfsoc_padmux lcd_16bits_padmux = {
 144         .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask),
 145         .muxmask = lcd_16bits_sirfsoc_muxmask,
 146         .funcmask = BIT(4),
 147         .funcval = 0,
 148 };
 149
 150 static const unsigned lcd_16bits_pins[] = { 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
 151         105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
 152
 153 static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
 154         {
 155                 .group = 3,
 156                 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
 157                         BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
 158                         BIT(17) | BIT(18),
 159         }, {
 160                 .group = 2,
 161                 .mask = BIT(31),
 162         }, {
 163                 .group = 0,
 164                 .mask = BIT(16) | BIT(17),
 165         },
 166 };
 167
 168 static const struct sirfsoc_padmux lcd_18bits_padmux = {
 169         .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask),
 170         .muxmask = lcd_18bits_muxmask,
 171         .funcmask = BIT(4),
 172         .funcval = 0,
 173 };
 174
 175 static const unsigned lcd_18bits_pins[] = { 16, 17, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
 176         105, 106, 107, 108, 109, 110, 111, 112, 113, 114};
 177
 178 static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
 179         {
 180                 .group = 3,
 181                 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
 182                         BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
 183                         BIT(17) | BIT(18),
 184         }, {
 185                 .group = 2,
 186                 .mask = BIT(31),
 187         }, {
 188                 .group = 0,
 189                 .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
 190         },
 191 };
 192
 193 static const struct sirfsoc_padmux lcd_24bits_padmux = {
 194         .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask),
 195         .muxmask = lcd_24bits_muxmask,
 196         .funcmask = BIT(4),
 197         .funcval = 0,
 198 };
 199
 200 static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
 201         105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
 202
 203 static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
 204         {
 205                 .group = 3,
 206                 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
 207                         BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
 208                         BIT(17) | BIT(18),
 209         }, {
 210                 .group = 2,
 211                 .mask = BIT(31),
 212         }, {
 213                 .group = 0,
 214                 .mask = BIT(23),
 215         },
 216 };
 217
 218 static const struct sirfsoc_padmux lcdrom_padmux = {
 219         .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask),
 220         .muxmask = lcdrom_muxmask,
 221         .funcmask = BIT(4),
 222         .funcval = BIT(4),
 223 };
 224
 225 static const unsigned lcdrom_pins[] = { 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
 226         105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
 227
 228 static const struct sirfsoc_muxmask uart0_muxmask[] = {
 229         {
 230                 .group = 2,
 231                 .mask = BIT(4) | BIT(5),
 232         }, {
 233                 .group = 1,
 234                 .mask = BIT(23) | BIT(28),
 235         },
 236 };
 237
 238 static const struct sirfsoc_padmux uart0_padmux = {
 239         .muxmask_counts = ARRAY_SIZE(uart0_muxmask),
 240         .muxmask = uart0_muxmask,
 241         .funcmask = BIT(9),
 242         .funcval = BIT(9),
 243 };
 244
 245 static const unsigned uart0_pins[] = { 55, 60, 68, 69 };
 246
 247 static const struct sirfsoc_muxmask uart0_nostreamctrl_muxmask[] = {
 248         {
 249                 .group = 2,
 250                 .mask = BIT(4) | BIT(5),
 251         },
 252 };
 253
 254 static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = {
 255         .muxmask_counts = ARRAY_SIZE(uart0_nostreamctrl_muxmask),
 256         .muxmask = uart0_nostreamctrl_muxmask,
 257 };
 258
 259 static const unsigned uart0_nostreamctrl_pins[] = { 68, 69 };
 260
 261 static const struct sirfsoc_muxmask uart1_muxmask[] = {
 262         {
 263                 .group = 1,
 264                 .mask = BIT(15) | BIT(17),
 265         },
 266 };
 267
 268 static const struct sirfsoc_padmux uart1_padmux = {
 269         .muxmask_counts = ARRAY_SIZE(uart1_muxmask),
 270         .muxmask = uart1_muxmask,
 271 };
 272
 273 static const unsigned uart1_pins[] = { 47, 49 };
 274
 275 static const struct sirfsoc_muxmask uart2_muxmask[] = {
 276         {
 277                 .group = 1,
 278                 .mask = BIT(16) | BIT(18) | BIT(24) | BIT(27),
 279         },
 280 };
 281
 282 static const struct sirfsoc_padmux uart2_padmux = {
 283         .muxmask_counts = ARRAY_SIZE(uart2_muxmask),
 284         .muxmask = uart2_muxmask,
 285         .funcmask = BIT(10),
 286         .funcval = BIT(10),
 287 };
 288
 289 static const unsigned uart2_pins[] = { 48, 50, 56, 59 };
 290
 291 static const struct sirfsoc_muxmask uart2_nostreamctrl_muxmask[] = {
 292         {
 293                 .group = 1,
 294                 .mask = BIT(16) | BIT(18),
 295         },
 296 };
 297
 298 static const struct sirfsoc_padmux uart2_nostreamctrl_padmux = {
 299         .muxmask_counts = ARRAY_SIZE(uart2_nostreamctrl_muxmask),
 300         .muxmask = uart2_nostreamctrl_muxmask,
 301 };
 302
 303 static const unsigned uart2_nostreamctrl_pins[] = { 48, 50 };
 304
 305 static const struct sirfsoc_muxmask sdmmc3_muxmask[] = {
 306         {
 307                 .group = 0,
 308                 .mask = BIT(30) | BIT(31),
 309         }, {
 310                 .group = 1,
 311                 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
 312         },
 313 };
 314
 315 static const struct sirfsoc_padmux sdmmc3_padmux = {
 316         .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask),
 317         .muxmask = sdmmc3_muxmask,
 318         .funcmask = BIT(7),
 319         .funcval = 0,
 320 };
 321
 322 static const unsigned sdmmc3_pins[] = { 30, 31, 32, 33, 34, 35 };
 323
 324 static const struct sirfsoc_muxmask spi0_muxmask[] = {
 325         {
 326                 .group = 1,
 327                 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
 328         },
 329 };
 330
 331 static const struct sirfsoc_padmux spi0_padmux = {
 332         .muxmask_counts = ARRAY_SIZE(spi0_muxmask),
 333         .muxmask = spi0_muxmask,
 334         .funcmask = BIT(7),
 335         .funcval = BIT(7),
 336 };
 337
 338 static const unsigned spi0_pins[] = { 32, 33, 34, 35 };
 339
 340 static const struct sirfsoc_muxmask sdmmc4_muxmask[] = {
 341         {
 342                 .group = 1,
 343                 .mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9),
 344         },
 345 };
 346
 347 static const struct sirfsoc_padmux sdmmc4_padmux = {
 348         .muxmask_counts = ARRAY_SIZE(sdmmc4_muxmask),
 349         .muxmask = sdmmc4_muxmask,
 350 };
 351
 352 static const unsigned sdmmc4_pins[] = { 36, 37, 38, 39, 40, 41 };
 353
 354 static const struct sirfsoc_muxmask cko1_muxmask[] = {
 355         {
 356                 .group = 1,
 357                 .mask = BIT(10),
 358         },
 359 };
 360
 361 static const struct sirfsoc_padmux cko1_padmux = {
 362         .muxmask_counts = ARRAY_SIZE(cko1_muxmask),
 363         .muxmask = cko1_muxmask,
 364         .funcmask = BIT(3),
 365         .funcval = 0,
 366 };
 367
 368 static const unsigned cko1_pins[] = { 42 };
 369
 370 static const struct sirfsoc_muxmask i2s_muxmask[] = {
 371         {
 372                 .group = 1,
 373                 .mask =
 374                         BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(19)
 375                                 | BIT(23) | BIT(28),
 376         },
 377 };
 378
 379 static const struct sirfsoc_padmux i2s_padmux = {
 380         .muxmask_counts = ARRAY_SIZE(i2s_muxmask),
 381         .muxmask = i2s_muxmask,
 382         .funcmask = BIT(3) | BIT(9),
 383         .funcval = BIT(3),
 384 };
 385
 386 static const unsigned i2s_pins[] = { 42, 43, 44, 45, 46, 51, 55, 60 };
 387
 388 static const struct sirfsoc_muxmask ac97_muxmask[] = {
 389         {
 390                 .group = 1,
 391                 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
 392         },
 393 };
 394
 395 static const struct sirfsoc_padmux ac97_padmux = {
 396         .muxmask_counts = ARRAY_SIZE(ac97_muxmask),
 397         .muxmask = ac97_muxmask,
 398         .funcmask = BIT(8),
 399         .funcval = 0,
 400 };
 401
 402 static const unsigned ac97_pins[] = { 33, 34, 35, 36 };
 403
 404 static const struct sirfsoc_muxmask spi1_muxmask[] = {
 405         {
 406                 .group = 1,
 407                 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
 408         },
 409 };
 410
 411 static const struct sirfsoc_padmux spi1_padmux = {
 412         .muxmask_counts = ARRAY_SIZE(spi1_muxmask),
 413         .muxmask = spi1_muxmask,
 414         .funcmask = BIT(8),
 415         .funcval = BIT(8),
 416 };
 417
 418 static const unsigned spi1_pins[] = { 43, 44, 45, 46 };
 419
 420 static const struct sirfsoc_muxmask sdmmc1_muxmask[] = {
 421         {
 422                 .group = 0,
 423                 .mask = BIT(27) | BIT(28) | BIT(29),
 424         },
 425 };
 426
 427 static const struct sirfsoc_padmux sdmmc1_padmux = {
 428         .muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask),
 429         .muxmask = sdmmc1_muxmask,
 430 };
 431
 432 static const unsigned sdmmc1_pins[] = { 27, 28, 29 };
 433
 434 static const struct sirfsoc_muxmask gps_muxmask[] = {
 435         {
 436                 .group = 0,
 437                 .mask = BIT(24) | BIT(25) | BIT(26),
 438         },
 439 };
 440
 441 static const struct sirfsoc_padmux gps_padmux = {
 442         .muxmask_counts = ARRAY_SIZE(gps_muxmask),
 443         .muxmask = gps_muxmask,
 444         .funcmask = BIT(12) | BIT(13) | BIT(14),
 445         .funcval = BIT(12),
 446 };
 447
 448 static const unsigned gps_pins[] = { 24, 25, 26 };
 449
 450 static const struct sirfsoc_muxmask sdmmc5_muxmask[] = {
 451         {
 452                 .group = 0,
 453                 .mask = BIT(24) | BIT(25) | BIT(26),
 454         }, {
 455                 .group = 1,
 456                 .mask = BIT(29),
 457         }, {
 458                 .group = 2,
 459                 .mask = BIT(0) | BIT(1),
 460         },
 461 };
 462
 463 static const struct sirfsoc_padmux sdmmc5_padmux = {
 464         .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask),
 465         .muxmask = sdmmc5_muxmask,
 466         .funcmask = BIT(13) | BIT(14),
 467         .funcval = BIT(13) | BIT(14),
 468 };
 469
 470 static const unsigned sdmmc5_pins[] = { 24, 25, 26, 61, 64, 65 };
 471
 472 static const struct sirfsoc_muxmask usp0_muxmask[] = {
 473         {
 474                 .group = 1,
 475                 .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
 476         },
 477 };
 478
 479 static const struct sirfsoc_padmux usp0_padmux = {
 480         .muxmask_counts = ARRAY_SIZE(usp0_muxmask),
 481         .muxmask = usp0_muxmask,
 482         .funcmask = BIT(1) | BIT(2) | BIT(6) | BIT(9),
 483         .funcval = 0,
 484 };
 485
 486 static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 };
 487
 488 static const struct sirfsoc_muxmask usp1_muxmask[] = {
 489         {
 490                 .group = 1,
 491                 .mask = BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28),
 492         },
 493 };
 494
 495 static const struct sirfsoc_padmux usp1_padmux = {
 496         .muxmask_counts = ARRAY_SIZE(usp1_muxmask),
 497         .muxmask = usp1_muxmask,
 498         .funcmask = BIT(1) | BIT(9) | BIT(10) | BIT(11),
 499         .funcval = 0,
 500 };
 501
 502 static const unsigned usp1_pins[] = { 56, 57, 58, 59, 60 };
 503
 504 static const struct sirfsoc_muxmask usp2_muxmask[] = {
 505         {
 506                 .group = 1,
 507                 .mask = BIT(29) | BIT(30) | BIT(31),
 508         }, {
 509                 .group = 2,
 510                 .mask = BIT(0) | BIT(1),
 511         },
 512 };
 513
 514 static const struct sirfsoc_padmux usp2_padmux = {
 515         .muxmask_counts = ARRAY_SIZE(usp2_muxmask),
 516         .muxmask = usp2_muxmask,
 517         .funcmask = BIT(13) | BIT(14),
 518         .funcval = 0,
 519 };
 520
 521 static const unsigned usp2_pins[] = { 61, 62, 63, 64, 65 };
 522
 523 static const struct sirfsoc_muxmask nand_muxmask[] = {
 524         {
 525                 .group = 2,
 526                 .mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30),
 527         },
 528 };
 529
 530 static const struct sirfsoc_padmux nand_padmux = {
 531         .muxmask_counts = ARRAY_SIZE(nand_muxmask),
 532         .muxmask = nand_muxmask,
 533         .funcmask = BIT(5),
 534         .funcval = 0,
 535 };
 536
 537 static const unsigned nand_pins[] = { 64, 65, 92, 93, 94 };
 538
 539 static const struct sirfsoc_padmux sdmmc0_padmux = {
 540         .muxmask_counts = 0,
 541         .funcmask = BIT(5),
 542         .funcval = 0,
 543 };
 544
 545 static const unsigned sdmmc0_pins[] = { };
 546
 547 static const struct sirfsoc_muxmask sdmmc2_muxmask[] = {
 548         {
 549                 .group = 2,
 550                 .mask = BIT(2) | BIT(3),
 551         },
 552 };
 553
 554 static const struct sirfsoc_padmux sdmmc2_padmux = {
 555         .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask),
 556         .muxmask = sdmmc2_muxmask,
 557         .funcmask = BIT(5),
 558         .funcval = BIT(5),
 559 };
 560
 561 static const unsigned sdmmc2_pins[] = { 66, 67 };
 562
 563 static const struct sirfsoc_muxmask cko0_muxmask[] = {
 564         {
 565                 .group = 2,
 566                 .mask = BIT(14),
 567         },
 568 };
 569
 570 static const struct sirfsoc_padmux cko0_padmux = {
 571         .muxmask_counts = ARRAY_SIZE(cko0_muxmask),
 572         .muxmask = cko0_muxmask,
 573 };
 574
 575 static const unsigned cko0_pins[] = { 78 };
 576
 577 static const struct sirfsoc_muxmask vip_muxmask[] = {
 578         {
 579                 .group = 2,
 580                 .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19)
 581                         | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) |
 582                         BIT(25),
 583         },
 584 };
 585
 586 static const struct sirfsoc_padmux vip_padmux = {
 587         .muxmask_counts = ARRAY_SIZE(vip_muxmask),
 588         .muxmask = vip_muxmask,
 589         .funcmask = BIT(0),
 590         .funcval = 0,
 591 };
 592
 593 static const unsigned vip_pins[] = { 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 };
 594
 595 static const struct sirfsoc_muxmask i2c0_muxmask[] = {
 596         {
 597                 .group = 2,
 598                 .mask = BIT(26) | BIT(27),
 599         },
 600 };
 601
 602 static const struct sirfsoc_padmux i2c0_padmux = {
 603         .muxmask_counts = ARRAY_SIZE(i2c0_muxmask),
 604         .muxmask = i2c0_muxmask,
 605 };
 606
 607 static const unsigned i2c0_pins[] = { 90, 91 };
 608
 609 static const struct sirfsoc_muxmask i2c1_muxmask[] = {
 610         {
 611                 .group = 0,
 612                 .mask = BIT(13) | BIT(15),
 613         },
 614 };
 615
 616 static const struct sirfsoc_padmux i2c1_padmux = {
 617         .muxmask_counts = ARRAY_SIZE(i2c1_muxmask),
 618         .muxmask = i2c1_muxmask,
 619 };
 620
 621 static const unsigned i2c1_pins[] = { 13, 15 };
 622
 623 static const struct sirfsoc_muxmask viprom_muxmask[] = {
 624         {
 625                 .group = 2,
 626                 .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19)
 627                         | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) |
 628                         BIT(25),
 629         }, {
 630                 .group = 0,
 631                 .mask = BIT(12),
 632         },
 633 };
 634
 635 static const struct sirfsoc_padmux viprom_padmux = {
 636         .muxmask_counts = ARRAY_SIZE(viprom_muxmask),
 637         .muxmask = viprom_muxmask,
 638         .funcmask = BIT(0),
 639         .funcval = BIT(0),
 640 };
 641
 642 static const unsigned viprom_pins[] = { 12, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 };
 643
 644 static const struct sirfsoc_muxmask pwm0_muxmask[] = {
 645         {
 646                 .group = 0,
 647                 .mask = BIT(4),
 648         },
 649 };
 650
 651 static const struct sirfsoc_padmux pwm0_padmux = {
 652         .muxmask_counts = ARRAY_SIZE(pwm0_muxmask),
 653         .muxmask = pwm0_muxmask,
 654         .funcmask = BIT(12),
 655         .funcval = 0,
 656 };
 657
 658 static const unsigned pwm0_pins[] = { 4 };
 659
 660 static const struct sirfsoc_muxmask pwm1_muxmask[] = {
 661         {
 662                 .group = 0,
 663                 .mask = BIT(5),
 664         },
 665 };
 666
 667 static const struct sirfsoc_padmux pwm1_padmux = {
 668         .muxmask_counts = ARRAY_SIZE(pwm1_muxmask),
 669         .muxmask = pwm1_muxmask,
 670 };
 671
 672 static const unsigned pwm1_pins[] = { 5 };
 673
 674 static const struct sirfsoc_muxmask pwm2_muxmask[] = {
 675         {
 676                 .group = 0,
 677                 .mask = BIT(6),
 678         },
 679 };
 680
 681 static const struct sirfsoc_padmux pwm2_padmux = {
 682         .muxmask_counts = ARRAY_SIZE(pwm2_muxmask),
 683         .muxmask = pwm2_muxmask,
 684 };
 685
 686 static const unsigned pwm2_pins[] = { 6 };
 687
 688 static const struct sirfsoc_muxmask pwm3_muxmask[] = {
 689         {
 690                 .group = 0,
 691                 .mask = BIT(7),
 692         },
 693 };
 694
 695 static const struct sirfsoc_padmux pwm3_padmux = {
 696         .muxmask_counts = ARRAY_SIZE(pwm3_muxmask),
 697         .muxmask = pwm3_muxmask,
 698 };
 699
 700 static const unsigned pwm3_pins[] = { 7 };
 701
 702 static const struct sirfsoc_muxmask warm_rst_muxmask[] = {
 703         {
 704                 .group = 0,
 705                 .mask = BIT(8),
 706         },
 707 };
 708
 709 static const struct sirfsoc_padmux warm_rst_padmux = {
 710         .muxmask_counts = ARRAY_SIZE(warm_rst_muxmask),
 711         .muxmask = warm_rst_muxmask,
 712 };
 713
 714 static const unsigned warm_rst_pins[] = { 8 };
 715
 716 static const struct sirfsoc_muxmask usb0_utmi_drvbus_muxmask[] = {
 717         {
 718                 .group = 1,
 719                 .mask = BIT(22),
 720         },
 721 };
 722 static const struct sirfsoc_padmux usb0_utmi_drvbus_padmux = {
 723         .muxmask_counts = ARRAY_SIZE(usb0_utmi_drvbus_muxmask),
 724         .muxmask = usb0_utmi_drvbus_muxmask,
 725         .funcmask = BIT(6),
 726         .funcval = BIT(6), /* refer to PAD_UTMI_DRVVBUS0_ENABLE */
 727 };
 728
 729 static const unsigned usb0_utmi_drvbus_pins[] = { 54 };
 730
 731 static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = {
 732         {
 733                 .group = 1,
 734                 .mask = BIT(27),
 735         },
 736 };
 737
 738 static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = {
 739         .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask),
 740         .muxmask = usb1_utmi_drvbus_muxmask,
 741         .funcmask = BIT(11),
 742         .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */
 743 };
 744
 745 static const unsigned usb1_utmi_drvbus_pins[] = { 59 };
 746
 747 static const struct sirfsoc_muxmask pulse_count_muxmask[] = {
 748         {
 749                 .group = 0,
 750                 .mask = BIT(9) | BIT(10) | BIT(11),
 751         },
 752 };
 753
 754 static const struct sirfsoc_padmux pulse_count_padmux = {
 755         .muxmask_counts = ARRAY_SIZE(pulse_count_muxmask),
 756         .muxmask = pulse_count_muxmask,
 757 };
 758
 759 static const unsigned pulse_count_pins[] = { 9, 10, 11 };
 760
 761 static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
 762         SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins),
 763         SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins),
 764         SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins),
 765         SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins),
 766         SIRFSOC_PIN_GROUP("uart0grp", uart0_pins),
 767         SIRFSOC_PIN_GROUP("uart1grp", uart1_pins),
 768         SIRFSOC_PIN_GROUP("uart2grp", uart2_pins),
 769         SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins),
 770         SIRFSOC_PIN_GROUP("usp0grp", usp0_pins),
 771         SIRFSOC_PIN_GROUP("usp1grp", usp1_pins),
 772         SIRFSOC_PIN_GROUP("usp2grp", usp2_pins),
 773         SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins),
 774         SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins),
 775         SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins),
 776         SIRFSOC_PIN_GROUP("pwm1grp", pwm1_pins),
 777         SIRFSOC_PIN_GROUP("pwm2grp", pwm2_pins),
 778         SIRFSOC_PIN_GROUP("pwm3grp", pwm3_pins),
 779         SIRFSOC_PIN_GROUP("vipgrp", vip_pins),
 780         SIRFSOC_PIN_GROUP("vipromgrp", viprom_pins),
 781         SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins),
 782         SIRFSOC_PIN_GROUP("cko0grp", cko0_pins),
 783         SIRFSOC_PIN_GROUP("cko1grp", cko1_pins),
 784         SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins),
 785         SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins),
 786         SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins),
 787         SIRFSOC_PIN_GROUP("sdmmc3grp", sdmmc3_pins),
 788         SIRFSOC_PIN_GROUP("sdmmc4grp", sdmmc4_pins),
 789         SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins),
 790         SIRFSOC_PIN_GROUP("usb0_utmi_drvbusgrp", usb0_utmi_drvbus_pins),
 791         SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins),
 792         SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
 793         SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
 794         SIRFSOC_PIN_GROUP("ac97grp", ac97_pins),
 795         SIRFSOC_PIN_GROUP("nandgrp", nand_pins),
 796         SIRFSOC_PIN_GROUP("spi0grp", spi0_pins),
 797         SIRFSOC_PIN_GROUP("spi1grp", spi1_pins),
 798         SIRFSOC_PIN_GROUP("gpsgrp", gps_pins),
 799 };
 800
 801 static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" };
 802 static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" };
 803 static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" };
 804 static const char * const lcdromgrp[] = { "lcdromgrp" };
 805 static const char * const uart0grp[] = { "uart0grp" };
 806 static const char * const uart1grp[] = { "uart1grp" };
 807 static const char * const uart2grp[] = { "uart2grp" };
 808 static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
 809 static const char * const usp0grp[] = { "usp0grp" };
 810 static const char * const usp1grp[] = { "usp1grp" };
 811 static const char * const usp2grp[] = { "usp2grp" };
 812 static const char * const i2c0grp[] = { "i2c0grp" };
 813 static const char * const i2c1grp[] = { "i2c1grp" };
 814 static const char * const pwm0grp[] = { "pwm0grp" };
 815 static const char * const pwm1grp[] = { "pwm1grp" };
 816 static const char * const pwm2grp[] = { "pwm2grp" };
 817 static const char * const pwm3grp[] = { "pwm3grp" };
 818 static const char * const vipgrp[] = { "vipgrp" };
 819 static const char * const vipromgrp[] = { "vipromgrp" };
 820 static const char * const warm_rstgrp[] = { "warm_rstgrp" };
 821 static const char * const cko0grp[] = { "cko0grp" };
 822 static const char * const cko1grp[] = { "cko1grp" };
 823 static const char * const sdmmc0grp[] = { "sdmmc0grp" };
 824 static const char * const sdmmc1grp[] = { "sdmmc1grp" };
 825 static const char * const sdmmc2grp[] = { "sdmmc2grp" };
 826 static const char * const sdmmc3grp[] = { "sdmmc3grp" };
 827 static const char * const sdmmc4grp[] = { "sdmmc4grp" };
 828 static const char * const sdmmc5grp[] = { "sdmmc5grp" };
 829 static const char * const usb0_utmi_drvbusgrp[] = { "usb0_utmi_drvbusgrp" };
 830 static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
 831 static const char * const pulse_countgrp[] = { "pulse_countgrp" };
 832 static const char * const i2sgrp[] = { "i2sgrp" };
 833 static const char * const ac97grp[] = { "ac97grp" };
 834 static const char * const nandgrp[] = { "nandgrp" };
 835 static const char * const spi0grp[] = { "spi0grp" };
 836 static const char * const spi1grp[] = { "spi1grp" };
 837 static const char * const gpsgrp[] = { "gpsgrp" };
 838
 839 static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
 840         SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux),
 841         SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux),
 842         SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux),
 843         SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux),
 844         SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux),
 845         SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
 846         SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
 847         SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
 848         SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
 849         SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
 850         SIRFSOC_PMX_FUNCTION("usp2", usp2grp, usp2_padmux),
 851         SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux),
 852         SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux),
 853         SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux),
 854         SIRFSOC_PMX_FUNCTION("pwm1", pwm1grp, pwm1_padmux),
 855         SIRFSOC_PMX_FUNCTION("pwm2", pwm2grp, pwm2_padmux),
 856         SIRFSOC_PMX_FUNCTION("pwm3", pwm3grp, pwm3_padmux),
 857         SIRFSOC_PMX_FUNCTION("vip", vipgrp, vip_padmux),
 858         SIRFSOC_PMX_FUNCTION("viprom", vipromgrp, viprom_padmux),
 859         SIRFSOC_PMX_FUNCTION("warm_rst", warm_rstgrp, warm_rst_padmux),
 860         SIRFSOC_PMX_FUNCTION("cko0", cko0grp, cko0_padmux),
 861         SIRFSOC_PMX_FUNCTION("cko1", cko1grp, cko1_padmux),
 862         SIRFSOC_PMX_FUNCTION("sdmmc0", sdmmc0grp, sdmmc0_padmux),
 863         SIRFSOC_PMX_FUNCTION("sdmmc1", sdmmc1grp, sdmmc1_padmux),
 864         SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux),
 865         SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux),
 866         SIRFSOC_PMX_FUNCTION("sdmmc4", sdmmc4grp, sdmmc4_padmux),
 867         SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
 868         SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus", usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux),
 869         SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
 870         SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
 871         SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
 872         SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux),
 873         SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux),
 874         SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux),
 875         SIRFSOC_PMX_FUNCTION("spi1", spi1grp, spi1_padmux),
 876         SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux),
 877 };
 878
 879 struct sirfsoc_pinctrl_data prima2_pinctrl_data = {
 880         (struct pinctrl_pin_desc *)sirfsoc_pads,
 881         ARRAY_SIZE(sirfsoc_pads),
 882         (struct sirfsoc_pin_group *)sirfsoc_pin_groups,
 883         ARRAY_SIZE(sirfsoc_pin_groups),
 884         (struct sirfsoc_pmx_func *)sirfsoc_pmx_functions,
 885         ARRAY_SIZE(sirfsoc_pmx_functions),
 886 };
 887