drivers/pinctrl/intel/pinctrl-intel.c

   1 /*
   2  * Intel pinctrl/GPIO core driver.
   3  *
   4  * Copyright (C) 2015, Intel Corporation
   5  * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
   6  *          Mika Westerberg <mika.westerberg@linux.intel.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/acpi.h>
  17 #include <linux/gpio.h>
  18 #include <linux/gpio/driver.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/pm.h>
  21 #include <linux/pinctrl/pinctrl.h>
  22 #include <linux/pinctrl/pinmux.h>
  23 #include <linux/pinctrl/pinconf.h>
  24 #include <linux/pinctrl/pinconf-generic.h>
  25
  26 #include "pinctrl-intel.h"
  27
  28 /* Offset from regs */
  29 #define PADBAR                          0x00c
  30 #define GPI_IS                          0x100
  31 #define GPI_GPE_STS                     0x140
  32 #define GPI_GPE_EN                      0x160
  33
  34 #define PADOWN_BITS                     4
  35 #define PADOWN_SHIFT(p)                 ((p) % 8 * PADOWN_BITS)
  36 #define PADOWN_MASK(p)                  (0xf << PADOWN_SHIFT(p))
  37 #define PADOWN_GPP(p)                   ((p) / 8)
  38
  39 /* Offset from pad_regs */
  40 #define PADCFG0                         0x000
  41 #define PADCFG0_RXEVCFG_SHIFT           25
  42 #define PADCFG0_RXEVCFG_MASK            (3 << PADCFG0_RXEVCFG_SHIFT)
  43 #define PADCFG0_RXEVCFG_LEVEL           0
  44 #define PADCFG0_RXEVCFG_EDGE            1
  45 #define PADCFG0_RXEVCFG_DISABLED        2
  46 #define PADCFG0_RXEVCFG_EDGE_BOTH       3
  47 #define PADCFG0_RXINV                   BIT(23)
  48 #define PADCFG0_GPIROUTIOXAPIC          BIT(20)
  49 #define PADCFG0_GPIROUTSCI              BIT(19)
  50 #define PADCFG0_GPIROUTSMI              BIT(18)
  51 #define PADCFG0_GPIROUTNMI              BIT(17)
  52 #define PADCFG0_PMODE_SHIFT             10
  53 #define PADCFG0_PMODE_MASK              (0xf << PADCFG0_PMODE_SHIFT)
  54 #define PADCFG0_GPIORXDIS               BIT(9)
  55 #define PADCFG0_GPIOTXDIS               BIT(8)
  56 #define PADCFG0_GPIORXSTATE             BIT(1)
  57 #define PADCFG0_GPIOTXSTATE             BIT(0)
  58
  59 #define PADCFG1                         0x004
  60 #define PADCFG1_TERM_UP                 BIT(13)
  61 #define PADCFG1_TERM_SHIFT              10
  62 #define PADCFG1_TERM_MASK               (7 << PADCFG1_TERM_SHIFT)
  63 #define PADCFG1_TERM_20K                4
  64 #define PADCFG1_TERM_2K                 3
  65 #define PADCFG1_TERM_5K                 2
  66 #define PADCFG1_TERM_1K                 1
  67
  68 struct intel_pad_context {
  69         u32 padcfg0;
  70         u32 padcfg1;
  71 };
  72
  73 struct intel_community_context {
  74         u32 *intmask;
  75 };
  76
  77 struct intel_pinctrl_context {
  78         struct intel_pad_context *pads;
  79         struct intel_community_context *communities;
  80 };
  81
  82 /**
  83  * struct intel_pinctrl - Intel pinctrl private structure
  84  * @dev: Pointer to the device structure
  85  * @lock: Lock to serialize register access
  86  * @pctldesc: Pin controller description
  87  * @pctldev: Pointer to the pin controller device
  88  * @chip: GPIO chip in this pin controller
  89  * @soc: SoC/PCH specific pin configuration data
  90  * @communities: All communities in this pin controller
  91  * @ncommunities: Number of communities in this pin controller
  92  * @context: Configuration saved over system sleep
  93  */
  94 struct intel_pinctrl {
  95         struct device *dev;
  96         spinlock_t lock;
  97         struct pinctrl_desc pctldesc;
  98         struct pinctrl_dev *pctldev;
  99         struct gpio_chip chip;
 100         const struct intel_pinctrl_soc_data *soc;
 101         struct intel_community *communities;
 102         size_t ncommunities;
 103         struct intel_pinctrl_context context;
 104 };
 105
 106 #define gpiochip_to_pinctrl(c)  container_of(c, struct intel_pinctrl, chip)
 107 #define pin_to_padno(c, p)      ((p) - (c)->pin_base)
 108
 109 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
 110                                                    unsigned pin)
 111 {
 112         struct intel_community *community;
 113         int i;
 114
 115         for (i = 0; i < pctrl->ncommunities; i++) {
 116                 community = &pctrl->communities[i];
 117                 if (pin >= community->pin_base &&
 118                     pin < community->pin_base + community->npins)
 119                         return community;
 120         }
 121
 122         dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
 123         return NULL;
 124 }
 125
 126 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin,
 127                                       unsigned reg)
 128 {
 129         const struct intel_community *community;
 130         unsigned padno;
 131
 132         community = intel_get_community(pctrl, pin);
 133         if (!community)
 134                 return NULL;
 135
 136         padno = pin_to_padno(community, pin);
 137         return community->pad_regs + reg + padno * 8;
 138 }
 139
 140 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
 141 {
 142         const struct intel_community *community;
 143         unsigned padno, gpp, offset, group;
 144         void __iomem *padown;
 145
 146         community = intel_get_community(pctrl, pin);
 147         if (!community)
 148                 return false;
 149         if (!community->padown_offset)
 150                 return true;
 151
 152         padno = pin_to_padno(community, pin);
 153         group = padno / community->gpp_size;
 154         gpp = PADOWN_GPP(padno % community->gpp_size);
 155         offset = community->padown_offset + 0x10 * group + gpp * 4;
 156         padown = community->regs + offset;
 157
 158         return !(readl(padown) & PADOWN_MASK(padno));
 159 }
 160
 161 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin)
 162 {
 163         const struct intel_community *community;
 164         unsigned padno, gpp, offset;
 165         void __iomem *hostown;
 166
 167         community = intel_get_community(pctrl, pin);
 168         if (!community)
 169                 return true;
 170         if (!community->hostown_offset)
 171                 return false;
 172
 173         padno = pin_to_padno(community, pin);
 174         gpp = padno / community->gpp_size;
 175         offset = community->hostown_offset + gpp * 4;
 176         hostown = community->regs + offset;
 177
 178         return !(readl(hostown) & BIT(padno % community->gpp_size));
 179 }
 180
 181 static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
 182 {
 183         struct intel_community *community;
 184         unsigned padno, gpp, offset;
 185         u32 value;
 186
 187         community = intel_get_community(pctrl, pin);
 188         if (!community)
 189                 return true;
 190         if (!community->padcfglock_offset)
 191                 return false;
 192
 193         padno = pin_to_padno(community, pin);
 194         gpp = padno / community->gpp_size;
 195
 196         /*
 197          * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
 198          * the pad is considered unlocked. Any other case means that it is
 199          * either fully or partially locked and we don't touch it.
 200          */
 201         offset = community->padcfglock_offset + gpp * 8;
 202         value = readl(community->regs + offset);
 203         if (value & BIT(pin % community->gpp_size))
 204                 return true;
 205
 206         offset = community->padcfglock_offset + 4 + gpp * 8;
 207         value = readl(community->regs + offset);
 208         if (value & BIT(pin % community->gpp_size))
 209                 return true;
 210
 211         return false;
 212 }
 213
 214 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin)
 215 {
 216         return intel_pad_owned_by_host(pctrl, pin) &&
 217                 !intel_pad_locked(pctrl, pin);
 218 }
 219
 220 static int intel_get_groups_count(struct pinctrl_dev *pctldev)
 221 {
 222         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 223
 224         return pctrl->soc->ngroups;
 225 }
 226
 227 static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
 228                                       unsigned group)
 229 {
 230         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 231
 232         return pctrl->soc->groups[group].name;
 233 }
 234
 235 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
 236                               const unsigned **pins, unsigned *npins)
 237 {
 238         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 239
 240         *pins = pctrl->soc->groups[group].pins;
 241         *npins = pctrl->soc->groups[group].npins;
 242         return 0;
 243 }
 244
 245 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 246                                unsigned pin)
 247 {
 248         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 249         u32 cfg0, cfg1, mode;
 250         bool locked, acpi;
 251
 252         if (!intel_pad_owned_by_host(pctrl, pin)) {
 253                 seq_puts(s, "not available");
 254                 return;
 255         }
 256
 257         cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
 258         cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
 259
 260         mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
 261         if (!mode)
 262                 seq_puts(s, "GPIO ");
 263         else
 264                 seq_printf(s, "mode %d ", mode);
 265
 266         seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
 267
 268         locked = intel_pad_locked(pctrl, pin);
 269         acpi = intel_pad_acpi_mode(pctrl, pin);
 270
 271         if (locked || acpi) {
 272                 seq_puts(s, " [");
 273                 if (locked) {
 274                         seq_puts(s, "LOCKED");
 275                         if (acpi)
 276                                 seq_puts(s, ", ");
 277                 }
 278                 if (acpi)
 279                         seq_puts(s, "ACPI");
 280                 seq_puts(s, "]");
 281         }
 282 }
 283
 284 static const struct pinctrl_ops intel_pinctrl_ops = {
 285         .get_groups_count = intel_get_groups_count,
 286         .get_group_name = intel_get_group_name,
 287         .get_group_pins = intel_get_group_pins,
 288         .pin_dbg_show = intel_pin_dbg_show,
 289 };
 290
 291 static int intel_get_functions_count(struct pinctrl_dev *pctldev)
 292 {
 293         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 294
 295         return pctrl->soc->nfunctions;
 296 }
 297
 298 static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
 299                                            unsigned function)
 300 {
 301         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 302
 303         return pctrl->soc->functions[function].name;
 304 }
 305
 306 static int intel_get_function_groups(struct pinctrl_dev *pctldev,
 307                                      unsigned function,
 308                                      const char * const **groups,
 309                                      unsigned * const ngroups)
 310 {
 311         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 312
 313         *groups = pctrl->soc->functions[function].groups;
 314         *ngroups = pctrl->soc->functions[function].ngroups;
 315         return 0;
 316 }
 317
 318 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
 319                                 unsigned group)
 320 {
 321         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 322         const struct intel_pingroup *grp = &pctrl->soc->groups[group];
 323         unsigned long flags;
 324         int i;
 325
 326         spin_lock_irqsave(&pctrl->lock, flags);
 327
 328         /*
 329          * All pins in the groups needs to be accessible and writable
 330          * before we can enable the mux for this group.
 331          */
 332         for (i = 0; i < grp->npins; i++) {
 333                 if (!intel_pad_usable(pctrl, grp->pins[i])) {
 334                         spin_unlock_irqrestore(&pctrl->lock, flags);
 335                         return -EBUSY;
 336                 }
 337         }
 338
 339         /* Now enable the mux setting for each pin in the group */
 340         for (i = 0; i < grp->npins; i++) {
 341                 void __iomem *padcfg0;
 342                 u32 value;
 343
 344                 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
 345                 value = readl(padcfg0);
 346
 347                 value &= ~PADCFG0_PMODE_MASK;
 348                 value |= grp->mode << PADCFG0_PMODE_SHIFT;
 349
 350                 writel(value, padcfg0);
 351         }
 352
 353         spin_unlock_irqrestore(&pctrl->lock, flags);
 354
 355         return 0;
 356 }
 357
 358 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
 359                                      struct pinctrl_gpio_range *range,
 360                                      unsigned pin)
 361 {
 362         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 363         void __iomem *padcfg0;
 364         unsigned long flags;
 365         u32 value;
 366
 367         spin_lock_irqsave(&pctrl->lock, flags);
 368
 369         if (!intel_pad_usable(pctrl, pin)) {
 370                 spin_unlock_irqrestore(&pctrl->lock, flags);
 371                 return -EBUSY;
 372         }
 373
 374         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 375         /* Put the pad into GPIO mode */
 376         value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
 377         /* Disable SCI/SMI/NMI generation */
 378         value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
 379         value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
 380         /* Disable TX buffer and enable RX (this will be input) */
 381         value &= ~PADCFG0_GPIORXDIS;
 382         value |= PADCFG0_GPIOTXDIS;
 383         writel(value, padcfg0);
 384
 385         spin_unlock_irqrestore(&pctrl->lock, flags);
 386
 387         return 0;
 388 }
 389
 390 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
 391                                     struct pinctrl_gpio_range *range,
 392                                     unsigned pin, bool input)
 393 {
 394         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 395         void __iomem *padcfg0;
 396         unsigned long flags;
 397         u32 value;
 398
 399         spin_lock_irqsave(&pctrl->lock, flags);
 400
 401         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 402
 403         value = readl(padcfg0);
 404         if (input)
 405                 value |= PADCFG0_GPIOTXDIS;
 406         else
 407                 value &= ~PADCFG0_GPIOTXDIS;
 408         writel(value, padcfg0);
 409
 410         spin_unlock_irqrestore(&pctrl->lock, flags);
 411
 412         return 0;
 413 }
 414
 415 static const struct pinmux_ops intel_pinmux_ops = {
 416         .get_functions_count = intel_get_functions_count,
 417         .get_function_name = intel_get_function_name,
 418         .get_function_groups = intel_get_function_groups,
 419         .set_mux = intel_pinmux_set_mux,
 420         .gpio_request_enable = intel_gpio_request_enable,
 421         .gpio_set_direction = intel_gpio_set_direction,
 422 };
 423
 424 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin,
 425                             unsigned long *config)
 426 {
 427         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 428         enum pin_config_param param = pinconf_to_config_param(*config);
 429         u32 value, term;
 430         u16 arg = 0;
 431
 432         if (!intel_pad_owned_by_host(pctrl, pin))
 433                 return -ENOTSUPP;
 434
 435         value = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
 436         term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
 437
 438         switch (param) {
 439         case PIN_CONFIG_BIAS_DISABLE:
 440                 if (term)
 441                         return -EINVAL;
 442                 break;
 443
 444         case PIN_CONFIG_BIAS_PULL_UP:
 445                 if (!term || !(value & PADCFG1_TERM_UP))
 446                         return -EINVAL;
 447
 448                 switch (term) {
 449                 case PADCFG1_TERM_1K:
 450                         arg = 1000;
 451                         break;
 452                 case PADCFG1_TERM_2K:
 453                         arg = 2000;
 454                         break;
 455                 case PADCFG1_TERM_5K:
 456                         arg = 5000;
 457                         break;
 458                 case PADCFG1_TERM_20K:
 459                         arg = 20000;
 460                         break;
 461                 }
 462
 463                 break;
 464
 465         case PIN_CONFIG_BIAS_PULL_DOWN:
 466                 if (!term || value & PADCFG1_TERM_UP)
 467                         return -EINVAL;
 468
 469                 switch (term) {
 470                 case PADCFG1_TERM_5K:
 471                         arg = 5000;
 472                         break;
 473                 case PADCFG1_TERM_20K:
 474                         arg = 20000;
 475                         break;
 476                 }
 477
 478                 break;
 479
 480         default:
 481                 return -ENOTSUPP;
 482         }
 483
 484         *config = pinconf_to_config_packed(param, arg);
 485         return 0;
 486 }
 487
 488 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin,
 489                                  unsigned long config)
 490 {
 491         unsigned param = pinconf_to_config_param(config);
 492         unsigned arg = pinconf_to_config_argument(config);
 493         void __iomem *padcfg1;
 494         unsigned long flags;
 495         int ret = 0;
 496         u32 value;
 497
 498         spin_lock_irqsave(&pctrl->lock, flags);
 499
 500         padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
 501         value = readl(padcfg1);
 502
 503         switch (param) {
 504         case PIN_CONFIG_BIAS_DISABLE:
 505                 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
 506                 break;
 507
 508         case PIN_CONFIG_BIAS_PULL_UP:
 509                 value &= ~PADCFG1_TERM_MASK;
 510
 511                 value |= PADCFG1_TERM_UP;
 512
 513                 switch (arg) {
 514                 case 20000:
 515                         value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
 516                         break;
 517                 case 5000:
 518                         value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
 519                         break;
 520                 case 2000:
 521                         value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT;
 522                         break;
 523                 case 1000:
 524                         value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
 525                         break;
 526                 default:
 527                         ret = -EINVAL;
 528                 }
 529
 530                 break;
 531
 532         case PIN_CONFIG_BIAS_PULL_DOWN:
 533                 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
 534
 535                 switch (arg) {
 536                 case 20000:
 537                         value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
 538                         break;
 539                 case 5000:
 540                         value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
 541                         break;
 542                 default:
 543                         ret = -EINVAL;
 544                 }
 545
 546                 break;
 547         }
 548
 549         if (!ret)
 550                 writel(value, padcfg1);
 551
 552         spin_unlock_irqrestore(&pctrl->lock, flags);
 553
 554         return ret;
 555 }
 556
 557 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin,
 558                           unsigned long *configs, unsigned nconfigs)
 559 {
 560         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 561         int i, ret;
 562
 563         if (!intel_pad_usable(pctrl, pin))
 564                 return -ENOTSUPP;
 565
 566         for (i = 0; i < nconfigs; i++) {
 567                 switch (pinconf_to_config_param(configs[i])) {
 568                 case PIN_CONFIG_BIAS_DISABLE:
 569                 case PIN_CONFIG_BIAS_PULL_UP:
 570                 case PIN_CONFIG_BIAS_PULL_DOWN:
 571                         ret = intel_config_set_pull(pctrl, pin, configs[i]);
 572                         if (ret)
 573                                 return ret;
 574                         break;
 575
 576                 default:
 577                         return -ENOTSUPP;
 578                 }
 579         }
 580
 581         return 0;
 582 }
 583
 584 static const struct pinconf_ops intel_pinconf_ops = {
 585         .is_generic = true,
 586         .pin_config_get = intel_config_get,
 587         .pin_config_set = intel_config_set,
 588 };
 589
 590 static const struct pinctrl_desc intel_pinctrl_desc = {
 591         .pctlops = &intel_pinctrl_ops,
 592         .pmxops = &intel_pinmux_ops,
 593         .confops = &intel_pinconf_ops,
 594         .owner = THIS_MODULE,
 595 };
 596
 597 static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
 598 {
 599         struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(chip);
 600         void __iomem *reg;
 601
 602         reg = intel_get_padcfg(pctrl, offset, PADCFG0);
 603         if (!reg)
 604                 return -EINVAL;
 605
 606         return !!(readl(reg) & PADCFG0_GPIORXSTATE);
 607 }
 608
 609 static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 610 {
 611         struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(chip);
 612         void __iomem *reg;
 613
 614         reg = intel_get_padcfg(pctrl, offset, PADCFG0);
 615         if (reg) {
 616                 unsigned long flags;
 617                 u32 padcfg0;
 618
 619                 spin_lock_irqsave(&pctrl->lock, flags);
 620                 padcfg0 = readl(reg);
 621                 if (value)
 622                         padcfg0 |= PADCFG0_GPIOTXSTATE;
 623                 else
 624                         padcfg0 &= ~PADCFG0_GPIOTXSTATE;
 625                 writel(padcfg0, reg);
 626                 spin_unlock_irqrestore(&pctrl->lock, flags);
 627         }
 628 }
 629
 630 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 631 {
 632         return pinctrl_gpio_direction_input(chip->base + offset);
 633 }
 634
 635 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
 636                                        int value)
 637 {
 638         intel_gpio_set(chip, offset, value);
 639         return pinctrl_gpio_direction_output(chip->base + offset);
 640 }
 641
 642 static const struct gpio_chip intel_gpio_chip = {
 643         .owner = THIS_MODULE,
 644         .request = gpiochip_generic_request,
 645         .free = gpiochip_generic_free,
 646         .direction_input = intel_gpio_direction_input,
 647         .direction_output = intel_gpio_direction_output,
 648         .get = intel_gpio_get,
 649         .set = intel_gpio_set,
 650 };
 651
 652 static void intel_gpio_irq_ack(struct irq_data *d)
 653 {
 654         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 655         struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc);
 656         const struct intel_community *community;
 657         unsigned pin = irqd_to_hwirq(d);
 658
 659         spin_lock(&pctrl->lock);
 660
 661         community = intel_get_community(pctrl, pin);
 662         if (community) {
 663                 unsigned padno = pin_to_padno(community, pin);
 664                 unsigned gpp_offset = padno % community->gpp_size;
 665                 unsigned gpp = padno / community->gpp_size;
 666
 667                 writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);
 668         }
 669
 670         spin_unlock(&pctrl->lock);
 671 }
 672
 673 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
 674 {
 675         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 676         struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc);
 677         const struct intel_community *community;
 678         unsigned pin = irqd_to_hwirq(d);
 679         unsigned long flags;
 680
 681         spin_lock_irqsave(&pctrl->lock, flags);
 682
 683         community = intel_get_community(pctrl, pin);
 684         if (community) {
 685                 unsigned padno = pin_to_padno(community, pin);
 686                 unsigned gpp_offset = padno % community->gpp_size;
 687                 unsigned gpp = padno / community->gpp_size;
 688                 void __iomem *reg;
 689                 u32 value;
 690
 691                 reg = community->regs + community->ie_offset + gpp * 4;
 692                 value = readl(reg);
 693                 if (mask)
 694                         value &= ~BIT(gpp_offset);
 695                 else
 696                         value |= BIT(gpp_offset);
 697                 writel(value, reg);
 698         }
 699
 700         spin_unlock_irqrestore(&pctrl->lock, flags);
 701 }
 702
 703 static void intel_gpio_irq_mask(struct irq_data *d)
 704 {
 705         intel_gpio_irq_mask_unmask(d, true);
 706 }
 707
 708 static void intel_gpio_irq_unmask(struct irq_data *d)
 709 {
 710         intel_gpio_irq_mask_unmask(d, false);
 711 }
 712
 713 static int intel_gpio_irq_type(struct irq_data *d, unsigned type)
 714 {
 715         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 716         struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc);
 717         unsigned pin = irqd_to_hwirq(d);
 718         unsigned long flags;
 719         void __iomem *reg;
 720         u32 value;
 721
 722         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 723         if (!reg)
 724                 return -EINVAL;
 725
 726         /*
 727          * If the pin is in ACPI mode it is still usable as a GPIO but it
 728          * cannot be used as IRQ because GPI_IS status bit will not be
 729          * updated by the host controller hardware.
 730          */
 731         if (intel_pad_acpi_mode(pctrl, pin)) {
 732                 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
 733                 return -EPERM;
 734         }
 735
 736         spin_lock_irqsave(&pctrl->lock, flags);
 737
 738         value = readl(reg);
 739
 740         value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
 741
 742         if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
 743                 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
 744         } else if (type & IRQ_TYPE_EDGE_FALLING) {
 745                 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
 746                 value |= PADCFG0_RXINV;
 747         } else if (type & IRQ_TYPE_EDGE_RISING) {
 748                 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
 749         } else if (type & IRQ_TYPE_LEVEL_LOW) {
 750                 value |= PADCFG0_RXINV;
 751         } else {
 752                 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
 753         }
 754
 755         writel(value, reg);
 756
 757         if (type & IRQ_TYPE_EDGE_BOTH)
 758                 irq_set_handler_locked(d, handle_edge_irq);
 759         else if (type & IRQ_TYPE_LEVEL_MASK)
 760                 irq_set_handler_locked(d, handle_level_irq);
 761
 762         spin_unlock_irqrestore(&pctrl->lock, flags);
 763
 764         return 0;
 765 }
 766
 767 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
 768 {
 769         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 770         struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc);
 771         const struct intel_community *community;
 772         unsigned pin = irqd_to_hwirq(d);
 773         unsigned padno, gpp, gpp_offset;
 774         u32 gpe_en;
 775
 776         community = intel_get_community(pctrl, pin);
 777         if (!community)
 778                 return -EINVAL;
 779
 780         padno = pin_to_padno(community, pin);
 781         gpp = padno / community->gpp_size;
 782         gpp_offset = padno % community->gpp_size;
 783
 784         /* Clear the existing wake status */
 785         writel(BIT(gpp_offset), community->regs + GPI_GPE_STS + gpp * 4);
 786
 787         /*
 788          * The controller will generate wake when GPE of the corresponding
 789          * pad is enabled and it is not routed to SCI (GPIROUTSCI is not
 790          * set).
 791          */
 792         gpe_en = readl(community->regs + GPI_GPE_EN + gpp * 4);
 793         if (on)
 794                 gpe_en |= BIT(gpp_offset);
 795         else
 796                 gpe_en &= ~BIT(gpp_offset);
 797         writel(gpe_en, community->regs + GPI_GPE_EN + gpp * 4);
 798
 799         dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
 800         return 0;
 801 }
 802
 803 static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
 804         const struct intel_community *community)
 805 {
 806         struct gpio_chip *gc = &pctrl->chip;
 807         irqreturn_t ret = IRQ_NONE;
 808         int gpp;
 809
 810         for (gpp = 0; gpp < community->ngpps; gpp++) {
 811                 unsigned long pending, enabled, gpp_offset;
 812
 813                 pending = readl(community->regs + GPI_IS + gpp * 4);
 814                 enabled = readl(community->regs + community->ie_offset +
 815                                 gpp * 4);
 816
 817                 /* Only interrupts that are enabled */
 818                 pending &= enabled;
 819
 820                 for_each_set_bit(gpp_offset, &pending, community->gpp_size) {
 821                         unsigned padno, irq;
 822
 823                         /*
 824                          * The last group in community can have less pins
 825                          * than NPADS_IN_GPP.
 826                          */
 827                         padno = gpp_offset + gpp * community->gpp_size;
 828                         if (padno >= community->npins)
 829                                 break;
 830
 831                         irq = irq_find_mapping(gc->irqdomain,
 832                                                community->pin_base + padno);
 833                         generic_handle_irq(irq);
 834
 835                         ret |= IRQ_HANDLED;
 836                 }
 837         }
 838
 839         return ret;
 840 }
 841
 842 static irqreturn_t intel_gpio_irq(int irq, void *data)
 843 {
 844         const struct intel_community *community;
 845         struct intel_pinctrl *pctrl = data;
 846         irqreturn_t ret = IRQ_NONE;
 847         int i;
 848
 849         /* Need to check all communities for pending interrupts */
 850         for (i = 0; i < pctrl->ncommunities; i++) {
 851                 community = &pctrl->communities[i];
 852                 ret |= intel_gpio_community_irq_handler(pctrl, community);
 853         }
 854
 855         return ret;
 856 }
 857
 858 static struct irq_chip intel_gpio_irqchip = {
 859         .name = "intel-gpio",
 860         .irq_ack = intel_gpio_irq_ack,
 861         .irq_mask = intel_gpio_irq_mask,
 862         .irq_unmask = intel_gpio_irq_unmask,
 863         .irq_set_type = intel_gpio_irq_type,
 864         .irq_set_wake = intel_gpio_irq_wake,
 865 };
 866
 867 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
 868 {
 869         int ret;
 870
 871         pctrl->chip = intel_gpio_chip;
 872
 873         pctrl->chip.ngpio = pctrl->soc->npins;
 874         pctrl->chip.label = dev_name(pctrl->dev);
 875         pctrl->chip.dev = pctrl->dev;
 876         pctrl->chip.base = -1;
 877
 878         ret = gpiochip_add(&pctrl->chip);
 879         if (ret) {
 880                 dev_err(pctrl->dev, "failed to register gpiochip\n");
 881                 return ret;
 882         }
 883
 884         ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
 885                                      0, 0, pctrl->soc->npins);
 886         if (ret) {
 887                 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
 888                 goto fail;
 889         }
 890
 891         /*
 892          * We need to request the interrupt here (instead of providing chip
 893          * to the irq directly) because on some platforms several GPIO
 894          * controllers share the same interrupt line.
 895          */
 896         ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq, IRQF_SHARED,
 897                                dev_name(pctrl->dev), pctrl);
 898         if (ret) {
 899                 dev_err(pctrl->dev, "failed to request interrupt\n");
 900                 goto fail;
 901         }
 902
 903         ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0,
 904                                    handle_simple_irq, IRQ_TYPE_NONE);
 905         if (ret) {
 906                 dev_err(pctrl->dev, "failed to add irqchip\n");
 907                 goto fail;
 908         }
 909
 910         gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq,
 911                                      NULL);
 912         return 0;
 913
 914 fail:
 915         gpiochip_remove(&pctrl->chip);
 916
 917         return ret;
 918 }
 919
 920 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
 921 {
 922 #ifdef CONFIG_PM_SLEEP
 923         const struct intel_pinctrl_soc_data *soc = pctrl->soc;
 924         struct intel_community_context *communities;
 925         struct intel_pad_context *pads;
 926         int i;
 927
 928         pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
 929         if (!pads)
 930                 return -ENOMEM;
 931
 932         communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
 933                                    sizeof(*communities), GFP_KERNEL);
 934         if (!communities)
 935                 return -ENOMEM;
 936
 937
 938         for (i = 0; i < pctrl->ncommunities; i++) {
 939                 struct intel_community *community = &pctrl->communities[i];
 940                 u32 *intmask;
 941
 942                 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
 943                                        sizeof(*intmask), GFP_KERNEL);
 944                 if (!intmask)
 945                         return -ENOMEM;
 946
 947                 communities[i].intmask = intmask;
 948         }
 949
 950         pctrl->context.pads = pads;
 951         pctrl->context.communities = communities;
 952 #endif
 953
 954         return 0;
 955 }
 956
 957 int intel_pinctrl_probe(struct platform_device *pdev,
 958                         const struct intel_pinctrl_soc_data *soc_data)
 959 {
 960         struct intel_pinctrl *pctrl;
 961         int i, ret, irq;
 962
 963         if (!soc_data)
 964                 return -EINVAL;
 965
 966         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
 967         if (!pctrl)
 968                 return -ENOMEM;
 969
 970         pctrl->dev = &pdev->dev;
 971         pctrl->soc = soc_data;
 972         spin_lock_init(&pctrl->lock);
 973
 974         /*
 975          * Make a copy of the communities which we can use to hold pointers
 976          * to the registers.
 977          */
 978         pctrl->ncommunities = pctrl->soc->ncommunities;
 979         pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
 980                                   sizeof(*pctrl->communities), GFP_KERNEL);
 981         if (!pctrl->communities)
 982                 return -ENOMEM;
 983
 984         for (i = 0; i < pctrl->ncommunities; i++) {
 985                 struct intel_community *community = &pctrl->communities[i];
 986                 struct resource *res;
 987                 void __iomem *regs;
 988                 u32 padbar;
 989
 990                 *community = pctrl->soc->communities[i];
 991
 992                 res = platform_get_resource(pdev, IORESOURCE_MEM,
 993                                             community->barno);
 994                 regs = devm_ioremap_resource(&pdev->dev, res);
 995                 if (IS_ERR(regs))
 996                         return PTR_ERR(regs);
 997
 998                 /* Read offset of the pad configuration registers */
 999                 padbar = readl(regs + PADBAR);
1000
1001                 community->regs = regs;
1002                 community->pad_regs = regs + padbar;
1003                 community->ngpps = DIV_ROUND_UP(community->npins,
1004                                                 community->gpp_size);
1005         }
1006
1007         irq = platform_get_irq(pdev, 0);
1008         if (irq < 0) {
1009                 dev_err(&pdev->dev, "failed to get interrupt number\n");
1010                 return irq;
1011         }
1012
1013         ret = intel_pinctrl_pm_init(pctrl);
1014         if (ret)
1015                 return ret;
1016
1017         pctrl->pctldesc = intel_pinctrl_desc;
1018         pctrl->pctldesc.name = dev_name(&pdev->dev);
1019         pctrl->pctldesc.pins = pctrl->soc->pins;
1020         pctrl->pctldesc.npins = pctrl->soc->npins;
1021
1022         pctrl->pctldev = pinctrl_register(&pctrl->pctldesc, &pdev->dev, pctrl);
1023         if (IS_ERR(pctrl->pctldev)) {
1024                 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1025                 return PTR_ERR(pctrl->pctldev);
1026         }
1027
1028         ret = intel_gpio_probe(pctrl, irq);
1029         if (ret) {
1030                 pinctrl_unregister(pctrl->pctldev);
1031                 return ret;
1032         }
1033
1034         platform_set_drvdata(pdev, pctrl);
1035
1036         return 0;
1037 }
1038 EXPORT_SYMBOL_GPL(intel_pinctrl_probe);
1039
1040 int intel_pinctrl_remove(struct platform_device *pdev)
1041 {
1042         struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1043
1044         gpiochip_remove(&pctrl->chip);
1045         pinctrl_unregister(pctrl->pctldev);
1046
1047         return 0;
1048 }
1049 EXPORT_SYMBOL_GPL(intel_pinctrl_remove);
1050
1051 #ifdef CONFIG_PM_SLEEP
1052 int intel_pinctrl_suspend(struct device *dev)
1053 {
1054         struct platform_device *pdev = to_platform_device(dev);
1055         struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1056         struct intel_community_context *communities;
1057         struct intel_pad_context *pads;
1058         int i;
1059
1060         pads = pctrl->context.pads;
1061         for (i = 0; i < pctrl->soc->npins; i++) {
1062                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1063                 u32 val;
1064
1065                 if (!intel_pad_usable(pctrl, desc->number))
1066                         continue;
1067
1068                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1069                 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1070                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1071                 pads[i].padcfg1 = val;
1072         }
1073
1074         communities = pctrl->context.communities;
1075         for (i = 0; i < pctrl->ncommunities; i++) {
1076                 struct intel_community *community = &pctrl->communities[i];
1077                 void __iomem *base;
1078                 unsigned gpp;
1079
1080                 base = community->regs + community->ie_offset;
1081                 for (gpp = 0; gpp < community->ngpps; gpp++)
1082                         communities[i].intmask[gpp] = readl(base + gpp * 4);
1083         }
1084
1085         return 0;
1086 }
1087 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend);
1088
1089 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1090 {
1091         size_t i;
1092
1093         for (i = 0; i < pctrl->ncommunities; i++) {
1094                 const struct intel_community *community;
1095                 void __iomem *base;
1096                 unsigned gpp;
1097
1098                 community = &pctrl->communities[i];
1099                 base = community->regs;
1100
1101                 for (gpp = 0; gpp < community->ngpps; gpp++) {
1102                         /* Mask and clear all interrupts */
1103                         writel(0, base + community->ie_offset + gpp * 4);
1104                         writel(0xffff, base + GPI_IS + gpp * 4);
1105                 }
1106         }
1107 }
1108
1109 int intel_pinctrl_resume(struct device *dev)
1110 {
1111         struct platform_device *pdev = to_platform_device(dev);
1112         struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1113         const struct intel_community_context *communities;
1114         const struct intel_pad_context *pads;
1115         int i;
1116
1117         /* Mask all interrupts */
1118         intel_gpio_irq_init(pctrl);
1119
1120         pads = pctrl->context.pads;
1121         for (i = 0; i < pctrl->soc->npins; i++) {
1122                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1123                 void __iomem *padcfg;
1124                 u32 val;
1125
1126                 if (!intel_pad_usable(pctrl, desc->number))
1127                         continue;
1128
1129                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0);
1130                 val = readl(padcfg) & ~PADCFG0_GPIORXSTATE;
1131                 if (val != pads[i].padcfg0) {
1132                         writel(pads[i].padcfg0, padcfg);
1133                         dev_dbg(dev, "restored pin %u padcfg0 %#08x\n",
1134                                 desc->number, readl(padcfg));
1135                 }
1136
1137                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1);
1138                 val = readl(padcfg);
1139                 if (val != pads[i].padcfg1) {
1140                         writel(pads[i].padcfg1, padcfg);
1141                         dev_dbg(dev, "restored pin %u padcfg1 %#08x\n",
1142                                 desc->number, readl(padcfg));
1143                 }
1144         }
1145
1146         communities = pctrl->context.communities;
1147         for (i = 0; i < pctrl->ncommunities; i++) {
1148                 struct intel_community *community = &pctrl->communities[i];
1149                 void __iomem *base;
1150                 unsigned gpp;
1151
1152                 base = community->regs + community->ie_offset;
1153                 for (gpp = 0; gpp < community->ngpps; gpp++) {
1154                         writel(communities[i].intmask[gpp], base + gpp * 4);
1155                         dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp,
1156                                 readl(base + gpp * 4));
1157                 }
1158         }
1159
1160         return 0;
1161 }
1162 EXPORT_SYMBOL_GPL(intel_pinctrl_resume);
1163 #endif
1164
1165 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1166 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1167 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1168 MODULE_LICENSE("GPL v2");