drivers/phy/rockchip/phy-rockchip-inno-hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (c) 2017 Rockchip Electronics Co. Ltd.
   4  *
   5  * Author: Zheng Yang <zhengyang@rock-chips.com>
   6  *         Heiko Stuebner <heiko@sntech.de>
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/clk-provider.h>
  11 #include <linux/delay.h>
  12 #include <linux/io.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/nvmem-consumer.h>
  17 #include <linux/of.h>
  18 #include <linux/of_device.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/regmap.h>
  21 #include <linux/phy/phy.h>
  22 #include <linux/slab.h>
  23
  24 #define UPDATE(x, h, l)         (((x) << (l)) & GENMASK((h), (l)))
  25
  26 /* REG: 0x00 */
  27 #define RK3228_PRE_PLL_REFCLK_SEL_PCLK                  BIT(0)
  28 /* REG: 0x01 */
  29 #define RK3228_BYPASS_RXSENSE_EN                        BIT(2)
  30 #define RK3228_BYPASS_PWRON_EN                          BIT(1)
  31 #define RK3228_BYPASS_PLLPD_EN                          BIT(0)
  32 /* REG: 0x02 */
  33 #define RK3228_BYPASS_PDATA_EN                          BIT(4)
  34 #define RK3228_PDATAEN_DISABLE                          BIT(0)
  35 /* REG: 0x03 */
  36 #define RK3228_BYPASS_AUTO_TERM_RES_CAL                 BIT(7)
  37 #define RK3228_AUTO_TERM_RES_CAL_SPEED_14_8(x)          UPDATE(x, 6, 0)
  38 /* REG: 0x04 */
  39 #define RK3228_AUTO_TERM_RES_CAL_SPEED_7_0(x)           UPDATE(x, 7, 0)
  40 /* REG: 0xaa */
  41 #define RK3228_POST_PLL_CTRL_MANUAL                     BIT(0)
  42 /* REG: 0xe0 */
  43 #define RK3228_POST_PLL_POWER_DOWN                      BIT(5)
  44 #define RK3228_PRE_PLL_POWER_DOWN                       BIT(4)
  45 #define RK3228_RXSENSE_CLK_CH_ENABLE                    BIT(3)
  46 #define RK3228_RXSENSE_DATA_CH2_ENABLE                  BIT(2)
  47 #define RK3228_RXSENSE_DATA_CH1_ENABLE                  BIT(1)
  48 #define RK3228_RXSENSE_DATA_CH0_ENABLE                  BIT(0)
  49 /* REG: 0xe1 */
  50 #define RK3228_BANDGAP_ENABLE                           BIT(4)
  51 #define RK3228_TMDS_DRIVER_ENABLE                       GENMASK(3, 0)
  52 /* REG: 0xe2 */
  53 #define RK3228_PRE_PLL_FB_DIV_8_MASK                    BIT(7)
  54 #define RK3228_PRE_PLL_FB_DIV_8(x)                      UPDATE((x) >> 8, 7, 7)
  55 #define RK3228_PCLK_VCO_DIV_5_MASK                      BIT(5)
  56 #define RK3228_PCLK_VCO_DIV_5(x)                        UPDATE(x, 5, 5)
  57 #define RK3228_PRE_PLL_PRE_DIV_MASK                     GENMASK(4, 0)
  58 #define RK3228_PRE_PLL_PRE_DIV(x)                       UPDATE(x, 4, 0)
  59 /* REG: 0xe3 */
  60 #define RK3228_PRE_PLL_FB_DIV_7_0(x)                    UPDATE(x, 7, 0)
  61 /* REG: 0xe4 */
  62 #define RK3228_PRE_PLL_PCLK_DIV_B_MASK                  GENMASK(6, 5)
  63 #define RK3228_PRE_PLL_PCLK_DIV_B_SHIFT                 5
  64 #define RK3228_PRE_PLL_PCLK_DIV_B(x)                    UPDATE(x, 6, 5)
  65 #define RK3228_PRE_PLL_PCLK_DIV_A_MASK                  GENMASK(4, 0)
  66 #define RK3228_PRE_PLL_PCLK_DIV_A(x)                    UPDATE(x, 4, 0)
  67 /* REG: 0xe5 */
  68 #define RK3228_PRE_PLL_PCLK_DIV_C_MASK                  GENMASK(6, 5)
  69 #define RK3228_PRE_PLL_PCLK_DIV_C(x)                    UPDATE(x, 6, 5)
  70 #define RK3228_PRE_PLL_PCLK_DIV_D_MASK                  GENMASK(4, 0)
  71 #define RK3228_PRE_PLL_PCLK_DIV_D(x)                    UPDATE(x, 4, 0)
  72 /* REG: 0xe6 */
  73 #define RK3228_PRE_PLL_TMDSCLK_DIV_C_MASK               GENMASK(5, 4)
  74 #define RK3228_PRE_PLL_TMDSCLK_DIV_C(x)                 UPDATE(x, 5, 4)
  75 #define RK3228_PRE_PLL_TMDSCLK_DIV_A_MASK               GENMASK(3, 2)
  76 #define RK3228_PRE_PLL_TMDSCLK_DIV_A(x)                 UPDATE(x, 3, 2)
  77 #define RK3228_PRE_PLL_TMDSCLK_DIV_B_MASK               GENMASK(1, 0)
  78 #define RK3228_PRE_PLL_TMDSCLK_DIV_B(x)                 UPDATE(x, 1, 0)
  79 /* REG: 0xe8 */
  80 #define RK3228_PRE_PLL_LOCK_STATUS                      BIT(0)
  81 /* REG: 0xe9 */
  82 #define RK3228_POST_PLL_POST_DIV_ENABLE                 UPDATE(3, 7, 6)
  83 #define RK3228_POST_PLL_PRE_DIV_MASK                    GENMASK(4, 0)
  84 #define RK3228_POST_PLL_PRE_DIV(x)                      UPDATE(x, 4, 0)
  85 /* REG: 0xea */
  86 #define RK3228_POST_PLL_FB_DIV_7_0(x)                   UPDATE(x, 7, 0)
  87 /* REG: 0xeb */
  88 #define RK3228_POST_PLL_FB_DIV_8_MASK                   BIT(7)
  89 #define RK3228_POST_PLL_FB_DIV_8(x)                     UPDATE((x) >> 8, 7, 7)
  90 #define RK3228_POST_PLL_POST_DIV_MASK                   GENMASK(5, 4)
  91 #define RK3228_POST_PLL_POST_DIV(x)                     UPDATE(x, 5, 4)
  92 #define RK3228_POST_PLL_LOCK_STATUS                     BIT(0)
  93 /* REG: 0xee */
  94 #define RK3228_TMDS_CH_TA_ENABLE                        GENMASK(7, 4)
  95 /* REG: 0xef */
  96 #define RK3228_TMDS_CLK_CH_TA(x)                        UPDATE(x, 7, 6)
  97 #define RK3228_TMDS_DATA_CH2_TA(x)                      UPDATE(x, 5, 4)
  98 #define RK3228_TMDS_DATA_CH1_TA(x)                      UPDATE(x, 3, 2)
  99 #define RK3228_TMDS_DATA_CH0_TA(x)                      UPDATE(x, 1, 0)
 100 /* REG: 0xf0 */
 101 #define RK3228_TMDS_DATA_CH2_PRE_EMPHASIS_MASK          GENMASK(5, 4)
 102 #define RK3228_TMDS_DATA_CH2_PRE_EMPHASIS(x)            UPDATE(x, 5, 4)
 103 #define RK3228_TMDS_DATA_CH1_PRE_EMPHASIS_MASK          GENMASK(3, 2)
 104 #define RK3228_TMDS_DATA_CH1_PRE_EMPHASIS(x)            UPDATE(x, 3, 2)
 105 #define RK3228_TMDS_DATA_CH0_PRE_EMPHASIS_MASK          GENMASK(1, 0)
 106 #define RK3228_TMDS_DATA_CH0_PRE_EMPHASIS(x)            UPDATE(x, 1, 0)
 107 /* REG: 0xf1 */
 108 #define RK3228_TMDS_CLK_CH_OUTPUT_SWING(x)              UPDATE(x, 7, 4)
 109 #define RK3228_TMDS_DATA_CH2_OUTPUT_SWING(x)            UPDATE(x, 3, 0)
 110 /* REG: 0xf2 */
 111 #define RK3228_TMDS_DATA_CH1_OUTPUT_SWING(x)            UPDATE(x, 7, 4)
 112 #define RK3228_TMDS_DATA_CH0_OUTPUT_SWING(x)            UPDATE(x, 3, 0)
 113
 114 /* REG: 0x01 */
 115 #define RK3328_BYPASS_RXSENSE_EN                        BIT(2)
 116 #define RK3328_BYPASS_POWERON_EN                        BIT(1)
 117 #define RK3328_BYPASS_PLLPD_EN                          BIT(0)
 118 /* REG: 0x02 */
 119 #define RK3328_INT_POL_HIGH                             BIT(7)
 120 #define RK3328_BYPASS_PDATA_EN                          BIT(4)
 121 #define RK3328_PDATA_EN                                 BIT(0)
 122 /* REG:0x05 */
 123 #define RK3328_INT_TMDS_CLK(x)                          UPDATE(x, 7, 4)
 124 #define RK3328_INT_TMDS_D2(x)                           UPDATE(x, 3, 0)
 125 /* REG:0x07 */
 126 #define RK3328_INT_TMDS_D1(x)                           UPDATE(x, 7, 4)
 127 #define RK3328_INT_TMDS_D0(x)                           UPDATE(x, 3, 0)
 128 /* for all RK3328_INT_TMDS_*, ESD_DET as defined in 0xc8-0xcb */
 129 #define RK3328_INT_AGND_LOW_PULSE_LOCKED                BIT(3)
 130 #define RK3328_INT_RXSENSE_LOW_PULSE_LOCKED             BIT(2)
 131 #define RK3328_INT_VSS_AGND_ESD_DET                     BIT(1)
 132 #define RK3328_INT_AGND_VSS_ESD_DET                     BIT(0)
 133 /* REG: 0xa0 */
 134 #define RK3328_PCLK_VCO_DIV_5_MASK                      BIT(1)
 135 #define RK3328_PCLK_VCO_DIV_5(x)                        UPDATE(x, 1, 1)
 136 #define RK3328_PRE_PLL_POWER_DOWN                       BIT(0)
 137 /* REG: 0xa1 */
 138 #define RK3328_PRE_PLL_PRE_DIV_MASK                     GENMASK(5, 0)
 139 #define RK3328_PRE_PLL_PRE_DIV(x)                       UPDATE(x, 5, 0)
 140 /* REG: 0xa2 */
 141 /* unset means center spread */
 142 #define RK3328_SPREAD_SPECTRUM_MOD_DOWN                 BIT(7)
 143 #define RK3328_SPREAD_SPECTRUM_MOD_DISABLE              BIT(6)
 144 #define RK3328_PRE_PLL_FRAC_DIV_DISABLE                 UPDATE(3, 5, 4)
 145 #define RK3328_PRE_PLL_FB_DIV_11_8_MASK                 GENMASK(3, 0)
 146 #define RK3328_PRE_PLL_FB_DIV_11_8(x)                   UPDATE((x) >> 8, 3, 0)
 147 /* REG: 0xa3 */
 148 #define RK3328_PRE_PLL_FB_DIV_7_0(x)                    UPDATE(x, 7, 0)
 149 /* REG: 0xa4*/
 150 #define RK3328_PRE_PLL_TMDSCLK_DIV_C_MASK               GENMASK(1, 0)
 151 #define RK3328_PRE_PLL_TMDSCLK_DIV_C(x)                 UPDATE(x, 1, 0)
 152 #define RK3328_PRE_PLL_TMDSCLK_DIV_B_MASK               GENMASK(3, 2)
 153 #define RK3328_PRE_PLL_TMDSCLK_DIV_B(x)                 UPDATE(x, 3, 2)
 154 #define RK3328_PRE_PLL_TMDSCLK_DIV_A_MASK               GENMASK(5, 4)
 155 #define RK3328_PRE_PLL_TMDSCLK_DIV_A(x)                 UPDATE(x, 5, 4)
 156 /* REG: 0xa5 */
 157 #define RK3328_PRE_PLL_PCLK_DIV_B_SHIFT                 5
 158 #define RK3328_PRE_PLL_PCLK_DIV_B_MASK                  GENMASK(6, 5)
 159 #define RK3328_PRE_PLL_PCLK_DIV_B(x)                    UPDATE(x, 6, 5)
 160 #define RK3328_PRE_PLL_PCLK_DIV_A_MASK                  GENMASK(4, 0)
 161 #define RK3328_PRE_PLL_PCLK_DIV_A(x)                    UPDATE(x, 4, 0)
 162 /* REG: 0xa6 */
 163 #define RK3328_PRE_PLL_PCLK_DIV_C_SHIFT                 5
 164 #define RK3328_PRE_PLL_PCLK_DIV_C_MASK                  GENMASK(6, 5)
 165 #define RK3328_PRE_PLL_PCLK_DIV_C(x)                    UPDATE(x, 6, 5)
 166 #define RK3328_PRE_PLL_PCLK_DIV_D_MASK                  GENMASK(4, 0)
 167 #define RK3328_PRE_PLL_PCLK_DIV_D(x)                    UPDATE(x, 4, 0)
 168 /* REG: 0xa9 */
 169 #define RK3328_PRE_PLL_LOCK_STATUS                      BIT(0)
 170 /* REG: 0xaa */
 171 #define RK3328_POST_PLL_POST_DIV_ENABLE                 GENMASK(3, 2)
 172 #define RK3328_POST_PLL_REFCLK_SEL_TMDS                 BIT(1)
 173 #define RK3328_POST_PLL_POWER_DOWN                      BIT(0)
 174 /* REG:0xab */
 175 #define RK3328_POST_PLL_FB_DIV_8(x)                     UPDATE((x) >> 8, 7, 7)
 176 #define RK3328_POST_PLL_PRE_DIV(x)                      UPDATE(x, 4, 0)
 177 /* REG: 0xac */
 178 #define RK3328_POST_PLL_FB_DIV_7_0(x)                   UPDATE(x, 7, 0)
 179 /* REG: 0xad */
 180 #define RK3328_POST_PLL_POST_DIV_MASK                   GENMASK(1, 0)
 181 #define RK3328_POST_PLL_POST_DIV_2                      0x0
 182 #define RK3328_POST_PLL_POST_DIV_4                      0x1
 183 #define RK3328_POST_PLL_POST_DIV_8                      0x3
 184 /* REG: 0xaf */
 185 #define RK3328_POST_PLL_LOCK_STATUS                     BIT(0)
 186 /* REG: 0xb0 */
 187 #define RK3328_BANDGAP_ENABLE                           BIT(2)
 188 /* REG: 0xb2 */
 189 #define RK3328_TMDS_CLK_DRIVER_EN                       BIT(3)
 190 #define RK3328_TMDS_D2_DRIVER_EN                        BIT(2)
 191 #define RK3328_TMDS_D1_DRIVER_EN                        BIT(1)
 192 #define RK3328_TMDS_D0_DRIVER_EN                        BIT(0)
 193 #define RK3328_TMDS_DRIVER_ENABLE               (RK3328_TMDS_CLK_DRIVER_EN | \
 194                                                 RK3328_TMDS_D2_DRIVER_EN | \
 195                                                 RK3328_TMDS_D1_DRIVER_EN | \
 196                                                 RK3328_TMDS_D0_DRIVER_EN)
 197 /* REG:0xc5 */
 198 #define RK3328_BYPASS_TERM_RESISTOR_CALIB               BIT(7)
 199 #define RK3328_TERM_RESISTOR_CALIB_SPEED_14_8(x)        UPDATE((x) >> 8, 6, 0)
 200 /* REG:0xc6 */
 201 #define RK3328_TERM_RESISTOR_CALIB_SPEED_7_0(x)         UPDATE(x, 7, 0)
 202 /* REG:0xc7 */
 203 #define RK3328_TERM_RESISTOR_50                         UPDATE(0, 2, 1)
 204 #define RK3328_TERM_RESISTOR_62_5                       UPDATE(1, 2, 1)
 205 #define RK3328_TERM_RESISTOR_75                         UPDATE(2, 2, 1)
 206 #define RK3328_TERM_RESISTOR_100                        UPDATE(3, 2, 1)
 207 /* REG 0xc8 - 0xcb */
 208 #define RK3328_ESD_DETECT_MASK                          GENMASK(7, 6)
 209 #define RK3328_ESD_DETECT_340MV                         (0x0 << 6)
 210 #define RK3328_ESD_DETECT_280MV                         (0x1 << 6)
 211 #define RK3328_ESD_DETECT_260MV                         (0x2 << 6)
 212 #define RK3328_ESD_DETECT_240MV                         (0x3 << 6)
 213 /* resistors can be used in parallel */
 214 #define RK3328_TMDS_TERM_RESIST_MASK                    GENMASK(5, 0)
 215 #define RK3328_TMDS_TERM_RESIST_75                      BIT(5)
 216 #define RK3328_TMDS_TERM_RESIST_150                     BIT(4)
 217 #define RK3328_TMDS_TERM_RESIST_300                     BIT(3)
 218 #define RK3328_TMDS_TERM_RESIST_600                     BIT(2)
 219 #define RK3328_TMDS_TERM_RESIST_1000                    BIT(1)
 220 #define RK3328_TMDS_TERM_RESIST_2000                    BIT(0)
 221 /* REG: 0xd1 */
 222 #define RK3328_PRE_PLL_FRAC_DIV_23_16(x)                UPDATE((x) >> 16, 7, 0)
 223 /* REG: 0xd2 */
 224 #define RK3328_PRE_PLL_FRAC_DIV_15_8(x)                 UPDATE((x) >> 8, 7, 0)
 225 /* REG: 0xd3 */
 226 #define RK3328_PRE_PLL_FRAC_DIV_7_0(x)                  UPDATE(x, 7, 0)
 227
 228 struct inno_hdmi_phy_drv_data;
 229
 230 struct inno_hdmi_phy {
 231         struct device *dev;
 232         struct regmap *regmap;
 233         int irq;
 234
 235         struct phy *phy;
 236         struct clk *sysclk;
 237         struct clk *refoclk;
 238         struct clk *refpclk;
 239
 240         /* platform data */
 241         const struct inno_hdmi_phy_drv_data *plat_data;
 242         int chip_version;
 243
 244         /* clk provider */
 245         struct clk_hw hw;
 246         struct clk *phyclk;
 247         unsigned long pixclock;
 248 };
 249
 250 struct pre_pll_config {
 251         unsigned long pixclock;
 252         unsigned long tmdsclock;
 253         u8 prediv;
 254         u16 fbdiv;
 255         u8 tmds_div_a;
 256         u8 tmds_div_b;
 257         u8 tmds_div_c;
 258         u8 pclk_div_a;
 259         u8 pclk_div_b;
 260         u8 pclk_div_c;
 261         u8 pclk_div_d;
 262         u8 vco_div_5_en;
 263         u32 fracdiv;
 264 };
 265
 266 struct post_pll_config {
 267         unsigned long tmdsclock;
 268         u8 prediv;
 269         u16 fbdiv;
 270         u8 postdiv;
 271         u8 version;
 272 };
 273
 274 struct phy_config {
 275         unsigned long   tmdsclock;
 276         u8              regs[14];
 277 };
 278
 279 struct inno_hdmi_phy_ops {
 280         int (*init)(struct inno_hdmi_phy *inno);
 281         int (*power_on)(struct inno_hdmi_phy *inno,
 282                         const struct post_pll_config *cfg,
 283                         const struct phy_config *phy_cfg);
 284         void (*power_off)(struct inno_hdmi_phy *inno);
 285 };
 286
 287 struct inno_hdmi_phy_drv_data {
 288         const struct inno_hdmi_phy_ops  *ops;
 289         const struct clk_ops            *clk_ops;
 290         const struct phy_config         *phy_cfg_table;
 291 };
 292
 293 static const struct pre_pll_config pre_pll_cfg_table[] = {
 294         { 27000000,  27000000, 1,  90, 3, 2, 2, 10, 3, 3, 4, 0, 0},
 295         { 27000000,  33750000, 1,  90, 1, 3, 3, 10, 3, 3, 4, 0, 0},
 296         { 40000000,  40000000, 1,  80, 2, 2, 2, 12, 2, 2, 2, 0, 0},
 297         { 59341000,  59341000, 1,  98, 3, 1, 2,  1, 3, 3, 4, 0, 0xE6AE6B},
 298         { 59400000,  59400000, 1,  99, 3, 1, 1,  1, 3, 3, 4, 0, 0},
 299         { 59341000,  74176250, 1,  98, 0, 3, 3,  1, 3, 3, 4, 0, 0xE6AE6B},
 300         { 59400000,  74250000, 1,  99, 1, 2, 2,  1, 3, 3, 4, 0, 0},
 301         { 74176000,  74176000, 1,  98, 1, 2, 2,  1, 2, 3, 4, 0, 0xE6AE6B},
 302         { 74250000,  74250000, 1,  99, 1, 2, 2,  1, 2, 3, 4, 0, 0},
 303         { 74176000,  92720000, 4, 494, 1, 2, 2,  1, 3, 3, 4, 0, 0x816817},
 304         { 74250000,  92812500, 4, 495, 1, 2, 2,  1, 3, 3, 4, 0, 0},
 305         {148352000, 148352000, 1,  98, 1, 1, 1,  1, 2, 2, 2, 0, 0xE6AE6B},
 306         {148500000, 148500000, 1,  99, 1, 1, 1,  1, 2, 2, 2, 0, 0},
 307         {148352000, 185440000, 4, 494, 0, 2, 2,  1, 3, 2, 2, 0, 0x816817},
 308         {148500000, 185625000, 4, 495, 0, 2, 2,  1, 3, 2, 2, 0, 0},
 309         {296703000, 296703000, 1,  98, 0, 1, 1,  1, 0, 2, 2, 0, 0xE6AE6B},
 310         {297000000, 297000000, 1,  99, 0, 1, 1,  1, 0, 2, 2, 0, 0},
 311         {296703000, 370878750, 4, 494, 1, 2, 0,  1, 3, 1, 1, 0, 0x816817},
 312         {297000000, 371250000, 4, 495, 1, 2, 0,  1, 3, 1, 1, 0, 0},
 313         {593407000, 296703500, 1,  98, 0, 1, 1,  1, 0, 2, 1, 0, 0xE6AE6B},
 314         {594000000, 297000000, 1,  99, 0, 1, 1,  1, 0, 2, 1, 0, 0},
 315         {593407000, 370879375, 4, 494, 1, 2, 0,  1, 3, 1, 1, 1, 0x816817},
 316         {594000000, 371250000, 4, 495, 1, 2, 0,  1, 3, 1, 1, 1, 0},
 317         {593407000, 593407000, 1,  98, 0, 2, 0,  1, 0, 1, 1, 0, 0xE6AE6B},
 318         {594000000, 594000000, 1,  99, 0, 2, 0,  1, 0, 1, 1, 0, 0},
 319         { /* sentinel */ }
 320 };
 321
 322 static const struct post_pll_config post_pll_cfg_table[] = {
 323         {33750000,  1, 40, 8, 1},
 324         {33750000,  1, 80, 8, 2},
 325         {74250000,  1, 40, 8, 1},
 326         {74250000, 18, 80, 8, 2},
 327         {148500000, 2, 40, 4, 3},
 328         {297000000, 4, 40, 2, 3},
 329         {594000000, 8, 40, 1, 3},
 330         { /* sentinel */ }
 331 };
 332
 333 /* phy tuning values for an undocumented set of registers */
 334 static const struct phy_config rk3228_phy_cfg[] = {
 335         {       165000000, {
 336                         0xaa, 0x00, 0x44, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00,
 337                         0x00, 0x00, 0x00, 0x00, 0x00,
 338                 },
 339         }, {
 340                 340000000, {
 341                         0xaa, 0x15, 0x6a, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00,
 342                         0x00, 0x00, 0x00, 0x00, 0x00,
 343                 },
 344         }, {
 345                 594000000, {
 346                         0xaa, 0x15, 0x7a, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00,
 347                         0x00, 0x00, 0x00, 0x00, 0x00,
 348                 },
 349         }, { /* sentinel */ },
 350 };
 351
 352 /* phy tuning values for an undocumented set of registers */
 353 static const struct phy_config rk3328_phy_cfg[] = {
 354         {       165000000, {
 355                         0x07, 0x0a, 0x0a, 0x0a, 0x00, 0x00, 0x08, 0x08, 0x08,
 356                         0x00, 0xac, 0xcc, 0xcc, 0xcc,
 357                 },
 358         }, {
 359                 340000000, {
 360                         0x0b, 0x0d, 0x0d, 0x0d, 0x07, 0x15, 0x08, 0x08, 0x08,
 361                         0x3f, 0xac, 0xcc, 0xcd, 0xdd,
 362                 },
 363         }, {
 364                 594000000, {
 365                         0x10, 0x1a, 0x1a, 0x1a, 0x07, 0x15, 0x08, 0x08, 0x08,
 366                         0x00, 0xac, 0xcc, 0xcc, 0xcc,
 367                 },
 368         }, { /* sentinel */ },
 369 };
 370
 371 static inline struct inno_hdmi_phy *to_inno_hdmi_phy(struct clk_hw *hw)
 372 {
 373         return container_of(hw, struct inno_hdmi_phy, hw);
 374 }
 375
 376 /*
 377  * The register description of the IP block does not use any distinct names
 378  * but instead the databook simply numbers the registers in one-increments.
 379  * As the registers are obviously 32bit sized, the inno_* functions
 380  * translate the databook register names to the actual registers addresses.
 381  */
 382 static inline void inno_write(struct inno_hdmi_phy *inno, u32 reg, u8 val)
 383 {
 384         regmap_write(inno->regmap, reg * 4, val);
 385 }
 386
 387 static inline u8 inno_read(struct inno_hdmi_phy *inno, u32 reg)
 388 {
 389         u32 val;
 390
 391         regmap_read(inno->regmap, reg * 4, &val);
 392
 393         return val;
 394 }
 395
 396 static inline void inno_update_bits(struct inno_hdmi_phy *inno, u8 reg,
 397                                     u8 mask, u8 val)
 398 {
 399         regmap_update_bits(inno->regmap, reg * 4, mask, val);
 400 }
 401
 402 #define inno_poll(inno, reg, val, cond, sleep_us, timeout_us) \
 403         regmap_read_poll_timeout((inno)->regmap, (reg) * 4, val, cond, \
 404                                  sleep_us, timeout_us)
 405
 406 static unsigned long inno_hdmi_phy_get_tmdsclk(struct inno_hdmi_phy *inno,
 407                                                unsigned long rate)
 408 {
 409         int bus_width = phy_get_bus_width(inno->phy);
 410
 411         switch (bus_width) {
 412         case 4:
 413         case 5:
 414         case 6:
 415         case 10:
 416         case 12:
 417         case 16:
 418                 return (u64)rate * bus_width / 8;
 419         default:
 420                 return rate;
 421         }
 422 }
 423
 424 static irqreturn_t inno_hdmi_phy_rk3328_hardirq(int irq, void *dev_id)
 425 {
 426         struct inno_hdmi_phy *inno = dev_id;
 427         int intr_stat1, intr_stat2, intr_stat3;
 428
 429         intr_stat1 = inno_read(inno, 0x04);
 430         intr_stat2 = inno_read(inno, 0x06);
 431         intr_stat3 = inno_read(inno, 0x08);
 432
 433         if (intr_stat1)
 434                 inno_write(inno, 0x04, intr_stat1);
 435         if (intr_stat2)
 436                 inno_write(inno, 0x06, intr_stat2);
 437         if (intr_stat3)
 438                 inno_write(inno, 0x08, intr_stat3);
 439
 440         if (intr_stat1 || intr_stat2 || intr_stat3)
 441                 return IRQ_WAKE_THREAD;
 442
 443         return IRQ_HANDLED;
 444 }
 445
 446 static irqreturn_t inno_hdmi_phy_rk3328_irq(int irq, void *dev_id)
 447 {
 448         struct inno_hdmi_phy *inno = dev_id;
 449
 450         inno_update_bits(inno, 0x02, RK3328_PDATA_EN, 0);
 451         usleep_range(10, 20);
 452         inno_update_bits(inno, 0x02, RK3328_PDATA_EN, RK3328_PDATA_EN);
 453
 454         return IRQ_HANDLED;
 455 }
 456
 457 static int inno_hdmi_phy_power_on(struct phy *phy)
 458 {
 459         struct inno_hdmi_phy *inno = phy_get_drvdata(phy);
 460         const struct post_pll_config *cfg = post_pll_cfg_table;
 461         const struct phy_config *phy_cfg = inno->plat_data->phy_cfg_table;
 462         unsigned long tmdsclock = inno_hdmi_phy_get_tmdsclk(inno,
 463                                                             inno->pixclock);
 464         int ret;
 465
 466         if (!tmdsclock) {
 467                 dev_err(inno->dev, "TMDS clock is zero!\n");
 468                 return -EINVAL;
 469         }
 470
 471         if (!inno->plat_data->ops->power_on)
 472                 return -EINVAL;
 473
 474         for (; cfg->tmdsclock != 0; cfg++)
 475                 if (tmdsclock <= cfg->tmdsclock &&
 476                     cfg->version & inno->chip_version)
 477                         break;
 478
 479         for (; phy_cfg->tmdsclock != 0; phy_cfg++)
 480                 if (tmdsclock <= phy_cfg->tmdsclock)
 481                         break;
 482
 483         if (cfg->tmdsclock == 0 || phy_cfg->tmdsclock == 0)
 484                 return -EINVAL;
 485
 486         dev_dbg(inno->dev, "Inno HDMI PHY Power On\n");
 487
 488         ret = clk_prepare_enable(inno->phyclk);
 489         if (ret)
 490                 return ret;
 491
 492         ret = inno->plat_data->ops->power_on(inno, cfg, phy_cfg);
 493         if (ret) {
 494                 clk_disable_unprepare(inno->phyclk);
 495                 return ret;
 496         }
 497
 498         return 0;
 499 }
 500
 501 static int inno_hdmi_phy_power_off(struct phy *phy)
 502 {
 503         struct inno_hdmi_phy *inno = phy_get_drvdata(phy);
 504
 505         if (!inno->plat_data->ops->power_off)
 506                 return -EINVAL;
 507
 508         inno->plat_data->ops->power_off(inno);
 509
 510         clk_disable_unprepare(inno->phyclk);
 511
 512         dev_dbg(inno->dev, "Inno HDMI PHY Power Off\n");
 513
 514         return 0;
 515 }
 516
 517 static const struct phy_ops inno_hdmi_phy_ops = {
 518         .owner = THIS_MODULE,
 519         .power_on = inno_hdmi_phy_power_on,
 520         .power_off = inno_hdmi_phy_power_off,
 521 };
 522
 523 static const
 524 struct pre_pll_config *inno_hdmi_phy_get_pre_pll_cfg(struct inno_hdmi_phy *inno,
 525                                                      unsigned long rate)
 526 {
 527         const struct pre_pll_config *cfg = pre_pll_cfg_table;
 528         unsigned long tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);
 529
 530         for (; cfg->pixclock != 0; cfg++)
 531                 if (cfg->pixclock == rate && cfg->tmdsclock == tmdsclock)
 532                         break;
 533
 534         if (cfg->pixclock == 0)
 535                 return ERR_PTR(-EINVAL);
 536
 537         return cfg;
 538 }
 539
 540 static int inno_hdmi_phy_rk3228_clk_is_prepared(struct clk_hw *hw)
 541 {
 542         struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
 543         u8 status;
 544
 545         status = inno_read(inno, 0xe0) & RK3228_PRE_PLL_POWER_DOWN;
 546         return status ? 0 : 1;
 547 }
 548
 549 static int inno_hdmi_phy_rk3228_clk_prepare(struct clk_hw *hw)
 550 {
 551         struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
 552
 553         inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN, 0);
 554         return 0;
 555 }
 556
 557 static void inno_hdmi_phy_rk3228_clk_unprepare(struct clk_hw *hw)
 558 {
 559         struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
 560
 561         inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN,
 562                          RK3228_PRE_PLL_POWER_DOWN);
 563 }
 564
 565 static
 566 unsigned long inno_hdmi_phy_rk3228_clk_recalc_rate(struct clk_hw *hw,
 567                                                    unsigned long parent_rate)
 568 {
 569         struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
 570         u8 nd, no_a, no_b, no_d;
 571         u64 vco;
 572         u16 nf;
 573
 574         nd = inno_read(inno, 0xe2) & RK3228_PRE_PLL_PRE_DIV_MASK;
 575         nf = (inno_read(inno, 0xe2) & RK3228_PRE_PLL_FB_DIV_8_MASK) << 1;
 576         nf |= inno_read(inno, 0xe3);
 577         vco = parent_rate * nf;
 578
 579         if (inno_read(inno, 0xe2) & RK3228_PCLK_VCO_DIV_5_MASK) {
 580                 do_div(vco, nd * 5);
 581         } else {
 582                 no_a = inno_read(inno, 0xe4) & RK3228_PRE_PLL_PCLK_DIV_A_MASK;
 583                 if (!no_a)
 584                         no_a = 1;
 585                 no_b = inno_read(inno, 0xe4) & RK3228_PRE_PLL_PCLK_DIV_B_MASK;
 586                 no_b >>= RK3228_PRE_PLL_PCLK_DIV_B_SHIFT;
 587                 no_b += 2;
 588                 no_d = inno_read(inno, 0xe5) & RK3228_PRE_PLL_PCLK_DIV_D_MASK;
 589
 590                 do_div(vco, (nd * (no_a == 1 ? no_b : no_a) * no_d * 2));
 591         }
 592
 593         inno->pixclock = vco;
 594
 595         dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock);
 596
 597         return vco;
 598 }
 599
 600 static long inno_hdmi_phy_rk3228_clk_round_rate(struct clk_hw *hw,
 601                                                 unsigned long rate,
 602                                                 unsigned long *parent_rate)
 603 {
 604         const struct pre_pll_config *cfg = pre_pll_cfg_table;
 605
 606         rate = (rate / 1000) * 1000;
 607
 608         for (; cfg->pixclock != 0; cfg++)
 609                 if (cfg->pixclock == rate && !cfg->fracdiv)
 610                         break;
 611
 612         if (cfg->pixclock == 0)
 613                 return -EINVAL;
 614
 615         return cfg->pixclock;
 616 }
 617
 618 static int inno_hdmi_phy_rk3228_clk_set_rate(struct clk_hw *hw,
 619                                              unsigned long rate,
 620                                              unsigned long parent_rate)
 621 {
 622         struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
 623         const struct pre_pll_config *cfg = pre_pll_cfg_table;
 624         unsigned long tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);
 625         u32 v;
 626         int ret;
 627
 628         dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n",
 629                 __func__, rate, tmdsclock);
 630
 631         cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate);
 632         if (IS_ERR(cfg))
 633                 return PTR_ERR(cfg);
 634
 635         /* Power down PRE-PLL */
 636         inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN,
 637                          RK3228_PRE_PLL_POWER_DOWN);
 638
 639         inno_update_bits(inno, 0xe2, RK3228_PRE_PLL_FB_DIV_8_MASK |
 640                          RK3228_PCLK_VCO_DIV_5_MASK |
 641                          RK3228_PRE_PLL_PRE_DIV_MASK,
 642                          RK3228_PRE_PLL_FB_DIV_8(cfg->fbdiv) |
 643                          RK3228_PCLK_VCO_DIV_5(cfg->vco_div_5_en) |
 644                          RK3228_PRE_PLL_PRE_DIV(cfg->prediv));
 645         inno_write(inno, 0xe3, RK3228_PRE_PLL_FB_DIV_7_0(cfg->fbdiv));
 646         inno_update_bits(inno, 0xe4, RK3228_PRE_PLL_PCLK_DIV_B_MASK |
 647                          RK3228_PRE_PLL_PCLK_DIV_A_MASK,
 648                          RK3228_PRE_PLL_PCLK_DIV_B(cfg->pclk_div_b) |
 649                          RK3228_PRE_PLL_PCLK_DIV_A(cfg->pclk_div_a));
 650         inno_update_bits(inno, 0xe5, RK3228_PRE_PLL_PCLK_DIV_C_MASK |
 651                          RK3228_PRE_PLL_PCLK_DIV_D_MASK,
 652                          RK3228_PRE_PLL_PCLK_DIV_C(cfg->pclk_div_c) |
 653                          RK3228_PRE_PLL_PCLK_DIV_D(cfg->pclk_div_d));
 654         inno_update_bits(inno, 0xe6, RK3228_PRE_PLL_TMDSCLK_DIV_C_MASK |
 655                          RK3228_PRE_PLL_TMDSCLK_DIV_A_MASK |
 656                          RK3228_PRE_PLL_TMDSCLK_DIV_B_MASK,
 657                          RK3228_PRE_PLL_TMDSCLK_DIV_C(cfg->tmds_div_c) |
 658                          RK3228_PRE_PLL_TMDSCLK_DIV_A(cfg->tmds_div_a) |
 659                          RK3228_PRE_PLL_TMDSCLK_DIV_B(cfg->tmds_div_b));
 660
 661         /* Power up PRE-PLL */
 662         inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN, 0);
 663
 664         /* Wait for Pre-PLL lock */
 665         ret = inno_poll(inno, 0xe8, v, v & RK3228_PRE_PLL_LOCK_STATUS,
 666                         100, 100000);
 667         if (ret) {
 668                 dev_err(inno->dev, "Pre-PLL locking failed\n");
 669                 return ret;
 670         }
 671
 672         inno->pixclock = rate;
 673
 674         return 0;
 675 }
 676
 677 static const struct clk_ops inno_hdmi_phy_rk3228_clk_ops = {
 678         .prepare = inno_hdmi_phy_rk3228_clk_prepare,
 679         .unprepare = inno_hdmi_phy_rk3228_clk_unprepare,
 680         .is_prepared = inno_hdmi_phy_rk3228_clk_is_prepared,
 681         .recalc_rate = inno_hdmi_phy_rk3228_clk_recalc_rate,
 682         .round_rate = inno_hdmi_phy_rk3228_clk_round_rate,
 683         .set_rate = inno_hdmi_phy_rk3228_clk_set_rate,
 684 };
 685
 686 static int inno_hdmi_phy_rk3328_clk_is_prepared(struct clk_hw *hw)
 687 {
 688         struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
 689         u8 status;
 690
 691         status = inno_read(inno, 0xa0) & RK3328_PRE_PLL_POWER_DOWN;
 692         return status ? 0 : 1;
 693 }
 694
 695 static int inno_hdmi_phy_rk3328_clk_prepare(struct clk_hw *hw)
 696 {
 697         struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
 698
 699         inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN, 0);
 700         return 0;
 701 }
 702
 703 static void inno_hdmi_phy_rk3328_clk_unprepare(struct clk_hw *hw)
 704 {
 705         struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
 706
 707         inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN,
 708                          RK3328_PRE_PLL_POWER_DOWN);
 709 }
 710
 711 static
 712 unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(struct clk_hw *hw,
 713                                                    unsigned long parent_rate)
 714 {
 715         struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
 716         unsigned long frac;
 717         u8 nd, no_a, no_b, no_c, no_d;
 718         u64 vco;
 719         u16 nf;
 720
 721         nd = inno_read(inno, 0xa1) & RK3328_PRE_PLL_PRE_DIV_MASK;
 722         nf = ((inno_read(inno, 0xa2) & RK3328_PRE_PLL_FB_DIV_11_8_MASK) << 8);
 723         nf |= inno_read(inno, 0xa3);
 724         vco = parent_rate * nf;
 725
 726         if (!(inno_read(inno, 0xa2) & RK3328_PRE_PLL_FRAC_DIV_DISABLE)) {
 727                 frac = inno_read(inno, 0xd3) |
 728                        (inno_read(inno, 0xd2) << 8) |
 729                        (inno_read(inno, 0xd1) << 16);
 730                 vco += DIV_ROUND_CLOSEST(parent_rate * frac, (1 << 24));
 731         }
 732
 733         if (inno_read(inno, 0xa0) & RK3328_PCLK_VCO_DIV_5_MASK) {
 734                 do_div(vco, nd * 5);
 735         } else {
 736                 no_a = inno_read(inno, 0xa5) & RK3328_PRE_PLL_PCLK_DIV_A_MASK;
 737                 no_b = inno_read(inno, 0xa5) & RK3328_PRE_PLL_PCLK_DIV_B_MASK;
 738                 no_b >>= RK3328_PRE_PLL_PCLK_DIV_B_SHIFT;
 739                 no_b += 2;
 740                 no_c = inno_read(inno, 0xa6) & RK3328_PRE_PLL_PCLK_DIV_C_MASK;
 741                 no_c >>= RK3328_PRE_PLL_PCLK_DIV_C_SHIFT;
 742                 no_c = 1 << no_c;
 743                 no_d = inno_read(inno, 0xa6) & RK3328_PRE_PLL_PCLK_DIV_D_MASK;
 744
 745                 do_div(vco, (nd * (no_a == 1 ? no_b : no_a) * no_d * 2));
 746         }
 747
 748         inno->pixclock = vco;
 749         dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock);
 750
 751         return vco;
 752 }
 753
 754 static long inno_hdmi_phy_rk3328_clk_round_rate(struct clk_hw *hw,
 755                                                 unsigned long rate,
 756                                                 unsigned long *parent_rate)
 757 {
 758         const struct pre_pll_config *cfg = pre_pll_cfg_table;
 759
 760         rate = (rate / 1000) * 1000;
 761
 762         for (; cfg->pixclock != 0; cfg++)
 763                 if (cfg->pixclock == rate)
 764                         break;
 765
 766         if (cfg->pixclock == 0)
 767                 return -EINVAL;
 768
 769         return cfg->pixclock;
 770 }
 771
 772 static int inno_hdmi_phy_rk3328_clk_set_rate(struct clk_hw *hw,
 773                                              unsigned long rate,
 774                                              unsigned long parent_rate)
 775 {
 776         struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
 777         const struct pre_pll_config *cfg = pre_pll_cfg_table;
 778         unsigned long tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);
 779         u32 val;
 780         int ret;
 781
 782         dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n",
 783                 __func__, rate, tmdsclock);
 784
 785         cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate);
 786         if (IS_ERR(cfg))
 787                 return PTR_ERR(cfg);
 788
 789         inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN,
 790                          RK3328_PRE_PLL_POWER_DOWN);
 791
 792         /* Configure pre-pll */
 793         inno_update_bits(inno, 0xa0, RK3228_PCLK_VCO_DIV_5_MASK,
 794                          RK3228_PCLK_VCO_DIV_5(cfg->vco_div_5_en));
 795         inno_write(inno, 0xa1, RK3328_PRE_PLL_PRE_DIV(cfg->prediv));
 796
 797         val = RK3328_SPREAD_SPECTRUM_MOD_DISABLE;
 798         if (!cfg->fracdiv)
 799                 val |= RK3328_PRE_PLL_FRAC_DIV_DISABLE;
 800         inno_write(inno, 0xa2, RK3328_PRE_PLL_FB_DIV_11_8(cfg->fbdiv) | val);
 801         inno_write(inno, 0xa3, RK3328_PRE_PLL_FB_DIV_7_0(cfg->fbdiv));
 802         inno_write(inno, 0xa5, RK3328_PRE_PLL_PCLK_DIV_A(cfg->pclk_div_a) |
 803                    RK3328_PRE_PLL_PCLK_DIV_B(cfg->pclk_div_b));
 804         inno_write(inno, 0xa6, RK3328_PRE_PLL_PCLK_DIV_C(cfg->pclk_div_c) |
 805                    RK3328_PRE_PLL_PCLK_DIV_D(cfg->pclk_div_d));
 806         inno_write(inno, 0xa4, RK3328_PRE_PLL_TMDSCLK_DIV_C(cfg->tmds_div_c) |
 807                    RK3328_PRE_PLL_TMDSCLK_DIV_A(cfg->tmds_div_a) |
 808                    RK3328_PRE_PLL_TMDSCLK_DIV_B(cfg->tmds_div_b));
 809         inno_write(inno, 0xd3, RK3328_PRE_PLL_FRAC_DIV_7_0(cfg->fracdiv));
 810         inno_write(inno, 0xd2, RK3328_PRE_PLL_FRAC_DIV_15_8(cfg->fracdiv));
 811         inno_write(inno, 0xd1, RK3328_PRE_PLL_FRAC_DIV_23_16(cfg->fracdiv));
 812
 813         inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN, 0);
 814
 815         /* Wait for Pre-PLL lock */
 816         ret = inno_poll(inno, 0xa9, val, val & RK3328_PRE_PLL_LOCK_STATUS,
 817                         1000, 10000);
 818         if (ret) {
 819                 dev_err(inno->dev, "Pre-PLL locking failed\n");
 820                 return ret;
 821         }
 822
 823         inno->pixclock = rate;
 824
 825         return 0;
 826 }
 827
 828 static const struct clk_ops inno_hdmi_phy_rk3328_clk_ops = {
 829         .prepare = inno_hdmi_phy_rk3328_clk_prepare,
 830         .unprepare = inno_hdmi_phy_rk3328_clk_unprepare,
 831         .is_prepared = inno_hdmi_phy_rk3328_clk_is_prepared,
 832         .recalc_rate = inno_hdmi_phy_rk3328_clk_recalc_rate,
 833         .round_rate = inno_hdmi_phy_rk3328_clk_round_rate,
 834         .set_rate = inno_hdmi_phy_rk3328_clk_set_rate,
 835 };
 836
 837 static int inno_hdmi_phy_clk_register(struct inno_hdmi_phy *inno)
 838 {
 839         struct device *dev = inno->dev;
 840         struct device_node *np = dev->of_node;
 841         struct clk_init_data init;
 842         const char *parent_name;
 843         int ret;
 844
 845         parent_name = __clk_get_name(inno->refoclk);
 846
 847         init.parent_names = &parent_name;
 848         init.num_parents = 1;
 849         init.flags = 0;
 850         init.name = "pin_hd20_pclk";
 851         init.ops = inno->plat_data->clk_ops;
 852
 853         /* optional override of the clock name */
 854         of_property_read_string(np, "clock-output-names", &init.name);
 855
 856         inno->hw.init = &init;
 857
 858         inno->phyclk = devm_clk_register(dev, &inno->hw);
 859         if (IS_ERR(inno->phyclk)) {
 860                 ret = PTR_ERR(inno->phyclk);
 861                 dev_err(dev, "failed to register clock: %d\n", ret);
 862                 return ret;
 863         }
 864
 865         ret = of_clk_add_provider(np, of_clk_src_simple_get, inno->phyclk);
 866         if (ret) {
 867                 dev_err(dev, "failed to register clock provider: %d\n", ret);
 868                 return ret;
 869         }
 870
 871         return 0;
 872 }
 873
 874 static int inno_hdmi_phy_rk3228_init(struct inno_hdmi_phy *inno)
 875 {
 876         /*
 877          * Use phy internal register control
 878          * rxsense/poweron/pllpd/pdataen signal.
 879          */
 880         inno_write(inno, 0x01, RK3228_BYPASS_RXSENSE_EN |
 881                    RK3228_BYPASS_PWRON_EN |
 882                    RK3228_BYPASS_PLLPD_EN);
 883         inno_update_bits(inno, 0x02, RK3228_BYPASS_PDATA_EN,
 884                          RK3228_BYPASS_PDATA_EN);
 885
 886         /* manual power down post-PLL */
 887         inno_update_bits(inno, 0xaa, RK3228_POST_PLL_CTRL_MANUAL,
 888                          RK3228_POST_PLL_CTRL_MANUAL);
 889
 890         inno->chip_version = 1;
 891
 892         return 0;
 893 }
 894
 895 static int
 896 inno_hdmi_phy_rk3228_power_on(struct inno_hdmi_phy *inno,
 897                               const struct post_pll_config *cfg,
 898                               const struct phy_config *phy_cfg)
 899 {
 900         int ret;
 901         u32 v;
 902
 903         inno_update_bits(inno, 0x02, RK3228_PDATAEN_DISABLE,
 904                          RK3228_PDATAEN_DISABLE);
 905         inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN |
 906                          RK3228_POST_PLL_POWER_DOWN,
 907                          RK3228_PRE_PLL_POWER_DOWN |
 908                          RK3228_POST_PLL_POWER_DOWN);
 909
 910         /* Post-PLL update */
 911         inno_update_bits(inno, 0xe9, RK3228_POST_PLL_PRE_DIV_MASK,
 912                          RK3228_POST_PLL_PRE_DIV(cfg->prediv));
 913         inno_update_bits(inno, 0xeb, RK3228_POST_PLL_FB_DIV_8_MASK,
 914                          RK3228_POST_PLL_FB_DIV_8(cfg->fbdiv));
 915         inno_write(inno, 0xea, RK3228_POST_PLL_FB_DIV_7_0(cfg->fbdiv));
 916
 917         if (cfg->postdiv == 1) {
 918                 inno_update_bits(inno, 0xe9, RK3228_POST_PLL_POST_DIV_ENABLE,
 919                                  0);
 920         } else {
 921                 int div = cfg->postdiv / 2 - 1;
 922
 923                 inno_update_bits(inno, 0xe9, RK3228_POST_PLL_POST_DIV_ENABLE,
 924                                  RK3228_POST_PLL_POST_DIV_ENABLE);
 925                 inno_update_bits(inno, 0xeb, RK3228_POST_PLL_POST_DIV_MASK,
 926                                  RK3228_POST_PLL_POST_DIV(div));
 927         }
 928
 929         for (v = 0; v < 4; v++)
 930                 inno_write(inno, 0xef + v, phy_cfg->regs[v]);
 931
 932         inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN |
 933                          RK3228_POST_PLL_POWER_DOWN, 0);
 934         inno_update_bits(inno, 0xe1, RK3228_BANDGAP_ENABLE,
 935                          RK3228_BANDGAP_ENABLE);
 936         inno_update_bits(inno, 0xe1, RK3228_TMDS_DRIVER_ENABLE,
 937                          RK3228_TMDS_DRIVER_ENABLE);
 938
 939         /* Wait for post PLL lock */
 940         ret = inno_poll(inno, 0xeb, v, v & RK3228_POST_PLL_LOCK_STATUS,
 941                         100, 100000);
 942         if (ret) {
 943                 dev_err(inno->dev, "Post-PLL locking failed\n");
 944                 return ret;
 945         }
 946
 947         if (cfg->tmdsclock > 340000000)
 948                 msleep(100);
 949
 950         inno_update_bits(inno, 0x02, RK3228_PDATAEN_DISABLE, 0);
 951         return 0;
 952 }
 953
 954 static void inno_hdmi_phy_rk3228_power_off(struct inno_hdmi_phy *inno)
 955 {
 956         inno_update_bits(inno, 0xe1, RK3228_TMDS_DRIVER_ENABLE, 0);
 957         inno_update_bits(inno, 0xe1, RK3228_BANDGAP_ENABLE, 0);
 958         inno_update_bits(inno, 0xe0, RK3228_POST_PLL_POWER_DOWN,
 959                          RK3228_POST_PLL_POWER_DOWN);
 960 }
 961
 962 static const struct inno_hdmi_phy_ops rk3228_hdmi_phy_ops = {
 963         .init = inno_hdmi_phy_rk3228_init,
 964         .power_on = inno_hdmi_phy_rk3228_power_on,
 965         .power_off = inno_hdmi_phy_rk3228_power_off,
 966 };
 967
 968 static int inno_hdmi_phy_rk3328_init(struct inno_hdmi_phy *inno)
 969 {
 970         struct nvmem_cell *cell;
 971         unsigned char *efuse_buf;
 972         size_t len;
 973
 974         /*
 975          * Use phy internal register control
 976          * rxsense/poweron/pllpd/pdataen signal.
 977          */
 978         inno_write(inno, 0x01, RK3328_BYPASS_RXSENSE_EN |
 979                    RK3328_BYPASS_POWERON_EN |
 980                    RK3328_BYPASS_PLLPD_EN);
 981         inno_write(inno, 0x02, RK3328_INT_POL_HIGH | RK3328_BYPASS_PDATA_EN |
 982                    RK3328_PDATA_EN);
 983
 984         /* Disable phy irq */
 985         inno_write(inno, 0x05, 0);
 986         inno_write(inno, 0x07, 0);
 987
 988         /* try to read the chip-version */
 989         inno->chip_version = 1;
 990         cell = nvmem_cell_get(inno->dev, "cpu-version");
 991         if (IS_ERR(cell)) {
 992                 if (PTR_ERR(cell) == -EPROBE_DEFER)
 993                         return -EPROBE_DEFER;
 994
 995                 return 0;
 996         }
 997
 998         efuse_buf = nvmem_cell_read(cell, &len);
 999         nvmem_cell_put(cell);
1000
1001         if (IS_ERR(efuse_buf))
1002                 return 0;
1003         if (len == 1)
1004                 inno->chip_version = efuse_buf[0] + 1;
1005         kfree(efuse_buf);
1006
1007         return 0;
1008 }
1009
1010 static int
1011 inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno,
1012                               const struct post_pll_config *cfg,
1013                               const struct phy_config *phy_cfg)
1014 {
1015         int ret;
1016         u32 v;
1017
1018         inno_update_bits(inno, 0x02, RK3328_PDATA_EN, 0);
1019         inno_update_bits(inno, 0xaa, RK3328_POST_PLL_POWER_DOWN,
1020                          RK3328_POST_PLL_POWER_DOWN);
1021
1022         inno_write(inno, 0xac, RK3328_POST_PLL_FB_DIV_7_0(cfg->fbdiv));
1023         if (cfg->postdiv == 1) {
1024                 inno_write(inno, 0xaa, RK3328_POST_PLL_REFCLK_SEL_TMDS);
1025                 inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) |
1026                            RK3328_POST_PLL_PRE_DIV(cfg->prediv));
1027         } else {
1028                 v = (cfg->postdiv / 2) - 1;
1029                 v &= RK3328_POST_PLL_POST_DIV_MASK;
1030                 inno_write(inno, 0xad, v);
1031                 inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) |
1032                            RK3328_POST_PLL_PRE_DIV(cfg->prediv));
1033                 inno_write(inno, 0xaa, RK3328_POST_PLL_POST_DIV_ENABLE |
1034                            RK3328_POST_PLL_REFCLK_SEL_TMDS);
1035         }
1036
1037         for (v = 0; v < 14; v++)
1038                 inno_write(inno, 0xb5 + v, phy_cfg->regs[v]);
1039
1040         /* set ESD detection threshold for TMDS CLK, D2, D1 and D0 */
1041         for (v = 0; v < 4; v++)
1042                 inno_update_bits(inno, 0xc8 + v, RK3328_ESD_DETECT_MASK,
1043                                  RK3328_ESD_DETECT_340MV);
1044
1045         if (phy_cfg->tmdsclock > 340000000) {
1046                 /* Set termination resistor to 100ohm */
1047                 v = clk_get_rate(inno->sysclk) / 100000;
1048                 inno_write(inno, 0xc5, RK3328_TERM_RESISTOR_CALIB_SPEED_14_8(v)
1049                            | RK3328_BYPASS_TERM_RESISTOR_CALIB);
1050                 inno_write(inno, 0xc6, RK3328_TERM_RESISTOR_CALIB_SPEED_7_0(v));
1051                 inno_write(inno, 0xc7, RK3328_TERM_RESISTOR_100);
1052                 inno_update_bits(inno, 0xc5,
1053                                  RK3328_BYPASS_TERM_RESISTOR_CALIB, 0);
1054         } else {
1055                 inno_write(inno, 0xc5, RK3328_BYPASS_TERM_RESISTOR_CALIB);
1056
1057                 /* clk termination resistor is 50ohm (parallel resistors) */
1058                 if (phy_cfg->tmdsclock > 165000000)
1059                         inno_update_bits(inno, 0xc8,
1060                                          RK3328_TMDS_TERM_RESIST_MASK,
1061                                          RK3328_TMDS_TERM_RESIST_75 |
1062                                          RK3328_TMDS_TERM_RESIST_150);
1063
1064                 /* data termination resistor for D2, D1 and D0 is 150ohm */
1065                 for (v = 0; v < 3; v++)
1066                         inno_update_bits(inno, 0xc9 + v,
1067                                          RK3328_TMDS_TERM_RESIST_MASK,
1068                                          RK3328_TMDS_TERM_RESIST_150);
1069         }
1070
1071         inno_update_bits(inno, 0xaa, RK3328_POST_PLL_POWER_DOWN, 0);
1072         inno_update_bits(inno, 0xb0, RK3328_BANDGAP_ENABLE,
1073                          RK3328_BANDGAP_ENABLE);
1074         inno_update_bits(inno, 0xb2, RK3328_TMDS_DRIVER_ENABLE,
1075                          RK3328_TMDS_DRIVER_ENABLE);
1076
1077         /* Wait for post PLL lock */
1078         ret = inno_poll(inno, 0xaf, v, v & RK3328_POST_PLL_LOCK_STATUS,
1079                         1000, 10000);
1080         if (ret) {
1081                 dev_err(inno->dev, "Post-PLL locking failed\n");
1082                 return ret;
1083         }
1084
1085         if (phy_cfg->tmdsclock > 340000000)
1086                 msleep(100);
1087
1088         inno_update_bits(inno, 0x02, RK3328_PDATA_EN, RK3328_PDATA_EN);
1089
1090         /* Enable PHY IRQ */
1091         inno_write(inno, 0x05, RK3328_INT_TMDS_CLK(RK3328_INT_VSS_AGND_ESD_DET)
1092                    | RK3328_INT_TMDS_D2(RK3328_INT_VSS_AGND_ESD_DET));
1093         inno_write(inno, 0x07, RK3328_INT_TMDS_D1(RK3328_INT_VSS_AGND_ESD_DET)
1094                    | RK3328_INT_TMDS_D0(RK3328_INT_VSS_AGND_ESD_DET));
1095         return 0;
1096 }
1097
1098 static void inno_hdmi_phy_rk3328_power_off(struct inno_hdmi_phy *inno)
1099 {
1100         inno_update_bits(inno, 0xb2, RK3328_TMDS_DRIVER_ENABLE, 0);
1101         inno_update_bits(inno, 0xb0, RK3328_BANDGAP_ENABLE, 0);
1102         inno_update_bits(inno, 0xaa, RK3328_POST_PLL_POWER_DOWN,
1103                          RK3328_POST_PLL_POWER_DOWN);
1104
1105         /* Disable PHY IRQ */
1106         inno_write(inno, 0x05, 0);
1107         inno_write(inno, 0x07, 0);
1108 }
1109
1110 static const struct inno_hdmi_phy_ops rk3328_hdmi_phy_ops = {
1111         .init = inno_hdmi_phy_rk3328_init,
1112         .power_on = inno_hdmi_phy_rk3328_power_on,
1113         .power_off = inno_hdmi_phy_rk3328_power_off,
1114 };
1115
1116 static const struct inno_hdmi_phy_drv_data rk3228_hdmi_phy_drv_data = {
1117         .ops = &rk3228_hdmi_phy_ops,
1118         .clk_ops = &inno_hdmi_phy_rk3228_clk_ops,
1119         .phy_cfg_table = rk3228_phy_cfg,
1120 };
1121
1122 static const struct inno_hdmi_phy_drv_data rk3328_hdmi_phy_drv_data = {
1123         .ops = &rk3328_hdmi_phy_ops,
1124         .clk_ops = &inno_hdmi_phy_rk3328_clk_ops,
1125         .phy_cfg_table = rk3328_phy_cfg,
1126 };
1127
1128 static const struct regmap_config inno_hdmi_phy_regmap_config = {
1129         .reg_bits = 32,
1130         .val_bits = 32,
1131         .reg_stride = 4,
1132         .max_register = 0x400,
1133 };
1134
1135 static void inno_hdmi_phy_action(void *data)
1136 {
1137         struct inno_hdmi_phy *inno = data;
1138
1139         clk_disable_unprepare(inno->refpclk);
1140         clk_disable_unprepare(inno->sysclk);
1141 }
1142
1143 static int inno_hdmi_phy_probe(struct platform_device *pdev)
1144 {
1145         struct inno_hdmi_phy *inno;
1146         struct phy_provider *phy_provider;
1147         struct resource *res;
1148         void __iomem *regs;
1149         int ret;
1150
1151         inno = devm_kzalloc(&pdev->dev, sizeof(*inno), GFP_KERNEL);
1152         if (!inno)
1153                 return -ENOMEM;
1154
1155         inno->dev = &pdev->dev;
1156
1157         inno->plat_data = of_device_get_match_data(inno->dev);
1158         if (!inno->plat_data || !inno->plat_data->ops)
1159                 return -EINVAL;
1160
1161         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1162         regs = devm_ioremap_resource(inno->dev, res);
1163         if (IS_ERR(regs))
1164                 return PTR_ERR(regs);
1165
1166         inno->sysclk = devm_clk_get(inno->dev, "sysclk");
1167         if (IS_ERR(inno->sysclk)) {
1168                 ret = PTR_ERR(inno->sysclk);
1169                 dev_err(inno->dev, "failed to get sysclk: %d\n", ret);
1170                 return ret;
1171         }
1172
1173         inno->refpclk = devm_clk_get(inno->dev, "refpclk");
1174         if (IS_ERR(inno->refpclk)) {
1175                 ret = PTR_ERR(inno->refpclk);
1176                 dev_err(inno->dev, "failed to get ref clock: %d\n", ret);
1177                 return ret;
1178         }
1179
1180         inno->refoclk = devm_clk_get(inno->dev, "refoclk");
1181         if (IS_ERR(inno->refoclk)) {
1182                 ret = PTR_ERR(inno->refoclk);
1183                 dev_err(inno->dev, "failed to get oscillator-ref clock: %d\n",
1184                         ret);
1185                 return ret;
1186         }
1187
1188         ret = clk_prepare_enable(inno->sysclk);
1189         if (ret) {
1190                 dev_err(inno->dev, "Cannot enable inno phy sysclk: %d\n", ret);
1191                 return ret;
1192         }
1193
1194         /*
1195          * Refpclk needs to be on, on at least the rk3328 for still
1196          * unknown reasons.
1197          */
1198         ret = clk_prepare_enable(inno->refpclk);
1199         if (ret) {
1200                 dev_err(inno->dev, "failed to enable refpclk\n");
1201                 clk_disable_unprepare(inno->sysclk);
1202                 return ret;
1203         }
1204
1205         ret = devm_add_action_or_reset(inno->dev, inno_hdmi_phy_action,
1206                                        inno);
1207         if (ret)
1208                 return ret;
1209
1210         inno->regmap = devm_regmap_init_mmio(inno->dev, regs,
1211                                              &inno_hdmi_phy_regmap_config);
1212         if (IS_ERR(inno->regmap))
1213                 return PTR_ERR(inno->regmap);
1214
1215         /* only the newer rk3328 hdmiphy has an interrupt */
1216         inno->irq = platform_get_irq(pdev, 0);
1217         if (inno->irq > 0) {
1218                 ret = devm_request_threaded_irq(inno->dev, inno->irq,
1219                                                 inno_hdmi_phy_rk3328_hardirq,
1220                                                 inno_hdmi_phy_rk3328_irq,
1221                                                 IRQF_SHARED,
1222                                                 dev_name(inno->dev), inno);
1223                 if (ret)
1224                         return ret;
1225         }
1226
1227         inno->phy = devm_phy_create(inno->dev, NULL, &inno_hdmi_phy_ops);
1228         if (IS_ERR(inno->phy)) {
1229                 dev_err(inno->dev, "failed to create HDMI PHY\n");
1230                 return PTR_ERR(inno->phy);
1231         }
1232
1233         phy_set_drvdata(inno->phy, inno);
1234         phy_set_bus_width(inno->phy, 8);
1235
1236         if (inno->plat_data->ops->init) {
1237                 ret = inno->plat_data->ops->init(inno);
1238                 if (ret)
1239                         return ret;
1240         }
1241
1242         ret = inno_hdmi_phy_clk_register(inno);
1243         if (ret)
1244                 return ret;
1245
1246         phy_provider = devm_of_phy_provider_register(inno->dev,
1247                                                      of_phy_simple_xlate);
1248         return PTR_ERR_OR_ZERO(phy_provider);
1249 }
1250
1251 static int inno_hdmi_phy_remove(struct platform_device *pdev)
1252 {
1253         of_clk_del_provider(pdev->dev.of_node);
1254
1255         return 0;
1256 }
1257
1258 static const struct of_device_id inno_hdmi_phy_of_match[] = {
1259         {
1260                 .compatible = "rockchip,rk3228-hdmi-phy",
1261                 .data = &rk3228_hdmi_phy_drv_data
1262         }, {
1263                 .compatible = "rockchip,rk3328-hdmi-phy",
1264                 .data = &rk3328_hdmi_phy_drv_data
1265         }, { /* sentinel */ }
1266 };
1267 MODULE_DEVICE_TABLE(of, inno_hdmi_phy_of_match);
1268
1269 static struct platform_driver inno_hdmi_phy_driver = {
1270         .probe  = inno_hdmi_phy_probe,
1271         .remove = inno_hdmi_phy_remove,
1272         .driver = {
1273                 .name = "inno-hdmi-phy",
1274                 .of_match_table = inno_hdmi_phy_of_match,
1275         },
1276 };
1277 module_platform_driver(inno_hdmi_phy_driver);
1278
1279 MODULE_AUTHOR("Zheng Yang <zhengyang@rock-chips.com>");
1280 MODULE_DESCRIPTION("Innosilion HDMI 2.0 Transmitter PHY Driver");
1281 MODULE_LICENSE("GPL v2");