drivers/phy/qualcomm/phy-qcom-qusb2.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/delay.h>
   8 #include <linux/err.h>
   9 #include <linux/io.h>
  10 #include <linux/kernel.h>
  11 #include <linux/mfd/syscon.h>
  12 #include <linux/module.h>
  13 #include <linux/nvmem-consumer.h>
  14 #include <linux/of.h>
  15 #include <linux/of_device.h>
  16 #include <linux/phy/phy.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/regmap.h>
  19 #include <linux/regulator/consumer.h>
  20 #include <linux/reset.h>
  21 #include <linux/slab.h>
  22
  23 #include <dt-bindings/phy/phy-qcom-qusb2.h>
  24
  25 #define QUSB2PHY_PLL_TEST               0x04
  26 #define CLK_REF_SEL                     BIT(7)
  27
  28 #define QUSB2PHY_PLL_TUNE               0x08
  29 #define QUSB2PHY_PLL_USER_CTL1          0x0c
  30 #define QUSB2PHY_PLL_USER_CTL2          0x10
  31 #define QUSB2PHY_PLL_AUTOPGM_CTL1       0x1c
  32 #define QUSB2PHY_PLL_PWR_CTRL           0x18
  33
  34 /* QUSB2PHY_PLL_STATUS register bits */
  35 #define PLL_LOCKED                      BIT(5)
  36
  37 /* QUSB2PHY_PLL_COMMON_STATUS_ONE register bits */
  38 #define CORE_READY_STATUS               BIT(0)
  39
  40 /* QUSB2PHY_PORT_POWERDOWN register bits */
  41 #define CLAMP_N_EN                      BIT(5)
  42 #define FREEZIO_N                       BIT(1)
  43 #define POWER_DOWN                      BIT(0)
  44
  45 /* QUSB2PHY_PWR_CTRL1 register bits */
  46 #define PWR_CTRL1_VREF_SUPPLY_TRIM      BIT(5)
  47 #define PWR_CTRL1_CLAMP_N_EN            BIT(1)
  48
  49 #define QUSB2PHY_REFCLK_ENABLE          BIT(0)
  50
  51 #define PHY_CLK_SCHEME_SEL              BIT(0)
  52
  53 /* QUSB2PHY_INTR_CTRL register bits */
  54 #define DMSE_INTR_HIGH_SEL                      BIT(4)
  55 #define DPSE_INTR_HIGH_SEL                      BIT(3)
  56 #define CHG_DET_INTR_EN                         BIT(2)
  57 #define DMSE_INTR_EN                            BIT(1)
  58 #define DPSE_INTR_EN                            BIT(0)
  59
  60 /* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE register bits */
  61 #define CORE_PLL_EN_FROM_RESET                  BIT(4)
  62 #define CORE_RESET                              BIT(5)
  63 #define CORE_RESET_MUX                          BIT(6)
  64
  65 /* QUSB2PHY_IMP_CTRL1 register bits */
  66 #define IMP_RES_OFFSET_MASK                     GENMASK(5, 0)
  67 #define IMP_RES_OFFSET_SHIFT                    0x0
  68
  69 /* QUSB2PHY_PORT_TUNE1 register bits */
  70 #define HSTX_TRIM_MASK                          GENMASK(7, 4)
  71 #define HSTX_TRIM_SHIFT                         0x4
  72 #define PREEMPH_WIDTH_HALF_BIT                  BIT(2)
  73 #define PREEMPHASIS_EN_MASK                     GENMASK(1, 0)
  74 #define PREEMPHASIS_EN_SHIFT                    0x0
  75
  76 #define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO        0x04
  77 #define QUSB2PHY_PLL_CLOCK_INVERTERS            0x18c
  78 #define QUSB2PHY_PLL_CMODE                      0x2c
  79 #define QUSB2PHY_PLL_LOCK_DELAY                 0x184
  80 #define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO         0xb4
  81 #define QUSB2PHY_PLL_BIAS_CONTROL_1             0x194
  82 #define QUSB2PHY_PLL_BIAS_CONTROL_2             0x198
  83 #define QUSB2PHY_PWR_CTRL2                      0x214
  84 #define QUSB2PHY_IMP_CTRL1                      0x220
  85 #define QUSB2PHY_IMP_CTRL2                      0x224
  86 #define QUSB2PHY_CHG_CTRL2                      0x23c
  87
  88 struct qusb2_phy_init_tbl {
  89         unsigned int offset;
  90         unsigned int val;
  91         /*
  92          * register part of layout ?
  93          * if yes, then offset gives index in the reg-layout
  94          */
  95         int in_layout;
  96 };
  97
  98 #define QUSB2_PHY_INIT_CFG(o, v) \
  99         {                       \
 100                 .offset = o,    \
 101                 .val = v,       \
 102         }
 103
 104 #define QUSB2_PHY_INIT_CFG_L(o, v) \
 105         {                       \
 106                 .offset = o,    \
 107                 .val = v,       \
 108                 .in_layout = 1, \
 109         }
 110
 111 /* set of registers with offsets different per-PHY */
 112 enum qusb2phy_reg_layout {
 113         QUSB2PHY_PLL_CORE_INPUT_OVERRIDE,
 114         QUSB2PHY_PLL_STATUS,
 115         QUSB2PHY_PORT_TUNE1,
 116         QUSB2PHY_PORT_TUNE2,
 117         QUSB2PHY_PORT_TUNE3,
 118         QUSB2PHY_PORT_TUNE4,
 119         QUSB2PHY_PORT_TUNE5,
 120         QUSB2PHY_PORT_TEST1,
 121         QUSB2PHY_PORT_TEST2,
 122         QUSB2PHY_PORT_POWERDOWN,
 123         QUSB2PHY_INTR_CTRL,
 124 };
 125
 126 static const unsigned int msm8996_regs_layout[] = {
 127         [QUSB2PHY_PLL_STATUS]           = 0x38,
 128         [QUSB2PHY_PORT_TUNE1]           = 0x80,
 129         [QUSB2PHY_PORT_TUNE2]           = 0x84,
 130         [QUSB2PHY_PORT_TUNE3]           = 0x88,
 131         [QUSB2PHY_PORT_TUNE4]           = 0x8c,
 132         [QUSB2PHY_PORT_TUNE5]           = 0x90,
 133         [QUSB2PHY_PORT_TEST1]           = 0xb8,
 134         [QUSB2PHY_PORT_TEST2]           = 0x9c,
 135         [QUSB2PHY_PORT_POWERDOWN]       = 0xb4,
 136         [QUSB2PHY_INTR_CTRL]            = 0xbc,
 137 };
 138
 139 static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = {
 140         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8),
 141         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xb3),
 142         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83),
 143         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xc0),
 144
 145         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
 146         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
 147         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
 148
 149         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14),
 150
 151         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f),
 152         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
 153 };
 154
 155 static const unsigned int msm8998_regs_layout[] = {
 156         [QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8,
 157         [QUSB2PHY_PLL_STATUS]              = 0x1a0,
 158         [QUSB2PHY_PORT_TUNE1]              = 0x23c,
 159         [QUSB2PHY_PORT_TUNE2]              = 0x240,
 160         [QUSB2PHY_PORT_TUNE3]              = 0x244,
 161         [QUSB2PHY_PORT_TUNE4]              = 0x248,
 162         [QUSB2PHY_PORT_TEST1]              = 0x24c,
 163         [QUSB2PHY_PORT_TEST2]              = 0x250,
 164         [QUSB2PHY_PORT_POWERDOWN]          = 0x210,
 165         [QUSB2PHY_INTR_CTRL]               = 0x22c,
 166 };
 167
 168 static const struct qusb2_phy_init_tbl msm8998_init_tbl[] = {
 169         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x13),
 170         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c),
 171         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80),
 172         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a),
 173
 174         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xa5),
 175         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x09),
 176
 177         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19),
 178 };
 179
 180 static const unsigned int sdm845_regs_layout[] = {
 181         [QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8,
 182         [QUSB2PHY_PLL_STATUS]           = 0x1a0,
 183         [QUSB2PHY_PORT_TUNE1]           = 0x240,
 184         [QUSB2PHY_PORT_TUNE2]           = 0x244,
 185         [QUSB2PHY_PORT_TUNE3]           = 0x248,
 186         [QUSB2PHY_PORT_TUNE4]           = 0x24c,
 187         [QUSB2PHY_PORT_TUNE5]           = 0x250,
 188         [QUSB2PHY_PORT_TEST1]           = 0x254,
 189         [QUSB2PHY_PORT_TEST2]           = 0x258,
 190         [QUSB2PHY_PORT_POWERDOWN]       = 0x210,
 191         [QUSB2PHY_INTR_CTRL]            = 0x230,
 192 };
 193
 194 static const struct qusb2_phy_init_tbl sdm845_init_tbl[] = {
 195         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x03),
 196         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c),
 197         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80),
 198         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a),
 199         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19),
 200         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_1, 0x40),
 201         QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_2, 0x20),
 202         QUSB2_PHY_INIT_CFG(QUSB2PHY_PWR_CTRL2, 0x21),
 203         QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL1, 0x0),
 204         QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL2, 0x58),
 205
 206         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0x30),
 207         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x29),
 208         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0xca),
 209         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x04),
 210         QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x03),
 211
 212         QUSB2_PHY_INIT_CFG(QUSB2PHY_CHG_CTRL2, 0x0),
 213 };
 214
 215 struct qusb2_phy_cfg {
 216         const struct qusb2_phy_init_tbl *tbl;
 217         /* number of entries in the table */
 218         unsigned int tbl_num;
 219         /* offset to PHY_CLK_SCHEME register in TCSR map */
 220         unsigned int clk_scheme_offset;
 221
 222         /* array of registers with different offsets */
 223         const unsigned int *regs;
 224         unsigned int mask_core_ready;
 225         unsigned int disable_ctrl;
 226         unsigned int autoresume_en;
 227
 228         /* true if PHY has PLL_TEST register to select clk_scheme */
 229         bool has_pll_test;
 230
 231         /* true if TUNE1 register must be updated by fused value, else TUNE2 */
 232         bool update_tune1_with_efuse;
 233
 234         /* true if PHY has PLL_CORE_INPUT_OVERRIDE register to reset PLL */
 235         bool has_pll_override;
 236 };
 237
 238 static const struct qusb2_phy_cfg msm8996_phy_cfg = {
 239         .tbl            = msm8996_init_tbl,
 240         .tbl_num        = ARRAY_SIZE(msm8996_init_tbl),
 241         .regs           = msm8996_regs_layout,
 242
 243         .has_pll_test   = true,
 244         .disable_ctrl   = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
 245         .mask_core_ready = PLL_LOCKED,
 246         .autoresume_en   = BIT(3),
 247 };
 248
 249 static const struct qusb2_phy_cfg msm8998_phy_cfg = {
 250         .tbl            = msm8998_init_tbl,
 251         .tbl_num        = ARRAY_SIZE(msm8998_init_tbl),
 252         .regs           = msm8998_regs_layout,
 253
 254         .disable_ctrl   = POWER_DOWN,
 255         .mask_core_ready = CORE_READY_STATUS,
 256         .has_pll_override = true,
 257         .autoresume_en   = BIT(0),
 258         .update_tune1_with_efuse = true,
 259 };
 260
 261 static const struct qusb2_phy_cfg sdm845_phy_cfg = {
 262         .tbl            = sdm845_init_tbl,
 263         .tbl_num        = ARRAY_SIZE(sdm845_init_tbl),
 264         .regs           = sdm845_regs_layout,
 265
 266         .disable_ctrl   = (PWR_CTRL1_VREF_SUPPLY_TRIM | PWR_CTRL1_CLAMP_N_EN |
 267                            POWER_DOWN),
 268         .mask_core_ready = CORE_READY_STATUS,
 269         .has_pll_override = true,
 270         .autoresume_en    = BIT(0),
 271         .update_tune1_with_efuse = true,
 272 };
 273
 274 static const char * const qusb2_phy_vreg_names[] = {
 275         "vdda-pll", "vdda-phy-dpdm",
 276 };
 277
 278 #define QUSB2_NUM_VREGS         ARRAY_SIZE(qusb2_phy_vreg_names)
 279
 280 /**
 281  * struct qusb2_phy - structure holding qusb2 phy attributes
 282  *
 283  * @phy: generic phy
 284  * @base: iomapped memory space for qubs2 phy
 285  *
 286  * @cfg_ahb_clk: AHB2PHY interface clock
 287  * @ref_clk: phy reference clock
 288  * @iface_clk: phy interface clock
 289  * @phy_reset: phy reset control
 290  * @vregs: regulator supplies bulk data
 291  *
 292  * @tcsr: TCSR syscon register map
 293  * @cell: nvmem cell containing phy tuning value
 294  *
 295  * @override_imp_res_offset: PHY should use different rescode offset
 296  * @imp_res_offset_value: rescode offset to be updated in IMP_CTRL1 register
 297  * @override_hstx_trim: PHY should use different HSTX o/p current value
 298  * @hstx_trim_value: HSTX_TRIM value to be updated in TUNE1 register
 299  * @override_preemphasis: PHY should use different pre-amphasis amplitude
 300  * @preemphasis_level: Amplitude Pre-Emphasis to be updated in TUNE1 register
 301  * @override_preemphasis_width: PHY should use different pre-emphasis duration
 302  * @preemphasis_width: half/full-width Pre-Emphasis updated via TUNE1
 303  *
 304  * @cfg: phy config data
 305  * @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme
 306  * @phy_initialized: indicate if PHY has been initialized
 307  * @mode: current PHY mode
 308  */
 309 struct qusb2_phy {
 310         struct phy *phy;
 311         void __iomem *base;
 312
 313         struct clk *cfg_ahb_clk;
 314         struct clk *ref_clk;
 315         struct clk *iface_clk;
 316         struct reset_control *phy_reset;
 317         struct regulator_bulk_data vregs[QUSB2_NUM_VREGS];
 318
 319         struct regmap *tcsr;
 320         struct nvmem_cell *cell;
 321
 322         bool override_imp_res_offset;
 323         u8 imp_res_offset_value;
 324         bool override_hstx_trim;
 325         u8 hstx_trim_value;
 326         bool override_preemphasis;
 327         u8 preemphasis_level;
 328         bool override_preemphasis_width;
 329         u8 preemphasis_width;
 330
 331         const struct qusb2_phy_cfg *cfg;
 332         bool has_se_clk_scheme;
 333         bool phy_initialized;
 334         enum phy_mode mode;
 335 };
 336
 337 static inline void qusb2_write_mask(void __iomem *base, u32 offset,
 338                                     u32 val, u32 mask)
 339 {
 340         u32 reg;
 341
 342         reg = readl(base + offset);
 343         reg &= ~mask;
 344         reg |= val & mask;
 345         writel(reg, base + offset);
 346
 347         /* Ensure above write is completed */
 348         readl(base + offset);
 349 }
 350
 351 static inline void qusb2_setbits(void __iomem *base, u32 offset, u32 val)
 352 {
 353         u32 reg;
 354
 355         reg = readl(base + offset);
 356         reg |= val;
 357         writel(reg, base + offset);
 358
 359         /* Ensure above write is completed */
 360         readl(base + offset);
 361 }
 362
 363 static inline void qusb2_clrbits(void __iomem *base, u32 offset, u32 val)
 364 {
 365         u32 reg;
 366
 367         reg = readl(base + offset);
 368         reg &= ~val;
 369         writel(reg, base + offset);
 370
 371         /* Ensure above write is completed */
 372         readl(base + offset);
 373 }
 374
 375 static inline
 376 void qcom_qusb2_phy_configure(void __iomem *base,
 377                               const unsigned int *regs,
 378                               const struct qusb2_phy_init_tbl tbl[], int num)
 379 {
 380         int i;
 381
 382         for (i = 0; i < num; i++) {
 383                 if (tbl[i].in_layout)
 384                         writel(tbl[i].val, base + regs[tbl[i].offset]);
 385                 else
 386                         writel(tbl[i].val, base + tbl[i].offset);
 387         }
 388 }
 389
 390 /*
 391  * Update board specific PHY tuning override values if specified from
 392  * device tree.
 393  */
 394 static void qusb2_phy_override_phy_params(struct qusb2_phy *qphy)
 395 {
 396         const struct qusb2_phy_cfg *cfg = qphy->cfg;
 397
 398         if (qphy->override_imp_res_offset)
 399                 qusb2_write_mask(qphy->base, QUSB2PHY_IMP_CTRL1,
 400                              qphy->imp_res_offset_value << IMP_RES_OFFSET_SHIFT,
 401                              IMP_RES_OFFSET_MASK);
 402
 403         if (qphy->override_hstx_trim)
 404                 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
 405                                  qphy->hstx_trim_value << HSTX_TRIM_SHIFT,
 406                                  HSTX_TRIM_MASK);
 407
 408         if (qphy->override_preemphasis)
 409                 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
 410                                 qphy->preemphasis_level << PREEMPHASIS_EN_SHIFT,
 411                                 PREEMPHASIS_EN_MASK);
 412
 413         if (qphy->override_preemphasis_width) {
 414                 if (qphy->preemphasis_width ==
 415                     QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT)
 416                         qusb2_setbits(qphy->base,
 417                                       cfg->regs[QUSB2PHY_PORT_TUNE1],
 418                                       PREEMPH_WIDTH_HALF_BIT);
 419                 else
 420                         qusb2_clrbits(qphy->base,
 421                                       cfg->regs[QUSB2PHY_PORT_TUNE1],
 422                                       PREEMPH_WIDTH_HALF_BIT);
 423         }
 424 }
 425
 426 /*
 427  * Fetches HS Tx tuning value from nvmem and sets the
 428  * QUSB2PHY_PORT_TUNE1/2 register.
 429  * For error case, skip setting the value and use the default value.
 430  */
 431 static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy)
 432 {
 433         struct device *dev = &qphy->phy->dev;
 434         const struct qusb2_phy_cfg *cfg = qphy->cfg;
 435         u8 *val;
 436
 437         /* efuse register is optional */
 438         if (!qphy->cell)
 439                 return;
 440
 441         /*
 442          * Read efuse register having TUNE2/1 parameter's high nibble.
 443          * If efuse register shows value as 0x0 (indicating value is not
 444          * fused), or if we fail to find a valid efuse register setting,
 445          * then use default value for high nibble that we have already
 446          * set while configuring the phy.
 447          */
 448         val = nvmem_cell_read(qphy->cell, NULL);
 449         if (IS_ERR(val) || !val[0]) {
 450                 dev_dbg(dev, "failed to read a valid hs-tx trim value\n");
 451                 return;
 452         }
 453
 454         /* Fused TUNE1/2 value is the higher nibble only */
 455         if (cfg->update_tune1_with_efuse)
 456                 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1],
 457                                  val[0] << HSTX_TRIM_SHIFT,
 458                                  HSTX_TRIM_MASK);
 459         else
 460                 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2],
 461                                  val[0] << HSTX_TRIM_SHIFT,
 462                                  HSTX_TRIM_MASK);
 463 }
 464
 465 static int qusb2_phy_set_mode(struct phy *phy,
 466                               enum phy_mode mode, int submode)
 467 {
 468         struct qusb2_phy *qphy = phy_get_drvdata(phy);
 469
 470         qphy->mode = mode;
 471
 472         return 0;
 473 }
 474
 475 static int __maybe_unused qusb2_phy_runtime_suspend(struct device *dev)
 476 {
 477         struct qusb2_phy *qphy = dev_get_drvdata(dev);
 478         const struct qusb2_phy_cfg *cfg = qphy->cfg;
 479         u32 intr_mask;
 480
 481         dev_vdbg(dev, "Suspending QUSB2 Phy, mode:%d\n", qphy->mode);
 482
 483         if (!qphy->phy_initialized) {
 484                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
 485                 return 0;
 486         }
 487
 488         /*
 489          * Enable DP/DM interrupts to detect line state changes based on current
 490          * speed. In other words, enable the triggers _opposite_ of what the
 491          * current D+/D- levels are e.g. if currently D+ high, D- low
 492          * (HS 'J'/Suspend), configure the mask to trigger on D+ low OR D- high
 493          */
 494         intr_mask = DPSE_INTR_EN | DMSE_INTR_EN;
 495         switch (qphy->mode) {
 496         case PHY_MODE_USB_HOST_HS:
 497         case PHY_MODE_USB_HOST_FS:
 498         case PHY_MODE_USB_DEVICE_HS:
 499         case PHY_MODE_USB_DEVICE_FS:
 500                 intr_mask |= DMSE_INTR_HIGH_SEL;
 501                 break;
 502         case PHY_MODE_USB_HOST_LS:
 503         case PHY_MODE_USB_DEVICE_LS:
 504                 intr_mask |= DPSE_INTR_HIGH_SEL;
 505                 break;
 506         default:
 507                 /* No device connected, enable both DP/DM high interrupt */
 508                 intr_mask |= DMSE_INTR_HIGH_SEL;
 509                 intr_mask |= DPSE_INTR_HIGH_SEL;
 510                 break;
 511         }
 512
 513         writel(intr_mask, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);
 514
 515         /* hold core PLL into reset */
 516         if (cfg->has_pll_override) {
 517                 qusb2_setbits(qphy->base,
 518                               cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE],
 519                               CORE_PLL_EN_FROM_RESET | CORE_RESET |
 520                               CORE_RESET_MUX);
 521         }
 522
 523         /* enable phy auto-resume only if device is connected on bus */
 524         if (qphy->mode != PHY_MODE_INVALID) {
 525                 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
 526                               cfg->autoresume_en);
 527                 /* Autoresume bit has to be toggled in order to enable it */
 528                 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1],
 529                               cfg->autoresume_en);
 530         }
 531
 532         if (!qphy->has_se_clk_scheme)
 533                 clk_disable_unprepare(qphy->ref_clk);
 534
 535         clk_disable_unprepare(qphy->cfg_ahb_clk);
 536         clk_disable_unprepare(qphy->iface_clk);
 537
 538         return 0;
 539 }
 540
 541 static int __maybe_unused qusb2_phy_runtime_resume(struct device *dev)
 542 {
 543         struct qusb2_phy *qphy = dev_get_drvdata(dev);
 544         const struct qusb2_phy_cfg *cfg = qphy->cfg;
 545         int ret;
 546
 547         dev_vdbg(dev, "Resuming QUSB2 phy, mode:%d\n", qphy->mode);
 548
 549         if (!qphy->phy_initialized) {
 550                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
 551                 return 0;
 552         }
 553
 554         ret = clk_prepare_enable(qphy->iface_clk);
 555         if (ret) {
 556                 dev_err(dev, "failed to enable iface_clk, %d\n", ret);
 557                 return ret;
 558         }
 559
 560         ret = clk_prepare_enable(qphy->cfg_ahb_clk);
 561         if (ret) {
 562                 dev_err(dev, "failed to enable cfg ahb clock, %d\n", ret);
 563                 goto disable_iface_clk;
 564         }
 565
 566         if (!qphy->has_se_clk_scheme) {
 567                 ret = clk_prepare_enable(qphy->ref_clk);
 568                 if (ret) {
 569                         dev_err(dev, "failed to enable ref clk, %d\n", ret);
 570                         goto disable_ahb_clk;
 571                 }
 572         }
 573
 574         writel(0x0, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]);
 575
 576         /* bring core PLL out of reset */
 577         if (cfg->has_pll_override) {
 578                 qusb2_clrbits(qphy->base,
 579                               cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE],
 580                               CORE_RESET | CORE_RESET_MUX);
 581         }
 582
 583         return 0;
 584
 585 disable_ahb_clk:
 586         clk_disable_unprepare(qphy->cfg_ahb_clk);
 587 disable_iface_clk:
 588         clk_disable_unprepare(qphy->iface_clk);
 589
 590         return ret;
 591 }
 592
 593 static int qusb2_phy_init(struct phy *phy)
 594 {
 595         struct qusb2_phy *qphy = phy_get_drvdata(phy);
 596         const struct qusb2_phy_cfg *cfg = qphy->cfg;
 597         unsigned int val = 0;
 598         unsigned int clk_scheme;
 599         int ret;
 600
 601         dev_vdbg(&phy->dev, "%s(): Initializing QUSB2 phy\n", __func__);
 602
 603         /* turn on regulator supplies */
 604         ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
 605         if (ret)
 606                 return ret;
 607
 608         ret = clk_prepare_enable(qphy->iface_clk);
 609         if (ret) {
 610                 dev_err(&phy->dev, "failed to enable iface_clk, %d\n", ret);
 611                 goto poweroff_phy;
 612         }
 613
 614         /* enable ahb interface clock to program phy */
 615         ret = clk_prepare_enable(qphy->cfg_ahb_clk);
 616         if (ret) {
 617                 dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret);
 618                 goto disable_iface_clk;
 619         }
 620
 621         /* Perform phy reset */
 622         ret = reset_control_assert(qphy->phy_reset);
 623         if (ret) {
 624                 dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret);
 625                 goto disable_ahb_clk;
 626         }
 627
 628         /* 100 us delay to keep PHY in reset mode */
 629         usleep_range(100, 150);
 630
 631         ret = reset_control_deassert(qphy->phy_reset);
 632         if (ret) {
 633                 dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret);
 634                 goto disable_ahb_clk;
 635         }
 636
 637         /* Disable the PHY */
 638         qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN],
 639                       qphy->cfg->disable_ctrl);
 640
 641         if (cfg->has_pll_test) {
 642                 /* save reset value to override reference clock scheme later */
 643                 val = readl(qphy->base + QUSB2PHY_PLL_TEST);
 644         }
 645
 646         qcom_qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl,
 647                                  cfg->tbl_num);
 648
 649         /* Override board specific PHY tuning values */
 650         qusb2_phy_override_phy_params(qphy);
 651
 652         /* Set efuse value for tuning the PHY */
 653         qusb2_phy_set_tune2_param(qphy);
 654
 655         /* Enable the PHY */
 656         qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN],
 657                       POWER_DOWN);
 658
 659         /* Required to get phy pll lock successfully */
 660         usleep_range(150, 160);
 661
 662         /* Default is single-ended clock on msm8996 */
 663         qphy->has_se_clk_scheme = true;
 664         /*
 665          * read TCSR_PHY_CLK_SCHEME register to check if single-ended
 666          * clock scheme is selected. If yes, then disable differential
 667          * ref_clk and use single-ended clock, otherwise use differential
 668          * ref_clk only.
 669          */
 670         if (qphy->tcsr) {
 671                 ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset,
 672                                   &clk_scheme);
 673                 if (ret) {
 674                         dev_err(&phy->dev, "failed to read clk scheme reg\n");
 675                         goto assert_phy_reset;
 676                 }
 677
 678                 /* is it a differential clock scheme ? */
 679                 if (!(clk_scheme & PHY_CLK_SCHEME_SEL)) {
 680                         dev_vdbg(&phy->dev, "%s(): select differential clk\n",
 681                                  __func__);
 682                         qphy->has_se_clk_scheme = false;
 683                 } else {
 684                         dev_vdbg(&phy->dev, "%s(): select single-ended clk\n",
 685                                  __func__);
 686                 }
 687         }
 688
 689         if (!qphy->has_se_clk_scheme) {
 690                 ret = clk_prepare_enable(qphy->ref_clk);
 691                 if (ret) {
 692                         dev_err(&phy->dev, "failed to enable ref clk, %d\n",
 693                                 ret);
 694                         goto assert_phy_reset;
 695                 }
 696         }
 697
 698         if (cfg->has_pll_test) {
 699                 if (!qphy->has_se_clk_scheme)
 700                         val &= ~CLK_REF_SEL;
 701                 else
 702                         val |= CLK_REF_SEL;
 703
 704                 writel(val, qphy->base + QUSB2PHY_PLL_TEST);
 705
 706                 /* ensure above write is through */
 707                 readl(qphy->base + QUSB2PHY_PLL_TEST);
 708         }
 709
 710         /* Required to get phy pll lock successfully */
 711         usleep_range(100, 110);
 712
 713         val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]);
 714         if (!(val & cfg->mask_core_ready)) {
 715                 dev_err(&phy->dev,
 716                         "QUSB2PHY pll lock failed: status reg = %x\n", val);
 717                 ret = -EBUSY;
 718                 goto disable_ref_clk;
 719         }
 720         qphy->phy_initialized = true;
 721
 722         return 0;
 723
 724 disable_ref_clk:
 725         if (!qphy->has_se_clk_scheme)
 726                 clk_disable_unprepare(qphy->ref_clk);
 727 assert_phy_reset:
 728         reset_control_assert(qphy->phy_reset);
 729 disable_ahb_clk:
 730         clk_disable_unprepare(qphy->cfg_ahb_clk);
 731 disable_iface_clk:
 732         clk_disable_unprepare(qphy->iface_clk);
 733 poweroff_phy:
 734         regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
 735
 736         return ret;
 737 }
 738
 739 static int qusb2_phy_exit(struct phy *phy)
 740 {
 741         struct qusb2_phy *qphy = phy_get_drvdata(phy);
 742
 743         /* Disable the PHY */
 744         qusb2_setbits(qphy->base, qphy->cfg->regs[QUSB2PHY_PORT_POWERDOWN],
 745                       qphy->cfg->disable_ctrl);
 746
 747         if (!qphy->has_se_clk_scheme)
 748                 clk_disable_unprepare(qphy->ref_clk);
 749
 750         reset_control_assert(qphy->phy_reset);
 751
 752         clk_disable_unprepare(qphy->cfg_ahb_clk);
 753         clk_disable_unprepare(qphy->iface_clk);
 754
 755         regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
 756
 757         qphy->phy_initialized = false;
 758
 759         return 0;
 760 }
 761
 762 static const struct phy_ops qusb2_phy_gen_ops = {
 763         .init           = qusb2_phy_init,
 764         .exit           = qusb2_phy_exit,
 765         .set_mode       = qusb2_phy_set_mode,
 766         .owner          = THIS_MODULE,
 767 };
 768
 769 static const struct of_device_id qusb2_phy_of_match_table[] = {
 770         {
 771                 .compatible     = "qcom,msm8996-qusb2-phy",
 772                 .data           = &msm8996_phy_cfg,
 773         }, {
 774                 .compatible     = "qcom,msm8998-qusb2-phy",
 775                 .data           = &msm8998_phy_cfg,
 776         }, {
 777                 .compatible     = "qcom,sdm845-qusb2-phy",
 778                 .data           = &sdm845_phy_cfg,
 779         },
 780         { },
 781 };
 782 MODULE_DEVICE_TABLE(of, qusb2_phy_of_match_table);
 783
 784 static const struct dev_pm_ops qusb2_phy_pm_ops = {
 785         SET_RUNTIME_PM_OPS(qusb2_phy_runtime_suspend,
 786                            qusb2_phy_runtime_resume, NULL)
 787 };
 788
 789 static int qusb2_phy_probe(struct platform_device *pdev)
 790 {
 791         struct device *dev = &pdev->dev;
 792         struct qusb2_phy *qphy;
 793         struct phy_provider *phy_provider;
 794         struct phy *generic_phy;
 795         struct resource *res;
 796         int ret, i;
 797         int num;
 798         u32 value;
 799
 800         qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
 801         if (!qphy)
 802                 return -ENOMEM;
 803
 804         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 805         qphy->base = devm_ioremap_resource(dev, res);
 806         if (IS_ERR(qphy->base))
 807                 return PTR_ERR(qphy->base);
 808
 809         qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb");
 810         if (IS_ERR(qphy->cfg_ahb_clk)) {
 811                 ret = PTR_ERR(qphy->cfg_ahb_clk);
 812                 if (ret != -EPROBE_DEFER)
 813                         dev_err(dev, "failed to get cfg ahb clk, %d\n", ret);
 814                 return ret;
 815         }
 816
 817         qphy->ref_clk = devm_clk_get(dev, "ref");
 818         if (IS_ERR(qphy->ref_clk)) {
 819                 ret = PTR_ERR(qphy->ref_clk);
 820                 if (ret != -EPROBE_DEFER)
 821                         dev_err(dev, "failed to get ref clk, %d\n", ret);
 822                 return ret;
 823         }
 824
 825         qphy->iface_clk = devm_clk_get_optional(dev, "iface");
 826         if (IS_ERR(qphy->iface_clk))
 827                 return PTR_ERR(qphy->iface_clk);
 828
 829         qphy->phy_reset = devm_reset_control_get_by_index(&pdev->dev, 0);
 830         if (IS_ERR(qphy->phy_reset)) {
 831                 dev_err(dev, "failed to get phy core reset\n");
 832                 return PTR_ERR(qphy->phy_reset);
 833         }
 834
 835         num = ARRAY_SIZE(qphy->vregs);
 836         for (i = 0; i < num; i++)
 837                 qphy->vregs[i].supply = qusb2_phy_vreg_names[i];
 838
 839         ret = devm_regulator_bulk_get(dev, num, qphy->vregs);
 840         if (ret) {
 841                 if (ret != -EPROBE_DEFER)
 842                         dev_err(dev, "failed to get regulator supplies: %d\n",
 843                                 ret);
 844                 return ret;
 845         }
 846
 847         /* Get the specific init parameters of QMP phy */
 848         qphy->cfg = of_device_get_match_data(dev);
 849
 850         qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node,
 851                                                         "qcom,tcsr-syscon");
 852         if (IS_ERR(qphy->tcsr)) {
 853                 dev_dbg(dev, "failed to lookup TCSR regmap\n");
 854                 qphy->tcsr = NULL;
 855         }
 856
 857         qphy->cell = devm_nvmem_cell_get(dev, NULL);
 858         if (IS_ERR(qphy->cell)) {
 859                 if (PTR_ERR(qphy->cell) == -EPROBE_DEFER)
 860                         return -EPROBE_DEFER;
 861                 qphy->cell = NULL;
 862                 dev_dbg(dev, "failed to lookup tune2 hstx trim value\n");
 863         }
 864
 865         if (!of_property_read_u32(dev->of_node, "qcom,imp-res-offset-value",
 866                                   &value)) {
 867                 qphy->imp_res_offset_value = (u8)value;
 868                 qphy->override_imp_res_offset = true;
 869         }
 870
 871         if (!of_property_read_u32(dev->of_node, "qcom,hstx-trim-value",
 872                                   &value)) {
 873                 qphy->hstx_trim_value = (u8)value;
 874                 qphy->override_hstx_trim = true;
 875         }
 876
 877         if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-level",
 878                                      &value)) {
 879                 qphy->preemphasis_level = (u8)value;
 880                 qphy->override_preemphasis = true;
 881         }
 882
 883         if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-width",
 884                                      &value)) {
 885                 qphy->preemphasis_width = (u8)value;
 886                 qphy->override_preemphasis_width = true;
 887         }
 888
 889         pm_runtime_set_active(dev);
 890         pm_runtime_enable(dev);
 891         /*
 892          * Prevent runtime pm from being ON by default. Users can enable
 893          * it using power/control in sysfs.
 894          */
 895         pm_runtime_forbid(dev);
 896
 897         generic_phy = devm_phy_create(dev, NULL, &qusb2_phy_gen_ops);
 898         if (IS_ERR(generic_phy)) {
 899                 ret = PTR_ERR(generic_phy);
 900                 dev_err(dev, "failed to create phy, %d\n", ret);
 901                 pm_runtime_disable(dev);
 902                 return ret;
 903         }
 904         qphy->phy = generic_phy;
 905
 906         dev_set_drvdata(dev, qphy);
 907         phy_set_drvdata(generic_phy, qphy);
 908
 909         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
 910         if (!IS_ERR(phy_provider))
 911                 dev_info(dev, "Registered Qcom-QUSB2 phy\n");
 912         else
 913                 pm_runtime_disable(dev);
 914
 915         return PTR_ERR_OR_ZERO(phy_provider);
 916 }
 917
 918 static struct platform_driver qusb2_phy_driver = {
 919         .probe          = qusb2_phy_probe,
 920         .driver = {
 921                 .name   = "qcom-qusb2-phy",
 922                 .pm     = &qusb2_phy_pm_ops,
 923                 .of_match_table = qusb2_phy_of_match_table,
 924         },
 925 };
 926
 927 module_platform_driver(qusb2_phy_driver);
 928
 929 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
 930 MODULE_DESCRIPTION("Qualcomm QUSB2 PHY driver");
 931 MODULE_LICENSE("GPL v2");