1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek PCIe host controller driver.
5 * Copyright (c) 2017 MediaTek Inc.
6 * Author: Ryder Lee <ryder.lee@mediatek.com>
7 * Honghui Zhang <honghui.zhang@mediatek.com>
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/iopoll.h>
13 #include <linux/irq.h>
14 #include <linux/irqchip/chained_irq.h>
15 #include <linux/irqdomain.h>
16 #include <linux/kernel.h>
17 #include <linux/msi.h>
18 #include <linux/module.h>
19 #include <linux/of_address.h>
20 #include <linux/of_pci.h>
21 #include <linux/of_platform.h>
22 #include <linux/pci.h>
23 #include <linux/phy/phy.h>
24 #include <linux/platform_device.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/reset.h>
30 /* PCIe shared registers */
31 #define PCIE_SYS_CFG 0x00
32 #define PCIE_INT_ENABLE 0x0c
33 #define PCIE_CFG_ADDR 0x20
34 #define PCIE_CFG_DATA 0x24
36 /* PCIe per port registers */
37 #define PCIE_BAR0_SETUP 0x10
38 #define PCIE_CLASS 0x34
39 #define PCIE_LINK_STATUS 0x50
41 #define PCIE_PORT_INT_EN(x) BIT(20 + (x))
42 #define PCIE_PORT_PERST(x) BIT(1 + (x))
43 #define PCIE_PORT_LINKUP BIT(0)
44 #define PCIE_BAR_MAP_MAX GENMASK(31, 16)
46 #define PCIE_BAR_ENABLE BIT(0)
47 #define PCIE_REVISION_ID BIT(0)
48 #define PCIE_CLASS_CODE (0x60400 << 8)
49 #define PCIE_CONF_REG(regn) (((regn) & GENMASK(7, 2)) | \
50 ((((regn) >> 8) & GENMASK(3, 0)) << 24))
51 #define PCIE_CONF_FUN(fun) (((fun) << 8) & GENMASK(10, 8))
52 #define PCIE_CONF_DEV(dev) (((dev) << 11) & GENMASK(15, 11))
53 #define PCIE_CONF_BUS(bus) (((bus) << 16) & GENMASK(23, 16))
54 #define PCIE_CONF_ADDR(regn, fun, dev, bus) \
55 (PCIE_CONF_REG(regn) | PCIE_CONF_FUN(fun) | \
56 PCIE_CONF_DEV(dev) | PCIE_CONF_BUS(bus))
58 /* MediaTek specific configuration registers */
59 #define PCIE_FTS_NUM 0x70c
60 #define PCIE_FTS_NUM_MASK GENMASK(15, 8)
61 #define PCIE_FTS_NUM_L0(x) ((x) & 0xff << 8)
63 #define PCIE_FC_CREDIT 0x73c
64 #define PCIE_FC_CREDIT_MASK (GENMASK(31, 31) | GENMASK(28, 16))
65 #define PCIE_FC_CREDIT_VAL(x) ((x) << 16)
67 /* PCIe V2 share registers */
68 #define PCIE_SYS_CFG_V2 0x0
69 #define PCIE_CSR_LTSSM_EN(x) BIT(0 + (x) * 8)
70 #define PCIE_CSR_ASPM_L1_EN(x) BIT(1 + (x) * 8)
72 /* PCIe V2 per-port registers */
73 #define PCIE_MSI_VECTOR 0x0c0
75 #define PCIE_CONF_VEND_ID 0x100
76 #define PCIE_CONF_DEVICE_ID 0x102
77 #define PCIE_CONF_CLASS_ID 0x106
79 #define PCIE_INT_MASK 0x420
80 #define INTX_MASK GENMASK(19, 16)
82 #define PCIE_INT_STATUS 0x424
83 #define MSI_STATUS BIT(23)
84 #define PCIE_IMSI_STATUS 0x42c
85 #define PCIE_IMSI_ADDR 0x430
86 #define MSI_MASK BIT(23)
87 #define MTK_MSI_IRQS_NUM 32
89 #define PCIE_AHB_TRANS_BASE0_L 0x438
90 #define PCIE_AHB_TRANS_BASE0_H 0x43c
91 #define AHB2PCIE_SIZE(x) ((x) & GENMASK(4, 0))
92 #define PCIE_AXI_WINDOW0 0x448
93 #define WIN_ENABLE BIT(7)
95 * Define PCIe to AHB window size as 2^33 to support max 8GB address space
96 * translate, support least 4GB DRAM size access from EP DMA(physical DRAM
97 * start from 0x40000000).
99 #define PCIE2AHB_SIZE 0x21
101 /* PCIe V2 configuration transaction header */
102 #define PCIE_CFG_HEADER0 0x460
103 #define PCIE_CFG_HEADER1 0x464
104 #define PCIE_CFG_HEADER2 0x468
105 #define PCIE_CFG_WDATA 0x470
106 #define PCIE_APP_TLP_REQ 0x488
107 #define PCIE_CFG_RDATA 0x48c
108 #define APP_CFG_REQ BIT(0)
109 #define APP_CPL_STATUS GENMASK(7, 5)
111 #define CFG_WRRD_TYPE_0 4
115 #define CFG_DW0_LENGTH(length) ((length) & GENMASK(9, 0))
116 #define CFG_DW0_TYPE(type) (((type) << 24) & GENMASK(28, 24))
117 #define CFG_DW0_FMT(fmt) (((fmt) << 29) & GENMASK(31, 29))
118 #define CFG_DW2_REGN(regn) ((regn) & GENMASK(11, 2))
119 #define CFG_DW2_FUN(fun) (((fun) << 16) & GENMASK(18, 16))
120 #define CFG_DW2_DEV(dev) (((dev) << 19) & GENMASK(23, 19))
121 #define CFG_DW2_BUS(bus) (((bus) << 24) & GENMASK(31, 24))
122 #define CFG_HEADER_DW0(type, fmt) \
123 (CFG_DW0_LENGTH(1) | CFG_DW0_TYPE(type) | CFG_DW0_FMT(fmt))
124 #define CFG_HEADER_DW1(where, size) \
125 (GENMASK(((size) - 1), 0) << ((where) & 0x3))
126 #define CFG_HEADER_DW2(regn, fun, dev, bus) \
127 (CFG_DW2_REGN(regn) | CFG_DW2_FUN(fun) | \
128 CFG_DW2_DEV(dev) | CFG_DW2_BUS(bus))
130 #define PCIE_RST_CTRL 0x510
131 #define PCIE_PHY_RSTB BIT(0)
132 #define PCIE_PIPE_SRSTB BIT(1)
133 #define PCIE_MAC_SRSTB BIT(2)
134 #define PCIE_CRSTB BIT(3)
135 #define PCIE_PERSTB BIT(8)
136 #define PCIE_LINKDOWN_RST_EN GENMASK(15, 13)
137 #define PCIE_LINK_STATUS_V2 0x804
138 #define PCIE_PORT_LINKUP_V2 BIT(10)
140 struct mtk_pcie_port;
143 * struct mtk_pcie_soc - differentiate between host generations
144 * @need_fix_class_id: whether this host's class ID needed to be fixed or not
145 * @need_fix_device_id: whether this host's device ID needed to be fixed or not
146 * @device_id: device ID which this host need to be fixed
147 * @ops: pointer to configuration access functions
148 * @startup: pointer to controller setting functions
149 * @setup_irq: pointer to initialize IRQ functions
151 struct mtk_pcie_soc {
152 bool need_fix_class_id;
153 bool need_fix_device_id;
154 unsigned int device_id;
156 int (*startup)(struct mtk_pcie_port *port);
157 int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node);
161 * struct mtk_pcie_port - PCIe port information
162 * @base: IO mapped register base
164 * @pcie: pointer to PCIe host info
165 * @reset: pointer to port reset control
166 * @sys_ck: pointer to transaction/data link layer clock
167 * @ahb_ck: pointer to AHB slave interface operating clock for CSR access
168 * and RC initiated MMIO access
169 * @axi_ck: pointer to application layer MMIO channel operating clock
170 * @aux_ck: pointer to pe2_mac_bridge and pe2_mac_core operating clock
171 * when pcie_mac_ck/pcie_pipe_ck is turned off
172 * @obff_ck: pointer to OBFF functional block operating clock
173 * @pipe_ck: pointer to LTSSM and PHY/MAC layer operating clock
174 * @phy: pointer to PHY control block
177 * @irq_domain: legacy INTx IRQ domain
178 * @inner_domain: inner IRQ domain
179 * @msi_domain: MSI IRQ domain
180 * @lock: protect the msi_irq_in_use bitmap
181 * @msi_irq_in_use: bit map for assigned MSI IRQ
183 struct mtk_pcie_port {
185 struct list_head list;
186 struct mtk_pcie *pcie;
187 struct reset_control *reset;
197 struct irq_domain *irq_domain;
198 struct irq_domain *inner_domain;
199 struct irq_domain *msi_domain;
201 DECLARE_BITMAP(msi_irq_in_use, MTK_MSI_IRQS_NUM);
205 * struct mtk_pcie - PCIe host information
206 * @dev: pointer to PCIe device
207 * @base: IO mapped register base
208 * @free_ck: free-run reference clock
209 * @mem: non-prefetchable memory resource
210 * @ports: pointer to PCIe port information
211 * @soc: pointer to SoC-dependent operations
212 * @busnr: root bus number
220 struct list_head ports;
221 const struct mtk_pcie_soc *soc;
225 static void mtk_pcie_subsys_powerdown(struct mtk_pcie *pcie)
227 struct device *dev = pcie->dev;
229 clk_disable_unprepare(pcie->free_ck);
231 pm_runtime_put_sync(dev);
232 pm_runtime_disable(dev);
235 static void mtk_pcie_port_free(struct mtk_pcie_port *port)
237 struct mtk_pcie *pcie = port->pcie;
238 struct device *dev = pcie->dev;
240 devm_iounmap(dev, port->base);
241 list_del(&port->list);
242 devm_kfree(dev, port);
245 static void mtk_pcie_put_resources(struct mtk_pcie *pcie)
247 struct mtk_pcie_port *port, *tmp;
249 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
250 phy_power_off(port->phy);
252 clk_disable_unprepare(port->pipe_ck);
253 clk_disable_unprepare(port->obff_ck);
254 clk_disable_unprepare(port->axi_ck);
255 clk_disable_unprepare(port->aux_ck);
256 clk_disable_unprepare(port->ahb_ck);
257 clk_disable_unprepare(port->sys_ck);
258 mtk_pcie_port_free(port);
261 mtk_pcie_subsys_powerdown(pcie);
264 static int mtk_pcie_check_cfg_cpld(struct mtk_pcie_port *port)
269 err = readl_poll_timeout_atomic(port->base + PCIE_APP_TLP_REQ, val,
270 !(val & APP_CFG_REQ), 10,
271 100 * USEC_PER_MSEC);
273 return PCIBIOS_SET_FAILED;
275 if (readl(port->base + PCIE_APP_TLP_REQ) & APP_CPL_STATUS)
276 return PCIBIOS_SET_FAILED;
278 return PCIBIOS_SUCCESSFUL;
281 static int mtk_pcie_hw_rd_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
282 int where, int size, u32 *val)
286 /* Write PCIe configuration transaction header for Cfgrd */
287 writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_RD_FMT),
288 port->base + PCIE_CFG_HEADER0);
289 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
290 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
291 port->base + PCIE_CFG_HEADER2);
293 /* Trigger h/w to transmit Cfgrd TLP */
294 tmp = readl(port->base + PCIE_APP_TLP_REQ);
296 writel(tmp, port->base + PCIE_APP_TLP_REQ);
298 /* Check completion status */
299 if (mtk_pcie_check_cfg_cpld(port))
300 return PCIBIOS_SET_FAILED;
302 /* Read cpld payload of Cfgrd */
303 *val = readl(port->base + PCIE_CFG_RDATA);
306 *val = (*val >> (8 * (where & 3))) & 0xff;
308 *val = (*val >> (8 * (where & 3))) & 0xffff;
310 return PCIBIOS_SUCCESSFUL;
313 static int mtk_pcie_hw_wr_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
314 int where, int size, u32 val)
316 /* Write PCIe configuration transaction header for Cfgwr */
317 writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_WR_FMT),
318 port->base + PCIE_CFG_HEADER0);
319 writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
320 writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
321 port->base + PCIE_CFG_HEADER2);
323 /* Write Cfgwr data */
324 val = val << 8 * (where & 3);
325 writel(val, port->base + PCIE_CFG_WDATA);
327 /* Trigger h/w to transmit Cfgwr TLP */
328 val = readl(port->base + PCIE_APP_TLP_REQ);
330 writel(val, port->base + PCIE_APP_TLP_REQ);
332 /* Check completion status */
333 return mtk_pcie_check_cfg_cpld(port);
336 static struct mtk_pcie_port *mtk_pcie_find_port(struct pci_bus *bus,
339 struct mtk_pcie *pcie = bus->sysdata;
340 struct mtk_pcie_port *port;
341 struct pci_dev *dev = NULL;
344 * Walk the bus hierarchy to get the devfn value
345 * of the port in the root bus.
347 while (bus && bus->number) {
353 list_for_each_entry(port, &pcie->ports, list)
354 if (port->slot == PCI_SLOT(devfn))
360 static int mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
361 int where, int size, u32 *val)
363 struct mtk_pcie_port *port;
364 u32 bn = bus->number;
367 port = mtk_pcie_find_port(bus, devfn);
370 return PCIBIOS_DEVICE_NOT_FOUND;
373 ret = mtk_pcie_hw_rd_cfg(port, bn, devfn, where, size, val);
380 static int mtk_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
381 int where, int size, u32 val)
383 struct mtk_pcie_port *port;
384 u32 bn = bus->number;
386 port = mtk_pcie_find_port(bus, devfn);
388 return PCIBIOS_DEVICE_NOT_FOUND;
390 return mtk_pcie_hw_wr_cfg(port, bn, devfn, where, size, val);
393 static struct pci_ops mtk_pcie_ops_v2 = {
394 .read = mtk_pcie_config_read,
395 .write = mtk_pcie_config_write,
398 static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
400 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
403 /* MT2712/MT7622 only support 32-bit MSI addresses */
404 addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
406 msg->address_lo = lower_32_bits(addr);
408 msg->data = data->hwirq;
410 dev_dbg(port->pcie->dev, "msi#%d address_hi %#x address_lo %#x\n",
411 (int)data->hwirq, msg->address_hi, msg->address_lo);
414 static int mtk_msi_set_affinity(struct irq_data *irq_data,
415 const struct cpumask *mask, bool force)
420 static void mtk_msi_ack_irq(struct irq_data *data)
422 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
423 u32 hwirq = data->hwirq;
425 writel(1 << hwirq, port->base + PCIE_IMSI_STATUS);
428 static struct irq_chip mtk_msi_bottom_irq_chip = {
430 .irq_compose_msi_msg = mtk_compose_msi_msg,
431 .irq_set_affinity = mtk_msi_set_affinity,
432 .irq_ack = mtk_msi_ack_irq,
435 static int mtk_pcie_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
436 unsigned int nr_irqs, void *args)
438 struct mtk_pcie_port *port = domain->host_data;
441 WARN_ON(nr_irqs != 1);
442 mutex_lock(&port->lock);
444 bit = find_first_zero_bit(port->msi_irq_in_use, MTK_MSI_IRQS_NUM);
445 if (bit >= MTK_MSI_IRQS_NUM) {
446 mutex_unlock(&port->lock);
450 __set_bit(bit, port->msi_irq_in_use);
452 mutex_unlock(&port->lock);
454 irq_domain_set_info(domain, virq, bit, &mtk_msi_bottom_irq_chip,
455 domain->host_data, handle_edge_irq,
461 static void mtk_pcie_irq_domain_free(struct irq_domain *domain,
462 unsigned int virq, unsigned int nr_irqs)
464 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
465 struct mtk_pcie_port *port = irq_data_get_irq_chip_data(d);
467 mutex_lock(&port->lock);
469 if (!test_bit(d->hwirq, port->msi_irq_in_use))
470 dev_err(port->pcie->dev, "trying to free unused MSI#%lu\n",
473 __clear_bit(d->hwirq, port->msi_irq_in_use);
475 mutex_unlock(&port->lock);
477 irq_domain_free_irqs_parent(domain, virq, nr_irqs);
480 static const struct irq_domain_ops msi_domain_ops = {
481 .alloc = mtk_pcie_irq_domain_alloc,
482 .free = mtk_pcie_irq_domain_free,
485 static struct irq_chip mtk_msi_irq_chip = {
486 .name = "MTK PCIe MSI",
487 .irq_ack = irq_chip_ack_parent,
488 .irq_mask = pci_msi_mask_irq,
489 .irq_unmask = pci_msi_unmask_irq,
492 static struct msi_domain_info mtk_msi_domain_info = {
493 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
495 .chip = &mtk_msi_irq_chip,
498 static int mtk_pcie_allocate_msi_domains(struct mtk_pcie_port *port)
500 struct fwnode_handle *fwnode = of_node_to_fwnode(port->pcie->dev->of_node);
502 mutex_init(&port->lock);
504 port->inner_domain = irq_domain_create_linear(fwnode, MTK_MSI_IRQS_NUM,
505 &msi_domain_ops, port);
506 if (!port->inner_domain) {
507 dev_err(port->pcie->dev, "failed to create IRQ domain\n");
511 port->msi_domain = pci_msi_create_irq_domain(fwnode, &mtk_msi_domain_info,
513 if (!port->msi_domain) {
514 dev_err(port->pcie->dev, "failed to create MSI domain\n");
515 irq_domain_remove(port->inner_domain);
522 static void mtk_pcie_enable_msi(struct mtk_pcie_port *port)
525 phys_addr_t msg_addr;
527 msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
528 val = lower_32_bits(msg_addr);
529 writel(val, port->base + PCIE_IMSI_ADDR);
531 val = readl(port->base + PCIE_INT_MASK);
533 writel(val, port->base + PCIE_INT_MASK);
536 static void mtk_pcie_irq_teardown(struct mtk_pcie *pcie)
538 struct mtk_pcie_port *port, *tmp;
540 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
541 irq_set_chained_handler_and_data(port->irq, NULL, NULL);
543 if (port->irq_domain)
544 irq_domain_remove(port->irq_domain);
546 if (IS_ENABLED(CONFIG_PCI_MSI)) {
547 if (port->msi_domain)
548 irq_domain_remove(port->msi_domain);
549 if (port->inner_domain)
550 irq_domain_remove(port->inner_domain);
553 irq_dispose_mapping(port->irq);
557 static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
558 irq_hw_number_t hwirq)
560 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
561 irq_set_chip_data(irq, domain->host_data);
566 static const struct irq_domain_ops intx_domain_ops = {
567 .map = mtk_pcie_intx_map,
570 static int mtk_pcie_init_irq_domain(struct mtk_pcie_port *port,
571 struct device_node *node)
573 struct device *dev = port->pcie->dev;
574 struct device_node *pcie_intc_node;
578 pcie_intc_node = of_get_next_child(node, NULL);
579 if (!pcie_intc_node) {
580 dev_err(dev, "no PCIe Intc node found\n");
584 port->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
585 &intx_domain_ops, port);
586 of_node_put(pcie_intc_node);
587 if (!port->irq_domain) {
588 dev_err(dev, "failed to get INTx IRQ domain\n");
592 if (IS_ENABLED(CONFIG_PCI_MSI)) {
593 ret = mtk_pcie_allocate_msi_domains(port);
601 static void mtk_pcie_intr_handler(struct irq_desc *desc)
603 struct mtk_pcie_port *port = irq_desc_get_handler_data(desc);
604 struct irq_chip *irqchip = irq_desc_get_chip(desc);
605 unsigned long status;
607 u32 bit = INTX_SHIFT;
609 chained_irq_enter(irqchip, desc);
611 status = readl(port->base + PCIE_INT_STATUS);
612 if (status & INTX_MASK) {
613 for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) {
615 writel(1 << bit, port->base + PCIE_INT_STATUS);
616 virq = irq_find_mapping(port->irq_domain,
618 generic_handle_irq(virq);
622 if (IS_ENABLED(CONFIG_PCI_MSI)) {
623 if (status & MSI_STATUS){
624 unsigned long imsi_status;
626 while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) {
627 for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM) {
628 virq = irq_find_mapping(port->inner_domain, bit);
629 generic_handle_irq(virq);
632 /* Clear MSI interrupt status */
633 writel(MSI_STATUS, port->base + PCIE_INT_STATUS);
637 chained_irq_exit(irqchip, desc);
640 static int mtk_pcie_setup_irq(struct mtk_pcie_port *port,
641 struct device_node *node)
643 struct mtk_pcie *pcie = port->pcie;
644 struct device *dev = pcie->dev;
645 struct platform_device *pdev = to_platform_device(dev);
648 err = mtk_pcie_init_irq_domain(port, node);
650 dev_err(dev, "failed to init PCIe IRQ domain\n");
654 port->irq = platform_get_irq(pdev, port->slot);
655 irq_set_chained_handler_and_data(port->irq,
656 mtk_pcie_intr_handler, port);
661 static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
663 struct mtk_pcie *pcie = port->pcie;
664 struct resource *mem = &pcie->mem;
665 const struct mtk_pcie_soc *soc = port->pcie->soc;
669 /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
671 val = readl(pcie->base + PCIE_SYS_CFG_V2);
672 val |= PCIE_CSR_LTSSM_EN(port->slot) |
673 PCIE_CSR_ASPM_L1_EN(port->slot);
674 writel(val, pcie->base + PCIE_SYS_CFG_V2);
677 /* Assert all reset signals */
678 writel(0, port->base + PCIE_RST_CTRL);
681 * Enable PCIe link down reset, if link status changed from link up to
682 * link down, this will reset MAC control registers and configuration
685 writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
687 /* De-assert PHY, PE, PIPE, MAC and configuration reset */
688 val = readl(port->base + PCIE_RST_CTRL);
689 val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
690 PCIE_MAC_SRSTB | PCIE_CRSTB;
691 writel(val, port->base + PCIE_RST_CTRL);
693 /* Set up vendor ID and class code */
694 if (soc->need_fix_class_id) {
695 val = PCI_VENDOR_ID_MEDIATEK;
696 writew(val, port->base + PCIE_CONF_VEND_ID);
698 val = PCI_CLASS_BRIDGE_PCI;
699 writew(val, port->base + PCIE_CONF_CLASS_ID);
702 if (soc->need_fix_device_id)
703 writew(soc->device_id, port->base + PCIE_CONF_DEVICE_ID);
705 /* 100ms timeout value should be enough for Gen1/2 training */
706 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
707 !!(val & PCIE_PORT_LINKUP_V2), 20,
708 100 * USEC_PER_MSEC);
713 val = readl(port->base + PCIE_INT_MASK);
715 writel(val, port->base + PCIE_INT_MASK);
717 if (IS_ENABLED(CONFIG_PCI_MSI))
718 mtk_pcie_enable_msi(port);
720 /* Set AHB to PCIe translation windows */
721 val = lower_32_bits(mem->start) |
722 AHB2PCIE_SIZE(fls(resource_size(mem)));
723 writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
725 val = upper_32_bits(mem->start);
726 writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
728 /* Set PCIe to AXI translation memory space.*/
729 val = PCIE2AHB_SIZE | WIN_ENABLE;
730 writel(val, port->base + PCIE_AXI_WINDOW0);
735 static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus,
736 unsigned int devfn, int where)
738 struct mtk_pcie *pcie = bus->sysdata;
740 writel(PCIE_CONF_ADDR(where, PCI_FUNC(devfn), PCI_SLOT(devfn),
741 bus->number), pcie->base + PCIE_CFG_ADDR);
743 return pcie->base + PCIE_CFG_DATA + (where & 3);
746 static struct pci_ops mtk_pcie_ops = {
747 .map_bus = mtk_pcie_map_bus,
748 .read = pci_generic_config_read,
749 .write = pci_generic_config_write,
752 static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
754 struct mtk_pcie *pcie = port->pcie;
755 u32 func = PCI_FUNC(port->slot << 3);
756 u32 slot = PCI_SLOT(port->slot << 3);
760 /* assert port PERST_N */
761 val = readl(pcie->base + PCIE_SYS_CFG);
762 val |= PCIE_PORT_PERST(port->slot);
763 writel(val, pcie->base + PCIE_SYS_CFG);
765 /* de-assert port PERST_N */
766 val = readl(pcie->base + PCIE_SYS_CFG);
767 val &= ~PCIE_PORT_PERST(port->slot);
768 writel(val, pcie->base + PCIE_SYS_CFG);
770 /* 100ms timeout value should be enough for Gen1/2 training */
771 err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val,
772 !!(val & PCIE_PORT_LINKUP), 20,
773 100 * USEC_PER_MSEC);
777 /* enable interrupt */
778 val = readl(pcie->base + PCIE_INT_ENABLE);
779 val |= PCIE_PORT_INT_EN(port->slot);
780 writel(val, pcie->base + PCIE_INT_ENABLE);
782 /* map to all DDR region. We need to set it before cfg operation. */
783 writel(PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
784 port->base + PCIE_BAR0_SETUP);
786 /* configure class code and revision ID */
787 writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS);
789 /* configure FC credit */
790 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0),
791 pcie->base + PCIE_CFG_ADDR);
792 val = readl(pcie->base + PCIE_CFG_DATA);
793 val &= ~PCIE_FC_CREDIT_MASK;
794 val |= PCIE_FC_CREDIT_VAL(0x806c);
795 writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0),
796 pcie->base + PCIE_CFG_ADDR);
797 writel(val, pcie->base + PCIE_CFG_DATA);
799 /* configure RC FTS number to 250 when it leaves L0s */
800 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
801 pcie->base + PCIE_CFG_ADDR);
802 val = readl(pcie->base + PCIE_CFG_DATA);
803 val &= ~PCIE_FTS_NUM_MASK;
804 val |= PCIE_FTS_NUM_L0(0x50);
805 writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
806 pcie->base + PCIE_CFG_ADDR);
807 writel(val, pcie->base + PCIE_CFG_DATA);
812 static void mtk_pcie_enable_port(struct mtk_pcie_port *port)
814 struct mtk_pcie *pcie = port->pcie;
815 struct device *dev = pcie->dev;
818 err = clk_prepare_enable(port->sys_ck);
820 dev_err(dev, "failed to enable sys_ck%d clock\n", port->slot);
824 err = clk_prepare_enable(port->ahb_ck);
826 dev_err(dev, "failed to enable ahb_ck%d\n", port->slot);
830 err = clk_prepare_enable(port->aux_ck);
832 dev_err(dev, "failed to enable aux_ck%d\n", port->slot);
836 err = clk_prepare_enable(port->axi_ck);
838 dev_err(dev, "failed to enable axi_ck%d\n", port->slot);
842 err = clk_prepare_enable(port->obff_ck);
844 dev_err(dev, "failed to enable obff_ck%d\n", port->slot);
848 err = clk_prepare_enable(port->pipe_ck);
850 dev_err(dev, "failed to enable pipe_ck%d\n", port->slot);
854 reset_control_assert(port->reset);
855 reset_control_deassert(port->reset);
857 err = phy_init(port->phy);
859 dev_err(dev, "failed to initialize port%d phy\n", port->slot);
863 err = phy_power_on(port->phy);
865 dev_err(dev, "failed to power on port%d phy\n", port->slot);
869 if (!pcie->soc->startup(port))
872 dev_info(dev, "Port%d link down\n", port->slot);
874 phy_power_off(port->phy);
878 clk_disable_unprepare(port->pipe_ck);
880 clk_disable_unprepare(port->obff_ck);
882 clk_disable_unprepare(port->axi_ck);
884 clk_disable_unprepare(port->aux_ck);
886 clk_disable_unprepare(port->ahb_ck);
888 clk_disable_unprepare(port->sys_ck);
890 mtk_pcie_port_free(port);
893 static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
894 struct device_node *node,
897 struct mtk_pcie_port *port;
898 struct resource *regs;
899 struct device *dev = pcie->dev;
900 struct platform_device *pdev = to_platform_device(dev);
904 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
908 snprintf(name, sizeof(name), "port%d", slot);
909 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
910 port->base = devm_ioremap_resource(dev, regs);
911 if (IS_ERR(port->base)) {
912 dev_err(dev, "failed to map port%d base\n", slot);
913 return PTR_ERR(port->base);
916 snprintf(name, sizeof(name), "sys_ck%d", slot);
917 port->sys_ck = devm_clk_get(dev, name);
918 if (IS_ERR(port->sys_ck)) {
919 dev_err(dev, "failed to get sys_ck%d clock\n", slot);
920 return PTR_ERR(port->sys_ck);
923 /* sys_ck might be divided into the following parts in some chips */
924 snprintf(name, sizeof(name), "ahb_ck%d", slot);
925 port->ahb_ck = devm_clk_get_optional(dev, name);
926 if (IS_ERR(port->ahb_ck))
927 return PTR_ERR(port->ahb_ck);
929 snprintf(name, sizeof(name), "axi_ck%d", slot);
930 port->axi_ck = devm_clk_get_optional(dev, name);
931 if (IS_ERR(port->axi_ck))
932 return PTR_ERR(port->axi_ck);
934 snprintf(name, sizeof(name), "aux_ck%d", slot);
935 port->aux_ck = devm_clk_get_optional(dev, name);
936 if (IS_ERR(port->aux_ck))
937 return PTR_ERR(port->aux_ck);
939 snprintf(name, sizeof(name), "obff_ck%d", slot);
940 port->obff_ck = devm_clk_get_optional(dev, name);
941 if (IS_ERR(port->obff_ck))
942 return PTR_ERR(port->obff_ck);
944 snprintf(name, sizeof(name), "pipe_ck%d", slot);
945 port->pipe_ck = devm_clk_get_optional(dev, name);
946 if (IS_ERR(port->pipe_ck))
947 return PTR_ERR(port->pipe_ck);
949 snprintf(name, sizeof(name), "pcie-rst%d", slot);
950 port->reset = devm_reset_control_get_optional_exclusive(dev, name);
951 if (PTR_ERR(port->reset) == -EPROBE_DEFER)
952 return PTR_ERR(port->reset);
954 /* some platforms may use default PHY setting */
955 snprintf(name, sizeof(name), "pcie-phy%d", slot);
956 port->phy = devm_phy_optional_get(dev, name);
957 if (IS_ERR(port->phy))
958 return PTR_ERR(port->phy);
963 if (pcie->soc->setup_irq) {
964 err = pcie->soc->setup_irq(port, node);
969 INIT_LIST_HEAD(&port->list);
970 list_add_tail(&port->list, &pcie->ports);
975 static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie)
977 struct device *dev = pcie->dev;
978 struct platform_device *pdev = to_platform_device(dev);
979 struct resource *regs;
982 /* get shared registers, which are optional */
983 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "subsys");
985 pcie->base = devm_ioremap_resource(dev, regs);
986 if (IS_ERR(pcie->base)) {
987 dev_err(dev, "failed to map shared register\n");
988 return PTR_ERR(pcie->base);
992 pcie->free_ck = devm_clk_get(dev, "free_ck");
993 if (IS_ERR(pcie->free_ck)) {
994 if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER)
995 return -EPROBE_DEFER;
997 pcie->free_ck = NULL;
1000 pm_runtime_enable(dev);
1001 pm_runtime_get_sync(dev);
1003 /* enable top level clock */
1004 err = clk_prepare_enable(pcie->free_ck);
1006 dev_err(dev, "failed to enable free_ck\n");
1013 pm_runtime_put_sync(dev);
1014 pm_runtime_disable(dev);
1019 static int mtk_pcie_setup(struct mtk_pcie *pcie)
1021 struct device *dev = pcie->dev;
1022 struct device_node *node = dev->of_node, *child;
1023 struct mtk_pcie_port *port, *tmp;
1024 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1025 struct list_head *windows = &host->windows;
1026 struct resource_entry *win, *tmp_win;
1027 resource_size_t io_base;
1030 err = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff,
1035 err = devm_request_pci_bus_resources(dev, windows);
1039 /* Get the I/O and memory ranges from DT */
1040 resource_list_for_each_entry_safe(win, tmp_win, windows) {
1041 switch (resource_type(win->res)) {
1043 err = devm_pci_remap_iospace(dev, win->res, io_base);
1045 dev_warn(dev, "error %d: failed to map resource %pR\n",
1047 resource_list_destroy_entry(win);
1050 case IORESOURCE_MEM:
1051 memcpy(&pcie->mem, win->res, sizeof(*win->res));
1052 pcie->mem.name = "non-prefetchable";
1054 case IORESOURCE_BUS:
1055 pcie->busnr = win->res->start;
1060 for_each_available_child_of_node(node, child) {
1063 err = of_pci_get_devfn(child);
1065 dev_err(dev, "failed to parse devfn: %d\n", err);
1069 slot = PCI_SLOT(err);
1071 err = mtk_pcie_parse_port(pcie, child, slot);
1076 err = mtk_pcie_subsys_powerup(pcie);
1080 /* enable each port, and then check link status */
1081 list_for_each_entry_safe(port, tmp, &pcie->ports, list)
1082 mtk_pcie_enable_port(port);
1084 /* power down PCIe subsys if slots are all empty (link down) */
1085 if (list_empty(&pcie->ports))
1086 mtk_pcie_subsys_powerdown(pcie);
1091 static int mtk_pcie_probe(struct platform_device *pdev)
1093 struct device *dev = &pdev->dev;
1094 struct mtk_pcie *pcie;
1095 struct pci_host_bridge *host;
1098 host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
1102 pcie = pci_host_bridge_priv(host);
1105 pcie->soc = of_device_get_match_data(dev);
1106 platform_set_drvdata(pdev, pcie);
1107 INIT_LIST_HEAD(&pcie->ports);
1109 err = mtk_pcie_setup(pcie);
1113 host->busnr = pcie->busnr;
1114 host->dev.parent = pcie->dev;
1115 host->ops = pcie->soc->ops;
1116 host->map_irq = of_irq_parse_and_map_pci;
1117 host->swizzle_irq = pci_common_swizzle;
1118 host->sysdata = pcie;
1120 err = pci_host_probe(host);
1127 if (!list_empty(&pcie->ports))
1128 mtk_pcie_put_resources(pcie);
1134 static void mtk_pcie_free_resources(struct mtk_pcie *pcie)
1136 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1137 struct list_head *windows = &host->windows;
1139 pci_free_resource_list(windows);
1142 static int mtk_pcie_remove(struct platform_device *pdev)
1144 struct mtk_pcie *pcie = platform_get_drvdata(pdev);
1145 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1147 pci_stop_root_bus(host->bus);
1148 pci_remove_root_bus(host->bus);
1149 mtk_pcie_free_resources(pcie);
1151 mtk_pcie_irq_teardown(pcie);
1153 mtk_pcie_put_resources(pcie);
1158 static int __maybe_unused mtk_pcie_suspend_noirq(struct device *dev)
1160 struct mtk_pcie *pcie = dev_get_drvdata(dev);
1161 struct mtk_pcie_port *port;
1163 if (list_empty(&pcie->ports))
1166 list_for_each_entry(port, &pcie->ports, list) {
1167 clk_disable_unprepare(port->pipe_ck);
1168 clk_disable_unprepare(port->obff_ck);
1169 clk_disable_unprepare(port->axi_ck);
1170 clk_disable_unprepare(port->aux_ck);
1171 clk_disable_unprepare(port->ahb_ck);
1172 clk_disable_unprepare(port->sys_ck);
1173 phy_power_off(port->phy);
1174 phy_exit(port->phy);
1177 clk_disable_unprepare(pcie->free_ck);
1182 static int __maybe_unused mtk_pcie_resume_noirq(struct device *dev)
1184 struct mtk_pcie *pcie = dev_get_drvdata(dev);
1185 struct mtk_pcie_port *port, *tmp;
1187 if (list_empty(&pcie->ports))
1190 clk_prepare_enable(pcie->free_ck);
1192 list_for_each_entry_safe(port, tmp, &pcie->ports, list)
1193 mtk_pcie_enable_port(port);
1195 /* In case of EP was removed while system suspend. */
1196 if (list_empty(&pcie->ports))
1197 clk_disable_unprepare(pcie->free_ck);
1202 static const struct dev_pm_ops mtk_pcie_pm_ops = {
1203 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq,
1204 mtk_pcie_resume_noirq)
1207 static const struct mtk_pcie_soc mtk_pcie_soc_v1 = {
1208 .ops = &mtk_pcie_ops,
1209 .startup = mtk_pcie_startup_port,
1212 static const struct mtk_pcie_soc mtk_pcie_soc_mt2712 = {
1213 .ops = &mtk_pcie_ops_v2,
1214 .startup = mtk_pcie_startup_port_v2,
1215 .setup_irq = mtk_pcie_setup_irq,
1218 static const struct mtk_pcie_soc mtk_pcie_soc_mt7622 = {
1219 .need_fix_class_id = true,
1220 .ops = &mtk_pcie_ops_v2,
1221 .startup = mtk_pcie_startup_port_v2,
1222 .setup_irq = mtk_pcie_setup_irq,
1225 static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = {
1226 .need_fix_class_id = true,
1227 .need_fix_device_id = true,
1228 .device_id = PCI_DEVICE_ID_MEDIATEK_7629,
1229 .ops = &mtk_pcie_ops_v2,
1230 .startup = mtk_pcie_startup_port_v2,
1231 .setup_irq = mtk_pcie_setup_irq,
1234 static const struct of_device_id mtk_pcie_ids[] = {
1235 { .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 },
1236 { .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 },
1237 { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 },
1238 { .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 },
1239 { .compatible = "mediatek,mt7629-pcie", .data = &mtk_pcie_soc_mt7629 },
1243 static struct platform_driver mtk_pcie_driver = {
1244 .probe = mtk_pcie_probe,
1245 .remove = mtk_pcie_remove,
1248 .of_match_table = mtk_pcie_ids,
1249 .suppress_bind_attrs = true,
1250 .pm = &mtk_pcie_pm_ops,
1253 module_platform_driver(mtk_pcie_driver);
1254 MODULE_LICENSE("GPL v2");