1 // SPDX-License-Identifier: GPL-2.0
3 * Qualcomm PCIe root complex driver
5 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 * Copyright 2015 Linaro Limited.
8 * Author: Stanimir Varbanov <svarbanov@mm-sol.com>
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/gpio/consumer.h>
14 #include <linux/interrupt.h>
16 #include <linux/iopoll.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/of_device.h>
20 #include <linux/of_gpio.h>
21 #include <linux/pci.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/platform_device.h>
24 #include <linux/phy/phy.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/reset.h>
27 #include <linux/slab.h>
28 #include <linux/types.h>
30 #include "pcie-designware.h"
32 #define PCIE20_PARF_SYS_CTRL 0x00
33 #define MST_WAKEUP_EN BIT(13)
34 #define SLV_WAKEUP_EN BIT(12)
35 #define MSTR_ACLK_CGC_DIS BIT(10)
36 #define SLV_ACLK_CGC_DIS BIT(9)
37 #define CORE_CLK_CGC_DIS BIT(6)
38 #define AUX_PWR_DET BIT(4)
39 #define L23_CLK_RMV_DIS BIT(2)
40 #define L1_CLK_RMV_DIS BIT(1)
42 #define PCIE20_COMMAND_STATUS 0x04
43 #define CMD_BME_VAL 0x4
44 #define PCIE20_DEVICE_CONTROL2_STATUS2 0x98
45 #define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10
47 #define PCIE20_PARF_PHY_CTRL 0x40
48 #define PCIE20_PARF_PHY_REFCLK 0x4C
49 #define PCIE20_PARF_DBI_BASE_ADDR 0x168
50 #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C
51 #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174
52 #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178
53 #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8
54 #define PCIE20_PARF_LTSSM 0x1B0
55 #define PCIE20_PARF_SID_OFFSET 0x234
56 #define PCIE20_PARF_BDF_TRANSLATE_CFG 0x24C
58 #define PCIE20_ELBI_SYS_CTRL 0x04
59 #define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0)
61 #define PCIE20_AXI_MSTR_RESP_COMP_CTRL0 0x818
62 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K 0x4
63 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_4K 0x5
64 #define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c
65 #define CFG_BRIDGE_SB_INIT BIT(0)
67 #define PCIE20_CAP 0x70
68 #define PCIE20_CAP_LINK_CAPABILITIES (PCIE20_CAP + 0xC)
69 #define PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT (BIT(10) | BIT(11))
70 #define PCIE20_CAP_LINK_1 (PCIE20_CAP + 0x14)
71 #define PCIE_CAP_LINK1_VAL 0x2FD7F
73 #define PCIE20_PARF_Q2A_FLUSH 0x1AC
75 #define PCIE20_MISC_CONTROL_1_REG 0x8BC
76 #define DBI_RO_WR_EN 1
78 #define PERST_DELAY_US 1000
80 #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
81 #define SLV_ADDR_SPACE_SZ 0x10000000
83 #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
84 struct qcom_pcie_resources_2_1_0 {
85 struct clk *iface_clk;
88 struct reset_control *pci_reset;
89 struct reset_control *axi_reset;
90 struct reset_control *ahb_reset;
91 struct reset_control *por_reset;
92 struct reset_control *phy_reset;
93 struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];
96 struct qcom_pcie_resources_1_0_0 {
99 struct clk *master_bus;
100 struct clk *slave_bus;
101 struct reset_control *core;
102 struct regulator *vdda;
105 #define QCOM_PCIE_2_3_2_MAX_SUPPLY 2
106 struct qcom_pcie_resources_2_3_2 {
108 struct clk *master_clk;
109 struct clk *slave_clk;
111 struct clk *pipe_clk;
112 struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY];
115 #define QCOM_PCIE_2_4_0_MAX_CLOCKS 4
116 struct qcom_pcie_resources_2_4_0 {
117 struct clk_bulk_data clks[QCOM_PCIE_2_4_0_MAX_CLOCKS];
119 struct reset_control *axi_m_reset;
120 struct reset_control *axi_s_reset;
121 struct reset_control *pipe_reset;
122 struct reset_control *axi_m_vmid_reset;
123 struct reset_control *axi_s_xpu_reset;
124 struct reset_control *parf_reset;
125 struct reset_control *phy_reset;
126 struct reset_control *axi_m_sticky_reset;
127 struct reset_control *pipe_sticky_reset;
128 struct reset_control *pwr_reset;
129 struct reset_control *ahb_reset;
130 struct reset_control *phy_ahb_reset;
133 struct qcom_pcie_resources_2_3_3 {
135 struct clk *axi_m_clk;
136 struct clk *axi_s_clk;
139 struct reset_control *rst[7];
142 union qcom_pcie_resources {
143 struct qcom_pcie_resources_1_0_0 v1_0_0;
144 struct qcom_pcie_resources_2_1_0 v2_1_0;
145 struct qcom_pcie_resources_2_3_2 v2_3_2;
146 struct qcom_pcie_resources_2_3_3 v2_3_3;
147 struct qcom_pcie_resources_2_4_0 v2_4_0;
152 struct qcom_pcie_ops {
153 int (*get_resources)(struct qcom_pcie *pcie);
154 int (*init)(struct qcom_pcie *pcie);
155 int (*post_init)(struct qcom_pcie *pcie);
156 void (*deinit)(struct qcom_pcie *pcie);
157 void (*post_deinit)(struct qcom_pcie *pcie);
158 void (*ltssm_enable)(struct qcom_pcie *pcie);
163 void __iomem *parf; /* DT parf */
164 void __iomem *elbi; /* DT elbi */
165 union qcom_pcie_resources res;
167 struct gpio_desc *reset;
168 const struct qcom_pcie_ops *ops;
171 #define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
173 static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
175 gpiod_set_value_cansleep(pcie->reset, 1);
176 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
179 static void qcom_ep_reset_deassert(struct qcom_pcie *pcie)
181 /* Ensure that PERST has been asserted for at least 100 ms */
183 gpiod_set_value_cansleep(pcie->reset, 0);
184 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
187 static int qcom_pcie_establish_link(struct qcom_pcie *pcie)
189 struct dw_pcie *pci = pcie->pci;
191 if (dw_pcie_link_up(pci))
194 /* Enable Link Training state machine */
195 if (pcie->ops->ltssm_enable)
196 pcie->ops->ltssm_enable(pcie);
198 return dw_pcie_wait_for_link(pci);
201 static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie)
205 /* enable link training */
206 val = readl(pcie->elbi + PCIE20_ELBI_SYS_CTRL);
207 val |= PCIE20_ELBI_SYS_CTRL_LT_ENABLE;
208 writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL);
211 static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
213 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
214 struct dw_pcie *pci = pcie->pci;
215 struct device *dev = pci->dev;
218 res->supplies[0].supply = "vdda";
219 res->supplies[1].supply = "vdda_phy";
220 res->supplies[2].supply = "vdda_refclk";
221 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
226 res->iface_clk = devm_clk_get(dev, "iface");
227 if (IS_ERR(res->iface_clk))
228 return PTR_ERR(res->iface_clk);
230 res->core_clk = devm_clk_get(dev, "core");
231 if (IS_ERR(res->core_clk))
232 return PTR_ERR(res->core_clk);
234 res->phy_clk = devm_clk_get(dev, "phy");
235 if (IS_ERR(res->phy_clk))
236 return PTR_ERR(res->phy_clk);
238 res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
239 if (IS_ERR(res->pci_reset))
240 return PTR_ERR(res->pci_reset);
242 res->axi_reset = devm_reset_control_get_exclusive(dev, "axi");
243 if (IS_ERR(res->axi_reset))
244 return PTR_ERR(res->axi_reset);
246 res->ahb_reset = devm_reset_control_get_exclusive(dev, "ahb");
247 if (IS_ERR(res->ahb_reset))
248 return PTR_ERR(res->ahb_reset);
250 res->por_reset = devm_reset_control_get_exclusive(dev, "por");
251 if (IS_ERR(res->por_reset))
252 return PTR_ERR(res->por_reset);
254 res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
255 return PTR_ERR_OR_ZERO(res->phy_reset);
258 static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
260 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
262 reset_control_assert(res->pci_reset);
263 reset_control_assert(res->axi_reset);
264 reset_control_assert(res->ahb_reset);
265 reset_control_assert(res->por_reset);
266 reset_control_assert(res->pci_reset);
267 clk_disable_unprepare(res->iface_clk);
268 clk_disable_unprepare(res->core_clk);
269 clk_disable_unprepare(res->phy_clk);
270 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
273 static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
275 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
276 struct dw_pcie *pci = pcie->pci;
277 struct device *dev = pci->dev;
281 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
283 dev_err(dev, "cannot enable regulators\n");
287 ret = reset_control_assert(res->ahb_reset);
289 dev_err(dev, "cannot assert ahb reset\n");
293 ret = clk_prepare_enable(res->iface_clk);
295 dev_err(dev, "cannot prepare/enable iface clock\n");
299 ret = clk_prepare_enable(res->phy_clk);
301 dev_err(dev, "cannot prepare/enable phy clock\n");
305 ret = clk_prepare_enable(res->core_clk);
307 dev_err(dev, "cannot prepare/enable core clock\n");
311 ret = reset_control_deassert(res->ahb_reset);
313 dev_err(dev, "cannot deassert ahb reset\n");
314 goto err_deassert_ahb;
317 /* enable PCIe clocks and resets */
318 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
320 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
322 /* enable external reference clock */
323 val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
325 writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
327 ret = reset_control_deassert(res->phy_reset);
329 dev_err(dev, "cannot deassert phy reset\n");
333 ret = reset_control_deassert(res->pci_reset);
335 dev_err(dev, "cannot deassert pci reset\n");
339 ret = reset_control_deassert(res->por_reset);
341 dev_err(dev, "cannot deassert por reset\n");
345 ret = reset_control_deassert(res->axi_reset);
347 dev_err(dev, "cannot deassert axi reset\n");
351 /* wait for clock acquisition */
352 usleep_range(1000, 1500);
355 /* Set the Max TLP size to 2K, instead of using default of 4K */
356 writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K,
357 pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
358 writel(CFG_BRIDGE_SB_INIT,
359 pci->dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
364 clk_disable_unprepare(res->core_clk);
366 clk_disable_unprepare(res->phy_clk);
368 clk_disable_unprepare(res->iface_clk);
370 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
375 static int qcom_pcie_get_resources_1_0_0(struct qcom_pcie *pcie)
377 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
378 struct dw_pcie *pci = pcie->pci;
379 struct device *dev = pci->dev;
381 res->vdda = devm_regulator_get(dev, "vdda");
382 if (IS_ERR(res->vdda))
383 return PTR_ERR(res->vdda);
385 res->iface = devm_clk_get(dev, "iface");
386 if (IS_ERR(res->iface))
387 return PTR_ERR(res->iface);
389 res->aux = devm_clk_get(dev, "aux");
390 if (IS_ERR(res->aux))
391 return PTR_ERR(res->aux);
393 res->master_bus = devm_clk_get(dev, "master_bus");
394 if (IS_ERR(res->master_bus))
395 return PTR_ERR(res->master_bus);
397 res->slave_bus = devm_clk_get(dev, "slave_bus");
398 if (IS_ERR(res->slave_bus))
399 return PTR_ERR(res->slave_bus);
401 res->core = devm_reset_control_get_exclusive(dev, "core");
402 return PTR_ERR_OR_ZERO(res->core);
405 static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pcie)
407 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
409 reset_control_assert(res->core);
410 clk_disable_unprepare(res->slave_bus);
411 clk_disable_unprepare(res->master_bus);
412 clk_disable_unprepare(res->iface);
413 clk_disable_unprepare(res->aux);
414 regulator_disable(res->vdda);
417 static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie)
419 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
420 struct dw_pcie *pci = pcie->pci;
421 struct device *dev = pci->dev;
424 ret = reset_control_deassert(res->core);
426 dev_err(dev, "cannot deassert core reset\n");
430 ret = clk_prepare_enable(res->aux);
432 dev_err(dev, "cannot prepare/enable aux clock\n");
436 ret = clk_prepare_enable(res->iface);
438 dev_err(dev, "cannot prepare/enable iface clock\n");
442 ret = clk_prepare_enable(res->master_bus);
444 dev_err(dev, "cannot prepare/enable master_bus clock\n");
448 ret = clk_prepare_enable(res->slave_bus);
450 dev_err(dev, "cannot prepare/enable slave_bus clock\n");
454 ret = regulator_enable(res->vdda);
456 dev_err(dev, "cannot enable vdda regulator\n");
460 /* change DBI base address */
461 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
463 if (IS_ENABLED(CONFIG_PCI_MSI)) {
464 u32 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
467 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
472 clk_disable_unprepare(res->slave_bus);
474 clk_disable_unprepare(res->master_bus);
476 clk_disable_unprepare(res->iface);
478 clk_disable_unprepare(res->aux);
480 reset_control_assert(res->core);
485 static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie)
489 /* enable link training */
490 val = readl(pcie->parf + PCIE20_PARF_LTSSM);
492 writel(val, pcie->parf + PCIE20_PARF_LTSSM);
495 static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie)
497 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
498 struct dw_pcie *pci = pcie->pci;
499 struct device *dev = pci->dev;
502 res->supplies[0].supply = "vdda";
503 res->supplies[1].supply = "vddpe-3v3";
504 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
509 res->aux_clk = devm_clk_get(dev, "aux");
510 if (IS_ERR(res->aux_clk))
511 return PTR_ERR(res->aux_clk);
513 res->cfg_clk = devm_clk_get(dev, "cfg");
514 if (IS_ERR(res->cfg_clk))
515 return PTR_ERR(res->cfg_clk);
517 res->master_clk = devm_clk_get(dev, "bus_master");
518 if (IS_ERR(res->master_clk))
519 return PTR_ERR(res->master_clk);
521 res->slave_clk = devm_clk_get(dev, "bus_slave");
522 if (IS_ERR(res->slave_clk))
523 return PTR_ERR(res->slave_clk);
525 res->pipe_clk = devm_clk_get(dev, "pipe");
526 return PTR_ERR_OR_ZERO(res->pipe_clk);
529 static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie)
531 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
533 clk_disable_unprepare(res->slave_clk);
534 clk_disable_unprepare(res->master_clk);
535 clk_disable_unprepare(res->cfg_clk);
536 clk_disable_unprepare(res->aux_clk);
538 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
541 static void qcom_pcie_post_deinit_2_3_2(struct qcom_pcie *pcie)
543 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
545 clk_disable_unprepare(res->pipe_clk);
548 static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie)
550 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
551 struct dw_pcie *pci = pcie->pci;
552 struct device *dev = pci->dev;
556 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
558 dev_err(dev, "cannot enable regulators\n");
562 ret = clk_prepare_enable(res->aux_clk);
564 dev_err(dev, "cannot prepare/enable aux clock\n");
568 ret = clk_prepare_enable(res->cfg_clk);
570 dev_err(dev, "cannot prepare/enable cfg clock\n");
574 ret = clk_prepare_enable(res->master_clk);
576 dev_err(dev, "cannot prepare/enable master clock\n");
580 ret = clk_prepare_enable(res->slave_clk);
582 dev_err(dev, "cannot prepare/enable slave clock\n");
586 /* enable PCIe clocks and resets */
587 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
589 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
591 /* change DBI base address */
592 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
594 /* MAC PHY_POWERDOWN MUX DISABLE */
595 val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
597 writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
599 val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
601 writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
603 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
605 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
610 clk_disable_unprepare(res->master_clk);
612 clk_disable_unprepare(res->cfg_clk);
614 clk_disable_unprepare(res->aux_clk);
617 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
622 static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)
624 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
625 struct dw_pcie *pci = pcie->pci;
626 struct device *dev = pci->dev;
629 ret = clk_prepare_enable(res->pipe_clk);
631 dev_err(dev, "cannot prepare/enable pipe clock\n");
638 static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie)
640 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
641 struct dw_pcie *pci = pcie->pci;
642 struct device *dev = pci->dev;
643 bool is_ipq = of_device_is_compatible(dev->of_node, "qcom,pcie-ipq4019");
646 res->clks[0].id = "aux";
647 res->clks[1].id = "master_bus";
648 res->clks[2].id = "slave_bus";
649 res->clks[3].id = "iface";
651 /* qcom,pcie-ipq4019 is defined without "iface" */
652 res->num_clks = is_ipq ? 3 : 4;
654 ret = devm_clk_bulk_get(dev, res->num_clks, res->clks);
658 res->axi_m_reset = devm_reset_control_get_exclusive(dev, "axi_m");
659 if (IS_ERR(res->axi_m_reset))
660 return PTR_ERR(res->axi_m_reset);
662 res->axi_s_reset = devm_reset_control_get_exclusive(dev, "axi_s");
663 if (IS_ERR(res->axi_s_reset))
664 return PTR_ERR(res->axi_s_reset);
668 * These resources relates to the PHY or are secure clocks, but
669 * are controlled here for IPQ4019
671 res->pipe_reset = devm_reset_control_get_exclusive(dev, "pipe");
672 if (IS_ERR(res->pipe_reset))
673 return PTR_ERR(res->pipe_reset);
675 res->axi_m_vmid_reset = devm_reset_control_get_exclusive(dev,
677 if (IS_ERR(res->axi_m_vmid_reset))
678 return PTR_ERR(res->axi_m_vmid_reset);
680 res->axi_s_xpu_reset = devm_reset_control_get_exclusive(dev,
682 if (IS_ERR(res->axi_s_xpu_reset))
683 return PTR_ERR(res->axi_s_xpu_reset);
685 res->parf_reset = devm_reset_control_get_exclusive(dev, "parf");
686 if (IS_ERR(res->parf_reset))
687 return PTR_ERR(res->parf_reset);
689 res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
690 if (IS_ERR(res->phy_reset))
691 return PTR_ERR(res->phy_reset);
694 res->axi_m_sticky_reset = devm_reset_control_get_exclusive(dev,
696 if (IS_ERR(res->axi_m_sticky_reset))
697 return PTR_ERR(res->axi_m_sticky_reset);
699 res->pipe_sticky_reset = devm_reset_control_get_exclusive(dev,
701 if (IS_ERR(res->pipe_sticky_reset))
702 return PTR_ERR(res->pipe_sticky_reset);
704 res->pwr_reset = devm_reset_control_get_exclusive(dev, "pwr");
705 if (IS_ERR(res->pwr_reset))
706 return PTR_ERR(res->pwr_reset);
708 res->ahb_reset = devm_reset_control_get_exclusive(dev, "ahb");
709 if (IS_ERR(res->ahb_reset))
710 return PTR_ERR(res->ahb_reset);
713 res->phy_ahb_reset = devm_reset_control_get_exclusive(dev, "phy_ahb");
714 if (IS_ERR(res->phy_ahb_reset))
715 return PTR_ERR(res->phy_ahb_reset);
721 static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie)
723 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
725 reset_control_assert(res->axi_m_reset);
726 reset_control_assert(res->axi_s_reset);
727 reset_control_assert(res->pipe_reset);
728 reset_control_assert(res->pipe_sticky_reset);
729 reset_control_assert(res->phy_reset);
730 reset_control_assert(res->phy_ahb_reset);
731 reset_control_assert(res->axi_m_sticky_reset);
732 reset_control_assert(res->pwr_reset);
733 reset_control_assert(res->ahb_reset);
734 clk_bulk_disable_unprepare(res->num_clks, res->clks);
737 static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie)
739 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
740 struct dw_pcie *pci = pcie->pci;
741 struct device *dev = pci->dev;
745 ret = reset_control_assert(res->axi_m_reset);
747 dev_err(dev, "cannot assert axi master reset\n");
751 ret = reset_control_assert(res->axi_s_reset);
753 dev_err(dev, "cannot assert axi slave reset\n");
757 usleep_range(10000, 12000);
759 ret = reset_control_assert(res->pipe_reset);
761 dev_err(dev, "cannot assert pipe reset\n");
765 ret = reset_control_assert(res->pipe_sticky_reset);
767 dev_err(dev, "cannot assert pipe sticky reset\n");
771 ret = reset_control_assert(res->phy_reset);
773 dev_err(dev, "cannot assert phy reset\n");
777 ret = reset_control_assert(res->phy_ahb_reset);
779 dev_err(dev, "cannot assert phy ahb reset\n");
783 usleep_range(10000, 12000);
785 ret = reset_control_assert(res->axi_m_sticky_reset);
787 dev_err(dev, "cannot assert axi master sticky reset\n");
791 ret = reset_control_assert(res->pwr_reset);
793 dev_err(dev, "cannot assert power reset\n");
797 ret = reset_control_assert(res->ahb_reset);
799 dev_err(dev, "cannot assert ahb reset\n");
803 usleep_range(10000, 12000);
805 ret = reset_control_deassert(res->phy_ahb_reset);
807 dev_err(dev, "cannot deassert phy ahb reset\n");
811 ret = reset_control_deassert(res->phy_reset);
813 dev_err(dev, "cannot deassert phy reset\n");
817 ret = reset_control_deassert(res->pipe_reset);
819 dev_err(dev, "cannot deassert pipe reset\n");
823 ret = reset_control_deassert(res->pipe_sticky_reset);
825 dev_err(dev, "cannot deassert pipe sticky reset\n");
826 goto err_rst_pipe_sticky;
829 usleep_range(10000, 12000);
831 ret = reset_control_deassert(res->axi_m_reset);
833 dev_err(dev, "cannot deassert axi master reset\n");
837 ret = reset_control_deassert(res->axi_m_sticky_reset);
839 dev_err(dev, "cannot deassert axi master sticky reset\n");
840 goto err_rst_axi_m_sticky;
843 ret = reset_control_deassert(res->axi_s_reset);
845 dev_err(dev, "cannot deassert axi slave reset\n");
849 ret = reset_control_deassert(res->pwr_reset);
851 dev_err(dev, "cannot deassert power reset\n");
855 ret = reset_control_deassert(res->ahb_reset);
857 dev_err(dev, "cannot deassert ahb reset\n");
861 usleep_range(10000, 12000);
863 ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
867 /* enable PCIe clocks and resets */
868 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
870 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
872 /* change DBI base address */
873 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
875 /* MAC PHY_POWERDOWN MUX DISABLE */
876 val = readl(pcie->parf + PCIE20_PARF_SYS_CTRL);
878 writel(val, pcie->parf + PCIE20_PARF_SYS_CTRL);
880 val = readl(pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
882 writel(val, pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL);
884 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
886 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2);
891 reset_control_assert(res->ahb_reset);
893 reset_control_assert(res->pwr_reset);
895 reset_control_assert(res->axi_s_reset);
897 reset_control_assert(res->axi_m_sticky_reset);
898 err_rst_axi_m_sticky:
899 reset_control_assert(res->axi_m_reset);
901 reset_control_assert(res->pipe_sticky_reset);
903 reset_control_assert(res->pipe_reset);
905 reset_control_assert(res->phy_reset);
907 reset_control_assert(res->phy_ahb_reset);
911 static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie)
913 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
914 struct dw_pcie *pci = pcie->pci;
915 struct device *dev = pci->dev;
917 const char *rst_names[] = { "axi_m", "axi_s", "pipe",
918 "axi_m_sticky", "sticky",
921 res->iface = devm_clk_get(dev, "iface");
922 if (IS_ERR(res->iface))
923 return PTR_ERR(res->iface);
925 res->axi_m_clk = devm_clk_get(dev, "axi_m");
926 if (IS_ERR(res->axi_m_clk))
927 return PTR_ERR(res->axi_m_clk);
929 res->axi_s_clk = devm_clk_get(dev, "axi_s");
930 if (IS_ERR(res->axi_s_clk))
931 return PTR_ERR(res->axi_s_clk);
933 res->ahb_clk = devm_clk_get(dev, "ahb");
934 if (IS_ERR(res->ahb_clk))
935 return PTR_ERR(res->ahb_clk);
937 res->aux_clk = devm_clk_get(dev, "aux");
938 if (IS_ERR(res->aux_clk))
939 return PTR_ERR(res->aux_clk);
941 for (i = 0; i < ARRAY_SIZE(rst_names); i++) {
942 res->rst[i] = devm_reset_control_get(dev, rst_names[i]);
943 if (IS_ERR(res->rst[i]))
944 return PTR_ERR(res->rst[i]);
950 static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie)
952 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
954 clk_disable_unprepare(res->iface);
955 clk_disable_unprepare(res->axi_m_clk);
956 clk_disable_unprepare(res->axi_s_clk);
957 clk_disable_unprepare(res->ahb_clk);
958 clk_disable_unprepare(res->aux_clk);
961 static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
963 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
964 struct dw_pcie *pci = pcie->pci;
965 struct device *dev = pci->dev;
969 for (i = 0; i < ARRAY_SIZE(res->rst); i++) {
970 ret = reset_control_assert(res->rst[i]);
972 dev_err(dev, "reset #%d assert failed (%d)\n", i, ret);
977 usleep_range(2000, 2500);
979 for (i = 0; i < ARRAY_SIZE(res->rst); i++) {
980 ret = reset_control_deassert(res->rst[i]);
982 dev_err(dev, "reset #%d deassert failed (%d)\n", i,
989 * Don't have a way to see if the reset has completed.
990 * Wait for some time.
992 usleep_range(2000, 2500);
994 ret = clk_prepare_enable(res->iface);
996 dev_err(dev, "cannot prepare/enable core clock\n");
1000 ret = clk_prepare_enable(res->axi_m_clk);
1002 dev_err(dev, "cannot prepare/enable core clock\n");
1006 ret = clk_prepare_enable(res->axi_s_clk);
1008 dev_err(dev, "cannot prepare/enable axi slave clock\n");
1012 ret = clk_prepare_enable(res->ahb_clk);
1014 dev_err(dev, "cannot prepare/enable ahb clock\n");
1018 ret = clk_prepare_enable(res->aux_clk);
1020 dev_err(dev, "cannot prepare/enable aux clock\n");
1024 writel(SLV_ADDR_SPACE_SZ,
1025 pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE);
1027 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
1029 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
1031 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
1033 writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS
1034 | SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
1035 AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
1036 pcie->parf + PCIE20_PARF_SYS_CTRL);
1037 writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
1039 writel(CMD_BME_VAL, pci->dbi_base + PCIE20_COMMAND_STATUS);
1040 writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
1041 writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + PCIE20_CAP_LINK_1);
1043 val = readl(pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES);
1044 val &= ~PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT;
1045 writel(val, pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES);
1047 writel(PCIE_CAP_CPL_TIMEOUT_DISABLE, pci->dbi_base +
1048 PCIE20_DEVICE_CONTROL2_STATUS2);
1053 clk_disable_unprepare(res->ahb_clk);
1055 clk_disable_unprepare(res->axi_s_clk);
1057 clk_disable_unprepare(res->axi_m_clk);
1059 clk_disable_unprepare(res->iface);
1062 * Not checking for failure, will anyway return
1063 * the original failure in 'ret'.
1065 for (i = 0; i < ARRAY_SIZE(res->rst); i++)
1066 reset_control_assert(res->rst[i]);
1071 static int qcom_pcie_link_up(struct dw_pcie *pci)
1073 u16 val = readw(pci->dbi_base + PCIE20_CAP + PCI_EXP_LNKSTA);
1075 return !!(val & PCI_EXP_LNKSTA_DLLLA);
1078 static int qcom_pcie_host_init(struct pcie_port *pp)
1080 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1081 struct qcom_pcie *pcie = to_qcom_pcie(pci);
1084 qcom_ep_reset_assert(pcie);
1086 ret = pcie->ops->init(pcie);
1090 ret = phy_power_on(pcie->phy);
1094 if (pcie->ops->post_init) {
1095 ret = pcie->ops->post_init(pcie);
1097 goto err_disable_phy;
1100 dw_pcie_setup_rc(pp);
1102 if (IS_ENABLED(CONFIG_PCI_MSI))
1103 dw_pcie_msi_init(pp);
1105 qcom_ep_reset_deassert(pcie);
1107 ret = qcom_pcie_establish_link(pcie);
1113 qcom_ep_reset_assert(pcie);
1114 if (pcie->ops->post_deinit)
1115 pcie->ops->post_deinit(pcie);
1117 phy_power_off(pcie->phy);
1119 pcie->ops->deinit(pcie);
1124 static const struct dw_pcie_host_ops qcom_pcie_dw_ops = {
1125 .host_init = qcom_pcie_host_init,
1128 /* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */
1129 static const struct qcom_pcie_ops ops_2_1_0 = {
1130 .get_resources = qcom_pcie_get_resources_2_1_0,
1131 .init = qcom_pcie_init_2_1_0,
1132 .deinit = qcom_pcie_deinit_2_1_0,
1133 .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,
1136 /* Qcom IP rev.: 1.0.0 Synopsys IP rev.: 4.11a */
1137 static const struct qcom_pcie_ops ops_1_0_0 = {
1138 .get_resources = qcom_pcie_get_resources_1_0_0,
1139 .init = qcom_pcie_init_1_0_0,
1140 .deinit = qcom_pcie_deinit_1_0_0,
1141 .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,
1144 /* Qcom IP rev.: 2.3.2 Synopsys IP rev.: 4.21a */
1145 static const struct qcom_pcie_ops ops_2_3_2 = {
1146 .get_resources = qcom_pcie_get_resources_2_3_2,
1147 .init = qcom_pcie_init_2_3_2,
1148 .post_init = qcom_pcie_post_init_2_3_2,
1149 .deinit = qcom_pcie_deinit_2_3_2,
1150 .post_deinit = qcom_pcie_post_deinit_2_3_2,
1151 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1154 /* Qcom IP rev.: 2.4.0 Synopsys IP rev.: 4.20a */
1155 static const struct qcom_pcie_ops ops_2_4_0 = {
1156 .get_resources = qcom_pcie_get_resources_2_4_0,
1157 .init = qcom_pcie_init_2_4_0,
1158 .deinit = qcom_pcie_deinit_2_4_0,
1159 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1162 /* Qcom IP rev.: 2.3.3 Synopsys IP rev.: 4.30a */
1163 static const struct qcom_pcie_ops ops_2_3_3 = {
1164 .get_resources = qcom_pcie_get_resources_2_3_3,
1165 .init = qcom_pcie_init_2_3_3,
1166 .deinit = qcom_pcie_deinit_2_3_3,
1167 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1170 static const struct dw_pcie_ops dw_pcie_ops = {
1171 .link_up = qcom_pcie_link_up,
1174 static int qcom_pcie_probe(struct platform_device *pdev)
1176 struct device *dev = &pdev->dev;
1177 struct resource *res;
1178 struct pcie_port *pp;
1179 struct dw_pcie *pci;
1180 struct qcom_pcie *pcie;
1183 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
1187 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
1191 pm_runtime_enable(dev);
1192 ret = pm_runtime_get_sync(dev);
1194 pm_runtime_disable(dev);
1199 pci->ops = &dw_pcie_ops;
1204 pcie->ops = of_device_get_match_data(dev);
1206 pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH);
1207 if (IS_ERR(pcie->reset)) {
1208 ret = PTR_ERR(pcie->reset);
1209 goto err_pm_runtime_put;
1212 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
1213 pcie->parf = devm_ioremap_resource(dev, res);
1214 if (IS_ERR(pcie->parf)) {
1215 ret = PTR_ERR(pcie->parf);
1216 goto err_pm_runtime_put;
1219 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
1220 pci->dbi_base = devm_pci_remap_cfg_resource(dev, res);
1221 if (IS_ERR(pci->dbi_base)) {
1222 ret = PTR_ERR(pci->dbi_base);
1223 goto err_pm_runtime_put;
1226 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi");
1227 pcie->elbi = devm_ioremap_resource(dev, res);
1228 if (IS_ERR(pcie->elbi)) {
1229 ret = PTR_ERR(pcie->elbi);
1230 goto err_pm_runtime_put;
1233 pcie->phy = devm_phy_optional_get(dev, "pciephy");
1234 if (IS_ERR(pcie->phy)) {
1235 ret = PTR_ERR(pcie->phy);
1236 goto err_pm_runtime_put;
1239 ret = pcie->ops->get_resources(pcie);
1241 goto err_pm_runtime_put;
1243 pp->ops = &qcom_pcie_dw_ops;
1245 if (IS_ENABLED(CONFIG_PCI_MSI)) {
1246 pp->msi_irq = platform_get_irq_byname(pdev, "msi");
1247 if (pp->msi_irq < 0) {
1249 goto err_pm_runtime_put;
1253 ret = phy_init(pcie->phy);
1255 pm_runtime_disable(&pdev->dev);
1256 goto err_pm_runtime_put;
1259 platform_set_drvdata(pdev, pcie);
1261 ret = dw_pcie_host_init(pp);
1263 dev_err(dev, "cannot initialize host\n");
1264 pm_runtime_disable(&pdev->dev);
1265 goto err_pm_runtime_put;
1271 pm_runtime_put(dev);
1272 pm_runtime_disable(dev);
1277 static const struct of_device_id qcom_pcie_match[] = {
1278 { .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 },
1279 { .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },
1280 { .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 },
1281 { .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 },
1282 { .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 },
1283 { .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 },
1284 { .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 },
1288 static void qcom_fixup_class(struct pci_dev *dev)
1290 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
1292 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0101, qcom_fixup_class);
1293 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0104, qcom_fixup_class);
1294 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0106, qcom_fixup_class);
1295 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0107, qcom_fixup_class);
1296 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0302, qcom_fixup_class);
1297 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1000, qcom_fixup_class);
1298 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1001, qcom_fixup_class);
1300 static struct platform_driver qcom_pcie_driver = {
1301 .probe = qcom_pcie_probe,
1303 .name = "qcom-pcie",
1304 .suppress_bind_attrs = true,
1305 .of_match_table = qcom_pcie_match,
1308 builtin_platform_driver(qcom_pcie_driver);