2 * This file is part of wlcore
4 * Copyright (C) 2011 Texas Instruments Inc.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
25 #include <linux/platform_device.h>
31 /* The maximum number of Tx descriptors in all chip families */
32 #define WLCORE_MAX_TX_DESCRIPTORS 32
35 * We always allocate this number of mac addresses. If we don't
36 * have enough allocated addresses, the LAA bit is used
38 #define WLCORE_NUM_MAC_ADDRESSES 3
40 /* wl12xx/wl18xx maximum transmission power (in dBm) */
41 #define WLCORE_MAX_TXPWR 25
43 /* forward declaration */
44 struct wl1271_tx_hw_descr;
46 struct wl1271_rx_descriptor;
49 int (*setup)(struct wl1271 *wl);
50 int (*identify_chip)(struct wl1271 *wl);
51 int (*identify_fw)(struct wl1271 *wl);
52 int (*boot)(struct wl1271 *wl);
53 int (*plt_init)(struct wl1271 *wl);
54 int (*trigger_cmd)(struct wl1271 *wl, int cmd_box_addr,
55 void *buf, size_t len);
56 int (*ack_event)(struct wl1271 *wl);
57 int (*wait_for_event)(struct wl1271 *wl, enum wlcore_wait_event event,
59 int (*process_mailbox_events)(struct wl1271 *wl);
60 u32 (*calc_tx_blocks)(struct wl1271 *wl, u32 len, u32 spare_blks);
61 void (*set_tx_desc_blocks)(struct wl1271 *wl,
62 struct wl1271_tx_hw_descr *desc,
63 u32 blks, u32 spare_blks);
64 void (*set_tx_desc_data_len)(struct wl1271 *wl,
65 struct wl1271_tx_hw_descr *desc,
67 enum wl_rx_buf_align (*get_rx_buf_align)(struct wl1271 *wl,
69 int (*prepare_read)(struct wl1271 *wl, u32 rx_desc, u32 len);
70 u32 (*get_rx_packet_len)(struct wl1271 *wl, void *rx_data,
72 int (*tx_delayed_compl)(struct wl1271 *wl);
73 void (*tx_immediate_compl)(struct wl1271 *wl);
74 int (*hw_init)(struct wl1271 *wl);
75 int (*init_vif)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
76 void (*convert_fw_status)(struct wl1271 *wl, void *raw_fw_status,
77 struct wl_fw_status *fw_status);
78 u32 (*sta_get_ap_rate_mask)(struct wl1271 *wl,
79 struct wl12xx_vif *wlvif);
80 int (*get_pg_ver)(struct wl1271 *wl, s8 *ver);
81 int (*get_mac)(struct wl1271 *wl);
82 void (*set_tx_desc_csum)(struct wl1271 *wl,
83 struct wl1271_tx_hw_descr *desc,
85 void (*set_rx_csum)(struct wl1271 *wl,
86 struct wl1271_rx_descriptor *desc,
88 u32 (*ap_get_mimo_wide_rate_mask)(struct wl1271 *wl,
89 struct wl12xx_vif *wlvif);
90 int (*debugfs_init)(struct wl1271 *wl, struct dentry *rootdir);
91 int (*handle_static_data)(struct wl1271 *wl,
92 struct wl1271_static_data *static_data);
93 int (*scan_start)(struct wl1271 *wl, struct wl12xx_vif *wlvif,
94 struct cfg80211_scan_request *req);
95 int (*scan_stop)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
96 int (*sched_scan_start)(struct wl1271 *wl, struct wl12xx_vif *wlvif,
97 struct cfg80211_sched_scan_request *req,
98 struct ieee80211_scan_ies *ies);
99 void (*sched_scan_stop)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
100 int (*get_spare_blocks)(struct wl1271 *wl, bool is_gem);
101 int (*set_key)(struct wl1271 *wl, enum set_key_cmd cmd,
102 struct ieee80211_vif *vif,
103 struct ieee80211_sta *sta,
104 struct ieee80211_key_conf *key_conf);
105 int (*channel_switch)(struct wl1271 *wl,
106 struct wl12xx_vif *wlvif,
107 struct ieee80211_channel_switch *ch_switch);
108 u32 (*pre_pkt_send)(struct wl1271 *wl, u32 buf_offset, u32 last_len);
109 void (*sta_rc_update)(struct wl1271 *wl, struct wl12xx_vif *wlvif,
110 struct ieee80211_sta *sta, u32 changed);
111 int (*set_peer_cap)(struct wl1271 *wl,
112 struct ieee80211_sta_ht_cap *ht_cap,
113 bool allow_ht_operation,
114 u32 rate_set, u8 hlid);
115 u32 (*convert_hwaddr)(struct wl1271 *wl, u32 hwaddr);
116 bool (*lnk_high_prio)(struct wl1271 *wl, u8 hlid,
117 struct wl1271_link *lnk);
118 bool (*lnk_low_prio)(struct wl1271 *wl, u8 hlid,
119 struct wl1271_link *lnk);
120 int (*smart_config_start)(struct wl1271 *wl, u32 group_bitmap);
121 int (*smart_config_stop)(struct wl1271 *wl);
122 int (*smart_config_set_group_key)(struct wl1271 *wl, u16 group_id,
123 u8 key_len, u8 *key);
126 enum wlcore_partitions {
131 PART_TOP_PRCM_ELP_SOC,
137 struct wlcore_partition {
142 struct wlcore_partition_set {
143 struct wlcore_partition mem;
144 struct wlcore_partition reg;
145 struct wlcore_partition mem2;
146 struct wlcore_partition mem3;
149 enum wlcore_registers {
150 /* register addresses, used with partition translation */
152 REG_INTERRUPT_NO_CLEAR,
154 REG_COMMAND_MAILBOX_PTR,
155 REG_EVENT_MAILBOX_PTR,
160 REG_CMD_MBOX_ADDRESS,
162 /* data access memory addresses, used with partition translation */
166 /* raw data access memory addresses */
167 REG_RAW_FW_STATUS_ADDR,
172 struct wl1271_stats {
174 unsigned long fw_stats_update;
177 unsigned int retry_count;
178 unsigned int excessive_retries;
183 struct ieee80211_hw *hw;
184 bool mac80211_registered;
187 struct platform_device *pdev;
191 struct wl1271_if_operations *if_ops;
197 enum wlcore_state state;
198 enum wl12xx_fw_type fw_type;
200 enum plt_mode plt_mode;
207 struct wlcore_partition_set curr_part;
209 struct wl1271_chip chip;
220 /* address read from the fuse ROM */
224 /* we have up to 2 MAC addresses */
225 struct mac_address addresses[WLCORE_NUM_MAC_ADDRESSES];
229 unsigned long links_map[BITS_TO_LONGS(WLCORE_MAX_LINKS)];
230 unsigned long roles_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
231 unsigned long roc_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
232 unsigned long rate_policies_map[
233 BITS_TO_LONGS(WL12XX_MAX_RATE_POLICIES)];
234 unsigned long klv_templates_map[
235 BITS_TO_LONGS(WLCORE_MAX_KLV_TEMPLATES)];
237 u8 session_ids[WLCORE_MAX_LINKS];
239 struct list_head wlvif_list;
244 struct wl1271_acx_mem_map *target_mem_map;
246 /* Accounting for allocated / available TX blocks on HW */
248 u32 tx_blocks_available;
249 u32 tx_allocated_blocks;
250 u32 tx_results_count;
252 /* Accounting for allocated / available Tx packets in HW */
253 u32 tx_pkts_freed[NUM_TX_QUEUES];
254 u32 tx_allocated_pkts[NUM_TX_QUEUES];
256 /* Transmitted TX packets counter for chipset interface */
257 u32 tx_packets_count;
259 /* Time-offset between host and chipset clocks */
262 /* Frames scheduled for transmission, not handled yet */
263 int tx_queue_count[NUM_TX_QUEUES];
264 unsigned long queue_stop_reasons[
265 NUM_TX_QUEUES * WLCORE_NUM_MAC_ADDRESSES];
267 /* Frames received, not handled yet by mac80211 */
268 struct sk_buff_head deferred_rx_queue;
270 /* Frames sent, not returned yet to mac80211 */
271 struct sk_buff_head deferred_tx_queue;
273 struct work_struct tx_work;
274 struct workqueue_struct *freezable_wq;
276 /* Pending TX frames */
277 unsigned long tx_frames_map[BITS_TO_LONGS(WLCORE_MAX_TX_DESCRIPTORS)];
278 struct sk_buff *tx_frames[WLCORE_MAX_TX_DESCRIPTORS];
284 /* Intermediate buffer, used for packet aggregation */
288 /* Reusable dummy packet template */
289 struct sk_buff *dummy_packet;
291 /* Network stack work */
292 struct work_struct netstack_work;
297 /* Number of valid bytes in the FW log buffer */
300 /* FW log end marker */
303 /* FW memory block size */
304 u32 fw_mem_block_size;
306 /* Sysfs FW log entry readers wait queue */
307 wait_queue_head_t fwlog_waitq;
309 /* Hardware recovery work */
310 struct work_struct recovery_work;
311 bool watchdog_recovery;
313 /* Reg domain last configuration */
314 u32 reg_ch_conf_last[2];
315 /* Reg domain pending configuration */
316 u32 reg_ch_conf_pending[2];
318 /* Pointer that holds DMA-friendly block for the mailbox */
321 /* The mbox event mask */
323 /* events to unmask only when ap interface is up */
326 /* Mailbox pointers */
330 /* Are we currently scanning */
331 struct wl12xx_vif *scan_wlvif;
332 struct wl1271_scan scan;
333 struct delayed_work scan_complete_work;
335 struct ieee80211_vif *roc_vif;
336 struct delayed_work roc_complete_work;
338 struct wl12xx_vif *sched_vif;
340 /* The current band */
341 enum ieee80211_band band;
343 struct completion *elp_compl;
344 struct delayed_work elp_work;
349 struct wl1271_stats stats;
353 u32 buffer_busyword[WL1271_BUSY_WORD_CNT];
356 struct wl_fw_status *fw_status;
357 struct wl1271_tx_hw_res_if *tx_res_if;
359 /* Current chipset configuration */
360 struct wlcore_conf conf;
368 /* Most recently reported noise in dBm */
371 /* bands supported by this instance of wl12xx */
372 struct ieee80211_supported_band bands[WLCORE_NUM_BANDS];
375 * wowlan trigger was configured during suspend.
376 * (currently, only "ANY" trigger is supported)
379 bool irq_wake_enabled;
382 * AP-mode - links indexed by HLID. The global and broadcast links
385 struct wl1271_link links[WLCORE_MAX_LINKS];
387 /* number of currently active links */
388 int active_link_count;
390 /* Fast/slow links bitmap according to FW */
391 unsigned long fw_fast_lnk_map;
393 /* AP-mode - a bitmap of links currently in PS mode according to FW */
394 unsigned long ap_fw_ps_map;
396 /* AP-mode - a bitmap of links currently in PS mode in mac80211 */
397 unsigned long ap_ps_map;
399 /* Quirks of specific hardware revisions */
402 /* Platform limitations */
403 unsigned int platform_quirks;
405 /* number of currently active RX BA sessions */
406 int ba_rx_session_count;
408 /* Maximum number of supported RX BA sessions */
409 int ba_rx_session_count_max;
411 /* AP-mode - number of currently connected stations */
412 int active_sta_count;
414 /* Flag determining whether AP should broadcast OFDM-only rates */
417 /* last wlvif we transmitted from */
418 struct wl12xx_vif *last_wlvif;
420 /* work to fire when Tx is stuck */
421 struct delayed_work tx_watchdog_work;
423 struct wlcore_ops *ops;
424 /* pointer to the lower driver partition table */
425 const struct wlcore_partition_set *ptable;
426 /* pointer to the lower driver register table */
428 /* name of the firmwares to load - for PLT, single role, multi-role */
429 const char *plt_fw_name;
430 const char *sr_fw_name;
431 const char *mr_fw_name;
433 u8 scan_templ_id_2_4;
435 u8 sched_scan_templ_id_2_4;
436 u8 sched_scan_templ_id_5;
439 /* per-chip-family private structure */
442 /* number of TX descriptors the HW supports. */
444 /* number of RX descriptors the HW supports. */
446 /* number of links the HW supports */
448 /* max stations a single AP can support */
451 /* translate HW Tx rates to standard rate-indices */
452 const u8 **band_rate_to_idx;
454 /* size of table for HW rates that can be received from chip */
455 u8 hw_tx_rate_tbl_size;
457 /* this HW rate and below are considered HT rates for this chip */
460 /* HW HT (11n) capabilities */
461 struct ieee80211_sta_ht_cap ht_cap[WLCORE_NUM_BANDS];
463 /* size of the private FW status data */
464 size_t fw_status_len;
465 size_t fw_status_priv_len;
467 /* RX Data filter rule state - enabled/disabled */
468 unsigned long rx_filter_enabled[BITS_TO_LONGS(WL1271_MAX_RX_FILTERS)];
470 /* size of the private static data */
471 size_t static_data_priv_len;
473 /* the current channel type */
474 enum nl80211_channel_type channel_type;
476 /* mutex for protecting the tx_flush function */
477 struct mutex flush_mutex;
479 /* sleep auth value currently configured to FW */
482 /* the number of allocated MAC addresses in this chip */
485 /* minimum FW version required for the driver to work in single-role */
486 unsigned int min_sr_fw_ver[NUM_FW_VER];
488 /* minimum FW version required for the driver to work in multi-role */
489 unsigned int min_mr_fw_ver[NUM_FW_VER];
491 struct completion nvs_loading_complete;
493 /* interface combinations supported by the hw */
494 const struct ieee80211_iface_combination *iface_combinations;
495 u8 n_iface_combinations;
498 int wlcore_probe(struct wl1271 *wl, struct platform_device *pdev);
499 int wlcore_remove(struct platform_device *pdev);
500 struct ieee80211_hw *wlcore_alloc_hw(size_t priv_size, u32 aggr_buf_size,
502 int wlcore_free_hw(struct wl1271 *wl);
503 int wlcore_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
504 struct ieee80211_vif *vif,
505 struct ieee80211_sta *sta,
506 struct ieee80211_key_conf *key_conf);
507 void wlcore_regdomain_config(struct wl1271 *wl);
508 void wlcore_update_inconn_sta(struct wl1271 *wl, struct wl12xx_vif *wlvif,
509 struct wl1271_station *wl_sta, bool in_conn);
512 wlcore_set_ht_cap(struct wl1271 *wl, enum ieee80211_band band,
513 struct ieee80211_sta_ht_cap *ht_cap)
515 memcpy(&wl->ht_cap[band], ht_cap, sizeof(*ht_cap));
518 /* Tell wlcore not to care about this element when checking the version */
519 #define WLCORE_FW_VER_IGNORE -1
522 wlcore_set_min_fw_ver(struct wl1271 *wl, unsigned int chip,
523 unsigned int iftype_sr, unsigned int major_sr,
524 unsigned int subtype_sr, unsigned int minor_sr,
525 unsigned int iftype_mr, unsigned int major_mr,
526 unsigned int subtype_mr, unsigned int minor_mr)
528 wl->min_sr_fw_ver[FW_VER_CHIP] = chip;
529 wl->min_sr_fw_ver[FW_VER_IF_TYPE] = iftype_sr;
530 wl->min_sr_fw_ver[FW_VER_MAJOR] = major_sr;
531 wl->min_sr_fw_ver[FW_VER_SUBTYPE] = subtype_sr;
532 wl->min_sr_fw_ver[FW_VER_MINOR] = minor_sr;
534 wl->min_mr_fw_ver[FW_VER_CHIP] = chip;
535 wl->min_mr_fw_ver[FW_VER_IF_TYPE] = iftype_mr;
536 wl->min_mr_fw_ver[FW_VER_MAJOR] = major_mr;
537 wl->min_mr_fw_ver[FW_VER_SUBTYPE] = subtype_mr;
538 wl->min_mr_fw_ver[FW_VER_MINOR] = minor_mr;
541 /* Firmware image load chunk size */
542 #define CHUNK_SIZE 16384
546 /* Each RX/TX transaction requires an end-of-transaction transfer */
547 #define WLCORE_QUIRK_END_OF_TRANSACTION BIT(0)
549 /* the first start_role(sta) sometimes doesn't work on wl12xx */
550 #define WLCORE_QUIRK_START_STA_FAILS BIT(1)
552 /* wl127x and SPI don't support SDIO block size alignment */
553 #define WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN BIT(2)
555 /* means aggregated Rx packets are aligned to a SDIO block */
556 #define WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN BIT(3)
558 /* Older firmwares did not implement the FW logger over bus feature */
559 #define WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED BIT(4)
561 /* Older firmwares use an old NVS format */
562 #define WLCORE_QUIRK_LEGACY_NVS BIT(5)
564 /* pad only the last frame in the aggregate buffer */
565 #define WLCORE_QUIRK_TX_PAD_LAST_FRAME BIT(7)
567 /* extra header space is required for TKIP */
568 #define WLCORE_QUIRK_TKIP_HEADER_SPACE BIT(8)
570 /* Some firmwares not support sched scans while connected */
571 #define WLCORE_QUIRK_NO_SCHED_SCAN_WHILE_CONN BIT(9)
573 /* separate probe response templates for one-shot and sched scans */
574 #define WLCORE_QUIRK_DUAL_PROBE_TMPL BIT(10)
576 /* Firmware requires reg domain configuration for active calibration */
577 #define WLCORE_QUIRK_REGDOMAIN_CONF BIT(11)
579 /* The FW only support a zero session id for AP */
580 #define WLCORE_QUIRK_AP_ZERO_SESSION_ID BIT(12)
582 /* TODO: move all these common registers and values elsewhere */
583 #define HW_ACCESS_ELP_CTRL_REG 0x1FFFC
585 /* ELP register commands */
586 #define ELPCTRL_WAKE_UP 0x1
587 #define ELPCTRL_WAKE_UP_WLAN_READY 0x5
588 #define ELPCTRL_SLEEP 0x0
589 /* ELP WLAN_READY bit */
590 #define ELPCTRL_WLAN_READY 0x2
592 /*************************************************************************
594 Interrupt Trigger Register (Host -> WiLink)
596 **************************************************************************/
598 /* Hardware to Embedded CPU Interrupts - first 32-bit register set */
601 * The host sets this bit to inform the Wlan
602 * FW that a TX packet is in the XFER
605 #define INTR_TRIG_TX_PROC0 BIT(2)
608 * The host sets this bit to inform the FW
609 * that it read a packet from RX XFER
612 #define INTR_TRIG_RX_PROC0 BIT(3)
614 #define INTR_TRIG_DEBUG_ACK BIT(4)
616 #define INTR_TRIG_STATE_CHANGED BIT(5)
618 /* Hardware to Embedded CPU Interrupts - second 32-bit register set */
621 * The host sets this bit to inform the FW
622 * that it read a packet from RX XFER
625 #define INTR_TRIG_RX_PROC1 BIT(17)
628 * The host sets this bit to inform the Wlan
629 * hardware that a TX packet is in the XFER
632 #define INTR_TRIG_TX_PROC1 BIT(18)
634 #define ACX_SLV_SOFT_RESET_BIT BIT(1)
635 #define SOFT_RESET_MAX_TIME 1000000
636 #define SOFT_RESET_STALL_TIME 1000
638 #define ECPU_CONTROL_HALT 0x00000101
640 #define WELP_ARM_COMMAND_VAL 0x4
642 #endif /* __WLCORE_H__ */