drivers/net/wireless/rtlwifi/rtl8723ae/sw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "../wifi.h"
  31 #include <linux/vmalloc.h>
  32 #include <linux/module.h>
  33
  34 #include "../core.h"
  35 #include "../pci.h"
  36 #include "../base.h"
  37 #include "reg.h"
  38 #include "def.h"
  39 #include "phy.h"
  40 #include "../rtl8723com/phy_common.h"
  41 #include "dm.h"
  42 #include "hw.h"
  43 #include "fw.h"
  44 #include "../rtl8723com/fw_common.h"
  45 #include "sw.h"
  46 #include "trx.h"
  47 #include "led.h"
  48 #include "table.h"
  49 #include "hal_btc.h"
  50
  51 static void rtl8723ae_init_aspm_vars(struct ieee80211_hw *hw)
  52 {
  53         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  54
  55         /*close ASPM for AMD defaultly */
  56         rtlpci->const_amdpci_aspm = 0;
  57
  58         /* ASPM PS mode.
  59          * 0 - Disable ASPM,
  60          * 1 - Enable ASPM without Clock Req,
  61          * 2 - Enable ASPM with Clock Req,
  62          * 3 - Alwyas Enable ASPM with Clock Req,
  63          * 4 - Always Enable ASPM without Clock Req.
  64          * set defult to RTL8192CE:3 RTL8192E:2
  65          */
  66         rtlpci->const_pci_aspm = 3;
  67
  68         /*Setting for PCI-E device */
  69         rtlpci->const_devicepci_aspm_setting = 0x03;
  70
  71         /*Setting for PCI-E bridge */
  72         rtlpci->const_hostpci_aspm_setting = 0x02;
  73
  74         /* In Hw/Sw Radio Off situation.
  75          * 0 - Default,
  76          * 1 - From ASPM setting without low Mac Pwr,
  77          * 2 - From ASPM setting with low Mac Pwr,
  78          * 3 - Bus D3
  79          * set default to RTL8192CE:0 RTL8192SE:2
  80          */
  81         rtlpci->const_hwsw_rfoff_d3 = 0;
  82
  83         /* This setting works for those device with
  84          * backdoor ASPM setting such as EPHY setting.
  85          * 0 - Not support ASPM,
  86          * 1 - Support ASPM,
  87          * 2 - According to chipset.
  88          */
  89         rtlpci->const_support_pciaspm = 1;
  90 }
  91
  92 int rtl8723ae_init_sw_vars(struct ieee80211_hw *hw)
  93 {
  94         struct rtl_priv *rtlpriv = rtl_priv(hw);
  95         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  96         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  97         int err;
  98
  99         rtl8723ae_bt_reg_init(hw);
 100         rtlpriv->dm.dm_initialgain_enable = 1;
 101         rtlpriv->dm.dm_flag = 0;
 102         rtlpriv->dm.disable_framebursting = 0;
 103         rtlpriv->dm.thermalvalue = 0;
 104         rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13);
 105
 106         /* compatible 5G band 88ce just 2.4G band & smsp */
 107         rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
 108         rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
 109         rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
 110
 111         rtlpci->receive_config = (RCR_APPFCS |
 112                                   RCR_APP_MIC |
 113                                   RCR_APP_ICV |
 114                                   RCR_APP_PHYST_RXFF |
 115                                   RCR_HTC_LOC_CTRL |
 116                                   RCR_AMF |
 117                                   RCR_ACF |
 118                                   RCR_ADF |
 119                                   RCR_AICV |
 120                                   RCR_AB |
 121                                   RCR_AM |
 122                                   RCR_APM |
 123                                   0);
 124
 125         rtlpci->irq_mask[0] =
 126             (u32) (PHIMR_ROK |
 127                    PHIMR_RDU |
 128                    PHIMR_VODOK |
 129                    PHIMR_VIDOK |
 130                    PHIMR_BEDOK |
 131                    PHIMR_BKDOK |
 132                    PHIMR_MGNTDOK |
 133                    PHIMR_HIGHDOK |
 134                    PHIMR_C2HCMD |
 135                    PHIMR_HISRE_IND |
 136                    PHIMR_TSF_BIT32_TOGGLE |
 137                    PHIMR_TXBCNOK |
 138                    PHIMR_PSTIMEOUT |
 139                    0);
 140
 141         rtlpci->irq_mask[1] = (u32)(PHIMR_RXFOVW | 0);
 142
 143         /* for debug level */
 144         rtlpriv->dbg.global_debuglevel = rtlpriv->cfg->mod_params->debug;
 145         /* for LPS & IPS */
 146         rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
 147         rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
 148         rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
 149         rtlpriv->psc.reg_fwctrl_lps = 3;
 150         rtlpriv->psc.reg_max_lps_awakeintvl = 5;
 151         /* for ASPM, you can close aspm through
 152          * set const_support_pciaspm = 0
 153          */
 154         rtl8723ae_init_aspm_vars(hw);
 155
 156         if (rtlpriv->psc.reg_fwctrl_lps == 1)
 157                 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
 158         else if (rtlpriv->psc.reg_fwctrl_lps == 2)
 159                 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
 160         else if (rtlpriv->psc.reg_fwctrl_lps == 3)
 161                 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
 162
 163         /* for firmware buf */
 164         rtlpriv->rtlhal.pfirmware = vmalloc(0x6000);
 165         if (!rtlpriv->rtlhal.pfirmware) {
 166                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 167                          "Can't alloc buffer for fw.\n");
 168                 return 1;
 169         }
 170
 171         if (IS_VENDOR_8723_A_CUT(rtlhal->version))
 172                 rtlpriv->cfg->fw_name = "/*(DEBLOBBED)*/";
 173         else if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version))
 174                 rtlpriv->cfg->fw_name = "/*(DEBLOBBED)*/";
 175
 176         rtlpriv->max_fw_size = 0x6000;
 177         pr_info("Using firmware %s\n", rtlpriv->cfg->fw_name);
 178         err = reject_firmware_nowait(THIS_MODULE, 1, rtlpriv->cfg->fw_name,
 179                                       rtlpriv->io.dev, GFP_KERNEL, hw,
 180                                       rtl_fw_cb);
 181         if (err) {
 182                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 183                          "Failed to request firmware!\n");
 184                 return 1;
 185         }
 186         return 0;
 187 }
 188
 189 void rtl8723ae_deinit_sw_vars(struct ieee80211_hw *hw)
 190 {
 191         struct rtl_priv *rtlpriv = rtl_priv(hw);
 192
 193         if (rtlpriv->rtlhal.pfirmware) {
 194                 vfree(rtlpriv->rtlhal.pfirmware);
 195                 rtlpriv->rtlhal.pfirmware = NULL;
 196         }
 197 }
 198
 199 static bool is_fw_header(struct rtl92c_firmware_header *hdr)
 200 {
 201         return (hdr->signature & 0xfff0) == 0x2300;
 202 }
 203
 204 static struct rtl_hal_ops rtl8723ae_hal_ops = {
 205         .init_sw_vars = rtl8723ae_init_sw_vars,
 206         .deinit_sw_vars = rtl8723ae_deinit_sw_vars,
 207         .read_eeprom_info = rtl8723ae_read_eeprom_info,
 208         .interrupt_recognized = rtl8723ae_interrupt_recognized,
 209         .hw_init = rtl8723ae_hw_init,
 210         .hw_disable = rtl8723ae_card_disable,
 211         .hw_suspend = rtl8723ae_suspend,
 212         .hw_resume = rtl8723ae_resume,
 213         .enable_interrupt = rtl8723ae_enable_interrupt,
 214         .disable_interrupt = rtl8723ae_disable_interrupt,
 215         .set_network_type = rtl8723ae_set_network_type,
 216         .set_chk_bssid = rtl8723ae_set_check_bssid,
 217         .set_qos = rtl8723ae_set_qos,
 218         .set_bcn_reg = rtl8723ae_set_beacon_related_registers,
 219         .set_bcn_intv = rtl8723ae_set_beacon_interval,
 220         .update_interrupt_mask = rtl8723ae_update_interrupt_mask,
 221         .get_hw_reg = rtl8723ae_get_hw_reg,
 222         .set_hw_reg = rtl8723ae_set_hw_reg,
 223         .update_rate_tbl = rtl8723ae_update_hal_rate_tbl,
 224         .fill_tx_desc = rtl8723ae_tx_fill_desc,
 225         .fill_tx_cmddesc = rtl8723ae_tx_fill_cmddesc,
 226         .query_rx_desc = rtl8723ae_rx_query_desc,
 227         .set_channel_access = rtl8723ae_update_channel_access_setting,
 228         .radio_onoff_checking = rtl8723ae_gpio_radio_on_off_checking,
 229         .set_bw_mode = rtl8723ae_phy_set_bw_mode,
 230         .switch_channel = rtl8723ae_phy_sw_chnl,
 231         .dm_watchdog = rtl8723ae_dm_watchdog,
 232         .scan_operation_backup = rtl_phy_scan_operation_backup,
 233         .set_rf_power_state = rtl8723ae_phy_set_rf_power_state,
 234         .led_control = rtl8723ae_led_control,
 235         .set_desc = rtl8723ae_set_desc,
 236         .get_desc = rtl8723ae_get_desc,
 237         .tx_polling = rtl8723ae_tx_polling,
 238         .enable_hw_sec = rtl8723ae_enable_hw_security_config,
 239         .set_key = rtl8723ae_set_key,
 240         .init_sw_leds = rtl8723ae_init_sw_leds,
 241         .get_bbreg = rtl8723_phy_query_bb_reg,
 242         .set_bbreg = rtl8723_phy_set_bb_reg,
 243         .get_rfreg = rtl8723ae_phy_query_rf_reg,
 244         .set_rfreg = rtl8723ae_phy_set_rf_reg,
 245         .c2h_command_handle = rtl_8723e_c2h_command_handle,
 246         .bt_wifi_media_status_notify = rtl_8723e_bt_wifi_media_status_notify,
 247         .bt_coex_off_before_lps = rtl8723ae_bt_coex_off_before_lps,
 248         .is_fw_header = is_fw_header,
 249 };
 250
 251 static struct rtl_mod_params rtl8723ae_mod_params = {
 252         .sw_crypto = false,
 253         .inactiveps = true,
 254         .swctrl_lps = false,
 255         .fwctrl_lps = true,
 256         .debug = DBG_EMERG,
 257 };
 258
 259 static struct rtl_hal_cfg rtl8723ae_hal_cfg = {
 260         .bar_id = 2,
 261         .write_readback = true,
 262         .name = "rtl8723ae_pci",
 263         .fw_name = "/*(DEBLOBBED)*/",
 264         .ops = &rtl8723ae_hal_ops,
 265         .mod_params = &rtl8723ae_mod_params,
 266         .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
 267         .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
 268         .maps[SYS_CLK] = REG_SYS_CLKR,
 269         .maps[MAC_RCR_AM] = AM,
 270         .maps[MAC_RCR_AB] = AB,
 271         .maps[MAC_RCR_ACRC32] = ACRC32,
 272         .maps[MAC_RCR_ACF] = ACF,
 273         .maps[MAC_RCR_AAP] = AAP,
 274         .maps[EFUSE_TEST] = REG_EFUSE_TEST,
 275         .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
 276         .maps[EFUSE_CLK] = 0,
 277         .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
 278         .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
 279         .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
 280         .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
 281         .maps[EFUSE_ANA8M] = ANA8M,
 282         .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
 283         .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
 284         .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
 285         .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
 286
 287         .maps[RWCAM] = REG_CAMCMD,
 288         .maps[WCAMI] = REG_CAMWRITE,
 289         .maps[RCAMO] = REG_CAMREAD,
 290         .maps[CAMDBG] = REG_CAMDBG,
 291         .maps[SECR] = REG_SECCFG,
 292         .maps[SEC_CAM_NONE] = CAM_NONE,
 293         .maps[SEC_CAM_WEP40] = CAM_WEP40,
 294         .maps[SEC_CAM_TKIP] = CAM_TKIP,
 295         .maps[SEC_CAM_AES] = CAM_AES,
 296         .maps[SEC_CAM_WEP104] = CAM_WEP104,
 297
 298         .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
 299         .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
 300         .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
 301         .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
 302         .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
 303         .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
 304         .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
 305         .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
 306         .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
 307         .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
 308         .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
 309         .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
 310         .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
 311         .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
 312         .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
 313         .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,
 314
 315         .maps[RTL_IMR_TXFOVW] = PHIMR_TXFOVW,
 316         .maps[RTL_IMR_PSTIMEOUT] = PHIMR_PSTIMEOUT,
 317         .maps[RTL_IMR_BCNINT] = PHIMR_BCNDMAINT0,
 318         .maps[RTL_IMR_RXFOVW] = PHIMR_RXFOVW,
 319         .maps[RTL_IMR_RDU] = PHIMR_RDU,
 320         .maps[RTL_IMR_ATIMEND] = PHIMR_ATIMEND_E,
 321         .maps[RTL_IMR_BDOK] = PHIMR_BCNDOK0,
 322         .maps[RTL_IMR_MGNTDOK] = PHIMR_MGNTDOK,
 323         .maps[RTL_IMR_TBDER] = PHIMR_TXBCNERR,
 324         .maps[RTL_IMR_HIGHDOK] = PHIMR_HIGHDOK,
 325         .maps[RTL_IMR_TBDOK] = PHIMR_TXBCNOK,
 326         .maps[RTL_IMR_BKDOK] = PHIMR_BKDOK,
 327         .maps[RTL_IMR_BEDOK] = PHIMR_BEDOK,
 328         .maps[RTL_IMR_VIDOK] = PHIMR_VIDOK,
 329         .maps[RTL_IMR_VODOK] = PHIMR_VODOK,
 330         .maps[RTL_IMR_ROK] = PHIMR_ROK,
 331         .maps[RTL_IBSS_INT_MASKS] = (PHIMR_BCNDMAINT0 |
 332                                      PHIMR_TXBCNOK | PHIMR_TXBCNERR),
 333         .maps[RTL_IMR_C2HCMD] = PHIMR_C2HCMD,
 334
 335
 336         .maps[RTL_RC_CCK_RATE1M] = DESC92_RATE1M,
 337         .maps[RTL_RC_CCK_RATE2M] = DESC92_RATE2M,
 338         .maps[RTL_RC_CCK_RATE5_5M] = DESC92_RATE5_5M,
 339         .maps[RTL_RC_CCK_RATE11M] = DESC92_RATE11M,
 340         .maps[RTL_RC_OFDM_RATE6M] = DESC92_RATE6M,
 341         .maps[RTL_RC_OFDM_RATE9M] = DESC92_RATE9M,
 342         .maps[RTL_RC_OFDM_RATE12M] = DESC92_RATE12M,
 343         .maps[RTL_RC_OFDM_RATE18M] = DESC92_RATE18M,
 344         .maps[RTL_RC_OFDM_RATE24M] = DESC92_RATE24M,
 345         .maps[RTL_RC_OFDM_RATE36M] = DESC92_RATE36M,
 346         .maps[RTL_RC_OFDM_RATE48M] = DESC92_RATE48M,
 347         .maps[RTL_RC_OFDM_RATE54M] = DESC92_RATE54M,
 348
 349         .maps[RTL_RC_HT_RATEMCS7] = DESC92_RATEMCS7,
 350         .maps[RTL_RC_HT_RATEMCS15] = DESC92_RATEMCS15,
 351 };
 352
 353 static struct pci_device_id rtl8723ae_pci_ids[] = {
 354         {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8723, rtl8723ae_hal_cfg)},
 355         {},
 356 };
 357
 358 MODULE_DEVICE_TABLE(pci, rtl8723ae_pci_ids);
 359
 360 MODULE_AUTHOR("lizhaoming       <chaoming_li@realsil.com.cn>");
 361 MODULE_AUTHOR("Realtek WlanFAE  <wlanfae@realtek.com>");
 362 MODULE_AUTHOR("Larry Finger     <Larry.Finger@lwfinger.net>");
 363 MODULE_LICENSE("GPL");
 364 MODULE_DESCRIPTION("Realtek 8723E 802.11n PCI wireless");
 365 /*(DEBLOBBED)*/
 366
 367 module_param_named(swenc, rtl8723ae_mod_params.sw_crypto, bool, 0444);
 368 module_param_named(debug, rtl8723ae_mod_params.debug, int, 0444);
 369 module_param_named(ips, rtl8723ae_mod_params.inactiveps, bool, 0444);
 370 module_param_named(swlps, rtl8723ae_mod_params.swctrl_lps, bool, 0444);
 371 module_param_named(fwlps, rtl8723ae_mod_params.fwctrl_lps, bool, 0444);
 372 MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
 373 MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
 374 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
 375 MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
 376 MODULE_PARM_DESC(debug, "Set debug level (0-5) (default 0)");
 377
 378 static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
 379
 380 static struct pci_driver rtl8723ae_driver = {
 381         .name = KBUILD_MODNAME,
 382         .id_table = rtl8723ae_pci_ids,
 383         .probe = rtl_pci_probe,
 384         .remove = rtl_pci_disconnect,
 385         .driver.pm = &rtlwifi_pm_ops,
 386 };
 387
 388 module_pci_driver(rtl8723ae_driver);