drivers/net/wireless/realtek/rtlwifi/rtl8192se/hw.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 2009-2012  Realtek Corporation.*/
   3
   4 #include "../wifi.h"
   5 #include "../efuse.h"
   6 #include "../base.h"
   7 #include "../regd.h"
   8 #include "../cam.h"
   9 #include "../ps.h"
  10 #include "../pci.h"
  11 #include "reg.h"
  12 #include "def.h"
  13 #include "phy.h"
  14 #include "dm.h"
  15 #include "fw.h"
  16 #include "led.h"
  17 #include "hw.h"
  18
  19 void rtl92se_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
  20 {
  21         struct rtl_priv *rtlpriv = rtl_priv(hw);
  22         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  23         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  24
  25         switch (variable) {
  26         case HW_VAR_RCR: {
  27                         *((u32 *) (val)) = rtlpci->receive_config;
  28                         break;
  29                 }
  30         case HW_VAR_RF_STATE: {
  31                         *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
  32                         break;
  33                 }
  34         case HW_VAR_FW_PSMODE_STATUS: {
  35                         *((bool *) (val)) = ppsc->fw_current_inpsmode;
  36                         break;
  37                 }
  38         case HW_VAR_CORRECT_TSF: {
  39                         u64 tsf;
  40                         u32 *ptsf_low = (u32 *)&tsf;
  41                         u32 *ptsf_high = ((u32 *)&tsf) + 1;
  42
  43                         *ptsf_high = rtl_read_dword(rtlpriv, (TSFR + 4));
  44                         *ptsf_low = rtl_read_dword(rtlpriv, TSFR);
  45
  46                         *((u64 *) (val)) = tsf;
  47
  48                         break;
  49                 }
  50         case HW_VAR_MRC: {
  51                         *((bool *)(val)) = rtlpriv->dm.current_mrc_switch;
  52                         break;
  53                 }
  54         case HAL_DEF_WOWLAN:
  55                 break;
  56         default:
  57                 pr_err("switch case %#x not processed\n", variable);
  58                 break;
  59         }
  60 }
  61
  62 void rtl92se_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
  63 {
  64         struct rtl_priv *rtlpriv = rtl_priv(hw);
  65         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  66         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  67         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  68         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  69         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  70
  71         switch (variable) {
  72         case HW_VAR_ETHER_ADDR:{
  73                         rtl_write_dword(rtlpriv, IDR0, ((u32 *)(val))[0]);
  74                         rtl_write_word(rtlpriv, IDR4, ((u16 *)(val + 4))[0]);
  75                         break;
  76                 }
  77         case HW_VAR_BASIC_RATE:{
  78                         u16 rate_cfg = ((u16 *) val)[0];
  79                         u8 rate_index = 0;
  80
  81                         if (rtlhal->version == VERSION_8192S_ACUT)
  82                                 rate_cfg = rate_cfg & 0x150;
  83                         else
  84                                 rate_cfg = rate_cfg & 0x15f;
  85
  86                         rate_cfg |= 0x01;
  87
  88                         rtl_write_byte(rtlpriv, RRSR, rate_cfg & 0xff);
  89                         rtl_write_byte(rtlpriv, RRSR + 1,
  90                                        (rate_cfg >> 8) & 0xff);
  91
  92                         while (rate_cfg > 0x1) {
  93                                 rate_cfg = (rate_cfg >> 1);
  94                                 rate_index++;
  95                         }
  96                         rtl_write_byte(rtlpriv, INIRTSMCS_SEL, rate_index);
  97
  98                         break;
  99                 }
 100         case HW_VAR_BSSID:{
 101                         rtl_write_dword(rtlpriv, BSSIDR, ((u32 *)(val))[0]);
 102                         rtl_write_word(rtlpriv, BSSIDR + 4,
 103                                        ((u16 *)(val + 4))[0]);
 104                         break;
 105                 }
 106         case HW_VAR_SIFS:{
 107                         rtl_write_byte(rtlpriv, SIFS_OFDM, val[0]);
 108                         rtl_write_byte(rtlpriv, SIFS_OFDM + 1, val[1]);
 109                         break;
 110                 }
 111         case HW_VAR_SLOT_TIME:{
 112                         u8 e_aci;
 113
 114                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 115                                  "HW_VAR_SLOT_TIME %x\n", val[0]);
 116
 117                         rtl_write_byte(rtlpriv, SLOT_TIME, val[0]);
 118
 119                         for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 120                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 121                                                 HW_VAR_AC_PARAM,
 122                                                 (&e_aci));
 123                         }
 124                         break;
 125                 }
 126         case HW_VAR_ACK_PREAMBLE:{
 127                         u8 reg_tmp;
 128                         u8 short_preamble = (bool) (*val);
 129                         reg_tmp = (mac->cur_40_prime_sc) << 5;
 130                         if (short_preamble)
 131                                 reg_tmp |= 0x80;
 132
 133                         rtl_write_byte(rtlpriv, RRSR + 2, reg_tmp);
 134                         break;
 135                 }
 136         case HW_VAR_AMPDU_MIN_SPACE:{
 137                         u8 min_spacing_to_set;
 138                         u8 sec_min_space;
 139
 140                         min_spacing_to_set = *val;
 141                         if (min_spacing_to_set <= 7) {
 142                                 if (rtlpriv->sec.pairwise_enc_algorithm ==
 143                                     NO_ENCRYPTION)
 144                                         sec_min_space = 0;
 145                                 else
 146                                         sec_min_space = 1;
 147
 148                                 if (min_spacing_to_set < sec_min_space)
 149                                         min_spacing_to_set = sec_min_space;
 150                                 if (min_spacing_to_set > 5)
 151                                         min_spacing_to_set = 5;
 152
 153                                 mac->min_space_cfg =
 154                                                 ((mac->min_space_cfg & 0xf8) |
 155                                                 min_spacing_to_set);
 156
 157                                 *val = min_spacing_to_set;
 158
 159                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 160                                          "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 161                                          mac->min_space_cfg);
 162
 163                                 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE,
 164                                                mac->min_space_cfg);
 165                         }
 166                         break;
 167                 }
 168         case HW_VAR_SHORTGI_DENSITY:{
 169                         u8 density_to_set;
 170
 171                         density_to_set = *val;
 172                         mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg;
 173                         mac->min_space_cfg |= (density_to_set << 3);
 174
 175                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 176                                  "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 177                                  mac->min_space_cfg);
 178
 179                         rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE,
 180                                        mac->min_space_cfg);
 181
 182                         break;
 183                 }
 184         case HW_VAR_AMPDU_FACTOR:{
 185                         u8 factor_toset;
 186                         u8 regtoset;
 187                         u8 factorlevel[18] = {
 188                                 2, 4, 4, 7, 7, 13, 13,
 189                                 13, 2, 7, 7, 13, 13,
 190                                 15, 15, 15, 15, 0};
 191                         u8 index = 0;
 192
 193                         factor_toset = *val;
 194                         if (factor_toset <= 3) {
 195                                 factor_toset = (1 << (factor_toset + 2));
 196                                 if (factor_toset > 0xf)
 197                                         factor_toset = 0xf;
 198
 199                                 for (index = 0; index < 17; index++) {
 200                                         if (factorlevel[index] > factor_toset)
 201                                                 factorlevel[index] =
 202                                                                  factor_toset;
 203                                 }
 204
 205                                 for (index = 0; index < 8; index++) {
 206                                         regtoset = ((factorlevel[index * 2]) |
 207                                                     (factorlevel[index *
 208                                                     2 + 1] << 4));
 209                                         rtl_write_byte(rtlpriv,
 210                                                        AGGLEN_LMT_L + index,
 211                                                        regtoset);
 212                                 }
 213
 214                                 regtoset = ((factorlevel[16]) |
 215                                             (factorlevel[17] << 4));
 216                                 rtl_write_byte(rtlpriv, AGGLEN_LMT_H, regtoset);
 217
 218                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 219                                          "Set HW_VAR_AMPDU_FACTOR: %#x\n",
 220                                          factor_toset);
 221                         }
 222                         break;
 223                 }
 224         case HW_VAR_AC_PARAM:{
 225                         u8 e_aci = *val;
 226                         rtl92s_dm_init_edca_turbo(hw);
 227
 228                         if (rtlpci->acm_method != EACMWAY2_SW)
 229                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 230                                                  HW_VAR_ACM_CTRL,
 231                                                  &e_aci);
 232                         break;
 233                 }
 234         case HW_VAR_ACM_CTRL:{
 235                         u8 e_aci = *val;
 236                         union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)(&(
 237                                                         mac->ac[0].aifs));
 238                         u8 acm = p_aci_aifsn->f.acm;
 239                         u8 acm_ctrl = rtl_read_byte(rtlpriv, ACMHWCTRL);
 240
 241                         acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ?
 242                                    0x0 : 0x1);
 243
 244                         if (acm) {
 245                                 switch (e_aci) {
 246                                 case AC0_BE:
 247                                         acm_ctrl |= ACMHW_BEQEN;
 248                                         break;
 249                                 case AC2_VI:
 250                                         acm_ctrl |= ACMHW_VIQEN;
 251                                         break;
 252                                 case AC3_VO:
 253                                         acm_ctrl |= ACMHW_VOQEN;
 254                                         break;
 255                                 default:
 256                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 257                                                  "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
 258                                                  acm);
 259                                         break;
 260                                 }
 261                         } else {
 262                                 switch (e_aci) {
 263                                 case AC0_BE:
 264                                         acm_ctrl &= (~ACMHW_BEQEN);
 265                                         break;
 266                                 case AC2_VI:
 267                                         acm_ctrl &= (~ACMHW_VIQEN);
 268                                         break;
 269                                 case AC3_VO:
 270                                         acm_ctrl &= (~ACMHW_VOQEN);
 271                                         break;
 272                                 default:
 273                                         pr_err("switch case %#x not processed\n",
 274                                                e_aci);
 275                                         break;
 276                                 }
 277                         }
 278
 279                         RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 280                                  "HW_VAR_ACM_CTRL Write 0x%X\n", acm_ctrl);
 281                         rtl_write_byte(rtlpriv, ACMHWCTRL, acm_ctrl);
 282                         break;
 283                 }
 284         case HW_VAR_RCR:{
 285                         rtl_write_dword(rtlpriv, RCR, ((u32 *) (val))[0]);
 286                         rtlpci->receive_config = ((u32 *) (val))[0];
 287                         break;
 288                 }
 289         case HW_VAR_RETRY_LIMIT:{
 290                         u8 retry_limit = val[0];
 291
 292                         rtl_write_word(rtlpriv, RETRY_LIMIT,
 293                                        retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 294                                        retry_limit << RETRY_LIMIT_LONG_SHIFT);
 295                         break;
 296                 }
 297         case HW_VAR_DUAL_TSF_RST: {
 298                         break;
 299                 }
 300         case HW_VAR_EFUSE_BYTES: {
 301                         rtlefuse->efuse_usedbytes = *((u16 *) val);
 302                         break;
 303                 }
 304         case HW_VAR_EFUSE_USAGE: {
 305                         rtlefuse->efuse_usedpercentage = *val;
 306                         break;
 307                 }
 308         case HW_VAR_IO_CMD: {
 309                         break;
 310                 }
 311         case HW_VAR_WPA_CONFIG: {
 312                         rtl_write_byte(rtlpriv, REG_SECR, *val);
 313                         break;
 314                 }
 315         case HW_VAR_SET_RPWM:{
 316                         break;
 317                 }
 318         case HW_VAR_H2C_FW_PWRMODE:{
 319                         break;
 320                 }
 321         case HW_VAR_FW_PSMODE_STATUS: {
 322                         ppsc->fw_current_inpsmode = *((bool *) val);
 323                         break;
 324                 }
 325         case HW_VAR_H2C_FW_JOINBSSRPT:{
 326                         break;
 327                 }
 328         case HW_VAR_AID:{
 329                         break;
 330                 }
 331         case HW_VAR_CORRECT_TSF:{
 332                         break;
 333                 }
 334         case HW_VAR_MRC: {
 335                         bool bmrc_toset = *((bool *)val);
 336                         u8 u1bdata = 0;
 337
 338                         if (bmrc_toset) {
 339                                 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
 340                                               MASKBYTE0, 0x33);
 341                                 u1bdata = (u8)rtl_get_bbreg(hw,
 342                                                 ROFDM1_TRXPATHENABLE,
 343                                                 MASKBYTE0);
 344                                 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE,
 345                                               MASKBYTE0,
 346                                               ((u1bdata & 0xf0) | 0x03));
 347                                 u1bdata = (u8)rtl_get_bbreg(hw,
 348                                                 ROFDM0_TRXPATHENABLE,
 349                                                 MASKBYTE1);
 350                                 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
 351                                               MASKBYTE1,
 352                                               (u1bdata | 0x04));
 353
 354                                 /* Update current settings. */
 355                                 rtlpriv->dm.current_mrc_switch = bmrc_toset;
 356                         } else {
 357                                 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
 358                                               MASKBYTE0, 0x13);
 359                                 u1bdata = (u8)rtl_get_bbreg(hw,
 360                                                  ROFDM1_TRXPATHENABLE,
 361                                                  MASKBYTE0);
 362                                 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE,
 363                                               MASKBYTE0,
 364                                               ((u1bdata & 0xf0) | 0x01));
 365                                 u1bdata = (u8)rtl_get_bbreg(hw,
 366                                                 ROFDM0_TRXPATHENABLE,
 367                                                 MASKBYTE1);
 368                                 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
 369                                               MASKBYTE1, (u1bdata & 0xfb));
 370
 371                                 /* Update current settings. */
 372                                 rtlpriv->dm.current_mrc_switch = bmrc_toset;
 373                         }
 374
 375                         break;
 376                 }
 377         case HW_VAR_FW_LPS_ACTION: {
 378                 bool enter_fwlps = *((bool *)val);
 379                 u8 rpwm_val, fw_pwrmode;
 380                 bool fw_current_inps;
 381
 382                 if (enter_fwlps) {
 383                         rpwm_val = 0x02;        /* RF off */
 384                         fw_current_inps = true;
 385                         rtlpriv->cfg->ops->set_hw_reg(hw,
 386                                         HW_VAR_FW_PSMODE_STATUS,
 387                                         (u8 *)(&fw_current_inps));
 388                         rtlpriv->cfg->ops->set_hw_reg(hw,
 389                                         HW_VAR_H2C_FW_PWRMODE,
 390                                         &ppsc->fwctrl_psmode);
 391
 392                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 393                                                       &rpwm_val);
 394                 } else {
 395                         rpwm_val = 0x0C;        /* RF on */
 396                         fw_pwrmode = FW_PS_ACTIVE_MODE;
 397                         fw_current_inps = false;
 398                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 399                                                       &rpwm_val);
 400                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 401                                                       &fw_pwrmode);
 402
 403                         rtlpriv->cfg->ops->set_hw_reg(hw,
 404                                         HW_VAR_FW_PSMODE_STATUS,
 405                                         (u8 *)(&fw_current_inps));
 406                 }
 407                 break; }
 408         default:
 409                 pr_err("switch case %#x not processed\n", variable);
 410                 break;
 411         }
 412
 413 }
 414
 415 void rtl92se_enable_hw_security_config(struct ieee80211_hw *hw)
 416 {
 417         struct rtl_priv *rtlpriv = rtl_priv(hw);
 418         u8 sec_reg_value = 0x0;
 419
 420         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 421                  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
 422                  rtlpriv->sec.pairwise_enc_algorithm,
 423                  rtlpriv->sec.group_enc_algorithm);
 424
 425         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
 426                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
 427                          "not open hw encryption\n");
 428                 return;
 429         }
 430
 431         sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE;
 432
 433         if (rtlpriv->sec.use_defaultkey) {
 434                 sec_reg_value |= SCR_TXUSEDK;
 435                 sec_reg_value |= SCR_RXUSEDK;
 436         }
 437
 438         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, "The SECR-value %x\n",
 439                  sec_reg_value);
 440
 441         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
 442
 443 }
 444
 445 static u8 _rtl92se_halset_sysclk(struct ieee80211_hw *hw, u8 data)
 446 {
 447         struct rtl_priv *rtlpriv = rtl_priv(hw);
 448         u8 waitcount = 100;
 449         bool bresult = false;
 450         u8 tmpvalue;
 451
 452         rtl_write_byte(rtlpriv, SYS_CLKR + 1, data);
 453
 454         /* Wait the MAC synchronized. */
 455         udelay(400);
 456
 457         /* Check if it is set ready. */
 458         tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
 459         bresult = ((tmpvalue & BIT(7)) == (data & BIT(7)));
 460
 461         if ((data & (BIT(6) | BIT(7))) == false) {
 462                 waitcount = 100;
 463                 tmpvalue = 0;
 464
 465                 while (1) {
 466                         waitcount--;
 467
 468                         tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
 469                         if ((tmpvalue & BIT(6)))
 470                                 break;
 471
 472                         pr_err("wait for BIT(6) return value %x\n", tmpvalue);
 473                         if (waitcount == 0)
 474                                 break;
 475
 476                         udelay(10);
 477                 }
 478
 479                 if (waitcount == 0)
 480                         bresult = false;
 481                 else
 482                         bresult = true;
 483         }
 484
 485         return bresult;
 486 }
 487
 488 void rtl8192se_gpiobit3_cfg_inputmode(struct ieee80211_hw *hw)
 489 {
 490         struct rtl_priv *rtlpriv = rtl_priv(hw);
 491         u8 u1tmp;
 492
 493         /* The following config GPIO function */
 494         rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
 495         u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL);
 496
 497         /* config GPIO3 to input */
 498         u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
 499         rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp);
 500
 501 }
 502
 503 static u8 _rtl92se_rf_onoff_detect(struct ieee80211_hw *hw)
 504 {
 505         struct rtl_priv *rtlpriv = rtl_priv(hw);
 506         u8 u1tmp;
 507         u8 retval = ERFON;
 508
 509         /* The following config GPIO function */
 510         rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
 511         u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL);
 512
 513         /* config GPIO3 to input */
 514         u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
 515         rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp);
 516
 517         /* On some of the platform, driver cannot read correct
 518          * value without delay between Write_GPIO_SEL and Read_GPIO_IN */
 519         mdelay(10);
 520
 521         /* check GPIO3 */
 522         u1tmp = rtl_read_byte(rtlpriv, GPIO_IN_SE);
 523         retval = (u1tmp & HAL_8192S_HW_GPIO_OFF_BIT) ? ERFON : ERFOFF;
 524
 525         return retval;
 526 }
 527
 528 static void _rtl92se_macconfig_before_fwdownload(struct ieee80211_hw *hw)
 529 {
 530         struct rtl_priv *rtlpriv = rtl_priv(hw);
 531         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 532         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 533
 534         u8 i;
 535         u8 tmpu1b;
 536         u16 tmpu2b;
 537         u8 pollingcnt = 20;
 538
 539         if (rtlpci->first_init) {
 540                 /* Reset PCIE Digital */
 541                 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
 542                 tmpu1b &= 0xFE;
 543                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
 544                 udelay(1);
 545                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b | BIT(0));
 546         }
 547
 548         /* Switch to SW IO control */
 549         tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
 550         if (tmpu1b & BIT(7)) {
 551                 tmpu1b &= ~(BIT(6) | BIT(7));
 552
 553                 /* Set failed, return to prevent hang. */
 554                 if (!_rtl92se_halset_sysclk(hw, tmpu1b))
 555                         return;
 556         }
 557
 558         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0);
 559         udelay(50);
 560         rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
 561         udelay(50);
 562
 563         /* Clear FW RPWM for FW control LPS.*/
 564         rtl_write_byte(rtlpriv, RPWM, 0x0);
 565
 566         /* Reset MAC-IO and CPU and Core Digital BIT(10)/11/15 */
 567         tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
 568         tmpu1b &= 0x73;
 569         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
 570         /* wait for BIT 10/11/15 to pull high automatically!! */
 571         mdelay(1);
 572
 573         rtl_write_byte(rtlpriv, CMDR, 0);
 574         rtl_write_byte(rtlpriv, TCR, 0);
 575
 576         /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
 577         tmpu1b = rtl_read_byte(rtlpriv, 0x562);
 578         tmpu1b |= 0x08;
 579         rtl_write_byte(rtlpriv, 0x562, tmpu1b);
 580         tmpu1b &= ~(BIT(3));
 581         rtl_write_byte(rtlpriv, 0x562, tmpu1b);
 582
 583         /* Enable AFE clock source */
 584         tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL);
 585         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01));
 586         /* Delay 1.5ms */
 587         mdelay(2);
 588         tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1);
 589         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb));
 590
 591         /* Enable AFE Macro Block's Bandgap */
 592         tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
 593         rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0)));
 594         mdelay(1);
 595
 596         /* Enable AFE Mbias */
 597         tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
 598         rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02));
 599         mdelay(1);
 600
 601         /* Enable LDOA15 block  */
 602         tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL);
 603         rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0)));
 604
 605         /* Set Digital Vdd to Retention isolation Path. */
 606         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
 607         rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11)));
 608
 609         /* For warm reboot NIC disappera bug. */
 610         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
 611         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13)));
 612
 613         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68);
 614
 615         /* Enable AFE PLL Macro Block */
 616         /* We need to delay 100u before enabling PLL. */
 617         udelay(200);
 618         tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL);
 619         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
 620
 621         /* for divider reset  */
 622         udelay(100);
 623         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) |
 624                        BIT(4) | BIT(6)));
 625         udelay(10);
 626         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
 627         udelay(10);
 628
 629         /* Enable MAC 80MHZ clock  */
 630         tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1);
 631         rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0)));
 632         mdelay(1);
 633
 634         /* Release isolation AFE PLL & MD */
 635         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6);
 636
 637         /* Enable MAC clock */
 638         tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
 639         rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11)));
 640
 641         /* Enable Core digital and enable IOREG R/W */
 642         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
 643         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11)));
 644
 645         tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
 646         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b & ~(BIT(7)));
 647
 648         /* enable REG_EN */
 649         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
 650
 651         /* Switch the control path. */
 652         tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
 653         rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2))));
 654
 655         tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
 656         tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6)));
 657         if (!_rtl92se_halset_sysclk(hw, tmpu1b))
 658                 return; /* Set failed, return to prevent hang. */
 659
 660         rtl_write_word(rtlpriv, CMDR, 0x07FC);
 661
 662         /* MH We must enable the section of code to prevent load IMEM fail. */
 663         /* Load MAC register from WMAc temporarily We simulate macreg. */
 664         /* txt HW will provide MAC txt later  */
 665         rtl_write_byte(rtlpriv, 0x6, 0x30);
 666         rtl_write_byte(rtlpriv, 0x49, 0xf0);
 667
 668         rtl_write_byte(rtlpriv, 0x4b, 0x81);
 669
 670         rtl_write_byte(rtlpriv, 0xb5, 0x21);
 671
 672         rtl_write_byte(rtlpriv, 0xdc, 0xff);
 673         rtl_write_byte(rtlpriv, 0xdd, 0xff);
 674         rtl_write_byte(rtlpriv, 0xde, 0xff);
 675         rtl_write_byte(rtlpriv, 0xdf, 0xff);
 676
 677         rtl_write_byte(rtlpriv, 0x11a, 0x00);
 678         rtl_write_byte(rtlpriv, 0x11b, 0x00);
 679
 680         for (i = 0; i < 32; i++)
 681                 rtl_write_byte(rtlpriv, INIMCS_SEL + i, 0x1b);
 682
 683         rtl_write_byte(rtlpriv, 0x236, 0xff);
 684
 685         rtl_write_byte(rtlpriv, 0x503, 0x22);
 686
 687         if (ppsc->support_aspm && !ppsc->support_backdoor)
 688                 rtl_write_byte(rtlpriv, 0x560, 0x40);
 689         else
 690                 rtl_write_byte(rtlpriv, 0x560, 0x00);
 691
 692         rtl_write_byte(rtlpriv, DBG_PORT, 0x91);
 693
 694         /* Set RX Desc Address */
 695         rtl_write_dword(rtlpriv, RDQDA, rtlpci->rx_ring[RX_MPDU_QUEUE].dma);
 696         rtl_write_dword(rtlpriv, RCDA, rtlpci->rx_ring[RX_CMD_QUEUE].dma);
 697
 698         /* Set TX Desc Address */
 699         rtl_write_dword(rtlpriv, TBKDA, rtlpci->tx_ring[BK_QUEUE].dma);
 700         rtl_write_dword(rtlpriv, TBEDA, rtlpci->tx_ring[BE_QUEUE].dma);
 701         rtl_write_dword(rtlpriv, TVIDA, rtlpci->tx_ring[VI_QUEUE].dma);
 702         rtl_write_dword(rtlpriv, TVODA, rtlpci->tx_ring[VO_QUEUE].dma);
 703         rtl_write_dword(rtlpriv, TBDA, rtlpci->tx_ring[BEACON_QUEUE].dma);
 704         rtl_write_dword(rtlpriv, TCDA, rtlpci->tx_ring[TXCMD_QUEUE].dma);
 705         rtl_write_dword(rtlpriv, TMDA, rtlpci->tx_ring[MGNT_QUEUE].dma);
 706         rtl_write_dword(rtlpriv, THPDA, rtlpci->tx_ring[HIGH_QUEUE].dma);
 707         rtl_write_dword(rtlpriv, HDA, rtlpci->tx_ring[HCCA_QUEUE].dma);
 708
 709         rtl_write_word(rtlpriv, CMDR, 0x37FC);
 710
 711         /* To make sure that TxDMA can ready to download FW. */
 712         /* We should reset TxDMA if IMEM RPT was not ready. */
 713         do {
 714                 tmpu1b = rtl_read_byte(rtlpriv, TCR);
 715                 if ((tmpu1b & TXDMA_INIT_VALUE) == TXDMA_INIT_VALUE)
 716                         break;
 717
 718                 udelay(5);
 719         } while (pollingcnt--);
 720
 721         if (pollingcnt <= 0) {
 722                 pr_err("Polling TXDMA_INIT_VALUE timeout!! Current TCR(%#x)\n",
 723                        tmpu1b);
 724                 tmpu1b = rtl_read_byte(rtlpriv, CMDR);
 725                 rtl_write_byte(rtlpriv, CMDR, tmpu1b & (~TXDMA_EN));
 726                 udelay(2);
 727                 /* Reset TxDMA */
 728                 rtl_write_byte(rtlpriv, CMDR, tmpu1b | TXDMA_EN);
 729         }
 730
 731         /* After MACIO reset,we must refresh LED state. */
 732         if ((ppsc->rfoff_reason == RF_CHANGE_BY_IPS) ||
 733            (ppsc->rfoff_reason == 0)) {
 734                 struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
 735                 enum rf_pwrstate rfpwr_state_toset;
 736                 rfpwr_state_toset = _rtl92se_rf_onoff_detect(hw);
 737
 738                 if (rfpwr_state_toset == ERFON)
 739                         rtl92se_sw_led_on(hw, pled0);
 740         }
 741 }
 742
 743 static void _rtl92se_macconfig_after_fwdownload(struct ieee80211_hw *hw)
 744 {
 745         struct rtl_priv *rtlpriv = rtl_priv(hw);
 746         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 747         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 748         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 749         u8 i;
 750         u16 tmpu2b;
 751
 752         /* 1. System Configure Register (Offset: 0x0000 - 0x003F) */
 753
 754         /* 2. Command Control Register (Offset: 0x0040 - 0x004F) */
 755         /* Turn on 0x40 Command register */
 756         rtl_write_word(rtlpriv, CMDR, (BBRSTN | BB_GLB_RSTN |
 757                         SCHEDULE_EN | MACRXEN | MACTXEN | DDMA_EN | FW2HW_EN |
 758                         RXDMA_EN | TXDMA_EN | HCI_RXDMA_EN | HCI_TXDMA_EN));
 759
 760         /* Set TCR TX DMA pre 2 FULL enable bit */
 761         rtl_write_dword(rtlpriv, TCR, rtl_read_dword(rtlpriv, TCR) |
 762                         TXDMAPRE2FULL);
 763
 764         /* Set RCR      */
 765         rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config);
 766
 767         /* 3. MACID Setting Register (Offset: 0x0050 - 0x007F) */
 768
 769         /* 4. Timing Control Register  (Offset: 0x0080 - 0x009F) */
 770         /* Set CCK/OFDM SIFS */
 771         /* CCK SIFS shall always be 10us. */
 772         rtl_write_word(rtlpriv, SIFS_CCK, 0x0a0a);
 773         rtl_write_word(rtlpriv, SIFS_OFDM, 0x1010);
 774
 775         /* Set AckTimeout */
 776         rtl_write_byte(rtlpriv, ACK_TIMEOUT, 0x40);
 777
 778         /* Beacon related */
 779         rtl_write_word(rtlpriv, BCN_INTERVAL, 100);
 780         rtl_write_word(rtlpriv, ATIMWND, 2);
 781
 782         /* 5. FIFO Control Register (Offset: 0x00A0 - 0x015F) */
 783         /* 5.1 Initialize Number of Reserved Pages in Firmware Queue */
 784         /* Firmware allocate now, associate with FW internal setting.!!! */
 785
 786         /* 5.2 Setting TX/RX page size 0/1/2/3/4=64/128/256/512/1024 */
 787         /* 5.3 Set driver info, we only accept PHY status now. */
 788         /* 5.4 Set RXDMA arbitration to control RXDMA/MAC/FW R/W for RXFIFO  */
 789         rtl_write_byte(rtlpriv, RXDMA, rtl_read_byte(rtlpriv, RXDMA) | BIT(6));
 790
 791         /* 6. Adaptive Control Register  (Offset: 0x0160 - 0x01CF) */
 792         /* Set RRSR to all legacy rate and HT rate
 793          * CCK rate is supported by default.
 794          * CCK rate will be filtered out only when associated
 795          * AP does not support it.
 796          * Only enable ACK rate to OFDM 24M
 797          * Disable RRSR for CCK rate in A-Cut   */
 798
 799         if (rtlhal->version == VERSION_8192S_ACUT)
 800                 rtl_write_byte(rtlpriv, RRSR, 0xf0);
 801         else if (rtlhal->version == VERSION_8192S_BCUT)
 802                 rtl_write_byte(rtlpriv, RRSR, 0xff);
 803         rtl_write_byte(rtlpriv, RRSR + 1, 0x01);
 804         rtl_write_byte(rtlpriv, RRSR + 2, 0x00);
 805
 806         /* A-Cut IC do not support CCK rate. We forbid ARFR to */
 807         /* fallback to CCK rate */
 808         for (i = 0; i < 8; i++) {
 809                 /*Disable RRSR for CCK rate in A-Cut */
 810                 if (rtlhal->version == VERSION_8192S_ACUT)
 811                         rtl_write_dword(rtlpriv, ARFR0 + i * 4, 0x1f0ff0f0);
 812         }
 813
 814         /* Different rate use different AMPDU size */
 815         /* MCS32/ MCS15_SG use max AMPDU size 15*2=30K */
 816         rtl_write_byte(rtlpriv, AGGLEN_LMT_H, 0x0f);
 817         /* MCS0/1/2/3 use max AMPDU size 4*2=8K */
 818         rtl_write_word(rtlpriv, AGGLEN_LMT_L, 0x7442);
 819         /* MCS4/5 use max AMPDU size 8*2=16K 6/7 use 10*2=20K */
 820         rtl_write_word(rtlpriv, AGGLEN_LMT_L + 2, 0xddd7);
 821         /* MCS8/9 use max AMPDU size 8*2=16K 10/11 use 10*2=20K */
 822         rtl_write_word(rtlpriv, AGGLEN_LMT_L + 4, 0xd772);
 823         /* MCS12/13/14/15 use max AMPDU size 15*2=30K */
 824         rtl_write_word(rtlpriv, AGGLEN_LMT_L + 6, 0xfffd);
 825
 826         /* Set Data / Response auto rate fallack retry count */
 827         rtl_write_dword(rtlpriv, DARFRC, 0x04010000);
 828         rtl_write_dword(rtlpriv, DARFRC + 4, 0x09070605);
 829         rtl_write_dword(rtlpriv, RARFRC, 0x04010000);
 830         rtl_write_dword(rtlpriv, RARFRC + 4, 0x09070605);
 831
 832         /* 7. EDCA Setting Register (Offset: 0x01D0 - 0x01FF) */
 833         /* Set all rate to support SG */
 834         rtl_write_word(rtlpriv, SG_RATE, 0xFFFF);
 835
 836         /* 8. WMAC, BA, and CCX related Register (Offset: 0x0200 - 0x023F) */
 837         /* Set NAV protection length */
 838         rtl_write_word(rtlpriv, NAV_PROT_LEN, 0x0080);
 839         /* CF-END Threshold */
 840         rtl_write_byte(rtlpriv, CFEND_TH, 0xFF);
 841         /* Set AMPDU minimum space */
 842         rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, 0x07);
 843         /* Set TXOP stall control for several queue/HI/BCN/MGT/ */
 844         rtl_write_byte(rtlpriv, TXOP_STALL_CTRL, 0x00);
 845
 846         /* 9. Security Control Register (Offset: 0x0240 - 0x025F) */
 847         /* 10. Power Save Control Register (Offset: 0x0260 - 0x02DF) */
 848         /* 11. General Purpose Register (Offset: 0x02E0 - 0x02FF) */
 849         /* 12. Host Interrupt Status Register (Offset: 0x0300 - 0x030F) */
 850         /* 13. Test mode and Debug Control Register (Offset: 0x0310 - 0x034F) */
 851
 852         /* 14. Set driver info, we only accept PHY status now. */
 853         rtl_write_byte(rtlpriv, RXDRVINFO_SZ, 4);
 854
 855         /* 15. For EEPROM R/W Workaround */
 856         /* 16. For EFUSE to share REG_SYS_FUNC_EN with EEPROM!!! */
 857         tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
 858         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmpu2b | BIT(13));
 859         tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
 860         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, tmpu2b & (~BIT(8)));
 861
 862         /* 17. For EFUSE */
 863         /* We may R/W EFUSE in EEPROM mode */
 864         if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
 865                 u8      tempval;
 866
 867                 tempval = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL + 1);
 868                 tempval &= 0xFE;
 869                 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, tempval);
 870
 871                 /* Change Program timing */
 872                 rtl_write_byte(rtlpriv, REG_EFUSE_CTRL + 3, 0x72);
 873                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "EFUSE CONFIG OK\n");
 874         }
 875
 876         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "OK\n");
 877
 878 }
 879
 880 static void _rtl92se_hw_configure(struct ieee80211_hw *hw)
 881 {
 882         struct rtl_priv *rtlpriv = rtl_priv(hw);
 883         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 884         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 885         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 886
 887         u8 reg_bw_opmode = 0;
 888         u32 reg_rrsr = 0;
 889         u8 regtmp = 0;
 890
 891         reg_bw_opmode = BW_OPMODE_20MHZ;
 892         reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 893
 894         regtmp = rtl_read_byte(rtlpriv, INIRTSMCS_SEL);
 895         reg_rrsr = ((reg_rrsr & 0x000fffff) << 8) | regtmp;
 896         rtl_write_dword(rtlpriv, INIRTSMCS_SEL, reg_rrsr);
 897         rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
 898
 899         /* Set Retry Limit here */
 900         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
 901                         (u8 *)(&rtlpci->shortretry_limit));
 902
 903         rtl_write_byte(rtlpriv, MLT, 0x8f);
 904
 905         /* For Min Spacing configuration. */
 906         switch (rtlphy->rf_type) {
 907         case RF_1T2R:
 908         case RF_1T1R:
 909                 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3);
 910                 break;
 911         case RF_2T2R:
 912         case RF_2T2R_GREEN:
 913                 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3);
 914                 break;
 915         }
 916         rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, rtlhal->minspace_cfg);
 917 }
 918
 919 int rtl92se_hw_init(struct ieee80211_hw *hw)
 920 {
 921         struct rtl_priv *rtlpriv = rtl_priv(hw);
 922         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 923         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 924         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 925         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 926         u8 tmp_byte = 0;
 927         unsigned long flags;
 928         bool rtstatus = true;
 929         u8 tmp_u1b;
 930         int err = false;
 931         u8 i;
 932         int wdcapra_add[] = {
 933                 EDCAPARA_BE, EDCAPARA_BK,
 934                 EDCAPARA_VI, EDCAPARA_VO};
 935         u8 secr_value = 0x0;
 936
 937         rtlpci->being_init_adapter = true;
 938
 939         /* As this function can take a very long time (up to 350 ms)
 940          * and can be called with irqs disabled, reenable the irqs
 941          * to let the other devices continue being serviced.
 942          *
 943          * It is safe doing so since our own interrupts will only be enabled
 944          * in a subsequent step.
 945          */
 946         local_save_flags(flags);
 947         local_irq_enable();
 948
 949         rtlpriv->intf_ops->disable_aspm(hw);
 950
 951         /* 1. MAC Initialize */
 952         /* Before FW download, we have to set some MAC register */
 953         _rtl92se_macconfig_before_fwdownload(hw);
 954
 955         rtlhal->version = (enum version_8192s)((rtl_read_dword(rtlpriv,
 956                         PMC_FSM) >> 16) & 0xF);
 957
 958         rtl8192se_gpiobit3_cfg_inputmode(hw);
 959
 960         /* 2. download firmware */
 961         rtstatus = rtl92s_download_fw(hw);
 962         if (!rtstatus) {
 963                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 964                          "Failed to download FW. Init HW without FW now... "
 965                          "Please copy FW into /lib/firmware/rtlwifi\n");
 966                 err = 1;
 967                 goto exit;
 968         }
 969
 970         /* After FW download, we have to reset MAC register */
 971         _rtl92se_macconfig_after_fwdownload(hw);
 972
 973         /*Retrieve default FW Cmd IO map. */
 974         rtlhal->fwcmd_iomap =   rtl_read_word(rtlpriv, LBUS_MON_ADDR);
 975         rtlhal->fwcmd_ioparam = rtl_read_dword(rtlpriv, LBUS_ADDR_MASK);
 976
 977         /* 3. Initialize MAC/PHY Config by MACPHY_reg.txt */
 978         if (!rtl92s_phy_mac_config(hw)) {
 979                 pr_err("MAC Config failed\n");
 980                 err = rtstatus;
 981                 goto exit;
 982         }
 983
 984         /* because last function modify RCR, so we update
 985          * rcr var here, or TP will unstable for receive_config
 986          * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
 987          * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
 988          */
 989         rtlpci->receive_config = rtl_read_dword(rtlpriv, RCR);
 990         rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
 991         rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config);
 992
 993         /* Make sure BB/RF write OK. We should prevent enter IPS. radio off. */
 994         /* We must set flag avoid BB/RF config period later!! */
 995         rtl_write_dword(rtlpriv, CMDR, 0x37FC);
 996
 997         /* 4. Initialize BB After MAC Config PHY_reg.txt, AGC_Tab.txt */
 998         if (!rtl92s_phy_bb_config(hw)) {
 999                 pr_err("BB Config failed\n");
1000                 err = rtstatus;
1001                 goto exit;
1002         }
1003
1004         /* 5. Initiailze RF RAIO_A.txt RF RAIO_B.txt */
1005         /* Before initalizing RF. We can not use FW to do RF-R/W. */
1006
1007         rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1008
1009         /* Before RF-R/W we must execute the IO from Scott's suggestion. */
1010         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, 0xDB);
1011         if (rtlhal->version == VERSION_8192S_ACUT)
1012                 rtl_write_byte(rtlpriv, SPS1_CTRL + 3, 0x07);
1013         else
1014                 rtl_write_byte(rtlpriv, RF_CTRL, 0x07);
1015
1016         if (!rtl92s_phy_rf_config(hw)) {
1017                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RF Config failed\n");
1018                 err = rtstatus;
1019                 goto exit;
1020         }
1021
1022         /* After read predefined TXT, we must set BB/MAC/RF
1023          * register as our requirement */
1024
1025         rtlphy->rfreg_chnlval[0] = rtl92s_phy_query_rf_reg(hw,
1026                                                            (enum radio_path)0,
1027                                                            RF_CHNLBW,
1028                                                            RFREG_OFFSET_MASK);
1029         rtlphy->rfreg_chnlval[1] = rtl92s_phy_query_rf_reg(hw,
1030                                                            (enum radio_path)1,
1031                                                            RF_CHNLBW,
1032                                                            RFREG_OFFSET_MASK);
1033
1034         /*---- Set CCK and OFDM Block "ON"----*/
1035         rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1036         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1037
1038         /*3 Set Hardware(Do nothing now) */
1039         _rtl92se_hw_configure(hw);
1040
1041         /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */
1042         /* TX power index for different rate set. */
1043         /* Get original hw reg values */
1044         rtl92s_phy_get_hw_reg_originalvalue(hw);
1045         /* Write correct tx power index */
1046         rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
1047
1048         /* We must set MAC address after firmware download. */
1049         for (i = 0; i < 6; i++)
1050                 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
1051
1052         /* EEPROM R/W workaround */
1053         tmp_u1b = rtl_read_byte(rtlpriv, MAC_PINMUX_CFG);
1054         rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, tmp_u1b & (~BIT(3)));
1055
1056         rtl_write_byte(rtlpriv, 0x4d, 0x0);
1057
1058         if (hal_get_firmwareversion(rtlpriv) >= 0x49) {
1059                 tmp_byte = rtl_read_byte(rtlpriv, FW_RSVD_PG_CRTL) & (~BIT(4));
1060                 tmp_byte = tmp_byte | BIT(5);
1061                 rtl_write_byte(rtlpriv, FW_RSVD_PG_CRTL, tmp_byte);
1062                 rtl_write_dword(rtlpriv, TXDESC_MSK, 0xFFFFCFFF);
1063         }
1064
1065         /* We enable high power and RA related mechanism after NIC
1066          * initialized. */
1067         if (hal_get_firmwareversion(rtlpriv) >= 0x35) {
1068                 /* Fw v.53 and later. */
1069                 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_INIT);
1070         } else if (hal_get_firmwareversion(rtlpriv) == 0x34) {
1071                 /* Fw v.52. */
1072                 rtl_write_dword(rtlpriv, WFM5, FW_RA_INIT);
1073                 rtl92s_phy_chk_fwcmd_iodone(hw);
1074         } else {
1075                 /* Compatible earlier FW version. */
1076                 rtl_write_dword(rtlpriv, WFM5, FW_RA_RESET);
1077                 rtl92s_phy_chk_fwcmd_iodone(hw);
1078                 rtl_write_dword(rtlpriv, WFM5, FW_RA_ACTIVE);
1079                 rtl92s_phy_chk_fwcmd_iodone(hw);
1080                 rtl_write_dword(rtlpriv, WFM5, FW_RA_REFRESH);
1081                 rtl92s_phy_chk_fwcmd_iodone(hw);
1082         }
1083
1084         /* Add to prevent ASPM bug. */
1085         /* Always enable hst and NIC clock request. */
1086         rtl92s_phy_switch_ephy_parameter(hw);
1087
1088         /* Security related
1089          * 1. Clear all H/W keys.
1090          * 2. Enable H/W encryption/decryption. */
1091         rtl_cam_reset_all_entry(hw);
1092         secr_value |= SCR_TXENCENABLE;
1093         secr_value |= SCR_RXENCENABLE;
1094         secr_value |= SCR_NOSKMC;
1095         rtl_write_byte(rtlpriv, REG_SECR, secr_value);
1096
1097         for (i = 0; i < 4; i++)
1098                 rtl_write_dword(rtlpriv, wdcapra_add[i], 0x5e4322);
1099
1100         if (rtlphy->rf_type == RF_1T2R) {
1101                 bool mrc2set = true;
1102                 /* Turn on B-Path */
1103                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MRC, (u8 *)&mrc2set);
1104         }
1105
1106         rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_ON);
1107         rtl92s_dm_init(hw);
1108 exit:
1109         local_irq_restore(flags);
1110         rtlpci->being_init_adapter = false;
1111         return err;
1112 }
1113
1114 void rtl92se_set_mac_addr(struct rtl_io *io, const u8 *addr)
1115 {
1116         /* This is a stub. */
1117 }
1118
1119 void rtl92se_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1120 {
1121         struct rtl_priv *rtlpriv = rtl_priv(hw);
1122         u32 reg_rcr;
1123
1124         if (rtlpriv->psc.rfpwr_state != ERFON)
1125                 return;
1126
1127         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1128
1129         if (check_bssid) {
1130                 reg_rcr |= (RCR_CBSSID);
1131                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1132         } else if (!check_bssid) {
1133                 reg_rcr &= (~RCR_CBSSID);
1134                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1135         }
1136
1137 }
1138
1139 static int _rtl92se_set_media_status(struct ieee80211_hw *hw,
1140                                      enum nl80211_iftype type)
1141 {
1142         struct rtl_priv *rtlpriv = rtl_priv(hw);
1143         u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1144         u32 temp;
1145         bt_msr &= ~MSR_LINK_MASK;
1146
1147         switch (type) {
1148         case NL80211_IFTYPE_UNSPECIFIED:
1149                 bt_msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
1150                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1151                          "Set Network type to NO LINK!\n");
1152                 break;
1153         case NL80211_IFTYPE_ADHOC:
1154                 bt_msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT);
1155                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1156                          "Set Network type to Ad Hoc!\n");
1157                 break;
1158         case NL80211_IFTYPE_STATION:
1159                 bt_msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT);
1160                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1161                          "Set Network type to STA!\n");
1162                 break;
1163         case NL80211_IFTYPE_AP:
1164                 bt_msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT);
1165                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1166                          "Set Network type to AP!\n");
1167                 break;
1168         default:
1169                 pr_err("Network type %d not supported!\n", type);
1170                 return 1;
1171
1172         }
1173
1174         if (type != NL80211_IFTYPE_AP &&
1175             rtlpriv->mac80211.link_state < MAC80211_LINKED)
1176                 bt_msr = rtl_read_byte(rtlpriv, MSR) & ~MSR_LINK_MASK;
1177         rtl_write_byte(rtlpriv, MSR, bt_msr);
1178
1179         temp = rtl_read_dword(rtlpriv, TCR);
1180         rtl_write_dword(rtlpriv, TCR, temp & (~BIT(8)));
1181         rtl_write_dword(rtlpriv, TCR, temp | BIT(8));
1182
1183
1184         return 0;
1185 }
1186
1187 /* HW_VAR_MEDIA_STATUS & HW_VAR_CECHK_BSSID */
1188 int rtl92se_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1189 {
1190         struct rtl_priv *rtlpriv = rtl_priv(hw);
1191
1192         if (_rtl92se_set_media_status(hw, type))
1193                 return -EOPNOTSUPP;
1194
1195         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1196                 if (type != NL80211_IFTYPE_AP)
1197                         rtl92se_set_check_bssid(hw, true);
1198         } else {
1199                 rtl92se_set_check_bssid(hw, false);
1200         }
1201
1202         return 0;
1203 }
1204
1205 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1206 void rtl92se_set_qos(struct ieee80211_hw *hw, int aci)
1207 {
1208         struct rtl_priv *rtlpriv = rtl_priv(hw);
1209         rtl92s_dm_init_edca_turbo(hw);
1210
1211         switch (aci) {
1212         case AC1_BK:
1213                 rtl_write_dword(rtlpriv, EDCAPARA_BK, 0xa44f);
1214                 break;
1215         case AC0_BE:
1216                 /* rtl_write_dword(rtlpriv, EDCAPARA_BE, u4b_ac_param); */
1217                 break;
1218         case AC2_VI:
1219                 rtl_write_dword(rtlpriv, EDCAPARA_VI, 0x5e4322);
1220                 break;
1221         case AC3_VO:
1222                 rtl_write_dword(rtlpriv, EDCAPARA_VO, 0x2f3222);
1223                 break;
1224         default:
1225                 WARN_ONCE(true, "rtl8192se: invalid aci: %d !\n", aci);
1226                 break;
1227         }
1228 }
1229
1230 void rtl92se_enable_interrupt(struct ieee80211_hw *hw)
1231 {
1232         struct rtl_priv *rtlpriv = rtl_priv(hw);
1233         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1234
1235         rtl_write_dword(rtlpriv, INTA_MASK, rtlpci->irq_mask[0]);
1236         /* Support Bit 32-37(Assign as Bit 0-5) interrupt setting now */
1237         rtl_write_dword(rtlpriv, INTA_MASK + 4, rtlpci->irq_mask[1] & 0x3F);
1238         rtlpci->irq_enabled = true;
1239 }
1240
1241 void rtl92se_disable_interrupt(struct ieee80211_hw *hw)
1242 {
1243         struct rtl_priv *rtlpriv;
1244         struct rtl_pci *rtlpci;
1245
1246         rtlpriv = rtl_priv(hw);
1247         /* if firmware not available, no interrupts */
1248         if (!rtlpriv || !rtlpriv->max_fw_size)
1249                 return;
1250         rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1251         rtl_write_dword(rtlpriv, INTA_MASK, 0);
1252         rtl_write_dword(rtlpriv, INTA_MASK + 4, 0);
1253         rtlpci->irq_enabled = false;
1254 }
1255
1256 static u8 _rtl92s_set_sysclk(struct ieee80211_hw *hw, u8 data)
1257 {
1258         struct rtl_priv *rtlpriv = rtl_priv(hw);
1259         u8 waitcnt = 100;
1260         bool result = false;
1261         u8 tmp;
1262
1263         rtl_write_byte(rtlpriv, SYS_CLKR + 1, data);
1264
1265         /* Wait the MAC synchronized. */
1266         udelay(400);
1267
1268         /* Check if it is set ready. */
1269         tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
1270         result = ((tmp & BIT(7)) == (data & BIT(7)));
1271
1272         if ((data & (BIT(6) | BIT(7))) == false) {
1273                 waitcnt = 100;
1274                 tmp = 0;
1275
1276                 while (1) {
1277                         waitcnt--;
1278                         tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
1279
1280                         if ((tmp & BIT(6)))
1281                                 break;
1282
1283                         pr_err("wait for BIT(6) return value %x\n", tmp);
1284
1285                         if (waitcnt == 0)
1286                                 break;
1287                         udelay(10);
1288                 }
1289
1290                 if (waitcnt == 0)
1291                         result = false;
1292                 else
1293                         result = true;
1294         }
1295
1296         return result;
1297 }
1298
1299 static void _rtl92s_phy_set_rfhalt(struct ieee80211_hw *hw)
1300 {
1301         struct rtl_priv *rtlpriv = rtl_priv(hw);
1302         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1303         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1304         u8 u1btmp;
1305
1306         if (rtlhal->driver_going2unload)
1307                 rtl_write_byte(rtlpriv, 0x560, 0x0);
1308
1309         /* Power save for BB/RF */
1310         u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL);
1311         u1btmp |= BIT(0);
1312         rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp);
1313         rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0);
1314         rtl_write_byte(rtlpriv, TXPAUSE, 0xFF);
1315         rtl_write_word(rtlpriv, CMDR, 0x57FC);
1316         udelay(100);
1317         rtl_write_word(rtlpriv, CMDR, 0x77FC);
1318         rtl_write_byte(rtlpriv, PHY_CCA, 0x0);
1319         udelay(10);
1320         rtl_write_word(rtlpriv, CMDR, 0x37FC);
1321         udelay(10);
1322         rtl_write_word(rtlpriv, CMDR, 0x77FC);
1323         udelay(10);
1324         rtl_write_word(rtlpriv, CMDR, 0x57FC);
1325         rtl_write_word(rtlpriv, CMDR, 0x0000);
1326
1327         if (rtlhal->driver_going2unload) {
1328                 u1btmp = rtl_read_byte(rtlpriv, (REG_SYS_FUNC_EN + 1));
1329                 u1btmp &= ~(BIT(0));
1330                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, u1btmp);
1331         }
1332
1333         u1btmp = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1334
1335         /* Add description. After switch control path. register
1336          * after page1 will be invisible. We can not do any IO
1337          * for register>0x40. After resume&MACIO reset, we need
1338          * to remember previous reg content. */
1339         if (u1btmp & BIT(7)) {
1340                 u1btmp &= ~(BIT(6) | BIT(7));
1341                 if (!_rtl92s_set_sysclk(hw, u1btmp)) {
1342                         pr_err("Switch ctrl path fail\n");
1343                         return;
1344                 }
1345         }
1346
1347         /* Power save for MAC */
1348         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS  &&
1349                 !rtlhal->driver_going2unload) {
1350                 /* enable LED function */
1351                 rtl_write_byte(rtlpriv, 0x03, 0xF9);
1352         /* SW/HW radio off or halt adapter!! For example S3/S4 */
1353         } else {
1354                 /* LED function disable. Power range is about 8mA now. */
1355                 /* if write 0xF1 disconnet_pci power
1356                  *       ifconfig wlan0 down power are both high 35:70 */
1357                 /* if write oxF9 disconnet_pci power
1358                  * ifconfig wlan0 down power are both low  12:45*/
1359                 rtl_write_byte(rtlpriv, 0x03, 0xF9);
1360         }
1361
1362         rtl_write_byte(rtlpriv, SYS_CLKR + 1, 0x70);
1363         rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, 0x68);
1364         rtl_write_byte(rtlpriv,  AFE_PLL_CTRL, 0x00);
1365         rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
1366         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, 0x0E);
1367         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1368
1369 }
1370
1371 static void _rtl92se_gen_refreshledstate(struct ieee80211_hw *hw)
1372 {
1373         struct rtl_priv *rtlpriv = rtl_priv(hw);
1374         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1375         struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
1376
1377         if (rtlpci->up_first_time == 1)
1378                 return;
1379
1380         if (rtlpriv->psc.rfoff_reason == RF_CHANGE_BY_IPS)
1381                 rtl92se_sw_led_on(hw, pled0);
1382         else
1383                 rtl92se_sw_led_off(hw, pled0);
1384 }
1385
1386
1387 static void _rtl92se_power_domain_init(struct ieee80211_hw *hw)
1388 {
1389         struct rtl_priv *rtlpriv = rtl_priv(hw);
1390         u16 tmpu2b;
1391         u8 tmpu1b;
1392
1393         rtlpriv->psc.pwrdomain_protect = true;
1394
1395         tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1396         if (tmpu1b & BIT(7)) {
1397                 tmpu1b &= ~(BIT(6) | BIT(7));
1398                 if (!_rtl92s_set_sysclk(hw, tmpu1b)) {
1399                         rtlpriv->psc.pwrdomain_protect = false;
1400                         return;
1401                 }
1402         }
1403
1404         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0);
1405         rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
1406
1407         /* Reset MAC-IO and CPU and Core Digital BIT10/11/15 */
1408         tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1409
1410         /* If IPS we need to turn LED on. So we not
1411          * not disable BIT 3/7 of reg3. */
1412         if (rtlpriv->psc.rfoff_reason & (RF_CHANGE_BY_IPS | RF_CHANGE_BY_HW))
1413                 tmpu1b &= 0xFB;
1414         else
1415                 tmpu1b &= 0x73;
1416
1417         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
1418         /* wait for BIT 10/11/15 to pull high automatically!! */
1419         mdelay(1);
1420
1421         rtl_write_byte(rtlpriv, CMDR, 0);
1422         rtl_write_byte(rtlpriv, TCR, 0);
1423
1424         /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
1425         tmpu1b = rtl_read_byte(rtlpriv, 0x562);
1426         tmpu1b |= 0x08;
1427         rtl_write_byte(rtlpriv, 0x562, tmpu1b);
1428         tmpu1b &= ~(BIT(3));
1429         rtl_write_byte(rtlpriv, 0x562, tmpu1b);
1430
1431         /* Enable AFE clock source */
1432         tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL);
1433         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01));
1434         /* Delay 1.5ms */
1435         udelay(1500);
1436         tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1);
1437         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb));
1438
1439         /* Enable AFE Macro Block's Bandgap */
1440         tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
1441         rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0)));
1442         mdelay(1);
1443
1444         /* Enable AFE Mbias */
1445         tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
1446         rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02));
1447         mdelay(1);
1448
1449         /* Enable LDOA15 block */
1450         tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL);
1451         rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0)));
1452
1453         /* Set Digital Vdd to Retention isolation Path. */
1454         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
1455         rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11)));
1456
1457
1458         /* For warm reboot NIC disappera bug. */
1459         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1460         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13)));
1461
1462         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68);
1463
1464         /* Enable AFE PLL Macro Block */
1465         tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL);
1466         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
1467         /* Enable MAC 80MHZ clock */
1468         tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1);
1469         rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0)));
1470         mdelay(1);
1471
1472         /* Release isolation AFE PLL & MD */
1473         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6);
1474
1475         /* Enable MAC clock */
1476         tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
1477         rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11)));
1478
1479         /* Enable Core digital and enable IOREG R/W */
1480         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1481         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11)));
1482         /* enable REG_EN */
1483         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
1484
1485         /* Switch the control path. */
1486         tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
1487         rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2))));
1488
1489         tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1490         tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6)));
1491         if (!_rtl92s_set_sysclk(hw, tmpu1b)) {
1492                 rtlpriv->psc.pwrdomain_protect = false;
1493                 return;
1494         }
1495
1496         rtl_write_word(rtlpriv, CMDR, 0x37FC);
1497
1498         /* After MACIO reset,we must refresh LED state. */
1499         _rtl92se_gen_refreshledstate(hw);
1500
1501         rtlpriv->psc.pwrdomain_protect = false;
1502 }
1503
1504 void rtl92se_card_disable(struct ieee80211_hw *hw)
1505 {
1506         struct rtl_priv *rtlpriv = rtl_priv(hw);
1507         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1508         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1509         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1510         enum nl80211_iftype opmode;
1511         u8 wait = 30;
1512
1513         rtlpriv->intf_ops->enable_aspm(hw);
1514
1515         if (rtlpci->driver_is_goingto_unload ||
1516                 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1517                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1518
1519         /* we should chnge GPIO to input mode
1520          * this will drop away current about 25mA*/
1521         rtl8192se_gpiobit3_cfg_inputmode(hw);
1522
1523         /* this is very important for ips power save */
1524         while (wait-- >= 10 && rtlpriv->psc.pwrdomain_protect) {
1525                 if (rtlpriv->psc.pwrdomain_protect)
1526                         mdelay(20);
1527                 else
1528                         break;
1529         }
1530
1531         mac->link_state = MAC80211_NOLINK;
1532         opmode = NL80211_IFTYPE_UNSPECIFIED;
1533         _rtl92se_set_media_status(hw, opmode);
1534
1535         _rtl92s_phy_set_rfhalt(hw);
1536         udelay(100);
1537 }
1538
1539 void rtl92se_interrupt_recognized(struct ieee80211_hw *hw,
1540                                   struct rtl_int *intvec)
1541 {
1542         struct rtl_priv *rtlpriv = rtl_priv(hw);
1543         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1544
1545         intvec->inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1546         rtl_write_dword(rtlpriv, ISR, intvec->inta);
1547
1548         intvec->intb = rtl_read_dword(rtlpriv, ISR + 4) & rtlpci->irq_mask[1];
1549         rtl_write_dword(rtlpriv, ISR + 4, intvec->intb);
1550 }
1551
1552 void rtl92se_set_beacon_related_registers(struct ieee80211_hw *hw)
1553 {
1554         struct rtl_priv *rtlpriv = rtl_priv(hw);
1555         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1556         u16 bcntime_cfg = 0;
1557         u16 bcn_cw = 6, bcn_ifs = 0xf;
1558         u16 atim_window = 2;
1559
1560         /* ATIM Window (in unit of TU). */
1561         rtl_write_word(rtlpriv, ATIMWND, atim_window);
1562
1563         /* Beacon interval (in unit of TU). */
1564         rtl_write_word(rtlpriv, BCN_INTERVAL, mac->beacon_interval);
1565
1566         /* DrvErlyInt (in unit of TU). (Time to send
1567          * interrupt to notify driver to change
1568          * beacon content) */
1569         rtl_write_word(rtlpriv, BCN_DRV_EARLY_INT, 10 << 4);
1570
1571         /* BcnDMATIM(in unit of us). Indicates the
1572          * time before TBTT to perform beacon queue DMA  */
1573         rtl_write_word(rtlpriv, BCN_DMATIME, 256);
1574
1575         /* Force beacon frame transmission even
1576          * after receiving beacon frame from
1577          * other ad hoc STA */
1578         rtl_write_byte(rtlpriv, BCN_ERR_THRESH, 100);
1579
1580         /* Beacon Time Configuration */
1581         if (mac->opmode == NL80211_IFTYPE_ADHOC)
1582                 bcntime_cfg |= (bcn_cw << BCN_TCFG_CW_SHIFT);
1583
1584         /* TODO: bcn_ifs may required to be changed on ASIC */
1585         bcntime_cfg |= bcn_ifs << BCN_TCFG_IFS;
1586
1587         /*for beacon changed */
1588         rtl92s_phy_set_beacon_hwreg(hw, mac->beacon_interval);
1589 }
1590
1591 void rtl92se_set_beacon_interval(struct ieee80211_hw *hw)
1592 {
1593         struct rtl_priv *rtlpriv = rtl_priv(hw);
1594         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1595         u16 bcn_interval = mac->beacon_interval;
1596
1597         /* Beacon interval (in unit of TU). */
1598         rtl_write_word(rtlpriv, BCN_INTERVAL, bcn_interval);
1599         /* 2008.10.24 added by tynli for beacon changed. */
1600         rtl92s_phy_set_beacon_hwreg(hw, bcn_interval);
1601 }
1602
1603 void rtl92se_update_interrupt_mask(struct ieee80211_hw *hw,
1604                 u32 add_msr, u32 rm_msr)
1605 {
1606         struct rtl_priv *rtlpriv = rtl_priv(hw);
1607         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1608
1609         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1610                  add_msr, rm_msr);
1611
1612         if (add_msr)
1613                 rtlpci->irq_mask[0] |= add_msr;
1614
1615         if (rm_msr)
1616                 rtlpci->irq_mask[0] &= (~rm_msr);
1617
1618         rtl92se_disable_interrupt(hw);
1619         rtl92se_enable_interrupt(hw);
1620 }
1621
1622 static void _rtl8192se_get_ic_inferiority(struct ieee80211_hw *hw)
1623 {
1624         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1625         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1626         u8 efuse_id;
1627
1628         rtlhal->ic_class = IC_INFERIORITY_A;
1629
1630         /* Only retrieving while using EFUSE. */
1631         if ((rtlefuse->epromtype == EEPROM_BOOT_EFUSE) &&
1632                 !rtlefuse->autoload_failflag) {
1633                 efuse_id = efuse_read_1byte(hw, EFUSE_IC_ID_OFFSET);
1634
1635                 if (efuse_id == 0xfe)
1636                         rtlhal->ic_class = IC_INFERIORITY_B;
1637         }
1638 }
1639
1640 static void _rtl92se_read_adapter_info(struct ieee80211_hw *hw)
1641 {
1642         struct rtl_priv *rtlpriv = rtl_priv(hw);
1643         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1644         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1645         struct device *dev = &rtl_pcipriv(hw)->dev.pdev->dev;
1646         u16 i, usvalue;
1647         u16     eeprom_id;
1648         u8 tempval;
1649         u8 hwinfo[HWSET_MAX_SIZE_92S];
1650         u8 rf_path, index;
1651
1652         switch (rtlefuse->epromtype) {
1653         case EEPROM_BOOT_EFUSE:
1654                 rtl_efuse_shadow_map_update(hw);
1655                 break;
1656
1657         case EEPROM_93C46:
1658                 pr_err("RTL819X Not boot from eeprom, check it !!\n");
1659                 return;
1660
1661         default:
1662                 dev_warn(dev, "no efuse data\n");
1663                 return;
1664         }
1665
1666         memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1667                HWSET_MAX_SIZE_92S);
1668
1669         RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP",
1670                       hwinfo, HWSET_MAX_SIZE_92S);
1671
1672         eeprom_id = *((u16 *)&hwinfo[0]);
1673         if (eeprom_id != RTL8190_EEPROM_ID) {
1674                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1675                          "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
1676                 rtlefuse->autoload_failflag = true;
1677         } else {
1678                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1679                 rtlefuse->autoload_failflag = false;
1680         }
1681
1682         if (rtlefuse->autoload_failflag)
1683                 return;
1684
1685         _rtl8192se_get_ic_inferiority(hw);
1686
1687         /* Read IC Version && Channel Plan */
1688         /* VID, DID      SE     0xA-D */
1689         rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
1690         rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
1691         rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
1692         rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
1693         rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1694
1695         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1696                  "EEPROMId = 0x%4x\n", eeprom_id);
1697         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1698                  "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
1699         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1700                  "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
1701         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1702                  "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
1703         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1704                  "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
1705
1706         for (i = 0; i < 6; i += 2) {
1707                 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1708                 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1709         }
1710
1711         for (i = 0; i < 6; i++)
1712                 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
1713
1714         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr);
1715
1716         /* Get Tx Power Level by Channel */
1717         /* Read Tx power of Channel 1 ~ 14 from EEPROM. */
1718         /* 92S suupport RF A & B */
1719         for (rf_path = 0; rf_path < 2; rf_path++) {
1720                 for (i = 0; i < 3; i++) {
1721                         /* Read CCK RF A & B Tx power  */
1722                         rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] =
1723                         hwinfo[EEPROM_TXPOWERBASE + rf_path * 3 + i];
1724
1725                         /* Read OFDM RF A & B Tx power for 1T */
1726                         rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1727                         hwinfo[EEPROM_TXPOWERBASE + 6 + rf_path * 3 + i];
1728
1729                         /* Read OFDM RF A & B Tx power for 2T */
1730                         rtlefuse->eprom_chnl_txpwr_ht40_2sdf[rf_path][i]
1731                                  = hwinfo[EEPROM_TXPOWERBASE + 12 +
1732                                    rf_path * 3 + i];
1733                 }
1734         }
1735
1736         for (rf_path = 0; rf_path < 2; rf_path++)
1737                 for (i = 0; i < 3; i++)
1738                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1739                                 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
1740                                 rf_path, i,
1741                                 rtlefuse->eeprom_chnlarea_txpwr_cck
1742                                 [rf_path][i]);
1743         for (rf_path = 0; rf_path < 2; rf_path++)
1744                 for (i = 0; i < 3; i++)
1745                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1746                                 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1747                                 rf_path, i,
1748                                 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1749                                 [rf_path][i]);
1750         for (rf_path = 0; rf_path < 2; rf_path++)
1751                 for (i = 0; i < 3; i++)
1752                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1753                                 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1754                                 rf_path, i,
1755                                 rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1756                                 [rf_path][i]);
1757
1758         for (rf_path = 0; rf_path < 2; rf_path++) {
1759
1760                 /* Assign dedicated channel tx power */
1761                 for (i = 0; i < 14; i++)        {
1762                         /* channel 1~3 use the same Tx Power Level. */
1763                         if (i < 3)
1764                                 index = 0;
1765                         /* Channel 4-8 */
1766                         else if (i < 8)
1767                                 index = 1;
1768                         /* Channel 9-14 */
1769                         else
1770                                 index = 2;
1771
1772                         /* Record A & B CCK /OFDM - 1T/2T Channel area
1773                          * tx power */
1774                         rtlefuse->txpwrlevel_cck[rf_path][i]  =
1775                                 rtlefuse->eeprom_chnlarea_txpwr_cck
1776                                                         [rf_path][index];
1777                         rtlefuse->txpwrlevel_ht40_1s[rf_path][i]  =
1778                                 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1779                                                         [rf_path][index];
1780                         rtlefuse->txpwrlevel_ht40_2s[rf_path][i]  =
1781                                 rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1782                                                         [rf_path][index];
1783                 }
1784
1785                 for (i = 0; i < 14; i++) {
1786                         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1787                                 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1788                                 rf_path, i,
1789                                 rtlefuse->txpwrlevel_cck[rf_path][i],
1790                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1791                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
1792                 }
1793         }
1794
1795         for (rf_path = 0; rf_path < 2; rf_path++) {
1796                 for (i = 0; i < 3; i++) {
1797                         /* Read Power diff limit. */
1798                         rtlefuse->eeprom_pwrgroup[rf_path][i] =
1799                                 hwinfo[EEPROM_TXPWRGROUP + rf_path * 3 + i];
1800                 }
1801         }
1802
1803         for (rf_path = 0; rf_path < 2; rf_path++) {
1804                 /* Fill Pwr group */
1805                 for (i = 0; i < 14; i++) {
1806                         /* Chanel 1-3 */
1807                         if (i < 3)
1808                                 index = 0;
1809                         /* Channel 4-8 */
1810                         else if (i < 8)
1811                                 index = 1;
1812                         /* Channel 9-13 */
1813                         else
1814                                 index = 2;
1815
1816                         rtlefuse->pwrgroup_ht20[rf_path][i] =
1817                                 (rtlefuse->eeprom_pwrgroup[rf_path][index] &
1818                                 0xf);
1819                         rtlefuse->pwrgroup_ht40[rf_path][i] =
1820                                 ((rtlefuse->eeprom_pwrgroup[rf_path][index] &
1821                                 0xf0) >> 4);
1822
1823                         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1824                                 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1825                                 rf_path, i,
1826                                 rtlefuse->pwrgroup_ht20[rf_path][i]);
1827                         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1828                                 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1829                                 rf_path, i,
1830                                 rtlefuse->pwrgroup_ht40[rf_path][i]);
1831                         }
1832         }
1833
1834         for (i = 0; i < 14; i++) {
1835                 /* Read tx power difference between HT OFDM 20/40 MHZ */
1836                 /* channel 1-3 */
1837                 if (i < 3)
1838                         index = 0;
1839                 /* Channel 4-8 */
1840                 else if (i < 8)
1841                         index = 1;
1842                 /* Channel 9-14 */
1843                 else
1844                         index = 2;
1845
1846                 tempval = hwinfo[EEPROM_TX_PWR_HT20_DIFF + index] & 0xff;
1847                 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1848                 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1849                                                  ((tempval >> 4) & 0xF);
1850
1851                 /* Read OFDM<->HT tx power diff */
1852                 /* Channel 1-3 */
1853                 if (i < 3)
1854                         index = 0;
1855                 /* Channel 4-8 */
1856                 else if (i < 8)
1857                         index = 0x11;
1858                 /* Channel 9-14 */
1859                 else
1860                         index = 1;
1861
1862                 tempval = hwinfo[EEPROM_TX_PWR_OFDM_DIFF + index] & 0xff;
1863                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] =
1864                                  (tempval & 0xF);
1865                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1866                                  ((tempval >> 4) & 0xF);
1867
1868                 tempval = hwinfo[TX_PWR_SAFETY_CHK];
1869                 rtlefuse->txpwr_safetyflag = (tempval & 0x01);
1870         }
1871
1872         rtlefuse->eeprom_regulatory = 0;
1873         if (rtlefuse->eeprom_version >= 2) {
1874                 /* BIT(0)~2 */
1875                 if (rtlefuse->eeprom_version >= 4)
1876                         rtlefuse->eeprom_regulatory =
1877                                  (hwinfo[EEPROM_REGULATORY] & 0x7);
1878                 else /* BIT(0) */
1879                         rtlefuse->eeprom_regulatory =
1880                                  (hwinfo[EEPROM_REGULATORY] & 0x1);
1881         }
1882         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1883                 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1884
1885         for (i = 0; i < 14; i++)
1886                 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1887                         "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
1888                         i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
1889         for (i = 0; i < 14; i++)
1890                 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1891                         "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
1892                         i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
1893         for (i = 0; i < 14; i++)
1894                 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1895                         "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
1896                         i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
1897         for (i = 0; i < 14; i++)
1898                 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1899                         "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
1900                         i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
1901
1902         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1903                 "TxPwrSafetyFlag = %d\n", rtlefuse->txpwr_safetyflag);
1904
1905         /* Read RF-indication and Tx Power gain
1906          * index diff of legacy to HT OFDM rate. */
1907         tempval = hwinfo[EEPROM_RFIND_POWERDIFF] & 0xff;
1908         rtlefuse->eeprom_txpowerdiff = tempval;
1909         rtlefuse->legacy_httxpowerdiff =
1910                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][0];
1911
1912         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1913                 "TxPowerDiff = %#x\n", rtlefuse->eeprom_txpowerdiff);
1914
1915         /* Get TSSI value for each path. */
1916         usvalue = *(u16 *)&hwinfo[EEPROM_TSSI_A];
1917         rtlefuse->eeprom_tssi[RF90_PATH_A] = (u8)((usvalue & 0xff00) >> 8);
1918         usvalue = hwinfo[EEPROM_TSSI_B];
1919         rtlefuse->eeprom_tssi[RF90_PATH_B] = (u8)(usvalue & 0xff);
1920
1921         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1922                 rtlefuse->eeprom_tssi[RF90_PATH_A],
1923                 rtlefuse->eeprom_tssi[RF90_PATH_B]);
1924
1925         /* Read antenna tx power offset of B/C/D to A  from EEPROM */
1926         /* and read ThermalMeter from EEPROM */
1927         tempval = hwinfo[EEPROM_THERMALMETER];
1928         rtlefuse->eeprom_thermalmeter = tempval;
1929         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1930                 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1931
1932         /* ThermalMeter, BIT(0)~3 for RFIC1, BIT(4)~7 for RFIC2 */
1933         rtlefuse->thermalmeter[0] = (rtlefuse->eeprom_thermalmeter & 0x1f);
1934         rtlefuse->tssi_13dbm = rtlefuse->eeprom_thermalmeter * 100;
1935
1936         /* Read CrystalCap from EEPROM */
1937         tempval = hwinfo[EEPROM_CRYSTALCAP] >> 4;
1938         rtlefuse->eeprom_crystalcap = tempval;
1939         /* CrystalCap, BIT(12)~15 */
1940         rtlefuse->crystalcap = rtlefuse->eeprom_crystalcap;
1941
1942         /* Read IC Version && Channel Plan */
1943         /* Version ID, Channel plan */
1944         rtlefuse->eeprom_channelplan = hwinfo[EEPROM_CHANNELPLAN];
1945         rtlefuse->txpwr_fromeprom = true;
1946         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1947                 "EEPROM ChannelPlan = 0x%4x\n", rtlefuse->eeprom_channelplan);
1948
1949         /* Read Customer ID or Board Type!!! */
1950         tempval = hwinfo[EEPROM_BOARDTYPE];
1951         /* Change RF type definition */
1952         if (tempval == 0)
1953                 rtlphy->rf_type = RF_2T2R;
1954         else if (tempval == 1)
1955                 rtlphy->rf_type = RF_1T2R;
1956         else if (tempval == 2)
1957                 rtlphy->rf_type = RF_1T2R;
1958         else if (tempval == 3)
1959                 rtlphy->rf_type = RF_1T1R;
1960
1961         /* 1T2R but 1SS (1x1 receive combining) */
1962         rtlefuse->b1x1_recvcombine = false;
1963         if (rtlphy->rf_type == RF_1T2R) {
1964                 tempval = rtl_read_byte(rtlpriv, 0x07);
1965                 if (!(tempval & BIT(0))) {
1966                         rtlefuse->b1x1_recvcombine = true;
1967                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1968                                  "RF_TYPE=1T2R but only 1SS\n");
1969                 }
1970         }
1971         rtlefuse->b1ss_support = rtlefuse->b1x1_recvcombine;
1972         rtlefuse->eeprom_oemid = *&hwinfo[EEPROM_CUSTOMID];
1973
1974         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM Customer ID: 0x%2x\n",
1975                  rtlefuse->eeprom_oemid);
1976
1977         /* set channel paln to world wide 13 */
1978         rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
1979 }
1980
1981 void rtl92se_read_eeprom_info(struct ieee80211_hw *hw)
1982 {
1983         struct rtl_priv *rtlpriv = rtl_priv(hw);
1984         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1985         u8 tmp_u1b = 0;
1986
1987         tmp_u1b = rtl_read_byte(rtlpriv, EPROM_CMD);
1988
1989         if (tmp_u1b & BIT(4)) {
1990                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1991                 rtlefuse->epromtype = EEPROM_93C46;
1992         } else {
1993                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1994                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1995         }
1996
1997         if (tmp_u1b & BIT(5)) {
1998                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1999                 rtlefuse->autoload_failflag = false;
2000                 _rtl92se_read_adapter_info(hw);
2001         } else {
2002                 pr_err("Autoload ERR!!\n");
2003                 rtlefuse->autoload_failflag = true;
2004         }
2005 }
2006
2007 static void rtl92se_update_hal_rate_table(struct ieee80211_hw *hw,
2008                                           struct ieee80211_sta *sta)
2009 {
2010         struct rtl_priv *rtlpriv = rtl_priv(hw);
2011         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2012         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2013         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2014         u32 ratr_value;
2015         u8 ratr_index = 0;
2016         u8 nmode = mac->ht_enable;
2017         u8 mimo_ps = IEEE80211_SMPS_OFF;
2018         u16 shortgi_rate = 0;
2019         u32 tmp_ratr_value = 0;
2020         u8 curtxbw_40mhz = mac->bw_40;
2021         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2022                                 1 : 0;
2023         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2024                                 1 : 0;
2025         enum wireless_mode wirelessmode = mac->mode;
2026
2027         if (rtlhal->current_bandtype == BAND_ON_5G)
2028                 ratr_value = sta->supp_rates[1] << 4;
2029         else
2030                 ratr_value = sta->supp_rates[0];
2031         if (mac->opmode == NL80211_IFTYPE_ADHOC)
2032                 ratr_value = 0xfff;
2033         ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2034                         sta->ht_cap.mcs.rx_mask[0] << 12);
2035         switch (wirelessmode) {
2036         case WIRELESS_MODE_B:
2037                 ratr_value &= 0x0000000D;
2038                 break;
2039         case WIRELESS_MODE_G:
2040                 ratr_value &= 0x00000FF5;
2041                 break;
2042         case WIRELESS_MODE_N_24G:
2043         case WIRELESS_MODE_N_5G:
2044                 nmode = 1;
2045                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2046                         ratr_value &= 0x0007F005;
2047                 } else {
2048                         u32 ratr_mask;
2049
2050                         if (get_rf_type(rtlphy) == RF_1T2R ||
2051                             get_rf_type(rtlphy) == RF_1T1R) {
2052                                 if (curtxbw_40mhz)
2053                                         ratr_mask = 0x000ff015;
2054                                 else
2055                                         ratr_mask = 0x000ff005;
2056                         } else {
2057                                 if (curtxbw_40mhz)
2058                                         ratr_mask = 0x0f0ff015;
2059                                 else
2060                                         ratr_mask = 0x0f0ff005;
2061                         }
2062
2063                         ratr_value &= ratr_mask;
2064                 }
2065                 break;
2066         default:
2067                 if (rtlphy->rf_type == RF_1T2R)
2068                         ratr_value &= 0x000ff0ff;
2069                 else
2070                         ratr_value &= 0x0f0ff0ff;
2071
2072                 break;
2073         }
2074
2075         if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT)
2076                 ratr_value &= 0x0FFFFFFF;
2077         else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT)
2078                 ratr_value &= 0x0FFFFFF0;
2079
2080         if (nmode && ((curtxbw_40mhz &&
2081                          curshortgi_40mhz) || (!curtxbw_40mhz &&
2082                                                  curshortgi_20mhz))) {
2083
2084                 ratr_value |= 0x10000000;
2085                 tmp_ratr_value = (ratr_value >> 12);
2086
2087                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2088                         if ((1 << shortgi_rate) & tmp_ratr_value)
2089                                 break;
2090                 }
2091
2092                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2093                     (shortgi_rate << 4) | (shortgi_rate);
2094
2095                 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate);
2096         }
2097
2098         rtl_write_dword(rtlpriv, ARFR0 + ratr_index * 4, ratr_value);
2099         if (ratr_value & 0xfffff000)
2100                 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_N);
2101         else
2102                 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_BG);
2103
2104         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
2105                  rtl_read_dword(rtlpriv, ARFR0));
2106 }
2107
2108 static void rtl92se_update_hal_rate_mask(struct ieee80211_hw *hw,
2109                                          struct ieee80211_sta *sta,
2110                                          u8 rssi_level, bool update_bw)
2111 {
2112         struct rtl_priv *rtlpriv = rtl_priv(hw);
2113         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2114         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2115         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2116         struct rtl_sta_info *sta_entry = NULL;
2117         u32 ratr_bitmap;
2118         u8 ratr_index = 0;
2119         u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0;
2120         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2121                                 1 : 0;
2122         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2123                                 1 : 0;
2124         enum wireless_mode wirelessmode = 0;
2125         bool shortgi = false;
2126         u32 ratr_value = 0;
2127         u8 shortgi_rate = 0;
2128         u32 mask = 0;
2129         u32 band = 0;
2130         bool bmulticast = false;
2131         u8 macid = 0;
2132         u8 mimo_ps = IEEE80211_SMPS_OFF;
2133
2134         sta_entry = (struct rtl_sta_info *) sta->drv_priv;
2135         wirelessmode = sta_entry->wireless_mode;
2136         if (mac->opmode == NL80211_IFTYPE_STATION)
2137                 curtxbw_40mhz = mac->bw_40;
2138         else if (mac->opmode == NL80211_IFTYPE_AP ||
2139                 mac->opmode == NL80211_IFTYPE_ADHOC)
2140                 macid = sta->aid + 1;
2141
2142         if (rtlhal->current_bandtype == BAND_ON_5G)
2143                 ratr_bitmap = sta->supp_rates[1] << 4;
2144         else
2145                 ratr_bitmap = sta->supp_rates[0];
2146         if (mac->opmode == NL80211_IFTYPE_ADHOC)
2147                 ratr_bitmap = 0xfff;
2148         ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2149                         sta->ht_cap.mcs.rx_mask[0] << 12);
2150         switch (wirelessmode) {
2151         case WIRELESS_MODE_B:
2152                 band |= WIRELESS_11B;
2153                 ratr_index = RATR_INX_WIRELESS_B;
2154                 if (ratr_bitmap & 0x0000000c)
2155                         ratr_bitmap &= 0x0000000d;
2156                 else
2157                         ratr_bitmap &= 0x0000000f;
2158                 break;
2159         case WIRELESS_MODE_G:
2160                 band |= (WIRELESS_11G | WIRELESS_11B);
2161                 ratr_index = RATR_INX_WIRELESS_GB;
2162
2163                 if (rssi_level == 1)
2164                         ratr_bitmap &= 0x00000f00;
2165                 else if (rssi_level == 2)
2166                         ratr_bitmap &= 0x00000ff0;
2167                 else
2168                         ratr_bitmap &= 0x00000ff5;
2169                 break;
2170         case WIRELESS_MODE_A:
2171                 band |= WIRELESS_11A;
2172                 ratr_index = RATR_INX_WIRELESS_A;
2173                 ratr_bitmap &= 0x00000ff0;
2174                 break;
2175         case WIRELESS_MODE_N_24G:
2176         case WIRELESS_MODE_N_5G:
2177                 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B);
2178                 ratr_index = RATR_INX_WIRELESS_NGB;
2179
2180                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2181                         if (rssi_level == 1)
2182                                 ratr_bitmap &= 0x00070000;
2183                         else if (rssi_level == 2)
2184                                 ratr_bitmap &= 0x0007f000;
2185                         else
2186                                 ratr_bitmap &= 0x0007f005;
2187                 } else {
2188                         if (rtlphy->rf_type == RF_1T2R ||
2189                                 rtlphy->rf_type == RF_1T1R) {
2190                                 if (rssi_level == 1) {
2191                                                 ratr_bitmap &= 0x000f0000;
2192                                 } else if (rssi_level == 3) {
2193                                         ratr_bitmap &= 0x000fc000;
2194                                 } else if (rssi_level == 5) {
2195                                                 ratr_bitmap &= 0x000ff000;
2196                                 } else {
2197                                         if (curtxbw_40mhz)
2198                                                 ratr_bitmap &= 0x000ff015;
2199                                         else
2200                                                 ratr_bitmap &= 0x000ff005;
2201                                 }
2202                         } else {
2203                                 if (rssi_level == 1) {
2204                                         ratr_bitmap &= 0x0f8f0000;
2205                                 } else if (rssi_level == 3) {
2206                                         ratr_bitmap &= 0x0f8fc000;
2207                                 } else if (rssi_level == 5) {
2208                                         ratr_bitmap &= 0x0f8ff000;
2209                                 } else {
2210                                         if (curtxbw_40mhz)
2211                                                 ratr_bitmap &= 0x0f8ff015;
2212                                         else
2213                                                 ratr_bitmap &= 0x0f8ff005;
2214                                 }
2215                         }
2216                 }
2217
2218                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2219                     (!curtxbw_40mhz && curshortgi_20mhz)) {
2220                         if (macid == 0)
2221                                 shortgi = true;
2222                         else if (macid == 1)
2223                                 shortgi = false;
2224                 }
2225                 break;
2226         default:
2227                 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B);
2228                 ratr_index = RATR_INX_WIRELESS_NGB;
2229
2230                 if (rtlphy->rf_type == RF_1T2R)
2231                         ratr_bitmap &= 0x000ff0ff;
2232                 else
2233                         ratr_bitmap &= 0x0f8ff0ff;
2234                 break;
2235         }
2236         sta_entry->ratr_index = ratr_index;
2237
2238         if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT)
2239                 ratr_bitmap &= 0x0FFFFFFF;
2240         else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT)
2241                 ratr_bitmap &= 0x0FFFFFF0;
2242
2243         if (shortgi) {
2244                 ratr_bitmap |= 0x10000000;
2245                 /* Get MAX MCS available. */
2246                 ratr_value = (ratr_bitmap >> 12);
2247                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2248                         if ((1 << shortgi_rate) & ratr_value)
2249                                 break;
2250                 }
2251
2252                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2253                         (shortgi_rate << 4) | (shortgi_rate);
2254                 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate);
2255         }
2256
2257         mask |= (bmulticast ? 1 : 0) << 9 | (macid & 0x1f) << 4 | (band & 0xf);
2258
2259         RT_TRACE(rtlpriv, COMP_RATR, DBG_TRACE, "mask = %x, bitmap = %x\n",
2260                  mask, ratr_bitmap);
2261         rtl_write_dword(rtlpriv, 0x2c4, ratr_bitmap);
2262         rtl_write_dword(rtlpriv, WFM5, (FW_RA_UPDATE_MASK | (mask << 8)));
2263
2264         if (macid != 0)
2265                 sta_entry->ratr_index = ratr_index;
2266 }
2267
2268 void rtl92se_update_hal_rate_tbl(struct ieee80211_hw *hw,
2269                 struct ieee80211_sta *sta, u8 rssi_level, bool update_bw)
2270 {
2271         struct rtl_priv *rtlpriv = rtl_priv(hw);
2272
2273         if (rtlpriv->dm.useramask)
2274                 rtl92se_update_hal_rate_mask(hw, sta, rssi_level, update_bw);
2275         else
2276                 rtl92se_update_hal_rate_table(hw, sta);
2277 }
2278
2279 void rtl92se_update_channel_access_setting(struct ieee80211_hw *hw)
2280 {
2281         struct rtl_priv *rtlpriv = rtl_priv(hw);
2282         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2283         u16 sifs_timer;
2284
2285         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2286                                       &mac->slot_time);
2287         sifs_timer = 0x0e0e;
2288         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2289
2290 }
2291
2292 /* this ifunction is for RFKILL, it's different with windows,
2293  * because UI will disable wireless when GPIO Radio Off.
2294  * And here we not check or Disable/Enable ASPM like windows*/
2295 bool rtl92se_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2296 {
2297         struct rtl_priv *rtlpriv = rtl_priv(hw);
2298         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2299         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2300         enum rf_pwrstate rfpwr_toset /*, cur_rfstate */;
2301         unsigned long flag = 0;
2302         bool actuallyset = false;
2303         bool turnonbypowerdomain = false;
2304
2305         /* just 8191se can check gpio before firstup, 92c/92d have fixed it */
2306         if ((rtlpci->up_first_time == 1) || (rtlpci->being_init_adapter))
2307                 return false;
2308
2309         if (ppsc->swrf_processing)
2310                 return false;
2311
2312         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2313         if (ppsc->rfchange_inprogress) {
2314                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2315                 return false;
2316         } else {
2317                 ppsc->rfchange_inprogress = true;
2318                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2319         }
2320
2321         /* cur_rfstate = ppsc->rfpwr_state;*/
2322
2323         /* because after _rtl92s_phy_set_rfhalt, all power
2324          * closed, so we must open some power for GPIO check,
2325          * or we will always check GPIO RFOFF here,
2326          * And we should close power after GPIO check */
2327         if (RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
2328                 _rtl92se_power_domain_init(hw);
2329                 turnonbypowerdomain = true;
2330         }
2331
2332         rfpwr_toset = _rtl92se_rf_onoff_detect(hw);
2333
2334         if ((ppsc->hwradiooff) && (rfpwr_toset == ERFON)) {
2335                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2336                          "RFKILL-HW Radio ON, RF ON\n");
2337
2338                 rfpwr_toset = ERFON;
2339                 ppsc->hwradiooff = false;
2340                 actuallyset = true;
2341         } else if ((!ppsc->hwradiooff) && (rfpwr_toset == ERFOFF)) {
2342                 RT_TRACE(rtlpriv, COMP_RF,
2343                          DBG_DMESG, "RFKILL-HW Radio OFF, RF OFF\n");
2344
2345                 rfpwr_toset = ERFOFF;
2346                 ppsc->hwradiooff = true;
2347                 actuallyset = true;
2348         }
2349
2350         if (actuallyset) {
2351                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2352                 ppsc->rfchange_inprogress = false;
2353                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2354
2355         /* this not include ifconfig wlan0 down case */
2356         /* } else if (rfpwr_toset == ERFOFF || cur_rfstate == ERFOFF) { */
2357         } else {
2358                 /* because power_domain_init may be happen when
2359                  * _rtl92s_phy_set_rfhalt, this will open some powers
2360                  * and cause current increasing about 40 mA for ips,
2361                  * rfoff and ifconfig down, so we set
2362                  * _rtl92s_phy_set_rfhalt again here */
2363                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC &&
2364                         turnonbypowerdomain) {
2365                         _rtl92s_phy_set_rfhalt(hw);
2366                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2367                 }
2368
2369                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2370                 ppsc->rfchange_inprogress = false;
2371                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2372         }
2373
2374         *valid = 1;
2375         return !ppsc->hwradiooff;
2376
2377 }
2378
2379 /* Is_wepkey just used for WEP used as group & pairwise key
2380  * if pairwise is AES ang group is WEP Is_wepkey == false.*/
2381 void rtl92se_set_key(struct ieee80211_hw *hw, u32 key_index, u8 *p_macaddr,
2382         bool is_group, u8 enc_algo, bool is_wepkey, bool clear_all)
2383 {
2384         struct rtl_priv *rtlpriv = rtl_priv(hw);
2385         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2386         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2387         u8 *macaddr = p_macaddr;
2388
2389         u32 entry_id = 0;
2390         bool is_pairwise = false;
2391
2392         static u8 cam_const_addr[4][6] = {
2393                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2394                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2395                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2396                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2397         };
2398         static u8 cam_const_broad[] = {
2399                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2400         };
2401
2402         if (clear_all) {
2403                 u8 idx = 0;
2404                 u8 cam_offset = 0;
2405                 u8 clear_number = 5;
2406
2407                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2408
2409                 for (idx = 0; idx < clear_number; idx++) {
2410                         rtl_cam_mark_invalid(hw, cam_offset + idx);
2411                         rtl_cam_empty_entry(hw, cam_offset + idx);
2412
2413                         if (idx < 5) {
2414                                 memset(rtlpriv->sec.key_buf[idx], 0,
2415                                        MAX_KEY_LEN);
2416                                 rtlpriv->sec.key_len[idx] = 0;
2417                         }
2418                 }
2419
2420         } else {
2421                 switch (enc_algo) {
2422                 case WEP40_ENCRYPTION:
2423                         enc_algo = CAM_WEP40;
2424                         break;
2425                 case WEP104_ENCRYPTION:
2426                         enc_algo = CAM_WEP104;
2427                         break;
2428                 case TKIP_ENCRYPTION:
2429                         enc_algo = CAM_TKIP;
2430                         break;
2431                 case AESCCMP_ENCRYPTION:
2432                         enc_algo = CAM_AES;
2433                         break;
2434                 default:
2435                         pr_err("switch case %#x not processed\n",
2436                                enc_algo);
2437                         enc_algo = CAM_TKIP;
2438                         break;
2439                 }
2440
2441                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2442                         macaddr = cam_const_addr[key_index];
2443                         entry_id = key_index;
2444                 } else {
2445                         if (is_group) {
2446                                 macaddr = cam_const_broad;
2447                                 entry_id = key_index;
2448                         } else {
2449                                 if (mac->opmode == NL80211_IFTYPE_AP) {
2450                                         entry_id = rtl_cam_get_free_entry(hw,
2451                                                                  p_macaddr);
2452                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
2453                                                 pr_err("Can not find free hw security cam entry\n");
2454                                                 return;
2455                                         }
2456                                 } else {
2457                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
2458                                 }
2459
2460                                 key_index = PAIRWISE_KEYIDX;
2461                                 is_pairwise = true;
2462                         }
2463                 }
2464
2465                 if (rtlpriv->sec.key_len[key_index] == 0) {
2466                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2467                                  "delete one entry, entry_id is %d\n",
2468                                  entry_id);
2469                         if (mac->opmode == NL80211_IFTYPE_AP)
2470                                 rtl_cam_del_entry(hw, p_macaddr);
2471                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2472                 } else {
2473                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2474                                  "add one entry\n");
2475                         if (is_pairwise) {
2476                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2477                                          "set Pairwise key\n");
2478
2479                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2480                                         entry_id, enc_algo,
2481                                         CAM_CONFIG_NO_USEDK,
2482                                         rtlpriv->sec.key_buf[key_index]);
2483                         } else {
2484                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2485                                          "set group key\n");
2486
2487                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2488                                         rtl_cam_add_one_entry(hw,
2489                                                 rtlefuse->dev_addr,
2490                                                 PAIRWISE_KEYIDX,
2491                                                 CAM_PAIRWISE_KEY_POSITION,
2492                                                 enc_algo, CAM_CONFIG_NO_USEDK,
2493                                                 rtlpriv->sec.key_buf[entry_id]);
2494                                 }
2495
2496                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2497                                               entry_id, enc_algo,
2498                                               CAM_CONFIG_NO_USEDK,
2499                                               rtlpriv->sec.key_buf[entry_id]);
2500                         }
2501
2502                 }
2503         }
2504 }
2505
2506 void rtl92se_suspend(struct ieee80211_hw *hw)
2507 {
2508         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2509
2510         rtlpci->up_first_time = true;
2511 }
2512
2513 void rtl92se_resume(struct ieee80211_hw *hw)
2514 {
2515         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2516         u32 val;
2517
2518         pci_read_config_dword(rtlpci->pdev, 0x40, &val);
2519         if ((val & 0x0000ff00) != 0)
2520                 pci_write_config_dword(rtlpci->pdev, 0x40,
2521                         val & 0xffff00ff);
2522 }