drivers/net/wireless/realtek/rtlwifi/rtl8192ee/sw.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright(c) 2009-2014  Realtek Corporation.*/
   3
   4 #include "../wifi.h"
   5 #include "../core.h"
   6 #include "../pci.h"
   7 #include "reg.h"
   8 #include "def.h"
   9 #include "phy.h"
  10 #include "dm.h"
  11 #include "hw.h"
  12 #include "sw.h"
  13 #include "fw.h"
  14 #include "trx.h"
  15 #include "led.h"
  16 #include "table.h"
  17
  18 #include "../btcoexist/rtl_btc.h"
  19
  20 #include <linux/vmalloc.h>
  21 #include <linux/module.h>
  22
  23 static void rtl92ee_init_aspm_vars(struct ieee80211_hw *hw)
  24 {
  25         struct rtl_priv *rtlpriv = rtl_priv(hw);
  26         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  27
  28         /*close ASPM for AMD defaultly */
  29         rtlpci->const_amdpci_aspm = 0;
  30
  31         /**
  32          * ASPM PS mode.
  33          * 0 - Disable ASPM,
  34          * 1 - Enable ASPM without Clock Req,
  35          * 2 - Enable ASPM with Clock Req,
  36          * 3 - Alwyas Enable ASPM with Clock Req,
  37          * 4 - Always Enable ASPM without Clock Req.
  38          * set defult to RTL8192CE:3 RTL8192E:2
  39          */
  40         rtlpci->const_pci_aspm = 3;
  41
  42         /*Setting for PCI-E device */
  43         rtlpci->const_devicepci_aspm_setting = 0x03;
  44
  45         /*Setting for PCI-E bridge */
  46         rtlpci->const_hostpci_aspm_setting = 0x02;
  47
  48         /**
  49          * In Hw/Sw Radio Off situation.
  50          * 0 - Default,
  51          * 1 - From ASPM setting without low Mac Pwr,
  52          * 2 - From ASPM setting with low Mac Pwr,
  53          * 3 - Bus D3
  54          * set default to RTL8192CE:0 RTL8192SE:2
  55          */
  56         rtlpci->const_hwsw_rfoff_d3 = 0;
  57
  58         /**
  59          * This setting works for those device with
  60          * backdoor ASPM setting such as EPHY setting.
  61          * 0 - Not support ASPM,
  62          * 1 - Support ASPM,
  63          * 2 - According to chipset.
  64          */
  65         rtlpci->const_support_pciaspm = rtlpriv->cfg->mod_params->aspm_support;
  66 }
  67
  68 int rtl92ee_init_sw_vars(struct ieee80211_hw *hw)
  69 {
  70         struct rtl_priv *rtlpriv = rtl_priv(hw);
  71         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  72         int err = 0;
  73         char *fw_name;
  74
  75         rtl92ee_bt_reg_init(hw);
  76         rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
  77         rtlpriv->btcoexist.btc_ops = rtl_btc_get_ops_pointer();
  78
  79         rtlpriv->dm.dm_initialgain_enable = 1;
  80         rtlpriv->dm.dm_flag = 0;
  81         rtlpriv->dm.disable_framebursting = 0;
  82         rtlpci->transmit_config = CFENDFORM | BIT(15);
  83
  84         /*just 2.4G band*/
  85         rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
  86         rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
  87         rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
  88
  89         rtlpci->receive_config = (RCR_APPFCS                    |
  90                                   RCR_APP_MIC                   |
  91                                   RCR_APP_ICV                   |
  92                                   RCR_APP_PHYST_RXFF            |
  93                                   RCR_HTC_LOC_CTRL              |
  94                                   RCR_AMF                       |
  95                                   RCR_ACF                       |
  96                                   RCR_ACRC32                    |
  97                                   RCR_AB                        |
  98                                   RCR_AM                        |
  99                                   RCR_APM                       |
 100                                   0);
 101
 102         rtlpci->irq_mask[0] = (u32)(IMR_PSTIMEOUT               |
 103                                      IMR_C2HCMD                 |
 104                                      IMR_HIGHDOK                |
 105                                      IMR_MGNTDOK                |
 106                                      IMR_BKDOK                  |
 107                                      IMR_BEDOK                  |
 108                                      IMR_VIDOK                  |
 109                                      IMR_VODOK                  |
 110                                      IMR_RDU                    |
 111                                      IMR_ROK                    |
 112                                      0);
 113         rtlpci->irq_mask[1] = (u32)(IMR_RXFOVW | 0);
 114
 115         /* for LPS & IPS */
 116         rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
 117         rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
 118         rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
 119         rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
 120         if (rtlpriv->cfg->mod_params->disable_watchdog)
 121                 pr_info("watchdog disabled\n");
 122         rtlpriv->psc.reg_fwctrl_lps = 3;
 123         rtlpriv->psc.reg_max_lps_awakeintvl = 5;
 124         /* for ASPM, you can close aspm through
 125          * set const_support_pciaspm = 0
 126          */
 127         rtl92ee_init_aspm_vars(hw);
 128
 129         if (rtlpriv->psc.reg_fwctrl_lps == 1)
 130                 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
 131         else if (rtlpriv->psc.reg_fwctrl_lps == 2)
 132                 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
 133         else if (rtlpriv->psc.reg_fwctrl_lps == 3)
 134                 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
 135
 136         /* for early mode */
 137         rtlpriv->rtlhal.earlymode_enable = false;
 138
 139         /*low power */
 140         rtlpriv->psc.low_power_enable = false;
 141
 142         /* for firmware buf */
 143         rtlpriv->rtlhal.pfirmware = vzalloc(0x8000);
 144         if (!rtlpriv->rtlhal.pfirmware) {
 145                 pr_err("Can't alloc buffer for fw\n");
 146                 return 1;
 147         }
 148
 149         /* request fw */
 150         fw_name = "/*(DEBLOBBED)*/";
 151
 152         rtlpriv->max_fw_size = 0x8000;
 153         pr_info("Using firmware %s\n", fw_name);
 154         err = reject_firmware_nowait(THIS_MODULE, 1, fw_name,
 155                                       rtlpriv->io.dev, GFP_KERNEL, hw,
 156                                       rtl_fw_cb);
 157         if (err) {
 158                 pr_err("Failed to request firmware!\n");
 159                 vfree(rtlpriv->rtlhal.pfirmware);
 160                 rtlpriv->rtlhal.pfirmware = NULL;
 161                 return 1;
 162         }
 163
 164         return 0;
 165 }
 166
 167 void rtl92ee_deinit_sw_vars(struct ieee80211_hw *hw)
 168 {
 169         struct rtl_priv *rtlpriv = rtl_priv(hw);
 170
 171         if (rtlpriv->rtlhal.pfirmware) {
 172                 vfree(rtlpriv->rtlhal.pfirmware);
 173                 rtlpriv->rtlhal.pfirmware = NULL;
 174         }
 175 }
 176
 177 /* get bt coexist status */
 178 bool rtl92ee_get_btc_status(void)
 179 {
 180         return true;
 181 }
 182
 183 static struct rtl_hal_ops rtl8192ee_hal_ops = {
 184         .init_sw_vars = rtl92ee_init_sw_vars,
 185         .deinit_sw_vars = rtl92ee_deinit_sw_vars,
 186         .read_eeprom_info = rtl92ee_read_eeprom_info,
 187         .interrupt_recognized = rtl92ee_interrupt_recognized,/*need check*/
 188         .hw_init = rtl92ee_hw_init,
 189         .hw_disable = rtl92ee_card_disable,
 190         .hw_suspend = rtl92ee_suspend,
 191         .hw_resume = rtl92ee_resume,
 192         .enable_interrupt = rtl92ee_enable_interrupt,
 193         .disable_interrupt = rtl92ee_disable_interrupt,
 194         .set_network_type = rtl92ee_set_network_type,
 195         .set_chk_bssid = rtl92ee_set_check_bssid,
 196         .set_qos = rtl92ee_set_qos,
 197         .set_bcn_reg = rtl92ee_set_beacon_related_registers,
 198         .set_bcn_intv = rtl92ee_set_beacon_interval,
 199         .update_interrupt_mask = rtl92ee_update_interrupt_mask,
 200         .get_hw_reg = rtl92ee_get_hw_reg,
 201         .set_hw_reg = rtl92ee_set_hw_reg,
 202         .update_rate_tbl = rtl92ee_update_hal_rate_tbl,
 203         .pre_fill_tx_bd_desc = rtl92ee_pre_fill_tx_bd_desc,
 204         .rx_desc_buff_remained_cnt = rtl92ee_rx_desc_buff_remained_cnt,
 205         .rx_check_dma_ok = rtl92ee_rx_check_dma_ok,
 206         .fill_tx_desc = rtl92ee_tx_fill_desc,
 207         .fill_tx_cmddesc = rtl92ee_tx_fill_cmddesc,
 208         .query_rx_desc = rtl92ee_rx_query_desc,
 209         .set_channel_access = rtl92ee_update_channel_access_setting,
 210         .radio_onoff_checking = rtl92ee_gpio_radio_on_off_checking,
 211         .set_bw_mode = rtl92ee_phy_set_bw_mode,
 212         .switch_channel = rtl92ee_phy_sw_chnl,
 213         .dm_watchdog = rtl92ee_dm_watchdog,
 214         .scan_operation_backup = rtl92ee_phy_scan_operation_backup,
 215         .set_rf_power_state = rtl92ee_phy_set_rf_power_state,
 216         .led_control = rtl92ee_led_control,
 217         .set_desc = rtl92ee_set_desc,
 218         .get_desc = rtl92ee_get_desc,
 219         .is_tx_desc_closed = rtl92ee_is_tx_desc_closed,
 220         .get_available_desc = rtl92ee_get_available_desc,
 221         .tx_polling = rtl92ee_tx_polling,
 222         .enable_hw_sec = rtl92ee_enable_hw_security_config,
 223         .set_key = rtl92ee_set_key,
 224         .init_sw_leds = rtl92ee_init_sw_leds,
 225         .get_bbreg = rtl92ee_phy_query_bb_reg,
 226         .set_bbreg = rtl92ee_phy_set_bb_reg,
 227         .get_rfreg = rtl92ee_phy_query_rf_reg,
 228         .set_rfreg = rtl92ee_phy_set_rf_reg,
 229         .fill_h2c_cmd = rtl92ee_fill_h2c_cmd,
 230         .get_btc_status = rtl92ee_get_btc_status,
 231         .c2h_ra_report_handler = rtl92ee_c2h_ra_report_handler,
 232 };
 233
 234 static struct rtl_mod_params rtl92ee_mod_params = {
 235         .sw_crypto = false,
 236         .inactiveps = true,
 237         .swctrl_lps = false,
 238         .fwctrl_lps = true,
 239         .msi_support = true,
 240         .dma64 = false,
 241         .aspm_support = 1,
 242         .debug_level = 0,
 243         .debug_mask = 0,
 244 };
 245
 246 static const struct rtl_hal_cfg rtl92ee_hal_cfg = {
 247         .bar_id = 2,
 248         .write_readback = true,
 249         .name = "rtl92ee_pci",
 250         .ops = &rtl8192ee_hal_ops,
 251         .mod_params = &rtl92ee_mod_params,
 252
 253         .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
 254         .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
 255         .maps[SYS_CLK] = REG_SYS_CLKR,
 256         .maps[MAC_RCR_AM] = AM,
 257         .maps[MAC_RCR_AB] = AB,
 258         .maps[MAC_RCR_ACRC32] = ACRC32,
 259         .maps[MAC_RCR_ACF] = ACF,
 260         .maps[MAC_RCR_AAP] = AAP,
 261         .maps[MAC_HIMR] = REG_HIMR,
 262         .maps[MAC_HIMRE] = REG_HIMRE,
 263
 264         .maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS,
 265
 266         .maps[EFUSE_TEST] = REG_EFUSE_TEST,
 267         .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
 268         .maps[EFUSE_CLK] = 0,
 269         .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
 270         .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
 271         .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
 272         .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
 273         .maps[EFUSE_ANA8M] = ANA8M,
 274         .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
 275         .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
 276         .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
 277         .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
 278
 279         .maps[RWCAM] = REG_CAMCMD,
 280         .maps[WCAMI] = REG_CAMWRITE,
 281         .maps[RCAMO] = REG_CAMREAD,
 282         .maps[CAMDBG] = REG_CAMDBG,
 283         .maps[SECR] = REG_SECCFG,
 284         .maps[SEC_CAM_NONE] = CAM_NONE,
 285         .maps[SEC_CAM_WEP40] = CAM_WEP40,
 286         .maps[SEC_CAM_TKIP] = CAM_TKIP,
 287         .maps[SEC_CAM_AES] = CAM_AES,
 288         .maps[SEC_CAM_WEP104] = CAM_WEP104,
 289
 290         .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
 291         .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
 292         .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
 293         .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
 294         .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
 295         .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
 296         .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
 297         .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
 298         .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
 299         .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
 300         .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
 301         .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
 302         .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
 303
 304         .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
 305         .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
 306         .maps[RTL_IMR_BCNINT] = IMR_BCNDMAINT0,
 307         .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
 308         .maps[RTL_IMR_RDU] = IMR_RDU,
 309         .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
 310         .maps[RTL_IMR_BDOK] = IMR_BCNDOK0,
 311         .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
 312         .maps[RTL_IMR_TBDER] = IMR_TBDER,
 313         .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
 314         .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
 315         .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
 316         .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
 317         .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
 318         .maps[RTL_IMR_VODOK] = IMR_VODOK,
 319         .maps[RTL_IMR_ROK] = IMR_ROK,
 320         .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 | IMR_TBDOK | IMR_TBDER),
 321
 322         .maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M,
 323         .maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M,
 324         .maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M,
 325         .maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M,
 326         .maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M,
 327         .maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M,
 328         .maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M,
 329         .maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M,
 330         .maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M,
 331         .maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M,
 332         .maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M,
 333         .maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M,
 334
 335         .maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7,
 336         .maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15,
 337 };
 338
 339 static const struct pci_device_id rtl92ee_pci_ids[] = {
 340         {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x818B, rtl92ee_hal_cfg)},
 341         {},
 342 };
 343
 344 MODULE_DEVICE_TABLE(pci, rtl92ee_pci_ids);
 345
 346 MODULE_AUTHOR("Realtek WlanFAE  <wlanfae@realtek.com>");
 347 MODULE_AUTHOR("Larry Finger     <Larry.Finger@lwfinger.net>");
 348 MODULE_LICENSE("GPL");
 349 MODULE_DESCRIPTION("Realtek 8192EE 802.11n PCI wireless");
 350 /*(DEBLOBBED)*/
 351
 352 module_param_named(swenc, rtl92ee_mod_params.sw_crypto, bool, 0444);
 353 module_param_named(debug_level, rtl92ee_mod_params.debug_level, int, 0644);
 354 module_param_named(debug_mask, rtl92ee_mod_params.debug_mask, ullong, 0644);
 355 module_param_named(ips, rtl92ee_mod_params.inactiveps, bool, 0444);
 356 module_param_named(swlps, rtl92ee_mod_params.swctrl_lps, bool, 0444);
 357 module_param_named(fwlps, rtl92ee_mod_params.fwctrl_lps, bool, 0444);
 358 module_param_named(msi, rtl92ee_mod_params.msi_support, bool, 0444);
 359 module_param_named(dma64, rtl92ee_mod_params.dma64, bool, 0444);
 360 module_param_named(aspm, rtl92ee_mod_params.aspm_support, int, 0444);
 361 module_param_named(disable_watchdog, rtl92ee_mod_params.disable_watchdog,
 362                    bool, 0444);
 363 MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
 364 MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
 365 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
 366 MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
 367 MODULE_PARM_DESC(msi, "Set to 1 to use MSI interrupts mode (default 1)\n");
 368 MODULE_PARM_DESC(dma64, "Set to 1 to use DMA 64 (default 0)\n");
 369 MODULE_PARM_DESC(aspm, "Set to 1 to enable ASPM (default 1)\n");
 370 MODULE_PARM_DESC(debug_level, "Set debug level (0-5) (default 0)");
 371 MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)");
 372 MODULE_PARM_DESC(disable_watchdog, "Set to 1 to disable the watchdog (default 0)\n");
 373
 374 static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
 375
 376 static struct pci_driver rtl92ee_driver = {
 377         .name = KBUILD_MODNAME,
 378         .id_table = rtl92ee_pci_ids,
 379         .probe = rtl_pci_probe,
 380         .remove = rtl_pci_disconnect,
 381         .driver.pm = &rtlwifi_pm_ops,
 382 };
 383
 384 module_pci_driver(rtl92ee_driver);