drivers/net/wireless/realtek/rtlwifi/rtl8192ee/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2014  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #include "../wifi.h"
  27 #include "../efuse.h"
  28 #include "../base.h"
  29 #include "../regd.h"
  30 #include "../cam.h"
  31 #include "../ps.h"
  32 #include "../pci.h"
  33 #include "reg.h"
  34 #include "def.h"
  35 #include "phy.h"
  36 #include "dm.h"
  37 #include "fw.h"
  38 #include "led.h"
  39 #include "hw.h"
  40 #include "../pwrseqcmd.h"
  41 #include "pwrseq.h"
  42
  43 #define LLT_CONFIG      5
  44
  45 static void _rtl92ee_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
  46                                       u8 set_bits, u8 clear_bits)
  47 {
  48         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  49         struct rtl_priv *rtlpriv = rtl_priv(hw);
  50
  51         rtlpci->reg_bcn_ctrl_val |= set_bits;
  52         rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
  53
  54         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
  55 }
  56
  57 static void _rtl92ee_stop_tx_beacon(struct ieee80211_hw *hw)
  58 {
  59         struct rtl_priv *rtlpriv = rtl_priv(hw);
  60         u8 tmp;
  61
  62         tmp = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  63         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp & (~BIT(6)));
  64         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
  65         tmp = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  66         tmp &= ~(BIT(0));
  67         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp);
  68 }
  69
  70 static void _rtl92ee_resume_tx_beacon(struct ieee80211_hw *hw)
  71 {
  72         struct rtl_priv *rtlpriv = rtl_priv(hw);
  73         u8 tmp;
  74
  75         tmp = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  76         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp | BIT(6));
  77         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
  78         tmp = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  79         tmp |= BIT(0);
  80         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp);
  81 }
  82
  83 static void _rtl92ee_enable_bcn_sub_func(struct ieee80211_hw *hw)
  84 {
  85         _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(1));
  86 }
  87
  88 static void _rtl92ee_disable_bcn_sub_func(struct ieee80211_hw *hw)
  89 {
  90         _rtl92ee_set_bcn_ctrl_reg(hw, BIT(1), 0);
  91 }
  92
  93 static void _rtl92ee_set_fw_clock_on(struct ieee80211_hw *hw,
  94                                      u8 rpwm_val, bool b_need_turn_off_ckk)
  95 {
  96         struct rtl_priv *rtlpriv = rtl_priv(hw);
  97         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  98         bool b_support_remote_wake_up;
  99         u32 count = 0, isr_regaddr, content;
 100         bool b_schedule_timer = b_need_turn_off_ckk;
 101
 102         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
 103                                       (u8 *)(&b_support_remote_wake_up));
 104
 105         if (!rtlhal->fw_ready)
 106                 return;
 107         if (!rtlpriv->psc.fw_current_inpsmode)
 108                 return;
 109
 110         while (1) {
 111                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 112                 if (rtlhal->fw_clk_change_in_progress) {
 113                         while (rtlhal->fw_clk_change_in_progress) {
 114                                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 115                                 count++;
 116                                 udelay(100);
 117                                 if (count > 1000)
 118                                         return;
 119                                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 120                         }
 121                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 122                 } else {
 123                         rtlhal->fw_clk_change_in_progress = false;
 124                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 125                         break;
 126                 }
 127         }
 128
 129         if (IS_IN_LOW_POWER_STATE_92E(rtlhal->fw_ps_state)) {
 130                 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
 131                                               (u8 *)(&rpwm_val));
 132                 if (FW_PS_IS_ACK(rpwm_val)) {
 133                         isr_regaddr = REG_HISR;
 134                         content = rtl_read_dword(rtlpriv, isr_regaddr);
 135                         while (!(content & IMR_CPWM) && (count < 500)) {
 136                                 udelay(50);
 137                                 count++;
 138                                 content = rtl_read_dword(rtlpriv, isr_regaddr);
 139                         }
 140
 141                         if (content & IMR_CPWM) {
 142                                 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
 143                                 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_92E;
 144                                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
 145                                          "Receive CPWM INT!!! PSState = %X\n",
 146                                          rtlhal->fw_ps_state);
 147                         }
 148                 }
 149
 150                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 151                 rtlhal->fw_clk_change_in_progress = false;
 152                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 153                 if (b_schedule_timer) {
 154                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 155                                   jiffies + MSECS(10));
 156                 }
 157         } else  {
 158                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 159                 rtlhal->fw_clk_change_in_progress = false;
 160                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 161         }
 162 }
 163
 164 static void _rtl92ee_set_fw_clock_off(struct ieee80211_hw *hw, u8 rpwm_val)
 165 {
 166         struct rtl_priv *rtlpriv = rtl_priv(hw);
 167         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 168         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 169         struct rtl8192_tx_ring *ring;
 170         enum rf_pwrstate rtstate;
 171         bool b_schedule_timer = false;
 172         u8 queue;
 173
 174         if (!rtlhal->fw_ready)
 175                 return;
 176         if (!rtlpriv->psc.fw_current_inpsmode)
 177                 return;
 178         if (!rtlhal->allow_sw_to_change_hwclc)
 179                 return;
 180
 181         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
 182         if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
 183                 return;
 184
 185         for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
 186                 ring = &rtlpci->tx_ring[queue];
 187                 if (skb_queue_len(&ring->queue)) {
 188                         b_schedule_timer = true;
 189                         break;
 190                 }
 191         }
 192
 193         if (b_schedule_timer) {
 194                 mod_timer(&rtlpriv->works.fw_clockoff_timer,
 195                           jiffies + MSECS(10));
 196                 return;
 197         }
 198
 199         if (FW_PS_STATE(rtlhal->fw_ps_state) != FW_PS_STATE_RF_OFF_LOW_PWR) {
 200                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 201                 if (!rtlhal->fw_clk_change_in_progress) {
 202                         rtlhal->fw_clk_change_in_progress = true;
 203                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 204                         rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
 205                         rtl_write_word(rtlpriv, REG_HISR, 0x0100);
 206                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 207                                                       (u8 *)(&rpwm_val));
 208                         spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 209                         rtlhal->fw_clk_change_in_progress = false;
 210                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 211                 } else {
 212                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 213                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 214                                   jiffies + MSECS(10));
 215                 }
 216         }
 217 }
 218
 219 static void _rtl92ee_set_fw_ps_rf_on(struct ieee80211_hw *hw)
 220 {
 221         u8 rpwm_val = 0;
 222
 223         rpwm_val |= (FW_PS_STATE_RF_OFF_92E | FW_PS_ACK);
 224         _rtl92ee_set_fw_clock_on(hw, rpwm_val, true);
 225 }
 226
 227 static void _rtl92ee_set_fw_ps_rf_off_low_power(struct ieee80211_hw *hw)
 228 {
 229         u8 rpwm_val = 0;
 230
 231         rpwm_val |= FW_PS_STATE_RF_OFF_LOW_PWR;
 232         _rtl92ee_set_fw_clock_off(hw, rpwm_val);
 233 }
 234
 235 void rtl92ee_fw_clk_off_timer_callback(unsigned long data)
 236 {
 237         struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
 238
 239         _rtl92ee_set_fw_ps_rf_off_low_power(hw);
 240 }
 241
 242 static void _rtl92ee_fwlps_leave(struct ieee80211_hw *hw)
 243 {
 244         struct rtl_priv *rtlpriv = rtl_priv(hw);
 245         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 246         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 247         bool fw_current_inps = false;
 248         u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
 249
 250         if (ppsc->low_power_enable) {
 251                 rpwm_val = (FW_PS_STATE_ALL_ON_92E | FW_PS_ACK);/* RF on */
 252                 _rtl92ee_set_fw_clock_on(hw, rpwm_val, false);
 253                 rtlhal->allow_sw_to_change_hwclc = false;
 254                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 255                                               (u8 *)(&fw_pwrmode));
 256                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 257                                               (u8 *)(&fw_current_inps));
 258         } else {
 259                 rpwm_val = FW_PS_STATE_ALL_ON_92E;      /* RF on */
 260                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 261                                               (u8 *)(&rpwm_val));
 262                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 263                                               (u8 *)(&fw_pwrmode));
 264                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 265                                               (u8 *)(&fw_current_inps));
 266         }
 267 }
 268
 269 static void _rtl92ee_fwlps_enter(struct ieee80211_hw *hw)
 270 {
 271         struct rtl_priv *rtlpriv = rtl_priv(hw);
 272         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 273         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 274         bool fw_current_inps = true;
 275         u8 rpwm_val;
 276
 277         if (ppsc->low_power_enable) {
 278                 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR;  /* RF off */
 279                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 280                                               (u8 *)(&fw_current_inps));
 281                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 282                                               (u8 *)(&ppsc->fwctrl_psmode));
 283                 rtlhal->allow_sw_to_change_hwclc = true;
 284                 _rtl92ee_set_fw_clock_off(hw, rpwm_val);
 285         } else {
 286                 rpwm_val = FW_PS_STATE_RF_OFF_92E;      /* RF off */
 287                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 288                                               (u8 *)(&fw_current_inps));
 289                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 290                                               (u8 *)(&ppsc->fwctrl_psmode));
 291                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 292                                               (u8 *)(&rpwm_val));
 293         }
 294 }
 295
 296 void rtl92ee_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 297 {
 298         struct rtl_priv *rtlpriv = rtl_priv(hw);
 299         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 300         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 301
 302         switch (variable) {
 303         case HW_VAR_RCR:
 304                 *((u32 *)(val)) = rtlpci->receive_config;
 305                 break;
 306         case HW_VAR_RF_STATE:
 307                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
 308                 break;
 309         case HW_VAR_FWLPS_RF_ON:{
 310                         enum rf_pwrstate rfstate;
 311                         u32 val_rcr;
 312
 313                         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
 314                                                       (u8 *)(&rfstate));
 315                         if (rfstate == ERFOFF) {
 316                                 *((bool *)(val)) = true;
 317                         } else {
 318                                 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
 319                                 val_rcr &= 0x00070000;
 320                                 if (val_rcr)
 321                                         *((bool *)(val)) = false;
 322                                 else
 323                                         *((bool *)(val)) = true;
 324                         }
 325                 }
 326                 break;
 327         case HW_VAR_FW_PSMODE_STATUS:
 328                 *((bool *)(val)) = ppsc->fw_current_inpsmode;
 329                 break;
 330         case HW_VAR_CORRECT_TSF:{
 331                 u64 tsf;
 332                 u32 *ptsf_low = (u32 *)&tsf;
 333                 u32 *ptsf_high = ((u32 *)&tsf) + 1;
 334
 335                 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
 336                 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
 337
 338                 *((u64 *)(val)) = tsf;
 339                 }
 340                 break;
 341         case HAL_DEF_WOWLAN:
 342                 break;
 343         default:
 344                 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
 345                          "switch case %#x not processed\n", variable);
 346                 break;
 347         }
 348 }
 349
 350 static void _rtl92ee_download_rsvd_page(struct ieee80211_hw *hw)
 351 {
 352         struct rtl_priv *rtlpriv = rtl_priv(hw);
 353         u8 tmp_regcr, tmp_reg422;
 354         u8 bcnvalid_reg, txbc_reg;
 355         u8 count = 0, dlbcn_count = 0;
 356         bool b_recover = false;
 357
 358         /*Set REG_CR bit 8. DMA beacon by SW.*/
 359         tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 360         rtl_write_byte(rtlpriv, REG_CR + 1, tmp_regcr | BIT(0));
 361
 362         /* Disable Hw protection for a time which revserd for Hw sending beacon.
 363          * Fix download reserved page packet fail
 364          * that access collision with the protection time.
 365          * 2010.05.11. Added by tynli.
 366          */
 367         _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
 368         _rtl92ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
 369
 370         /* Set FWHW_TXQ_CTRL 0x422[6]=0 to
 371          * tell Hw the packet is not a real beacon frame.
 372          */
 373         tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
 374         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422 & (~BIT(6)));
 375
 376         if (tmp_reg422 & BIT(6))
 377                 b_recover = true;
 378
 379         do {
 380                 /* Clear beacon valid check bit */
 381                 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_DWBCN0_CTRL + 2);
 382                 rtl_write_byte(rtlpriv, REG_DWBCN0_CTRL + 2,
 383                                bcnvalid_reg | BIT(0));
 384
 385                 /* download rsvd page */
 386                 rtl92ee_set_fw_rsvdpagepkt(hw, false);
 387
 388                 txbc_reg = rtl_read_byte(rtlpriv, REG_MGQ_TXBD_NUM + 3);
 389                 count = 0;
 390                 while ((txbc_reg & BIT(4)) && count < 20) {
 391                         count++;
 392                         udelay(10);
 393                         txbc_reg = rtl_read_byte(rtlpriv, REG_MGQ_TXBD_NUM + 3);
 394                 }
 395                 rtl_write_byte(rtlpriv, REG_MGQ_TXBD_NUM + 3,
 396                                txbc_reg | BIT(4));
 397
 398                 /* check rsvd page download OK. */
 399                 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_DWBCN0_CTRL + 2);
 400                 count = 0;
 401                 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
 402                         count++;
 403                         udelay(50);
 404                         bcnvalid_reg = rtl_read_byte(rtlpriv,
 405                                                      REG_DWBCN0_CTRL + 2);
 406                 }
 407
 408                 if (bcnvalid_reg & BIT(0))
 409                         rtl_write_byte(rtlpriv, REG_DWBCN0_CTRL + 2, BIT(0));
 410
 411                 dlbcn_count++;
 412         } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
 413
 414         if (!(bcnvalid_reg & BIT(0)))
 415                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 416                          "Download RSVD page failed!\n");
 417
 418         /* Enable Bcn */
 419         _rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
 420         _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
 421
 422         if (b_recover)
 423                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422);
 424
 425         tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 426         rtl_write_byte(rtlpriv, REG_CR + 1, tmp_regcr & (~BIT(0)));
 427 }
 428
 429 void rtl92ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 430 {
 431         struct rtl_priv *rtlpriv = rtl_priv(hw);
 432         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 433         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 434         struct rtl_efuse *efuse = rtl_efuse(rtl_priv(hw));
 435         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 436         u8 idx;
 437
 438         switch (variable) {
 439         case HW_VAR_ETHER_ADDR:
 440                 for (idx = 0; idx < ETH_ALEN; idx++)
 441                         rtl_write_byte(rtlpriv, (REG_MACID + idx), val[idx]);
 442                 break;
 443         case HW_VAR_BASIC_RATE:{
 444                 u16 b_rate_cfg = ((u16 *)val)[0];
 445
 446                 b_rate_cfg = b_rate_cfg & 0x15f;
 447                 b_rate_cfg |= 0x01;
 448                 b_rate_cfg = (b_rate_cfg | 0xd) & (~BIT(1));
 449                 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
 450                 rtl_write_byte(rtlpriv, REG_RRSR + 1, (b_rate_cfg >> 8) & 0xff);
 451                 break; }
 452         case HW_VAR_BSSID:
 453                 for (idx = 0; idx < ETH_ALEN; idx++)
 454                         rtl_write_byte(rtlpriv, (REG_BSSID + idx), val[idx]);
 455                 break;
 456         case HW_VAR_SIFS:
 457                 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
 458                 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
 459
 460                 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
 461                 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
 462
 463                 if (!mac->ht_enable)
 464                         rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 0x0e0e);
 465                 else
 466                         rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 467                                        *((u16 *)val));
 468                 break;
 469         case HW_VAR_SLOT_TIME:{
 470                 u8 e_aci;
 471
 472                 RT_TRACE(rtlpriv, COMP_MLME, DBG_TRACE,
 473                          "HW_VAR_SLOT_TIME %x\n", val[0]);
 474
 475                 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
 476
 477                 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 478                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
 479                                                       (u8 *)(&e_aci));
 480                 }
 481                 break; }
 482         case HW_VAR_ACK_PREAMBLE:{
 483                 u8 reg_tmp;
 484                 u8 short_preamble = (bool)(*(u8 *)val);
 485
 486                 reg_tmp = (rtlpriv->mac80211.cur_40_prime_sc) << 5;
 487                 if (short_preamble)
 488                         reg_tmp |= 0x80;
 489                 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
 490                 rtlpriv->mac80211.short_preamble = short_preamble;
 491                 }
 492                 break;
 493         case HW_VAR_WPA_CONFIG:
 494                 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
 495                 break;
 496         case HW_VAR_AMPDU_FACTOR:{
 497                 u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 };
 498                 u8 fac;
 499                 u8 *reg = NULL;
 500                 u8 i = 0;
 501
 502                 reg = regtoset_normal;
 503
 504                 fac = *((u8 *)val);
 505                 if (fac <= 3) {
 506                         fac = (1 << (fac + 2));
 507                         if (fac > 0xf)
 508                                 fac = 0xf;
 509                         for (i = 0; i < 4; i++) {
 510                                 if ((reg[i] & 0xf0) > (fac << 4))
 511                                         reg[i] = (reg[i] & 0x0f) |
 512                                                 (fac << 4);
 513                                 if ((reg[i] & 0x0f) > fac)
 514                                         reg[i] = (reg[i] & 0xf0) | fac;
 515                                 rtl_write_byte(rtlpriv,
 516                                                (REG_AGGLEN_LMT + i),
 517                                                reg[i]);
 518                         }
 519                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 520                                  "Set HW_VAR_AMPDU_FACTOR:%#x\n", fac);
 521                 }
 522                 }
 523                 break;
 524         case HW_VAR_AC_PARAM:{
 525                 u8 e_aci = *((u8 *)val);
 526
 527                 if (rtlpci->acm_method != EACMWAY2_SW)
 528                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL,
 529                                                       (u8 *)(&e_aci));
 530                 }
 531                 break;
 532         case HW_VAR_ACM_CTRL:{
 533                 u8 e_aci = *((u8 *)val);
 534                 union aci_aifsn *aifs = (union aci_aifsn *)(&mac->ac[0].aifs);
 535
 536                 u8 acm = aifs->f.acm;
 537                 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
 538
 539                 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
 540
 541                 if (acm) {
 542                         switch (e_aci) {
 543                         case AC0_BE:
 544                                 acm_ctrl |= ACMHW_BEQEN;
 545                                 break;
 546                         case AC2_VI:
 547                                 acm_ctrl |= ACMHW_VIQEN;
 548                                 break;
 549                         case AC3_VO:
 550                                 acm_ctrl |= ACMHW_VOQEN;
 551                                 break;
 552                         default:
 553                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 554                                          "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
 555                                          acm);
 556                                 break;
 557                         }
 558                 } else {
 559                         switch (e_aci) {
 560                         case AC0_BE:
 561                                 acm_ctrl &= (~ACMHW_BEQEN);
 562                                 break;
 563                         case AC2_VI:
 564                                 acm_ctrl &= (~ACMHW_VIQEN);
 565                                 break;
 566                         case AC3_VO:
 567                                 acm_ctrl &= (~ACMHW_VOQEN);
 568                                 break;
 569                         default:
 570                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
 571                                          "switch case %#x not processed\n",
 572                                          e_aci);
 573                                 break;
 574                         }
 575                 }
 576
 577                 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 578                          "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
 579                           acm_ctrl);
 580                 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
 581                 }
 582                 break;
 583         case HW_VAR_RCR:{
 584                 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
 585                 rtlpci->receive_config = ((u32 *)(val))[0];
 586                 }
 587                 break;
 588         case HW_VAR_RETRY_LIMIT:{
 589                 u8 retry_limit = ((u8 *)(val))[0];
 590
 591                 rtl_write_word(rtlpriv, REG_RETRY_LIMIT,
 592                                retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 593                                retry_limit << RETRY_LIMIT_LONG_SHIFT);
 594                 }
 595                 break;
 596         case HW_VAR_DUAL_TSF_RST:
 597                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
 598                 break;
 599         case HW_VAR_EFUSE_BYTES:
 600                 efuse->efuse_usedbytes = *((u16 *)val);
 601                 break;
 602         case HW_VAR_EFUSE_USAGE:
 603                 efuse->efuse_usedpercentage = *((u8 *)val);
 604                 break;
 605         case HW_VAR_IO_CMD:
 606                 rtl92ee_phy_set_io_cmd(hw, (*(enum io_type *)val));
 607                 break;
 608         case HW_VAR_SET_RPWM:{
 609                 u8 rpwm_val;
 610
 611                 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
 612                 udelay(1);
 613
 614                 if (rpwm_val & BIT(7)) {
 615                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, (*(u8 *)val));
 616                 } else {
 617                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 618                                        ((*(u8 *)val) | BIT(7)));
 619                 }
 620                 }
 621                 break;
 622         case HW_VAR_H2C_FW_PWRMODE:
 623                 rtl92ee_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
 624                 break;
 625         case HW_VAR_FW_PSMODE_STATUS:
 626                 ppsc->fw_current_inpsmode = *((bool *)val);
 627                 break;
 628         case HW_VAR_RESUME_CLK_ON:
 629                 _rtl92ee_set_fw_ps_rf_on(hw);
 630                 break;
 631         case HW_VAR_FW_LPS_ACTION:{
 632                 bool b_enter_fwlps = *((bool *)val);
 633
 634                 if (b_enter_fwlps)
 635                         _rtl92ee_fwlps_enter(hw);
 636                 else
 637                         _rtl92ee_fwlps_leave(hw);
 638                 }
 639                 break;
 640         case HW_VAR_H2C_FW_JOINBSSRPT:{
 641                 u8 mstatus = (*(u8 *)val);
 642
 643                 if (mstatus == RT_MEDIA_CONNECT) {
 644                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
 645                         _rtl92ee_download_rsvd_page(hw);
 646                 }
 647                 rtl92ee_set_fw_media_status_rpt_cmd(hw, mstatus);
 648                 }
 649                 break;
 650         case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
 651                 rtl92ee_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
 652                 break;
 653         case HW_VAR_AID:{
 654                 u16 u2btmp;
 655
 656                 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
 657                 u2btmp &= 0xC000;
 658                 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
 659                                (u2btmp | mac->assoc_id));
 660                 }
 661                 break;
 662         case HW_VAR_CORRECT_TSF:{
 663                 u8 btype_ibss = ((u8 *)(val))[0];
 664
 665                 if (btype_ibss)
 666                         _rtl92ee_stop_tx_beacon(hw);
 667
 668                 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
 669
 670                 rtl_write_dword(rtlpriv, REG_TSFTR,
 671                                 (u32)(mac->tsf & 0xffffffff));
 672                 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
 673                                 (u32)((mac->tsf >> 32) & 0xffffffff));
 674
 675                 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
 676
 677                 if (btype_ibss)
 678                         _rtl92ee_resume_tx_beacon(hw);
 679                 }
 680                 break;
 681         case HW_VAR_KEEP_ALIVE: {
 682                 u8 array[2];
 683
 684                 array[0] = 0xff;
 685                 array[1] = *((u8 *)val);
 686                 rtl92ee_fill_h2c_cmd(hw, H2C_92E_KEEP_ALIVE_CTRL, 2, array);
 687                 }
 688                 break;
 689         default:
 690                 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
 691                          "switch case %#x not processed\n", variable);
 692                 break;
 693         }
 694 }
 695
 696 static bool _rtl92ee_llt_table_init(struct ieee80211_hw *hw)
 697 {
 698         struct rtl_priv *rtlpriv = rtl_priv(hw);
 699         u8 txpktbuf_bndy;
 700         u8 u8tmp, testcnt = 0;
 701
 702         txpktbuf_bndy = 0xFA;
 703
 704         rtl_write_dword(rtlpriv, REG_RQPN, 0x80E90808);
 705
 706         rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
 707         rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x3d00 - 1);
 708
 709         rtl_write_byte(rtlpriv, REG_DWBCN0_CTRL + 1, txpktbuf_bndy);
 710         rtl_write_byte(rtlpriv, REG_DWBCN1_CTRL + 1, txpktbuf_bndy);
 711
 712         rtl_write_byte(rtlpriv, REG_BCNQ_BDNY, txpktbuf_bndy);
 713         rtl_write_byte(rtlpriv, REG_BCNQ1_BDNY, txpktbuf_bndy);
 714
 715         rtl_write_byte(rtlpriv, REG_MGQ_BDNY, txpktbuf_bndy);
 716         rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
 717
 718         rtl_write_byte(rtlpriv, REG_PBP, 0x31);
 719         rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
 720
 721         u8tmp = rtl_read_byte(rtlpriv, REG_AUTO_LLT + 2);
 722         rtl_write_byte(rtlpriv, REG_AUTO_LLT + 2, u8tmp | BIT(0));
 723
 724         while (u8tmp & BIT(0)) {
 725                 u8tmp = rtl_read_byte(rtlpriv, REG_AUTO_LLT + 2);
 726                 udelay(10);
 727                 testcnt++;
 728                 if (testcnt > 10)
 729                         break;
 730         }
 731
 732         return true;
 733 }
 734
 735 static void _rtl92ee_gen_refresh_led_state(struct ieee80211_hw *hw)
 736 {
 737         struct rtl_priv *rtlpriv = rtl_priv(hw);
 738         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 739         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 740         struct rtl_led *pled0 = &pcipriv->ledctl.sw_led0;
 741
 742         if (rtlpriv->rtlhal.up_first_time)
 743                 return;
 744
 745         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 746                 rtl92ee_sw_led_on(hw, pled0);
 747         else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
 748                 rtl92ee_sw_led_on(hw, pled0);
 749         else
 750                 rtl92ee_sw_led_off(hw, pled0);
 751 }
 752
 753 static bool _rtl92ee_init_mac(struct ieee80211_hw *hw)
 754 {
 755         struct rtl_priv *rtlpriv = rtl_priv(hw);
 756         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 757         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 758
 759         u8 bytetmp;
 760         u16 wordtmp;
 761         u32 dwordtmp;
 762
 763         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
 764
 765         dwordtmp = rtl_read_dword(rtlpriv, REG_SYS_CFG1);
 766         if (dwordtmp & BIT(24)) {
 767                 rtl_write_byte(rtlpriv, 0x7c, 0xc3);
 768         } else {
 769                 bytetmp = rtl_read_byte(rtlpriv, 0x16);
 770                 rtl_write_byte(rtlpriv, 0x16, bytetmp | BIT(4) | BIT(6));
 771                 rtl_write_byte(rtlpriv, 0x7c, 0x83);
 772         }
 773         /* 1. 40Mhz crystal source*/
 774         bytetmp = rtl_read_byte(rtlpriv, REG_AFE_CTRL2);
 775         bytetmp &= 0xfb;
 776         rtl_write_byte(rtlpriv, REG_AFE_CTRL2, bytetmp);
 777
 778         dwordtmp = rtl_read_dword(rtlpriv, REG_AFE_CTRL4);
 779         dwordtmp &= 0xfffffc7f;
 780         rtl_write_dword(rtlpriv, REG_AFE_CTRL4, dwordtmp);
 781
 782         /* 2. 92E AFE parameter
 783          * MP chip then check version
 784          */
 785         bytetmp = rtl_read_byte(rtlpriv, REG_AFE_CTRL2);
 786         bytetmp &= 0xbf;
 787         rtl_write_byte(rtlpriv, REG_AFE_CTRL2, bytetmp);
 788
 789         dwordtmp = rtl_read_dword(rtlpriv, REG_AFE_CTRL4);
 790         dwordtmp &= 0xffdfffff;
 791         rtl_write_dword(rtlpriv, REG_AFE_CTRL4, dwordtmp);
 792
 793         /* HW Power on sequence */
 794         if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
 795                                       PWR_INTF_PCI_MSK,
 796                                       RTL8192E_NIC_ENABLE_FLOW)) {
 797                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 798                          "init MAC Fail as rtl_hal_pwrseqcmdparsing\n");
 799                 return false;
 800         }
 801
 802         /* Release MAC IO register reset */
 803         bytetmp = rtl_read_byte(rtlpriv, REG_CR);
 804         bytetmp = 0xff;
 805         rtl_write_byte(rtlpriv, REG_CR, bytetmp);
 806         mdelay(2);
 807         bytetmp = 0x7f;
 808         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp);
 809         mdelay(2);
 810
 811         /* Add for wakeup online */
 812         bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
 813         rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp | BIT(3));
 814         bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1);
 815         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp & (~BIT(4)));
 816         /* Release MAC IO register reset */
 817         rtl_write_word(rtlpriv, REG_CR, 0x2ff);
 818
 819         if (!rtlhal->mac_func_enable) {
 820                 if (_rtl92ee_llt_table_init(hw) == false) {
 821                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 822                                  "LLT table init fail\n");
 823                         return false;
 824                 }
 825         }
 826
 827         rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
 828         rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
 829
 830         wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
 831         wordtmp &= 0xf;
 832         wordtmp |= 0xF5B1;
 833         rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
 834         /* Reported Tx status from HW for rate adaptive.*/
 835         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
 836
 837         /* Set RCR register */
 838         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
 839         rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xffff);
 840
 841         /* Set TCR register */
 842         rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
 843
 844         /* Set TX/RX descriptor physical address(from OS API). */
 845         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
 846                         ((u64)rtlpci->tx_ring[BEACON_QUEUE].buffer_desc_dma) &
 847                         DMA_BIT_MASK(32));
 848         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
 849                         (u64)rtlpci->tx_ring[MGNT_QUEUE].buffer_desc_dma &
 850                         DMA_BIT_MASK(32));
 851         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
 852                         (u64)rtlpci->tx_ring[VO_QUEUE].buffer_desc_dma &
 853                         DMA_BIT_MASK(32));
 854         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
 855                         (u64)rtlpci->tx_ring[VI_QUEUE].buffer_desc_dma &
 856                         DMA_BIT_MASK(32));
 857
 858         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
 859                         (u64)rtlpci->tx_ring[BE_QUEUE].buffer_desc_dma &
 860                         DMA_BIT_MASK(32));
 861
 862         dwordtmp = rtl_read_dword(rtlpriv, REG_BEQ_DESA);
 863
 864         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
 865                         (u64)rtlpci->tx_ring[BK_QUEUE].buffer_desc_dma &
 866                         DMA_BIT_MASK(32));
 867         rtl_write_dword(rtlpriv, REG_HQ0_DESA,
 868                         (u64)rtlpci->tx_ring[HIGH_QUEUE].buffer_desc_dma &
 869                         DMA_BIT_MASK(32));
 870
 871         rtl_write_dword(rtlpriv, REG_RX_DESA,
 872                         (u64)rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
 873                         DMA_BIT_MASK(32));
 874
 875         /* if we want to support 64 bit DMA, we should set it here,
 876          * but now we do not support 64 bit DMA
 877          */
 878
 879         rtl_write_dword(rtlpriv, REG_TSFTIMER_HCI, 0x3fffffff);
 880
 881         bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 3);
 882         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, bytetmp | 0xF7);
 883
 884         rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
 885
 886         rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
 887
 888         rtl_write_word(rtlpriv, REG_MGQ_TXBD_NUM,
 889                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 890         rtl_write_word(rtlpriv, REG_VOQ_TXBD_NUM,
 891                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 892         rtl_write_word(rtlpriv, REG_VIQ_TXBD_NUM,
 893                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 894         rtl_write_word(rtlpriv, REG_BEQ_TXBD_NUM,
 895                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 896         rtl_write_word(rtlpriv, REG_VOQ_TXBD_NUM,
 897                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 898         rtl_write_word(rtlpriv, REG_BKQ_TXBD_NUM,
 899                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 900         rtl_write_word(rtlpriv, REG_HI0Q_TXBD_NUM,
 901                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 902         rtl_write_word(rtlpriv, REG_HI1Q_TXBD_NUM,
 903                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 904         rtl_write_word(rtlpriv, REG_HI2Q_TXBD_NUM,
 905                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 906         rtl_write_word(rtlpriv, REG_HI3Q_TXBD_NUM,
 907                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 908         rtl_write_word(rtlpriv, REG_HI4Q_TXBD_NUM,
 909                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 910         rtl_write_word(rtlpriv, REG_HI5Q_TXBD_NUM,
 911                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 912         rtl_write_word(rtlpriv, REG_HI6Q_TXBD_NUM,
 913                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 914         rtl_write_word(rtlpriv, REG_HI7Q_TXBD_NUM,
 915                        TX_DESC_NUM_92E | ((RTL8192EE_SEG_NUM << 12) & 0x3000));
 916         /*Rx*/
 917 #if (DMA_IS_64BIT == 1)
 918         rtl_write_word(rtlpriv, REG_RX_RXBD_NUM,
 919                        RX_DESC_NUM_92E |
 920                        ((RTL8192EE_SEG_NUM << 13) & 0x6000) | 0x8000);
 921 #else
 922         rtl_write_word(rtlpriv, REG_RX_RXBD_NUM,
 923                        RX_DESC_NUM_92E |
 924                        ((RTL8192EE_SEG_NUM << 13) & 0x6000) | 0x0000);
 925 #endif
 926
 927         rtl_write_dword(rtlpriv, REG_TSFTIMER_HCI, 0XFFFFFFFF);
 928
 929         _rtl92ee_gen_refresh_led_state(hw);
 930         return true;
 931 }
 932
 933 static void _rtl92ee_hw_configure(struct ieee80211_hw *hw)
 934 {
 935         struct rtl_priv *rtlpriv = rtl_priv(hw);
 936         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 937         u32 reg_rrsr;
 938
 939         reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 940         /* Init value for RRSR. */
 941         rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
 942
 943         /* ARFB table 9 for 11ac 5G 2SS */
 944         rtl_write_dword(rtlpriv, REG_ARFR0, 0x00000010);
 945         rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0x3e0ff000);
 946
 947         /* ARFB table 10 for 11ac 5G 1SS */
 948         rtl_write_dword(rtlpriv, REG_ARFR1, 0x00000010);
 949         rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x000ff000);
 950
 951         /* Set SLOT time */
 952         rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
 953
 954         /* CF-End setting. */
 955         rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
 956
 957         /* Set retry limit */
 958         rtl_write_word(rtlpriv, REG_RETRY_LIMIT, 0x0707);
 959
 960         /* BAR settings */
 961         rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x0201ffff);
 962
 963         /* Set Data / Response auto rate fallack retry count */
 964         rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
 965         rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
 966         rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
 967         rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
 968
 969         /* Beacon related, for rate adaptive */
 970         rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
 971         rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
 972
 973         rtlpci->reg_bcn_ctrl_val = 0x1d;
 974         rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
 975
 976         /* Marked out by Bruce, 2010-09-09.
 977          * This register is configured for the 2nd Beacon (multiple BSSID).
 978          * We shall disable this register if we only support 1 BSSID.
 979          * vivi guess 92d also need this, also 92d now doesnot set this reg
 980          */
 981         rtl_write_byte(rtlpriv, REG_BCN_CTRL_1, 0);
 982
 983         /* TBTT prohibit hold time. Suggested by designer TimChen. */
 984         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); /* 8 ms */
 985
 986         rtl_write_byte(rtlpriv, REG_PIFS, 0);
 987         rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
 988
 989         rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
 990         rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x08ff);
 991
 992         /* For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/
 993         rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
 994
 995         /* ACKTO for IOT issue. */
 996         rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
 997
 998         /* Set Spec SIFS (used in NAV) */
 999         rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x100a);
1000         rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x100a);
1001
1002         /* Set SIFS for CCK */
1003         rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x100a);
1004
1005         /* Set SIFS for OFDM */
1006         rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x100a);
1007
1008         /* Note Data sheet don't define */
1009         rtl_write_byte(rtlpriv, 0x4C7, 0x80);
1010
1011         rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20);
1012
1013         rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, 0x1717);
1014
1015         /* Set Multicast Address. 2009.01.07. by tynli. */
1016         rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
1017         rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
1018 }
1019
1020 static void _rtl92ee_enable_aspm_back_door(struct ieee80211_hw *hw)
1021 {
1022         struct rtl_priv *rtlpriv = rtl_priv(hw);
1023         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1024         u32 tmp32 = 0, count = 0;
1025         u8 tmp8 = 0;
1026
1027         rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0x78);
1028         rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x2);
1029         tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1030         count = 0;
1031         while (tmp8 && count < 20) {
1032                 udelay(10);
1033                 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1034                 count++;
1035         }
1036
1037         if (0 == tmp8) {
1038                 tmp32 = rtl_read_dword(rtlpriv, REG_BACKDOOR_DBI_RDATA);
1039                 if ((tmp32 & 0xff00) != 0x2000) {
1040                         tmp32 &= 0xffff00ff;
1041                         rtl_write_dword(rtlpriv, REG_BACKDOOR_DBI_WDATA,
1042                                         tmp32 | BIT(13));
1043                         rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0xf078);
1044                         rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x1);
1045
1046                         tmp8 = rtl_read_byte(rtlpriv,
1047                                              REG_BACKDOOR_DBI_DATA + 2);
1048                         count = 0;
1049                         while (tmp8 && count < 20) {
1050                                 udelay(10);
1051                                 tmp8 = rtl_read_byte(rtlpriv,
1052                                                      REG_BACKDOOR_DBI_DATA + 2);
1053                                 count++;
1054                         }
1055                 }
1056         }
1057
1058         rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0x70c);
1059         rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x2);
1060         tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1061         count = 0;
1062         while (tmp8 && count < 20) {
1063                 udelay(10);
1064                 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1065                 count++;
1066         }
1067         if (0 == tmp8) {
1068                 tmp32 = rtl_read_dword(rtlpriv, REG_BACKDOOR_DBI_RDATA);
1069                 rtl_write_dword(rtlpriv, REG_BACKDOOR_DBI_WDATA,
1070                                 tmp32 | BIT(31));
1071                 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0xf70c);
1072                 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x1);
1073         }
1074
1075         tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1076         count = 0;
1077         while (tmp8 && count < 20) {
1078                 udelay(10);
1079                 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1080                 count++;
1081         }
1082
1083         rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0x718);
1084         rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x2);
1085         tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1086         count = 0;
1087         while (tmp8 && count < 20) {
1088                 udelay(10);
1089                 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1090                 count++;
1091         }
1092         if (ppsc->support_backdoor || (0 == tmp8)) {
1093                 tmp32 = rtl_read_dword(rtlpriv, REG_BACKDOOR_DBI_RDATA);
1094                 rtl_write_dword(rtlpriv, REG_BACKDOOR_DBI_WDATA,
1095                                 tmp32 | BIT(11) | BIT(12));
1096                 rtl_write_word(rtlpriv, REG_BACKDOOR_DBI_DATA, 0xf718);
1097                 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2, 0x1);
1098         }
1099         tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1100         count = 0;
1101         while (tmp8 && count < 20) {
1102                 udelay(10);
1103                 tmp8 = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 2);
1104                 count++;
1105         }
1106 }
1107
1108 void rtl92ee_enable_hw_security_config(struct ieee80211_hw *hw)
1109 {
1110         struct rtl_priv *rtlpriv = rtl_priv(hw);
1111         u8 sec_reg_value;
1112         u8 tmp;
1113
1114         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1115                  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1116                   rtlpriv->sec.pairwise_enc_algorithm,
1117                   rtlpriv->sec.group_enc_algorithm);
1118
1119         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1120                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1121                          "not open hw encryption\n");
1122                 return;
1123         }
1124
1125         sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1126
1127         if (rtlpriv->sec.use_defaultkey) {
1128                 sec_reg_value |= SCR_TXUSEDK;
1129                 sec_reg_value |= SCR_RXUSEDK;
1130         }
1131
1132         sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1133
1134         tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1135         rtl_write_byte(rtlpriv, REG_CR + 1, tmp | BIT(1));
1136
1137         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1138                  "The SECR-value %x\n", sec_reg_value);
1139
1140         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1141 }
1142
1143 static bool _rtl8192ee_check_pcie_dma_hang(struct rtl_priv *rtlpriv)
1144 {
1145         u8 tmp;
1146
1147         /* write reg 0x350 Bit[26]=1. Enable debug port. */
1148         tmp = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 3);
1149         if (!(tmp & BIT(2))) {
1150                 rtl_write_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 3,
1151                                tmp | BIT(2));
1152                 mdelay(100); /* Suggested by DD Justin_tsai. */
1153         }
1154
1155         /* read reg 0x350 Bit[25] if 1 : RX hang
1156          * read reg 0x350 Bit[24] if 1 : TX hang
1157          */
1158         tmp = rtl_read_byte(rtlpriv, REG_BACKDOOR_DBI_DATA + 3);
1159         if ((tmp & BIT(0)) || (tmp & BIT(1))) {
1160                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1161                          "CheckPcieDMAHang8192EE(): true!!\n");
1162                 return true;
1163         }
1164         return false;
1165 }
1166
1167 static void _rtl8192ee_reset_pcie_interface_dma(struct rtl_priv *rtlpriv,
1168                                                 bool mac_power_on)
1169 {
1170         u8 tmp;
1171         bool release_mac_rx_pause;
1172         u8 backup_pcie_dma_pause;
1173
1174         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1175                  "ResetPcieInterfaceDMA8192EE()\n");
1176
1177         /* Revise Note: Follow the document "PCIe RX DMA Hang Reset Flow_v03"
1178          * released by SD1 Alan.
1179          */
1180
1181         /* 1. disable register write lock
1182          *      write 0x1C bit[1:0] = 2'h0
1183          *      write 0xCC bit[2] = 1'b1
1184          */
1185         tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL);
1186         tmp &= ~(BIT(1) | BIT(0));
1187         rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp);
1188         tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1189         tmp |= BIT(2);
1190         rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1191
1192         /* 2. Check and pause TRX DMA
1193          *      write 0x284 bit[18] = 1'b1
1194          *      write 0x301 = 0xFF
1195          */
1196         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1197         if (tmp & BIT(2)) {
1198                 /* Already pause before the function for another reason. */
1199                 release_mac_rx_pause = false;
1200         } else {
1201                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1202                 release_mac_rx_pause = true;
1203         }
1204
1205         backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 1);
1206         if (backup_pcie_dma_pause != 0xFF)
1207                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF);
1208
1209         if (mac_power_on) {
1210                 /* 3. reset TRX function
1211                  *      write 0x100 = 0x00
1212                  */
1213                 rtl_write_byte(rtlpriv, REG_CR, 0);
1214         }
1215
1216         /* 4. Reset PCIe DMA
1217          *      write 0x003 bit[0] = 0
1218          */
1219         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1220         tmp &= ~(BIT(0));
1221         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1222
1223         /* 5. Enable PCIe DMA
1224          *      write 0x003 bit[0] = 1
1225          */
1226         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1227         tmp |= BIT(0);
1228         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1229
1230         if (mac_power_on) {
1231                 /* 6. enable TRX function
1232                  *      write 0x100 = 0xFF
1233                  */
1234                 rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1235
1236                 /* We should init LLT & RQPN and
1237                  * prepare Tx/Rx descrptor address later
1238                  * because MAC function is reset.
1239                  */
1240         }
1241
1242         /* 7. Restore PCIe autoload down bit
1243          *      write 0xF8 bit[17] = 1'b1
1244          */
1245         tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2);
1246         tmp |= BIT(1);
1247         rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2, tmp);
1248
1249         /* In MAC power on state, BB and RF maybe in ON state,
1250          * if we release TRx DMA here
1251          * it will cause packets to be started to Tx/Rx,
1252          * so we release Tx/Rx DMA later.
1253          */
1254         if (!mac_power_on) {
1255                 /* 8. release TRX DMA
1256                  *      write 0x284 bit[18] = 1'b0
1257                  *      write 0x301 = 0x00
1258                  */
1259                 if (release_mac_rx_pause) {
1260                         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1261                         rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL,
1262                                        (tmp & (~BIT(2))));
1263                 }
1264                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1,
1265                                backup_pcie_dma_pause);
1266         }
1267
1268         /* 9. lock system register
1269          *      write 0xCC bit[2] = 1'b0
1270          */
1271         tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1272         tmp &= ~(BIT(2));
1273         rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1274 }
1275
1276 int rtl92ee_hw_init(struct ieee80211_hw *hw)
1277 {
1278         struct rtl_priv *rtlpriv = rtl_priv(hw);
1279         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1280         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1281         struct rtl_phy *rtlphy = &rtlpriv->phy;
1282         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1283         bool rtstatus = true;
1284         int err = 0;
1285         u8 tmp_u1b, u1byte;
1286         u32 tmp_u4b;
1287
1288         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, " Rtl8192EE hw init\n");
1289         rtlpriv->rtlhal.being_init_adapter = true;
1290         rtlpriv->intf_ops->disable_aspm(hw);
1291
1292         tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CLKR+1);
1293         u1byte = rtl_read_byte(rtlpriv, REG_CR);
1294         if ((tmp_u1b & BIT(3)) && (u1byte != 0 && u1byte != 0xEA)) {
1295                 rtlhal->mac_func_enable = true;
1296         } else {
1297                 rtlhal->mac_func_enable = false;
1298                 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_92E;
1299         }
1300
1301         if (_rtl8192ee_check_pcie_dma_hang(rtlpriv)) {
1302                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "92ee dma hang!\n");
1303                 _rtl8192ee_reset_pcie_interface_dma(rtlpriv,
1304                                                     rtlhal->mac_func_enable);
1305                 rtlhal->mac_func_enable = false;
1306         }
1307
1308         rtstatus = _rtl92ee_init_mac(hw);
1309
1310         rtl_write_byte(rtlpriv, 0x577, 0x03);
1311
1312         /*for Crystal 40 Mhz setting */
1313         rtl_write_byte(rtlpriv, REG_AFE_CTRL4, 0x2A);
1314         rtl_write_byte(rtlpriv, REG_AFE_CTRL4 + 1, 0x00);
1315         rtl_write_byte(rtlpriv, REG_AFE_CTRL2, 0x83);
1316
1317         /*Forced the antenna b to wifi */
1318         if (rtlpriv->btcoexist.btc_info.btcoexist == 1) {
1319                 rtl_write_byte(rtlpriv, 0x64, 0);
1320                 rtl_write_byte(rtlpriv, 0x65, 1);
1321         }
1322         if (!rtstatus) {
1323                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
1324                 err = 1;
1325                 return err;
1326         }
1327         rtlhal->rx_tag = 0;
1328         rtl_write_word(rtlpriv, REG_PCIE_CTRL_REG, 0x8000);
1329         err = rtl92ee_download_fw(hw, false);
1330         if (err) {
1331                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1332                          "Failed to download FW. Init HW without FW now..\n");
1333                 err = 1;
1334                 rtlhal->fw_ready = false;
1335                 return err;
1336         }
1337         rtlhal->fw_ready = true;
1338         /*fw related variable initialize */
1339         ppsc->fw_current_inpsmode = false;
1340         rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_92E;
1341         rtlhal->fw_clk_change_in_progress = false;
1342         rtlhal->allow_sw_to_change_hwclc = false;
1343         rtlhal->last_hmeboxnum = 0;
1344
1345         rtl92ee_phy_mac_config(hw);
1346
1347         rtl92ee_phy_bb_config(hw);
1348
1349         rtl92ee_phy_rf_config(hw);
1350
1351         rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, RF90_PATH_A,
1352                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1353         rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, RF90_PATH_B,
1354                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1355         rtlphy->backup_rf_0x1a = (u32)rtl_get_rfreg(hw, RF90_PATH_A, RF_RX_G1,
1356                                                     RFREG_OFFSET_MASK);
1357         rtlphy->rfreg_chnlval[0] = (rtlphy->rfreg_chnlval[0] & 0xfffff3ff) |
1358                                    BIT(10) | BIT(11);
1359
1360         rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
1361                       rtlphy->rfreg_chnlval[0]);
1362         rtl_set_rfreg(hw, RF90_PATH_B, RF_CHNLBW, RFREG_OFFSET_MASK,
1363                       rtlphy->rfreg_chnlval[0]);
1364
1365         /*---- Set CCK and OFDM Block "ON"----*/
1366         rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1367         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1368
1369         /* Must set this,
1370          * otherwise the rx sensitivity will be very pool. Maddest
1371          */
1372         rtl_set_rfreg(hw, RF90_PATH_A, 0xB1, RFREG_OFFSET_MASK, 0x54418);
1373
1374         /*Set Hardware(MAC default setting.)*/
1375         _rtl92ee_hw_configure(hw);
1376
1377         rtlhal->mac_func_enable = true;
1378
1379         rtl_cam_reset_all_entry(hw);
1380         rtl92ee_enable_hw_security_config(hw);
1381
1382         ppsc->rfpwr_state = ERFON;
1383
1384         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1385         _rtl92ee_enable_aspm_back_door(hw);
1386         rtlpriv->intf_ops->enable_aspm(hw);
1387
1388         rtl92ee_bt_hw_init(hw);
1389
1390         rtlpriv->rtlhal.being_init_adapter = false;
1391
1392         if (ppsc->rfpwr_state == ERFON) {
1393                 if (rtlphy->iqk_initialized) {
1394                         rtl92ee_phy_iq_calibrate(hw, true);
1395                 } else {
1396                         rtl92ee_phy_iq_calibrate(hw, false);
1397                         rtlphy->iqk_initialized = true;
1398                 }
1399         }
1400
1401         rtlphy->rfpath_rx_enable[0] = true;
1402         if (rtlphy->rf_type == RF_2T2R)
1403                 rtlphy->rfpath_rx_enable[1] = true;
1404
1405         efuse_one_byte_read(hw, 0x1FA, &tmp_u1b);
1406         if (!(tmp_u1b & BIT(0))) {
1407                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
1408                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path A\n");
1409         }
1410
1411         if ((!(tmp_u1b & BIT(1))) && (rtlphy->rf_type == RF_2T2R)) {
1412                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05);
1413                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path B\n");
1414         }
1415
1416         rtl_write_byte(rtlpriv, REG_NAV_UPPER, ((30000 + 127) / 128));
1417
1418         /*Fixed LDPC rx hang issue. */
1419         tmp_u4b = rtl_read_dword(rtlpriv, REG_SYS_SWR_CTRL1);
1420         rtl_write_byte(rtlpriv, REG_SYS_SWR_CTRL2, 0x75);
1421         tmp_u4b =  (tmp_u4b & 0xfff00fff) | (0x7E << 12);
1422         rtl_write_dword(rtlpriv, REG_SYS_SWR_CTRL1, tmp_u4b);
1423
1424         rtl92ee_dm_init(hw);
1425
1426         rtl_write_dword(rtlpriv, 0x4fc, 0);
1427
1428         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1429                  "end of Rtl8192EE hw init %x\n", err);
1430         return 0;
1431 }
1432
1433 static enum version_8192e _rtl92ee_read_chip_version(struct ieee80211_hw *hw)
1434 {
1435         struct rtl_priv *rtlpriv = rtl_priv(hw);
1436         struct rtl_phy *rtlphy = &rtlpriv->phy;
1437         enum version_8192e version = VERSION_UNKNOWN;
1438         u32 value32;
1439
1440         rtlphy->rf_type = RF_2T2R;
1441
1442         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG1);
1443         if (value32 & TRP_VAUX_EN)
1444                 version = (enum version_8192e)VERSION_TEST_CHIP_2T2R_8192E;
1445         else
1446                 version = (enum version_8192e)VERSION_NORMAL_CHIP_2T2R_8192E;
1447
1448         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1449                  "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1450                   "RF_2T2R" : "RF_1T1R");
1451
1452         return version;
1453 }
1454
1455 static int _rtl92ee_set_media_status(struct ieee80211_hw *hw,
1456                                      enum nl80211_iftype type)
1457 {
1458         struct rtl_priv *rtlpriv = rtl_priv(hw);
1459         u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc;
1460         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1461         u8 mode = MSR_NOLINK;
1462
1463         switch (type) {
1464         case NL80211_IFTYPE_UNSPECIFIED:
1465                 mode = MSR_NOLINK;
1466                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1467                          "Set Network type to NO LINK!\n");
1468                 break;
1469         case NL80211_IFTYPE_ADHOC:
1470         case NL80211_IFTYPE_MESH_POINT:
1471                 mode = MSR_ADHOC;
1472                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1473                          "Set Network type to Ad Hoc!\n");
1474                 break;
1475         case NL80211_IFTYPE_STATION:
1476                 mode = MSR_INFRA;
1477                 ledaction = LED_CTL_LINK;
1478                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1479                          "Set Network type to STA!\n");
1480                 break;
1481         case NL80211_IFTYPE_AP:
1482                 mode = MSR_AP;
1483                 ledaction = LED_CTL_LINK;
1484                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1485                          "Set Network type to AP!\n");
1486                 break;
1487         default:
1488                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1489                          "Network type %d not support!\n", type);
1490                 return 1;
1491         }
1492
1493         /* MSR_INFRA == Link in infrastructure network;
1494          * MSR_ADHOC == Link in ad hoc network;
1495          * Therefore, check link state is necessary.
1496          *
1497          * MSR_AP == AP mode; link state is not cared here.
1498          */
1499         if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1500                 mode = MSR_NOLINK;
1501                 ledaction = LED_CTL_NO_LINK;
1502         }
1503
1504         if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1505                 _rtl92ee_stop_tx_beacon(hw);
1506                 _rtl92ee_enable_bcn_sub_func(hw);
1507         } else if (mode == MSR_ADHOC || mode == MSR_AP) {
1508                 _rtl92ee_resume_tx_beacon(hw);
1509                 _rtl92ee_disable_bcn_sub_func(hw);
1510         } else {
1511                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1512                          "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1513                          mode);
1514         }
1515
1516         rtl_write_byte(rtlpriv, MSR, bt_msr | mode);
1517         rtlpriv->cfg->ops->led_control(hw, ledaction);
1518         if (mode == MSR_AP)
1519                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1520         else
1521                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1522         return 0;
1523 }
1524
1525 void rtl92ee_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1526 {
1527         struct rtl_priv *rtlpriv = rtl_priv(hw);
1528         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1529         u32 reg_rcr = rtlpci->receive_config;
1530
1531         if (rtlpriv->psc.rfpwr_state != ERFON)
1532                 return;
1533
1534         if (check_bssid) {
1535                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1536                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1537                                               (u8 *)(&reg_rcr));
1538                 _rtl92ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
1539         } else {
1540                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1541                 _rtl92ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
1542                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1543                                               (u8 *)(&reg_rcr));
1544         }
1545 }
1546
1547 int rtl92ee_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1548 {
1549         struct rtl_priv *rtlpriv = rtl_priv(hw);
1550
1551         if (_rtl92ee_set_media_status(hw, type))
1552                 return -EOPNOTSUPP;
1553
1554         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1555                 if (type != NL80211_IFTYPE_AP &&
1556                     type != NL80211_IFTYPE_MESH_POINT)
1557                         rtl92ee_set_check_bssid(hw, true);
1558         } else {
1559                 rtl92ee_set_check_bssid(hw, false);
1560         }
1561
1562         return 0;
1563 }
1564
1565 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1566 void rtl92ee_set_qos(struct ieee80211_hw *hw, int aci)
1567 {
1568         struct rtl_priv *rtlpriv = rtl_priv(hw);
1569
1570         rtl92ee_dm_init_edca_turbo(hw);
1571         switch (aci) {
1572         case AC1_BK:
1573                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1574                 break;
1575         case AC0_BE:
1576                 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
1577                 break;
1578         case AC2_VI:
1579                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1580                 break;
1581         case AC3_VO:
1582                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1583                 break;
1584         default:
1585                 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1586                 break;
1587         }
1588 }
1589
1590 void rtl92ee_enable_interrupt(struct ieee80211_hw *hw)
1591 {
1592         struct rtl_priv *rtlpriv = rtl_priv(hw);
1593         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1594
1595         rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1596         rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1597         rtlpci->irq_enabled = true;
1598 }
1599
1600 void rtl92ee_disable_interrupt(struct ieee80211_hw *hw)
1601 {
1602         struct rtl_priv *rtlpriv = rtl_priv(hw);
1603         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1604
1605         rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
1606         rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
1607         rtlpci->irq_enabled = false;
1608         /*synchronize_irq(rtlpci->pdev->irq);*/
1609 }
1610
1611 static void _rtl92ee_poweroff_adapter(struct ieee80211_hw *hw)
1612 {
1613         struct rtl_priv *rtlpriv = rtl_priv(hw);
1614         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1615         u8 u1b_tmp;
1616
1617         rtlhal->mac_func_enable = false;
1618
1619         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "POWER OFF adapter\n");
1620
1621         /* Run LPS WL RFOFF flow */
1622         rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1623                                  PWR_INTF_PCI_MSK, RTL8192E_NIC_LPS_ENTER_FLOW);
1624         /* turn off RF */
1625         rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1626
1627         /* ==== Reset digital sequence   ======  */
1628         if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready)
1629                 rtl92ee_firmware_selfreset(hw);
1630
1631         /* Reset MCU  */
1632         u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1633         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2))));
1634
1635         /* reset MCU ready status */
1636         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1637
1638         /* HW card disable configuration. */
1639         rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1640                                  PWR_INTF_PCI_MSK, RTL8192E_NIC_DISABLE_FLOW);
1641
1642         /* Reset MCU IO Wrapper */
1643         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1644         rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1645         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1646         rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp | BIT(0)));
1647
1648         /* lock ISO/CLK/Power control register */
1649         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1650 }
1651
1652 void rtl92ee_card_disable(struct ieee80211_hw *hw)
1653 {
1654         struct rtl_priv *rtlpriv = rtl_priv(hw);
1655         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1656         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1657         enum nl80211_iftype opmode;
1658
1659         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "RTL8192ee card disable\n");
1660
1661         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1662
1663         mac->link_state = MAC80211_NOLINK;
1664         opmode = NL80211_IFTYPE_UNSPECIFIED;
1665
1666         _rtl92ee_set_media_status(hw, opmode);
1667
1668         if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1669             ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1670                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1671
1672         _rtl92ee_poweroff_adapter(hw);
1673
1674         /* after power off we should do iqk again */
1675         rtlpriv->phy.iqk_initialized = false;
1676 }
1677
1678 void rtl92ee_interrupt_recognized(struct ieee80211_hw *hw,
1679                                   u32 *p_inta, u32 *p_intb)
1680 {
1681         struct rtl_priv *rtlpriv = rtl_priv(hw);
1682         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1683
1684         *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1685         rtl_write_dword(rtlpriv, ISR, *p_inta);
1686
1687         *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1688         rtl_write_dword(rtlpriv, REG_HISRE, *p_intb);
1689 }
1690
1691 void rtl92ee_set_beacon_related_registers(struct ieee80211_hw *hw)
1692 {
1693         struct rtl_priv *rtlpriv = rtl_priv(hw);
1694         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1695         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1696         u16 bcn_interval, atim_window;
1697
1698         bcn_interval = mac->beacon_interval;
1699         atim_window = 2;        /*FIX MERGE */
1700         rtl92ee_disable_interrupt(hw);
1701         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1702         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1703         rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1704         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1705         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1706         rtl_write_byte(rtlpriv, 0x606, 0x30);
1707         rtlpci->reg_bcn_ctrl_val |= BIT(3);
1708         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
1709 }
1710
1711 void rtl92ee_set_beacon_interval(struct ieee80211_hw *hw)
1712 {
1713         struct rtl_priv *rtlpriv = rtl_priv(hw);
1714         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1715         u16 bcn_interval = mac->beacon_interval;
1716
1717         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1718                  "beacon_interval:%d\n", bcn_interval);
1719         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1720 }
1721
1722 void rtl92ee_update_interrupt_mask(struct ieee80211_hw *hw,
1723                                    u32 add_msr, u32 rm_msr)
1724 {
1725         struct rtl_priv *rtlpriv = rtl_priv(hw);
1726         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1727
1728         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1729                  "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
1730
1731         if (add_msr)
1732                 rtlpci->irq_mask[0] |= add_msr;
1733         if (rm_msr)
1734                 rtlpci->irq_mask[0] &= (~rm_msr);
1735         rtl92ee_disable_interrupt(hw);
1736         rtl92ee_enable_interrupt(hw);
1737 }
1738
1739 static u8 _rtl92ee_get_chnl_group(u8 chnl)
1740 {
1741         u8 group = 0;
1742
1743         if (chnl <= 14) {
1744                 if (1 <= chnl && chnl <= 2)
1745                         group = 0;
1746                 else if (3 <= chnl && chnl <= 5)
1747                         group = 1;
1748                 else if (6 <= chnl && chnl <= 8)
1749                         group = 2;
1750                 else if (9 <= chnl && chnl <= 11)
1751                         group = 3;
1752                 else if (12 <= chnl && chnl <= 14)
1753                         group = 4;
1754         } else {
1755                 if (36 <= chnl && chnl <= 42)
1756                         group = 0;
1757                 else if (44 <= chnl && chnl <= 48)
1758                         group = 1;
1759                 else if (50 <= chnl && chnl <= 58)
1760                         group = 2;
1761                 else if (60 <= chnl && chnl <= 64)
1762                         group = 3;
1763                 else if (100 <= chnl && chnl <= 106)
1764                         group = 4;
1765                 else if (108 <= chnl && chnl <= 114)
1766                         group = 5;
1767                 else if (116 <= chnl && chnl <= 122)
1768                         group = 6;
1769                 else if (124 <= chnl && chnl <= 130)
1770                         group = 7;
1771                 else if (132 <= chnl && chnl <= 138)
1772                         group = 8;
1773                 else if (140 <= chnl && chnl <= 144)
1774                         group = 9;
1775                 else if (149 <= chnl && chnl <= 155)
1776                         group = 10;
1777                 else if (157 <= chnl && chnl <= 161)
1778                         group = 11;
1779                 else if (165 <= chnl && chnl <= 171)
1780                         group = 12;
1781                 else if (173 <= chnl && chnl <= 177)
1782                         group = 13;
1783         }
1784         return group;
1785 }
1786
1787 static void _rtl8192ee_read_power_value_fromprom(struct ieee80211_hw *hw,
1788                                                  struct txpower_info_2g *pwr2g,
1789                                                  struct txpower_info_5g *pwr5g,
1790                                                  bool autoload_fail, u8 *hwinfo)
1791 {
1792         struct rtl_priv *rtlpriv = rtl_priv(hw);
1793         u32 rf, addr = EEPROM_TX_PWR_INX, group, i = 0;
1794
1795         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1796                  "hal_ReadPowerValueFromPROM92E(): PROMContent[0x%x]=0x%x\n",
1797                  (addr + 1), hwinfo[addr + 1]);
1798         if (0xFF == hwinfo[addr+1])  /*YJ,add,120316*/
1799                 autoload_fail = true;
1800
1801         if (autoload_fail) {
1802                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1803                          "auto load fail : Use Default value!\n");
1804                 for (rf = 0 ; rf < MAX_RF_PATH ; rf++) {
1805                         /* 2.4G default value */
1806                         for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1807                                 pwr2g->index_cck_base[rf][group] = 0x2D;
1808                                 pwr2g->index_bw40_base[rf][group] = 0x2D;
1809                         }
1810                         for (i = 0; i < MAX_TX_COUNT; i++) {
1811                                 if (i == 0) {
1812                                         pwr2g->bw20_diff[rf][0] = 0x02;
1813                                         pwr2g->ofdm_diff[rf][0] = 0x04;
1814                                 } else {
1815                                         pwr2g->bw20_diff[rf][i] = 0xFE;
1816                                         pwr2g->bw40_diff[rf][i] = 0xFE;
1817                                         pwr2g->cck_diff[rf][i] = 0xFE;
1818                                         pwr2g->ofdm_diff[rf][i] = 0xFE;
1819                                 }
1820                         }
1821
1822                         /*5G default value*/
1823                         for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++)
1824                                 pwr5g->index_bw40_base[rf][group] = 0x2A;
1825
1826                         for (i = 0; i < MAX_TX_COUNT; i++) {
1827                                 if (i == 0) {
1828                                         pwr5g->ofdm_diff[rf][0] = 0x04;
1829                                         pwr5g->bw20_diff[rf][0] = 0x00;
1830                                         pwr5g->bw80_diff[rf][0] = 0xFE;
1831                                         pwr5g->bw160_diff[rf][0] = 0xFE;
1832                                 } else {
1833                                         pwr5g->ofdm_diff[rf][0] = 0xFE;
1834                                         pwr5g->bw20_diff[rf][0] = 0xFE;
1835                                         pwr5g->bw40_diff[rf][0] = 0xFE;
1836                                         pwr5g->bw80_diff[rf][0] = 0xFE;
1837                                         pwr5g->bw160_diff[rf][0] = 0xFE;
1838                                 }
1839                         }
1840                 }
1841                 return;
1842         }
1843
1844         rtl_priv(hw)->efuse.txpwr_fromeprom = true;
1845
1846         for (rf = 0 ; rf < MAX_RF_PATH ; rf++) {
1847                 /*2.4G default value*/
1848                 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1849                         pwr2g->index_cck_base[rf][group] = hwinfo[addr++];
1850                         if (pwr2g->index_cck_base[rf][group] == 0xFF)
1851                                 pwr2g->index_cck_base[rf][group] = 0x2D;
1852                 }
1853                 for (group = 0 ; group < MAX_CHNL_GROUP_24G - 1; group++) {
1854                         pwr2g->index_bw40_base[rf][group] = hwinfo[addr++];
1855                         if (pwr2g->index_bw40_base[rf][group] == 0xFF)
1856                                 pwr2g->index_bw40_base[rf][group] = 0x2D;
1857                 }
1858                 for (i = 0; i < MAX_TX_COUNT; i++) {
1859                         if (i == 0) {
1860                                 pwr2g->bw40_diff[rf][i] = 0;
1861                                 if (hwinfo[addr] == 0xFF) {
1862                                         pwr2g->bw20_diff[rf][i] = 0x02;
1863                                 } else {
1864                                         pwr2g->bw20_diff[rf][i] = (hwinfo[addr]
1865                                                                    & 0xf0) >> 4;
1866                                         if (pwr2g->bw20_diff[rf][i] & BIT(3))
1867                                                 pwr2g->bw20_diff[rf][i] |= 0xF0;
1868                                 }
1869
1870                                 if (hwinfo[addr] == 0xFF) {
1871                                         pwr2g->ofdm_diff[rf][i] = 0x04;
1872                                 } else {
1873                                         pwr2g->ofdm_diff[rf][i] = (hwinfo[addr]
1874                                                                    & 0x0f);
1875                                         if (pwr2g->ofdm_diff[rf][i] & BIT(3))
1876                                                 pwr2g->ofdm_diff[rf][i] |= 0xF0;
1877                                 }
1878                                 pwr2g->cck_diff[rf][i] = 0;
1879                                 addr++;
1880                         } else {
1881                                 if (hwinfo[addr] == 0xFF) {
1882                                         pwr2g->bw40_diff[rf][i] = 0xFE;
1883                                 } else {
1884                                         pwr2g->bw40_diff[rf][i] = (hwinfo[addr]
1885                                                                    & 0xf0) >> 4;
1886                                         if (pwr2g->bw40_diff[rf][i] & BIT(3))
1887                                                 pwr2g->bw40_diff[rf][i] |= 0xF0;
1888                                 }
1889
1890                                 if (hwinfo[addr] == 0xFF) {
1891                                         pwr2g->bw20_diff[rf][i] = 0xFE;
1892                                 } else {
1893                                         pwr2g->bw20_diff[rf][i] = (hwinfo[addr]
1894                                                                    & 0x0f);
1895                                         if (pwr2g->bw20_diff[rf][i] & BIT(3))
1896                                                 pwr2g->bw20_diff[rf][i] |= 0xF0;
1897                                 }
1898                                 addr++;
1899
1900                                 if (hwinfo[addr] == 0xFF) {
1901                                         pwr2g->ofdm_diff[rf][i] = 0xFE;
1902                                 } else {
1903                                         pwr2g->ofdm_diff[rf][i] = (hwinfo[addr]
1904                                                                    & 0xf0) >> 4;
1905                                         if (pwr2g->ofdm_diff[rf][i] & BIT(3))
1906                                                 pwr2g->ofdm_diff[rf][i] |= 0xF0;
1907                                 }
1908
1909                                 if (hwinfo[addr] == 0xFF) {
1910                                         pwr2g->cck_diff[rf][i] = 0xFE;
1911                                 } else {
1912                                         pwr2g->cck_diff[rf][i] = (hwinfo[addr]
1913                                                                   & 0x0f);
1914                                         if (pwr2g->cck_diff[rf][i] & BIT(3))
1915                                                 pwr2g->cck_diff[rf][i] |= 0xF0;
1916                                 }
1917                                 addr++;
1918                         }
1919                 }
1920
1921                 /*5G default value*/
1922                 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) {
1923                         pwr5g->index_bw40_base[rf][group] = hwinfo[addr++];
1924                         if (pwr5g->index_bw40_base[rf][group] == 0xFF)
1925                                 pwr5g->index_bw40_base[rf][group] = 0xFE;
1926                 }
1927
1928                 for (i = 0; i < MAX_TX_COUNT; i++) {
1929                         if (i == 0) {
1930                                 pwr5g->bw40_diff[rf][i] = 0;
1931
1932                                 if (hwinfo[addr] == 0xFF) {
1933                                         pwr5g->bw20_diff[rf][i] = 0;
1934                                 } else {
1935                                         pwr5g->bw20_diff[rf][0] = (hwinfo[addr]
1936                                                                    & 0xf0) >> 4;
1937                                         if (pwr5g->bw20_diff[rf][i] & BIT(3))
1938                                                 pwr5g->bw20_diff[rf][i] |= 0xF0;
1939                                 }
1940
1941                                 if (hwinfo[addr] == 0xFF) {
1942                                         pwr5g->ofdm_diff[rf][i] = 0x04;
1943                                 } else {
1944                                         pwr5g->ofdm_diff[rf][0] = (hwinfo[addr]
1945                                                                    & 0x0f);
1946                                         if (pwr5g->ofdm_diff[rf][i] & BIT(3))
1947                                                 pwr5g->ofdm_diff[rf][i] |= 0xF0;
1948                                 }
1949                                 addr++;
1950                         } else {
1951                                 if (hwinfo[addr] == 0xFF) {
1952                                         pwr5g->bw40_diff[rf][i] = 0xFE;
1953                                 } else {
1954                                         pwr5g->bw40_diff[rf][i] = (hwinfo[addr]
1955                                                                   & 0xf0) >> 4;
1956                                         if (pwr5g->bw40_diff[rf][i] & BIT(3))
1957                                                 pwr5g->bw40_diff[rf][i] |= 0xF0;
1958                                 }
1959
1960                                 if (hwinfo[addr] == 0xFF) {
1961                                         pwr5g->bw20_diff[rf][i] = 0xFE;
1962                                 } else {
1963                                         pwr5g->bw20_diff[rf][i] = (hwinfo[addr]
1964                                                                    & 0x0f);
1965                                         if (pwr5g->bw20_diff[rf][i] & BIT(3))
1966                                                 pwr5g->bw20_diff[rf][i] |= 0xF0;
1967                                 }
1968                                 addr++;
1969                         }
1970                 }
1971
1972                 if (hwinfo[addr] == 0xFF) {
1973                         pwr5g->ofdm_diff[rf][1] = 0xFE;
1974                         pwr5g->ofdm_diff[rf][2] = 0xFE;
1975                 } else {
1976                         pwr5g->ofdm_diff[rf][1] = (hwinfo[addr] & 0xf0) >> 4;
1977                         pwr5g->ofdm_diff[rf][2] = (hwinfo[addr] & 0x0f);
1978                 }
1979                 addr++;
1980
1981                 if (hwinfo[addr] == 0xFF)
1982                         pwr5g->ofdm_diff[rf][3] = 0xFE;
1983                 else
1984                         pwr5g->ofdm_diff[rf][3] = (hwinfo[addr] & 0x0f);
1985                 addr++;
1986
1987                 for (i = 1; i < MAX_TX_COUNT; i++) {
1988                         if (pwr5g->ofdm_diff[rf][i] == 0xFF)
1989                                 pwr5g->ofdm_diff[rf][i] = 0xFE;
1990                         else if (pwr5g->ofdm_diff[rf][i] & BIT(3))
1991                                 pwr5g->ofdm_diff[rf][i] |= 0xF0;
1992                 }
1993
1994                 for (i = 0; i < MAX_TX_COUNT; i++) {
1995                         if (hwinfo[addr] == 0xFF) {
1996                                 pwr5g->bw80_diff[rf][i] = 0xFE;
1997                         } else {
1998                                 pwr5g->bw80_diff[rf][i] = (hwinfo[addr] & 0xf0)
1999                                                           >> 4;
2000                                 if (pwr5g->bw80_diff[rf][i] & BIT(3))
2001                                         pwr5g->bw80_diff[rf][i] |= 0xF0;
2002                         }
2003
2004                         if (hwinfo[addr] == 0xFF) {
2005                                 pwr5g->bw160_diff[rf][i] = 0xFE;
2006                         } else {
2007                                 pwr5g->bw160_diff[rf][i] =
2008                                   (hwinfo[addr] & 0x0f);
2009                                 if (pwr5g->bw160_diff[rf][i] & BIT(3))
2010                                         pwr5g->bw160_diff[rf][i] |= 0xF0;
2011                         }
2012                         addr++;
2013                 }
2014         }
2015 }
2016
2017 static void _rtl92ee_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
2018                                                  bool autoload_fail, u8 *hwinfo)
2019 {
2020         struct rtl_priv *rtlpriv = rtl_priv(hw);
2021         struct rtl_efuse *efu = rtl_efuse(rtl_priv(hw));
2022         struct txpower_info_2g pwr2g;
2023         struct txpower_info_5g pwr5g;
2024         u8 rf, idx;
2025         u8 i;
2026
2027         _rtl8192ee_read_power_value_fromprom(hw, &pwr2g, &pwr5g,
2028                                              autoload_fail, hwinfo);
2029
2030         for (rf = 0; rf < MAX_RF_PATH; rf++) {
2031                 for (i = 0; i < 14; i++) {
2032                         idx = _rtl92ee_get_chnl_group(i + 1);
2033
2034                         if (i == CHANNEL_MAX_NUMBER_2G - 1) {
2035                                 efu->txpwrlevel_cck[rf][i] =
2036                                                 pwr2g.index_cck_base[rf][5];
2037                                 efu->txpwrlevel_ht40_1s[rf][i] =
2038                                                 pwr2g.index_bw40_base[rf][idx];
2039                         } else {
2040                                 efu->txpwrlevel_cck[rf][i] =
2041                                                 pwr2g.index_cck_base[rf][idx];
2042                                 efu->txpwrlevel_ht40_1s[rf][i] =
2043                                                 pwr2g.index_bw40_base[rf][idx];
2044                         }
2045                 }
2046                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
2047                         idx = _rtl92ee_get_chnl_group(channel5g[i]);
2048                         efu->txpwr_5g_bw40base[rf][i] =
2049                                         pwr5g.index_bw40_base[rf][idx];
2050                 }
2051                 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
2052                         u8 upper, lower;
2053
2054                         idx = _rtl92ee_get_chnl_group(channel5g_80m[i]);
2055                         upper = pwr5g.index_bw40_base[rf][idx];
2056                         lower = pwr5g.index_bw40_base[rf][idx + 1];
2057
2058                         efu->txpwr_5g_bw80base[rf][i] = (upper + lower) / 2;
2059                 }
2060                 for (i = 0; i < MAX_TX_COUNT; i++) {
2061                         efu->txpwr_cckdiff[rf][i] = pwr2g.cck_diff[rf][i];
2062                         efu->txpwr_legacyhtdiff[rf][i] = pwr2g.ofdm_diff[rf][i];
2063                         efu->txpwr_ht20diff[rf][i] = pwr2g.bw20_diff[rf][i];
2064                         efu->txpwr_ht40diff[rf][i] = pwr2g.bw40_diff[rf][i];
2065
2066                         efu->txpwr_5g_ofdmdiff[rf][i] = pwr5g.ofdm_diff[rf][i];
2067                         efu->txpwr_5g_bw20diff[rf][i] = pwr5g.bw20_diff[rf][i];
2068                         efu->txpwr_5g_bw40diff[rf][i] = pwr5g.bw40_diff[rf][i];
2069                         efu->txpwr_5g_bw80diff[rf][i] = pwr5g.bw80_diff[rf][i];
2070                 }
2071         }
2072
2073         if (!autoload_fail)
2074                 efu->eeprom_thermalmeter = hwinfo[EEPROM_THERMAL_METER_92E];
2075         else
2076                 efu->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
2077
2078         if (efu->eeprom_thermalmeter == 0xff || autoload_fail) {
2079                 efu->apk_thermalmeterignore = true;
2080                 efu->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
2081         }
2082
2083         efu->thermalmeter[0] = efu->eeprom_thermalmeter;
2084         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2085                 "thermalmeter = 0x%x\n", efu->eeprom_thermalmeter);
2086
2087         if (!autoload_fail) {
2088                 efu->eeprom_regulatory = hwinfo[EEPROM_RF_BOARD_OPTION_92E]
2089                                          & 0x07;
2090                 if (hwinfo[EEPROM_RF_BOARD_OPTION_92E] == 0xFF)
2091                         efu->eeprom_regulatory = 0;
2092         } else {
2093                 efu->eeprom_regulatory = 0;
2094         }
2095         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2096                 "eeprom_regulatory = 0x%x\n", efu->eeprom_regulatory);
2097 }
2098
2099 static void _rtl92ee_read_adapter_info(struct ieee80211_hw *hw)
2100 {
2101         struct rtl_priv *rtlpriv = rtl_priv(hw);
2102         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2103         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2104         int params[] = {RTL8192E_EEPROM_ID, EEPROM_VID, EEPROM_DID,
2105                         EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
2106                         EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
2107                         COUNTRY_CODE_WORLD_WIDE_13};
2108         u8 *hwinfo;
2109
2110         hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
2111         if (!hwinfo)
2112                 return;
2113
2114         if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
2115                 goto exit;
2116
2117         if (rtlefuse->eeprom_oemid == 0xFF)
2118                 rtlefuse->eeprom_oemid = 0;
2119
2120         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2121                  "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
2122         /* set channel plan from efuse */
2123         rtlefuse->channel_plan = rtlefuse->eeprom_channelplan;
2124         /*tx power*/
2125         _rtl92ee_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
2126                                              hwinfo);
2127
2128         rtl92ee_read_bt_coexist_info_from_hwpg(hw, rtlefuse->autoload_failflag,
2129                                                hwinfo);
2130
2131         /*board type*/
2132         rtlefuse->board_type = (((*(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION_92E])
2133                                 & 0xE0) >> 5);
2134         if ((*(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION_92E]) == 0xFF)
2135                 rtlefuse->board_type = 0;
2136
2137         rtlhal->board_type = rtlefuse->board_type;
2138         /*parse xtal*/
2139         rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_92E];
2140         if (hwinfo[EEPROM_XTAL_92E] == 0xFF)
2141                 rtlefuse->crystalcap = 0x20;
2142
2143         /*antenna diversity*/
2144         rtlefuse->antenna_div_type = NO_ANTDIV;
2145         rtlefuse->antenna_div_cfg = 0;
2146
2147         if (rtlhal->oem_id == RT_CID_DEFAULT) {
2148                 switch (rtlefuse->eeprom_oemid) {
2149                 case EEPROM_CID_DEFAULT:
2150                         if (rtlefuse->eeprom_did == 0x818B) {
2151                                 if ((rtlefuse->eeprom_svid == 0x10EC) &&
2152                                     (rtlefuse->eeprom_smid == 0x001B))
2153                                         rtlhal->oem_id = RT_CID_819X_LENOVO;
2154                         } else {
2155                                 rtlhal->oem_id = RT_CID_DEFAULT;
2156                         }
2157                         break;
2158                 default:
2159                         rtlhal->oem_id = RT_CID_DEFAULT;
2160                         break;
2161                 }
2162         }
2163 exit:
2164         kfree(hwinfo);
2165 }
2166
2167 static void _rtl92ee_hal_customized_behavior(struct ieee80211_hw *hw)
2168 {
2169         struct rtl_priv *rtlpriv = rtl_priv(hw);
2170         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2171         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2172
2173         pcipriv->ledctl.led_opendrain = true;
2174
2175         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2176                  "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
2177 }
2178
2179 void rtl92ee_read_eeprom_info(struct ieee80211_hw *hw)
2180 {
2181         struct rtl_priv *rtlpriv = rtl_priv(hw);
2182         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2183         struct rtl_phy *rtlphy = &rtlpriv->phy;
2184         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2185         u8 tmp_u1b;
2186
2187         rtlhal->version = _rtl92ee_read_chip_version(hw);
2188         if (get_rf_type(rtlphy) == RF_1T1R) {
2189                 rtlpriv->dm.rfpath_rxenable[0] = true;
2190         } else {
2191                 rtlpriv->dm.rfpath_rxenable[0] = true;
2192                 rtlpriv->dm.rfpath_rxenable[1] = true;
2193         }
2194         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
2195                  rtlhal->version);
2196         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
2197         if (tmp_u1b & BIT(4)) {
2198                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
2199                 rtlefuse->epromtype = EEPROM_93C46;
2200         } else {
2201                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
2202                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
2203         }
2204         if (tmp_u1b & BIT(5)) {
2205                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
2206                 rtlefuse->autoload_failflag = false;
2207                 _rtl92ee_read_adapter_info(hw);
2208         } else {
2209                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
2210         }
2211         _rtl92ee_hal_customized_behavior(hw);
2212
2213         rtlphy->rfpath_rx_enable[0] = true;
2214         if (rtlphy->rf_type == RF_2T2R)
2215                 rtlphy->rfpath_rx_enable[1] = true;
2216 }
2217
2218 static u8 _rtl92ee_mrate_idx_to_arfr_id(struct ieee80211_hw *hw, u8 rate_index)
2219 {
2220         u8 ret = 0;
2221
2222         switch (rate_index) {
2223         case RATR_INX_WIRELESS_NGB:
2224                 ret = 0;
2225                 break;
2226         case RATR_INX_WIRELESS_N:
2227         case RATR_INX_WIRELESS_NG:
2228                 ret = 4;
2229                 break;
2230         case RATR_INX_WIRELESS_NB:
2231                 ret = 2;
2232                 break;
2233         case RATR_INX_WIRELESS_GB:
2234                 ret = 6;
2235                 break;
2236         case RATR_INX_WIRELESS_G:
2237                 ret = 7;
2238                 break;
2239         case RATR_INX_WIRELESS_B:
2240                 ret = 8;
2241                 break;
2242         default:
2243                 ret = 0;
2244                 break;
2245         }
2246         return ret;
2247 }
2248
2249 static void rtl92ee_update_hal_rate_mask(struct ieee80211_hw *hw,
2250                                          struct ieee80211_sta *sta,
2251                                          u8 rssi_level)
2252 {
2253         struct rtl_priv *rtlpriv = rtl_priv(hw);
2254         struct rtl_phy *rtlphy = &rtlpriv->phy;
2255         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2256         struct rtl_sta_info *sta_entry = NULL;
2257         u32 ratr_bitmap;
2258         u8 ratr_index;
2259         u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
2260                              ? 1 : 0;
2261         u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2262                                 1 : 0;
2263         u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2264                                 1 : 0;
2265         enum wireless_mode wirelessmode = 0;
2266         bool b_shortgi = false;
2267         u8 rate_mask[7] = {0};
2268         u8 macid = 0;
2269         /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/
2270         sta_entry = (struct rtl_sta_info *)sta->drv_priv;
2271         wirelessmode = sta_entry->wireless_mode;
2272         if (mac->opmode == NL80211_IFTYPE_STATION ||
2273             mac->opmode == NL80211_IFTYPE_MESH_POINT)
2274                 curtxbw_40mhz = mac->bw_40;
2275         else if (mac->opmode == NL80211_IFTYPE_AP ||
2276                  mac->opmode == NL80211_IFTYPE_ADHOC)
2277                 macid = sta->aid + 1;
2278
2279         ratr_bitmap = sta->supp_rates[0];
2280         if (mac->opmode == NL80211_IFTYPE_ADHOC)
2281                 ratr_bitmap = 0xfff;
2282
2283         ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2284                         sta->ht_cap.mcs.rx_mask[0] << 12);
2285
2286         switch (wirelessmode) {
2287         case WIRELESS_MODE_B:
2288                 ratr_index = RATR_INX_WIRELESS_B;
2289                 if (ratr_bitmap & 0x0000000c)
2290                         ratr_bitmap &= 0x0000000d;
2291                 else
2292                         ratr_bitmap &= 0x0000000f;
2293                 break;
2294         case WIRELESS_MODE_G:
2295                 ratr_index = RATR_INX_WIRELESS_GB;
2296
2297                 if (rssi_level == 1)
2298                         ratr_bitmap &= 0x00000f00;
2299                 else if (rssi_level == 2)
2300                         ratr_bitmap &= 0x00000ff0;
2301                 else
2302                         ratr_bitmap &= 0x00000ff5;
2303                 break;
2304         case WIRELESS_MODE_N_24G:
2305                 if (curtxbw_40mhz)
2306                         ratr_index = RATR_INX_WIRELESS_NGB;
2307                 else
2308                         ratr_index = RATR_INX_WIRELESS_NB;
2309
2310                 if (rtlphy->rf_type == RF_1T1R) {
2311                         if (curtxbw_40mhz) {
2312                                 if (rssi_level == 1)
2313                                         ratr_bitmap &= 0x000f0000;
2314                                 else if (rssi_level == 2)
2315                                         ratr_bitmap &= 0x000ff000;
2316                                 else
2317                                         ratr_bitmap &= 0x000ff015;
2318                         } else {
2319                                 if (rssi_level == 1)
2320                                         ratr_bitmap &= 0x000f0000;
2321                                 else if (rssi_level == 2)
2322                                         ratr_bitmap &= 0x000ff000;
2323                                 else
2324                                         ratr_bitmap &= 0x000ff005;
2325                         }
2326                 } else {
2327                         if (curtxbw_40mhz) {
2328                                 if (rssi_level == 1)
2329                                         ratr_bitmap &= 0x0f8f0000;
2330                                 else if (rssi_level == 2)
2331                                         ratr_bitmap &= 0x0ffff000;
2332                                 else
2333                                         ratr_bitmap &= 0x0ffff015;
2334                         } else {
2335                                 if (rssi_level == 1)
2336                                         ratr_bitmap &= 0x0f8f0000;
2337                                 else if (rssi_level == 2)
2338                                         ratr_bitmap &= 0x0ffff000;
2339                                 else
2340                                         ratr_bitmap &= 0x0ffff005;
2341                         }
2342                 }
2343
2344                 if ((curtxbw_40mhz && b_curshortgi_40mhz) ||
2345                     (!curtxbw_40mhz && b_curshortgi_20mhz)) {
2346                         if (macid == 0)
2347                                 b_shortgi = true;
2348                         else if (macid == 1)
2349                                 b_shortgi = false;
2350                 }
2351                 break;
2352         default:
2353                 ratr_index = RATR_INX_WIRELESS_NGB;
2354
2355                 if (rtlphy->rf_type == RF_1T1R)
2356                         ratr_bitmap &= 0x000ff0ff;
2357                 else
2358                         ratr_bitmap &= 0x0f8ff0ff;
2359                 break;
2360         }
2361         ratr_index = _rtl92ee_mrate_idx_to_arfr_id(hw, ratr_index);
2362         sta_entry->ratr_index = ratr_index;
2363
2364         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2365                  "ratr_bitmap :%x\n", ratr_bitmap);
2366         *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2367                                        (ratr_index << 28);
2368         rate_mask[0] = macid;
2369         rate_mask[1] = ratr_index | (b_shortgi ? 0x80 : 0x00);
2370         rate_mask[2] = curtxbw_40mhz;
2371         rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);
2372         rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8);
2373         rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
2374         rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
2375         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2376                  "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
2377                   ratr_index, ratr_bitmap, rate_mask[0], rate_mask[1],
2378                   rate_mask[2], rate_mask[3], rate_mask[4],
2379                   rate_mask[5], rate_mask[6]);
2380         rtl92ee_fill_h2c_cmd(hw, H2C_92E_RA_MASK, 7, rate_mask);
2381         _rtl92ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
2382 }
2383
2384 void rtl92ee_update_hal_rate_tbl(struct ieee80211_hw *hw,
2385                                  struct ieee80211_sta *sta, u8 rssi_level)
2386 {
2387         struct rtl_priv *rtlpriv = rtl_priv(hw);
2388
2389         if (rtlpriv->dm.useramask)
2390                 rtl92ee_update_hal_rate_mask(hw, sta, rssi_level);
2391 }
2392
2393 void rtl92ee_update_channel_access_setting(struct ieee80211_hw *hw)
2394 {
2395         struct rtl_priv *rtlpriv = rtl_priv(hw);
2396         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2397         u16 sifs_timer;
2398
2399         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2400                                       (u8 *)&mac->slot_time);
2401         if (!mac->ht_enable)
2402                 sifs_timer = 0x0a0a;
2403         else
2404                 sifs_timer = 0x0e0e;
2405         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2406 }
2407
2408 bool rtl92ee_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2409 {
2410         *valid = 1;
2411         return true;
2412 }
2413
2414 void rtl92ee_set_key(struct ieee80211_hw *hw, u32 key_index,
2415                      u8 *p_macaddr, bool is_group, u8 enc_algo,
2416                      bool is_wepkey, bool clear_all)
2417 {
2418         struct rtl_priv *rtlpriv = rtl_priv(hw);
2419         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2420         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2421         u8 *macaddr = p_macaddr;
2422         u32 entry_id = 0;
2423         bool is_pairwise = false;
2424
2425         static u8 cam_const_addr[4][6] = {
2426                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2427                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2428                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2429                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2430         };
2431         static u8 cam_const_broad[] = {
2432                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2433         };
2434
2435         if (clear_all) {
2436                 u8 idx = 0;
2437                 u8 cam_offset = 0;
2438                 u8 clear_number = 5;
2439
2440                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2441
2442                 for (idx = 0; idx < clear_number; idx++) {
2443                         rtl_cam_mark_invalid(hw, cam_offset + idx);
2444                         rtl_cam_empty_entry(hw, cam_offset + idx);
2445
2446                         if (idx < 5) {
2447                                 memset(rtlpriv->sec.key_buf[idx], 0,
2448                                        MAX_KEY_LEN);
2449                                 rtlpriv->sec.key_len[idx] = 0;
2450                         }
2451                 }
2452
2453         } else {
2454                 switch (enc_algo) {
2455                 case WEP40_ENCRYPTION:
2456                         enc_algo = CAM_WEP40;
2457                         break;
2458                 case WEP104_ENCRYPTION:
2459                         enc_algo = CAM_WEP104;
2460                         break;
2461                 case TKIP_ENCRYPTION:
2462                         enc_algo = CAM_TKIP;
2463                         break;
2464                 case AESCCMP_ENCRYPTION:
2465                         enc_algo = CAM_AES;
2466                         break;
2467                 default:
2468                         RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
2469                                  "switch case %#x not processed\n", enc_algo);
2470                         enc_algo = CAM_TKIP;
2471                         break;
2472                 }
2473
2474                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2475                         macaddr = cam_const_addr[key_index];
2476                         entry_id = key_index;
2477                 } else {
2478                         if (is_group) {
2479                                 macaddr = cam_const_broad;
2480                                 entry_id = key_index;
2481                         } else {
2482                                 if (mac->opmode == NL80211_IFTYPE_AP ||
2483                                     mac->opmode == NL80211_IFTYPE_MESH_POINT) {
2484                                         entry_id = rtl_cam_get_free_entry(hw,
2485                                                                      p_macaddr);
2486                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
2487                                                 RT_TRACE(rtlpriv, COMP_SEC,
2488                                                          DBG_EMERG,
2489                                                          "Can not find free hw security cam entry\n");
2490                                                 return;
2491                                         }
2492                                 } else {
2493                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
2494                                 }
2495
2496                                 key_index = PAIRWISE_KEYIDX;
2497                                 is_pairwise = true;
2498                         }
2499                 }
2500
2501                 if (rtlpriv->sec.key_len[key_index] == 0) {
2502                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2503                                  "delete one entry, entry_id is %d\n",
2504                                  entry_id);
2505                         if (mac->opmode == NL80211_IFTYPE_AP ||
2506                             mac->opmode == NL80211_IFTYPE_MESH_POINT)
2507                                 rtl_cam_del_entry(hw, p_macaddr);
2508                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2509                 } else {
2510                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2511                                  "add one entry\n");
2512                         if (is_pairwise) {
2513                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2514                                          "set Pairwiase key\n");
2515
2516                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2517                                                entry_id, enc_algo,
2518                                                CAM_CONFIG_NO_USEDK,
2519                                                rtlpriv->sec.key_buf[key_index]);
2520                         } else {
2521                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2522                                          "set group key\n");
2523
2524                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2525                                         rtl_cam_add_one_entry(hw,
2526                                                 rtlefuse->dev_addr,
2527                                                 PAIRWISE_KEYIDX,
2528                                                 CAM_PAIRWISE_KEY_POSITION,
2529                                                 enc_algo, CAM_CONFIG_NO_USEDK,
2530                                                 rtlpriv->sec.key_buf[entry_id]);
2531                                 }
2532
2533                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2534                                                 entry_id, enc_algo,
2535                                                 CAM_CONFIG_NO_USEDK,
2536                                                 rtlpriv->sec.key_buf[entry_id]);
2537                         }
2538                 }
2539         }
2540 }
2541
2542 void rtl92ee_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2543                                             bool auto_load_fail, u8 *hwinfo)
2544 {
2545         struct rtl_priv *rtlpriv = rtl_priv(hw);
2546         u8 value;
2547
2548         if (!auto_load_fail) {
2549                 value = hwinfo[EEPROM_RF_BOARD_OPTION_92E];
2550                 if (((value & 0xe0) >> 5) == 0x1)
2551                         rtlpriv->btcoexist.btc_info.btcoexist = 1;
2552                 else
2553                         rtlpriv->btcoexist.btc_info.btcoexist = 0;
2554
2555                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8192E;
2556                 rtlpriv->btcoexist.btc_info.ant_num = ANT_TOTAL_X2;
2557         } else {
2558                 rtlpriv->btcoexist.btc_info.btcoexist = 1;
2559                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8192E;
2560                 rtlpriv->btcoexist.btc_info.ant_num = ANT_TOTAL_X1;
2561         }
2562 }
2563
2564 void rtl92ee_bt_reg_init(struct ieee80211_hw *hw)
2565 {
2566         struct rtl_priv *rtlpriv = rtl_priv(hw);
2567
2568         /* 0:Low, 1:High, 2:From Efuse. */
2569         rtlpriv->btcoexist.reg_bt_iso = 2;
2570         /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2571         rtlpriv->btcoexist.reg_bt_sco = 3;
2572         /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2573         rtlpriv->btcoexist.reg_bt_sco = 0;
2574 }
2575
2576 void rtl92ee_bt_hw_init(struct ieee80211_hw *hw)
2577 {
2578         struct rtl_priv *rtlpriv = rtl_priv(hw);
2579
2580         if (rtlpriv->cfg->ops->get_btc_status())
2581                 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
2582 }
2583
2584 void rtl92ee_suspend(struct ieee80211_hw *hw)
2585 {
2586 }
2587
2588 void rtl92ee_resume(struct ieee80211_hw *hw)
2589 {
2590 }
2591
2592 /* Turn on AAP (RCR:bit 0) for promicuous mode. */
2593 void rtl92ee_allow_all_destaddr(struct ieee80211_hw *hw,
2594                                 bool allow_all_da, bool write_into_reg)
2595 {
2596         struct rtl_priv *rtlpriv = rtl_priv(hw);
2597         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2598
2599         if (allow_all_da)       /* Set BIT0 */
2600                 rtlpci->receive_config |= RCR_AAP;
2601         else                    /* Clear BIT0 */
2602                 rtlpci->receive_config &= ~RCR_AAP;
2603
2604         if (write_into_reg)
2605                 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
2606
2607         RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD,
2608                  "receive_config=0x%08X, write_into_reg=%d\n",
2609                   rtlpci->receive_config, write_into_reg);
2610 }