drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #include "../wifi.h"
  27 #include "../rtl8192ce/reg.h"
  28 #include "../rtl8192ce/def.h"
  29 #include "dm_common.h"
  30 #include "fw_common.h"
  31 #include "phy_common.h"
  32 #include <linux/export.h>
  33
  34 u32 rtl92c_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
  35 {
  36         struct rtl_priv *rtlpriv = rtl_priv(hw);
  37         u32 returnvalue, originalvalue, bitshift;
  38
  39         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n",
  40                  regaddr, bitmask);
  41         originalvalue = rtl_read_dword(rtlpriv, regaddr);
  42         bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
  43         returnvalue = (originalvalue & bitmask) >> bitshift;
  44
  45         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  46                  "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
  47                  bitmask, regaddr, originalvalue);
  48
  49         return returnvalue;
  50 }
  51 EXPORT_SYMBOL(rtl92c_phy_query_bb_reg);
  52
  53 void rtl92c_phy_set_bb_reg(struct ieee80211_hw *hw,
  54                            u32 regaddr, u32 bitmask, u32 data)
  55 {
  56         struct rtl_priv *rtlpriv = rtl_priv(hw);
  57         u32 originalvalue, bitshift;
  58
  59         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  60                  "regaddr(%#x), bitmask(%#x), data(%#x)\n",
  61                  regaddr, bitmask, data);
  62
  63         if (bitmask != MASKDWORD) {
  64                 originalvalue = rtl_read_dword(rtlpriv, regaddr);
  65                 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
  66                 data = ((originalvalue & (~bitmask)) | (data << bitshift));
  67         }
  68
  69         rtl_write_dword(rtlpriv, regaddr, data);
  70
  71         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  72                  "regaddr(%#x), bitmask(%#x), data(%#x)\n",
  73                  regaddr, bitmask, data);
  74 }
  75 EXPORT_SYMBOL(rtl92c_phy_set_bb_reg);
  76
  77 u32 _rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw *hw,
  78                                   enum radio_path rfpath, u32 offset)
  79 {
  80         WARN_ONCE(true, "rtl8192c-common: _rtl92c_phy_fw_rf_serial_read deprecated!\n");
  81         return 0;
  82 }
  83 EXPORT_SYMBOL(_rtl92c_phy_fw_rf_serial_read);
  84
  85 void _rtl92c_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
  86                                     enum radio_path rfpath, u32 offset,
  87                                     u32 data)
  88 {
  89         WARN_ONCE(true, "rtl8192c-common: _rtl92c_phy_fw_rf_serial_write deprecated!\n");
  90 }
  91 EXPORT_SYMBOL(_rtl92c_phy_fw_rf_serial_write);
  92
  93 u32 _rtl92c_phy_rf_serial_read(struct ieee80211_hw *hw,
  94                                enum radio_path rfpath, u32 offset)
  95 {
  96         struct rtl_priv *rtlpriv = rtl_priv(hw);
  97         struct rtl_phy *rtlphy = &(rtlpriv->phy);
  98         struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
  99         u32 newoffset;
 100         u32 tmplong, tmplong2;
 101         u8 rfpi_enable = 0;
 102         u32 retvalue;
 103
 104         offset &= 0x3f;
 105         newoffset = offset;
 106         if (RT_CANNOT_IO(hw)) {
 107                 pr_err("return all one\n");
 108                 return 0xFFFFFFFF;
 109         }
 110         tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
 111         if (rfpath == RF90_PATH_A)
 112                 tmplong2 = tmplong;
 113         else
 114                 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
 115         tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
 116             (newoffset << 23) | BLSSIREADEDGE;
 117         rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
 118                       tmplong & (~BLSSIREADEDGE));
 119         mdelay(1);
 120         rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
 121         mdelay(1);
 122         rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
 123                       tmplong | BLSSIREADEDGE);
 124         mdelay(1);
 125         if (rfpath == RF90_PATH_A)
 126                 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
 127                                                  BIT(8));
 128         else if (rfpath == RF90_PATH_B)
 129                 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
 130                                                  BIT(8));
 131         if (rfpi_enable)
 132                 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
 133                                          BLSSIREADBACKDATA);
 134         else
 135                 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
 136                                          BLSSIREADBACKDATA);
 137         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]=0x%x\n",
 138                                                rfpath, pphyreg->rf_rb,
 139                                                retvalue);
 140         return retvalue;
 141 }
 142 EXPORT_SYMBOL(_rtl92c_phy_rf_serial_read);
 143
 144 void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw,
 145                                  enum radio_path rfpath, u32 offset,
 146                                  u32 data)
 147 {
 148         u32 data_and_addr;
 149         u32 newoffset;
 150         struct rtl_priv *rtlpriv = rtl_priv(hw);
 151         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 152         struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
 153
 154         if (RT_CANNOT_IO(hw)) {
 155                 pr_err("stop\n");
 156                 return;
 157         }
 158         offset &= 0x3f;
 159         newoffset = offset;
 160         data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
 161         rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
 162         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
 163                                                rfpath, pphyreg->rf3wire_offset,
 164                                                data_and_addr);
 165 }
 166 EXPORT_SYMBOL(_rtl92c_phy_rf_serial_write);
 167
 168 u32 _rtl92c_phy_calculate_bit_shift(u32 bitmask)
 169 {
 170         u32 i;
 171
 172         for (i = 0; i <= 31; i++) {
 173                 if (((bitmask >> i) & 0x1) == 1)
 174                         break;
 175         }
 176         return i;
 177 }
 178 EXPORT_SYMBOL(_rtl92c_phy_calculate_bit_shift);
 179
 180 static void _rtl92c_phy_bb_config_1t(struct ieee80211_hw *hw)
 181 {
 182         rtl_set_bbreg(hw, RFPGA0_TXINFO, 0x3, 0x2);
 183         rtl_set_bbreg(hw, RFPGA1_TXINFO, 0x300033, 0x200022);
 184         rtl_set_bbreg(hw, RCCK0_AFESETTING, MASKBYTE3, 0x45);
 185         rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x23);
 186         rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, 0x30, 0x1);
 187         rtl_set_bbreg(hw, 0xe74, 0x0c000000, 0x2);
 188         rtl_set_bbreg(hw, 0xe78, 0x0c000000, 0x2);
 189         rtl_set_bbreg(hw, 0xe7c, 0x0c000000, 0x2);
 190         rtl_set_bbreg(hw, 0xe80, 0x0c000000, 0x2);
 191         rtl_set_bbreg(hw, 0xe88, 0x0c000000, 0x2);
 192 }
 193
 194 bool rtl92c_phy_rf_config(struct ieee80211_hw *hw)
 195 {
 196         struct rtl_priv *rtlpriv = rtl_priv(hw);
 197
 198         return rtlpriv->cfg->ops->phy_rf6052_config(hw);
 199 }
 200 EXPORT_SYMBOL(rtl92c_phy_rf_config);
 201
 202 bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw)
 203 {
 204         struct rtl_priv *rtlpriv = rtl_priv(hw);
 205         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 206         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 207         bool rtstatus;
 208
 209         rtstatus = rtlpriv->cfg->ops->config_bb_with_headerfile(hw,
 210                                                  BASEBAND_CONFIG_PHY_REG);
 211         if (!rtstatus) {
 212                 pr_err("Write BB Reg Fail!!\n");
 213                 return false;
 214         }
 215         if (rtlphy->rf_type == RF_1T2R) {
 216                 _rtl92c_phy_bb_config_1t(hw);
 217                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Config to 1T!!\n");
 218         }
 219         if (rtlefuse->autoload_failflag == false) {
 220                 rtlphy->pwrgroup_cnt = 0;
 221                 rtstatus = rtlpriv->cfg->ops->config_bb_with_pgheaderfile(hw,
 222                                                    BASEBAND_CONFIG_PHY_REG);
 223         }
 224         if (!rtstatus) {
 225                 pr_err("BB_PG Reg Fail!!\n");
 226                 return false;
 227         }
 228         rtstatus = rtlpriv->cfg->ops->config_bb_with_headerfile(hw,
 229                                                  BASEBAND_CONFIG_AGC_TAB);
 230         if (!rtstatus) {
 231                 pr_err("AGC Table Fail\n");
 232                 return false;
 233         }
 234         rtlphy->cck_high_power =
 235                 (bool)(rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, 0x200));
 236
 237         return true;
 238 }
 239
 240 EXPORT_SYMBOL(_rtl92c_phy_bb8192c_config_parafile);
 241
 242 void _rtl92c_store_pwrIndex_diffrate_offset(struct ieee80211_hw *hw,
 243                                             u32 regaddr, u32 bitmask,
 244                                             u32 data)
 245 {
 246         struct rtl_priv *rtlpriv = rtl_priv(hw);
 247         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 248
 249         if (regaddr == RTXAGC_A_RATE18_06) {
 250                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][0] =
 251                     data;
 252                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 253                          "MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n",
 254                           rtlphy->pwrgroup_cnt,
 255                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 256                                                             pwrgroup_cnt][0]);
 257         }
 258         if (regaddr == RTXAGC_A_RATE54_24) {
 259                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][1] =
 260                     data;
 261                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 262                          "MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n",
 263                           rtlphy->pwrgroup_cnt,
 264                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 265                                                             pwrgroup_cnt][1]);
 266         }
 267         if (regaddr == RTXAGC_A_CCK1_MCS32) {
 268                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][6] =
 269                     data;
 270                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 271                          "MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n",
 272                           rtlphy->pwrgroup_cnt,
 273                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 274                                                             pwrgroup_cnt][6]);
 275         }
 276         if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) {
 277                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][7] =
 278                     data;
 279                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 280                          "MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n",
 281                           rtlphy->pwrgroup_cnt,
 282                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 283                                                             pwrgroup_cnt][7]);
 284         }
 285         if (regaddr == RTXAGC_A_MCS03_MCS00) {
 286                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][2] =
 287                     data;
 288                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 289                          "MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n",
 290                           rtlphy->pwrgroup_cnt,
 291                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 292                                                             pwrgroup_cnt][2]);
 293         }
 294         if (regaddr == RTXAGC_A_MCS07_MCS04) {
 295                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][3] =
 296                     data;
 297                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 298                          "MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n",
 299                           rtlphy->pwrgroup_cnt,
 300                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 301                                                             pwrgroup_cnt][3]);
 302         }
 303         if (regaddr == RTXAGC_A_MCS11_MCS08) {
 304                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][4] =
 305                     data;
 306                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 307                          "MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n",
 308                           rtlphy->pwrgroup_cnt,
 309                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 310                                                             pwrgroup_cnt][4]);
 311         }
 312         if (regaddr == RTXAGC_A_MCS15_MCS12) {
 313                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][5] =
 314                     data;
 315                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 316                          "MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n",
 317                           rtlphy->pwrgroup_cnt,
 318                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 319                                                             pwrgroup_cnt][5]);
 320         }
 321         if (regaddr == RTXAGC_B_RATE18_06) {
 322                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][8] =
 323                     data;
 324                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 325                          "MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n",
 326                           rtlphy->pwrgroup_cnt,
 327                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 328                                                             pwrgroup_cnt][8]);
 329         }
 330         if (regaddr == RTXAGC_B_RATE54_24) {
 331                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][9] =
 332                     data;
 333                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 334                          "MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n",
 335                           rtlphy->pwrgroup_cnt,
 336                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 337                                                             pwrgroup_cnt][9]);
 338         }
 339         if (regaddr == RTXAGC_B_CCK1_55_MCS32) {
 340                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][14] =
 341                     data;
 342                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 343                          "MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n",
 344                           rtlphy->pwrgroup_cnt,
 345                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 346                                                             pwrgroup_cnt][14]);
 347         }
 348         if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) {
 349                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][15] =
 350                     data;
 351                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 352                          "MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n",
 353                           rtlphy->pwrgroup_cnt,
 354                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 355                                                             pwrgroup_cnt][15]);
 356         }
 357         if (regaddr == RTXAGC_B_MCS03_MCS00) {
 358                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][10] =
 359                     data;
 360                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 361                          "MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n",
 362                           rtlphy->pwrgroup_cnt,
 363                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 364                                                             pwrgroup_cnt][10]);
 365         }
 366         if (regaddr == RTXAGC_B_MCS07_MCS04) {
 367                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][11] =
 368                     data;
 369                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 370                          "MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n",
 371                           rtlphy->pwrgroup_cnt,
 372                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 373                                                             pwrgroup_cnt][11]);
 374         }
 375         if (regaddr == RTXAGC_B_MCS11_MCS08) {
 376                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][12] =
 377                     data;
 378                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 379                          "MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n",
 380                           rtlphy->pwrgroup_cnt,
 381                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 382                                                             pwrgroup_cnt][12]);
 383         }
 384         if (regaddr == RTXAGC_B_MCS15_MCS12) {
 385                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][13] =
 386                     data;
 387                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 388                          "MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n",
 389                           rtlphy->pwrgroup_cnt,
 390                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 391                                                             pwrgroup_cnt][13]);
 392
 393                 rtlphy->pwrgroup_cnt++;
 394         }
 395 }
 396 EXPORT_SYMBOL(_rtl92c_store_pwrIndex_diffrate_offset);
 397
 398 void rtl92c_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
 399 {
 400         struct rtl_priv *rtlpriv = rtl_priv(hw);
 401         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 402
 403         rtlphy->default_initialgain[0] =
 404             (u8)rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
 405         rtlphy->default_initialgain[1] =
 406             (u8)rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
 407         rtlphy->default_initialgain[2] =
 408             (u8)rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
 409         rtlphy->default_initialgain[3] =
 410             (u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
 411
 412         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 413                  "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
 414                   rtlphy->default_initialgain[0],
 415                   rtlphy->default_initialgain[1],
 416                   rtlphy->default_initialgain[2],
 417                   rtlphy->default_initialgain[3]);
 418
 419         rtlphy->framesync = (u8)rtl_get_bbreg(hw,
 420                                                ROFDM0_RXDETECTOR3, MASKBYTE0);
 421         rtlphy->framesync_c34 = rtl_get_bbreg(hw,
 422                                               ROFDM0_RXDETECTOR2, MASKDWORD);
 423
 424         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 425                  "Default framesync (0x%x) = 0x%x\n",
 426                   ROFDM0_RXDETECTOR3, rtlphy->framesync);
 427 }
 428
 429 void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
 430 {
 431         struct rtl_priv *rtlpriv = rtl_priv(hw);
 432         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 433
 434         rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
 435         rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
 436         rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
 437         rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
 438
 439         rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
 440         rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
 441         rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
 442         rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
 443
 444         rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
 445         rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
 446
 447         rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
 448         rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
 449
 450         rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
 451             RFPGA0_XA_LSSIPARAMETER;
 452         rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
 453             RFPGA0_XB_LSSIPARAMETER;
 454
 455         rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = rFPGA0_XAB_RFPARAMETER;
 456         rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = rFPGA0_XAB_RFPARAMETER;
 457         rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = rFPGA0_XCD_RFPARAMETER;
 458         rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = rFPGA0_XCD_RFPARAMETER;
 459
 460         rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 461         rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 462         rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 463         rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 464
 465         rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
 466         rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
 467
 468         rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
 469         rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
 470
 471         rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
 472         rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
 473         rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
 474         rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
 475
 476         rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
 477         rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
 478         rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
 479         rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
 480
 481         rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
 482         rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
 483         rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
 484         rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
 485
 486         rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
 487         rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
 488         rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBANLANCE;
 489         rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;
 490
 491         rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
 492         rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
 493         rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
 494         rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
 495
 496         rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;
 497         rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;
 498         rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;
 499         rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;
 500
 501         rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
 502         rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
 503         rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
 504         rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
 505
 506         rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
 507         rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
 508         rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;
 509         rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;
 510
 511         rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK;
 512         rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK;
 513
 514 }
 515 EXPORT_SYMBOL(_rtl92c_phy_init_bb_rf_register_definition);
 516
 517 void rtl92c_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
 518 {
 519         struct rtl_priv *rtlpriv = rtl_priv(hw);
 520         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 521         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 522         u8 txpwr_level;
 523         long txpwr_dbm;
 524
 525         txpwr_level = rtlphy->cur_cck_txpwridx;
 526         txpwr_dbm = _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_B,
 527                                                  txpwr_level);
 528         txpwr_level = rtlphy->cur_ofdm24g_txpwridx +
 529             rtlefuse->legacy_ht_txpowerdiff;
 530         if (_rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
 531                                          txpwr_level) > txpwr_dbm)
 532                 txpwr_dbm =
 533                     _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
 534                                                  txpwr_level);
 535         txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
 536         if (_rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
 537                                          txpwr_level) > txpwr_dbm)
 538                 txpwr_dbm =
 539                     _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
 540                                                  txpwr_level);
 541         *powerlevel = txpwr_dbm;
 542 }
 543
 544 static void _rtl92c_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
 545                                       u8 *cckpowerlevel, u8 *ofdmpowerlevel)
 546 {
 547         struct rtl_priv *rtlpriv = rtl_priv(hw);
 548         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 549         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 550         u8 index = (channel - 1);
 551
 552         cckpowerlevel[RF90_PATH_A] =
 553             rtlefuse->txpwrlevel_cck[RF90_PATH_A][index];
 554         cckpowerlevel[RF90_PATH_B] =
 555             rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];
 556         if (get_rf_type(rtlphy) == RF_1T2R || get_rf_type(rtlphy) == RF_1T1R) {
 557                 ofdmpowerlevel[RF90_PATH_A] =
 558                     rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index];
 559                 ofdmpowerlevel[RF90_PATH_B] =
 560                     rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];
 561         } else if (get_rf_type(rtlphy) == RF_2T2R) {
 562                 ofdmpowerlevel[RF90_PATH_A] =
 563                     rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index];
 564                 ofdmpowerlevel[RF90_PATH_B] =
 565                     rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index];
 566         }
 567 }
 568
 569 static void _rtl92c_ccxpower_index_check(struct ieee80211_hw *hw,
 570                                          u8 channel, u8 *cckpowerlevel,
 571                                          u8 *ofdmpowerlevel)
 572 {
 573         struct rtl_priv *rtlpriv = rtl_priv(hw);
 574         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 575
 576         rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
 577         rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
 578 }
 579
 580 void rtl92c_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
 581 {
 582         struct rtl_priv *rtlpriv = rtl_priv(hw);
 583         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 584         u8 cckpowerlevel[2], ofdmpowerlevel[2];
 585
 586         if (!rtlefuse->txpwr_fromeprom)
 587                 return;
 588         _rtl92c_get_txpower_index(hw, channel,
 589                                   &cckpowerlevel[0], &ofdmpowerlevel[0]);
 590         _rtl92c_ccxpower_index_check(hw, channel, &cckpowerlevel[0],
 591                                      &ofdmpowerlevel[0]);
 592         rtlpriv->cfg->ops->phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
 593         rtlpriv->cfg->ops->phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0],
 594                                                        channel);
 595 }
 596 EXPORT_SYMBOL(rtl92c_phy_set_txpower_level);
 597
 598 bool rtl92c_phy_update_txpower_dbm(struct ieee80211_hw *hw, long power_indbm)
 599 {
 600         struct rtl_priv *rtlpriv = rtl_priv(hw);
 601         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 602         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 603         u8 idx;
 604         u8 rf_path;
 605         u8 ccktxpwridx = _rtl92c_phy_dbm_to_txpwr_idx(hw, WIRELESS_MODE_B,
 606                                                       power_indbm);
 607         u8 ofdmtxpwridx = _rtl92c_phy_dbm_to_txpwr_idx(hw, WIRELESS_MODE_N_24G,
 608                                                        power_indbm);
 609         if (ofdmtxpwridx - rtlefuse->legacy_ht_txpowerdiff > 0)
 610                 ofdmtxpwridx -= rtlefuse->legacy_ht_txpowerdiff;
 611         else
 612                 ofdmtxpwridx = 0;
 613         RT_TRACE(rtlpriv, COMP_TXAGC, DBG_TRACE,
 614                  "%lx dBm, ccktxpwridx = %d, ofdmtxpwridx = %d\n",
 615                   power_indbm, ccktxpwridx, ofdmtxpwridx);
 616         for (idx = 0; idx < 14; idx++) {
 617                 for (rf_path = 0; rf_path < 2; rf_path++) {
 618                         rtlefuse->txpwrlevel_cck[rf_path][idx] = ccktxpwridx;
 619                         rtlefuse->txpwrlevel_ht40_1s[rf_path][idx] =
 620                             ofdmtxpwridx;
 621                         rtlefuse->txpwrlevel_ht40_2s[rf_path][idx] =
 622                             ofdmtxpwridx;
 623                 }
 624         }
 625         rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
 626         return true;
 627 }
 628 EXPORT_SYMBOL(rtl92c_phy_update_txpower_dbm);
 629
 630 u8 _rtl92c_phy_dbm_to_txpwr_idx(struct ieee80211_hw *hw,
 631                                 enum wireless_mode wirelessmode,
 632                                 long power_indbm)
 633 {
 634         u8 txpwridx;
 635         long offset;
 636
 637         switch (wirelessmode) {
 638         case WIRELESS_MODE_B:
 639                 offset = -7;
 640                 break;
 641         case WIRELESS_MODE_G:
 642         case WIRELESS_MODE_N_24G:
 643                 offset = -8;
 644                 break;
 645         default:
 646                 offset = -8;
 647                 break;
 648         }
 649
 650         if ((power_indbm - offset) > 0)
 651                 txpwridx = (u8)((power_indbm - offset) * 2);
 652         else
 653                 txpwridx = 0;
 654
 655         if (txpwridx > MAX_TXPWR_IDX_NMODE_92S)
 656                 txpwridx = MAX_TXPWR_IDX_NMODE_92S;
 657
 658         return txpwridx;
 659 }
 660 EXPORT_SYMBOL(_rtl92c_phy_dbm_to_txpwr_idx);
 661
 662 long _rtl92c_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
 663                                   enum wireless_mode wirelessmode,
 664                                   u8 txpwridx)
 665 {
 666         long offset;
 667         long pwrout_dbm;
 668
 669         switch (wirelessmode) {
 670         case WIRELESS_MODE_B:
 671                 offset = -7;
 672                 break;
 673         case WIRELESS_MODE_G:
 674         case WIRELESS_MODE_N_24G:
 675                 offset = -8;
 676                 break;
 677         default:
 678                 offset = -8;
 679                 break;
 680         }
 681         pwrout_dbm = txpwridx / 2 + offset;
 682         return pwrout_dbm;
 683 }
 684 EXPORT_SYMBOL(_rtl92c_phy_txpwr_idx_to_dbm);
 685
 686 void rtl92c_phy_set_bw_mode(struct ieee80211_hw *hw,
 687                             enum nl80211_channel_type ch_type)
 688 {
 689         struct rtl_priv *rtlpriv = rtl_priv(hw);
 690         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 691         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 692         u8 tmp_bw = rtlphy->current_chan_bw;
 693
 694         if (rtlphy->set_bwmode_inprogress)
 695                 return;
 696         rtlphy->set_bwmode_inprogress = true;
 697         if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
 698                 rtlpriv->cfg->ops->phy_set_bw_mode_callback(hw);
 699         } else {
 700                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 701                          "false driver sleep or unload\n");
 702                 rtlphy->set_bwmode_inprogress = false;
 703                 rtlphy->current_chan_bw = tmp_bw;
 704         }
 705 }
 706 EXPORT_SYMBOL(rtl92c_phy_set_bw_mode);
 707
 708 void rtl92c_phy_sw_chnl_callback(struct ieee80211_hw *hw)
 709 {
 710         struct rtl_priv *rtlpriv = rtl_priv(hw);
 711         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 712         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 713         u32 delay;
 714
 715         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
 716                  "switch to channel%d\n", rtlphy->current_channel);
 717         if (is_hal_stop(rtlhal))
 718                 return;
 719         do {
 720                 if (!rtlphy->sw_chnl_inprogress)
 721                         break;
 722                 if (!_rtl92c_phy_sw_chnl_step_by_step
 723                     (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage,
 724                      &rtlphy->sw_chnl_step, &delay)) {
 725                         if (delay > 0)
 726                                 mdelay(delay);
 727                         else
 728                                 continue;
 729                 } else {
 730                         rtlphy->sw_chnl_inprogress = false;
 731                 }
 732                 break;
 733         } while (true);
 734         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "\n");
 735 }
 736 EXPORT_SYMBOL(rtl92c_phy_sw_chnl_callback);
 737
 738 u8 rtl92c_phy_sw_chnl(struct ieee80211_hw *hw)
 739 {
 740         struct rtl_priv *rtlpriv = rtl_priv(hw);
 741         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 742         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 743
 744         if (rtlphy->sw_chnl_inprogress)
 745                 return 0;
 746         if (rtlphy->set_bwmode_inprogress)
 747                 return 0;
 748         WARN_ONCE((rtlphy->current_channel > 14),
 749                   "rtl8192c-common: WIRELESS_MODE_G but channel>14");
 750         rtlphy->sw_chnl_inprogress = true;
 751         rtlphy->sw_chnl_stage = 0;
 752         rtlphy->sw_chnl_step = 0;
 753         if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
 754                 rtl92c_phy_sw_chnl_callback(hw);
 755                 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
 756                          "sw_chnl_inprogress false schedule workitem\n");
 757                 rtlphy->sw_chnl_inprogress = false;
 758         } else {
 759                 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
 760                          "sw_chnl_inprogress false driver sleep or unload\n");
 761                 rtlphy->sw_chnl_inprogress = false;
 762         }
 763         return 1;
 764 }
 765 EXPORT_SYMBOL(rtl92c_phy_sw_chnl);
 766
 767 static void _rtl92c_phy_sw_rf_seting(struct ieee80211_hw *hw, u8 channel)
 768 {
 769         struct rtl_priv *rtlpriv = rtl_priv(hw);
 770         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 771         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 772         if (IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version)) {
 773                 if (channel == 6 &&
 774                     rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) {
 775                         rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1,
 776                                       MASKDWORD, 0x00255);
 777                 } else {
 778                         u32 backuprf0x1A =
 779                           (u32)rtl_get_rfreg(hw, RF90_PATH_A, RF_RX_G1,
 780                                              RFREG_OFFSET_MASK);
 781                         rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD,
 782                                       backuprf0x1A);
 783                 }
 784         }
 785 }
 786
 787 static bool _rtl92c_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
 788                                              u32 cmdtableidx, u32 cmdtablesz,
 789                                              enum swchnlcmd_id cmdid,
 790                                              u32 para1, u32 para2, u32 msdelay)
 791 {
 792         struct swchnlcmd *pcmd;
 793
 794         if (cmdtable == NULL) {
 795                 WARN_ONCE(true, "rtl8192c-common: cmdtable cannot be NULL.\n");
 796                 return false;
 797         }
 798
 799         if (cmdtableidx >= cmdtablesz)
 800                 return false;
 801
 802         pcmd = cmdtable + cmdtableidx;
 803         pcmd->cmdid = cmdid;
 804         pcmd->para1 = para1;
 805         pcmd->para2 = para2;
 806         pcmd->msdelay = msdelay;
 807         return true;
 808 }
 809
 810 bool _rtl92c_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
 811                                       u8 channel, u8 *stage, u8 *step,
 812                                       u32 *delay)
 813 {
 814         struct rtl_priv *rtlpriv = rtl_priv(hw);
 815         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 816         struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
 817         u32 precommoncmdcnt;
 818         struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
 819         u32 postcommoncmdcnt;
 820         struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
 821         u32 rfdependcmdcnt;
 822         struct swchnlcmd *currentcmd = NULL;
 823         u8 rfpath;
 824         u8 num_total_rfpath = rtlphy->num_total_rfpath;
 825
 826         precommoncmdcnt = 0;
 827         _rtl92c_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
 828                                          MAX_PRECMD_CNT,
 829                                          CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
 830         _rtl92c_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
 831                                          MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
 832
 833         postcommoncmdcnt = 0;
 834
 835         _rtl92c_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
 836                                          MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
 837
 838         rfdependcmdcnt = 0;
 839
 840         WARN_ONCE((channel < 1 || channel > 14),
 841                   "rtl8192c-common: illegal channel for Zebra: %d\n", channel);
 842
 843         _rtl92c_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
 844                                          MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
 845                                          RF_CHNLBW, channel, 10);
 846
 847         _rtl92c_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
 848                                          MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0,
 849                                          0);
 850
 851         do {
 852                 switch (*stage) {
 853                 case 0:
 854                         currentcmd = &precommoncmd[*step];
 855                         break;
 856                 case 1:
 857                         currentcmd = &rfdependcmd[*step];
 858                         break;
 859                 case 2:
 860                         currentcmd = &postcommoncmd[*step];
 861                         break;
 862                 default:
 863                         pr_err("Invalid 'stage' = %d, Check it!\n",
 864                                *stage);
 865                         return true;
 866                 }
 867
 868                 if (currentcmd->cmdid == CMDID_END) {
 869                         if ((*stage) == 2) {
 870                                 return true;
 871                         } else {
 872                                 (*stage)++;
 873                                 (*step) = 0;
 874                                 continue;
 875                         }
 876                 }
 877
 878                 switch (currentcmd->cmdid) {
 879                 case CMDID_SET_TXPOWEROWER_LEVEL:
 880                         rtl92c_phy_set_txpower_level(hw, channel);
 881                         break;
 882                 case CMDID_WRITEPORT_ULONG:
 883                         rtl_write_dword(rtlpriv, currentcmd->para1,
 884                                         currentcmd->para2);
 885                         break;
 886                 case CMDID_WRITEPORT_USHORT:
 887                         rtl_write_word(rtlpriv, currentcmd->para1,
 888                                        (u16) currentcmd->para2);
 889                         break;
 890                 case CMDID_WRITEPORT_UCHAR:
 891                         rtl_write_byte(rtlpriv, currentcmd->para1,
 892                                        (u8)currentcmd->para2);
 893                         break;
 894                 case CMDID_RF_WRITEREG:
 895                         for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
 896                                 rtlphy->rfreg_chnlval[rfpath] =
 897                                     ((rtlphy->rfreg_chnlval[rfpath] &
 898                                       0xfffffc00) | currentcmd->para2);
 899
 900                                 rtl_set_rfreg(hw, (enum radio_path)rfpath,
 901                                               currentcmd->para1,
 902                                               RFREG_OFFSET_MASK,
 903                                               rtlphy->rfreg_chnlval[rfpath]);
 904                         }
 905                         _rtl92c_phy_sw_rf_seting(hw, channel);
 906                         break;
 907                 default:
 908                         RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
 909                                  "switch case %#x not processed\n",
 910                                  currentcmd->cmdid);
 911                         break;
 912                 }
 913
 914                 break;
 915         } while (true);
 916
 917         (*delay) = currentcmd->msdelay;
 918         (*step)++;
 919         return false;
 920 }
 921
 922 bool rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw *hw, u32 rfpath)
 923 {
 924         return true;
 925 }
 926 EXPORT_SYMBOL(rtl8192_phy_check_is_legal_rfpath);
 927
 928 static u8 _rtl92c_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb)
 929 {
 930         u32 reg_eac, reg_e94, reg_e9c, reg_ea4;
 931         u8 result = 0x00;
 932
 933         rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f);
 934         rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f);
 935         rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102);
 936         rtl_set_bbreg(hw, 0xe3c, MASKDWORD,
 937                       config_pathb ? 0x28160202 : 0x28160502);
 938
 939         if (config_pathb) {
 940                 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22);
 941                 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22);
 942                 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102);
 943                 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160202);
 944         }
 945
 946         rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x001028d1);
 947         rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
 948         rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
 949
 950         mdelay(IQK_DELAY_TIME);
 951
 952         reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
 953         reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
 954         reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
 955         reg_ea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
 956
 957         if (!(reg_eac & BIT(28)) &&
 958             (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
 959             (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
 960                 result |= 0x01;
 961         else
 962                 return result;
 963
 964         if (!(reg_eac & BIT(27)) &&
 965             (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
 966             (((reg_eac & 0x03FF0000) >> 16) != 0x36))
 967                 result |= 0x02;
 968         return result;
 969 }
 970
 971 static u8 _rtl92c_phy_path_b_iqk(struct ieee80211_hw *hw)
 972 {
 973         u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
 974         u8 result = 0x00;
 975
 976         rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
 977         rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
 978         mdelay(IQK_DELAY_TIME);
 979         reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
 980         reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
 981         reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
 982         reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
 983         reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
 984
 985         if (!(reg_eac & BIT(31)) &&
 986             (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) &&
 987             (((reg_ebc & 0x03FF0000) >> 16) != 0x42))
 988                 result |= 0x01;
 989         else
 990                 return result;
 991         if (!(reg_eac & BIT(30)) &&
 992             (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) &&
 993             (((reg_ecc & 0x03FF0000) >> 16) != 0x36))
 994                 result |= 0x02;
 995         return result;
 996 }
 997
 998 static void _rtl92c_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw,
 999                                                bool b_iqk_ok, long result[][8],
1000                                                u8 final_candidate, bool btxonly)
1001 {
1002         u32 oldval_0, x, tx0_a, reg;
1003         long y, tx0_c;
1004
1005         if (final_candidate == 0xFF) {
1006                 return;
1007         } else if (b_iqk_ok) {
1008                 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
1009                                           MASKDWORD) >> 22) & 0x3FF;
1010                 x = result[final_candidate][0];
1011                 if ((x & 0x00000200) != 0)
1012                         x = x | 0xFFFFFC00;
1013                 tx0_a = (x * oldval_0) >> 8;
1014                 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a);
1015                 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31),
1016                               ((x * oldval_0 >> 7) & 0x1));
1017                 y = result[final_candidate][1];
1018                 if ((y & 0x00000200) != 0)
1019                         y = y | 0xFFFFFC00;
1020                 tx0_c = (y * oldval_0) >> 8;
1021                 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
1022                               ((tx0_c & 0x3C0) >> 6));
1023                 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000,
1024                               (tx0_c & 0x3F));
1025                 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29),
1026                               ((y * oldval_0 >> 7) & 0x1));
1027                 if (btxonly)
1028                         return;
1029                 reg = result[final_candidate][2];
1030                 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
1031                 reg = result[final_candidate][3] & 0x3F;
1032                 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
1033                 reg = (result[final_candidate][3] >> 6) & 0xF;
1034                 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
1035         }
1036 }
1037
1038 static void _rtl92c_phy_path_b_fill_iqk_matrix(struct ieee80211_hw *hw,
1039                                                bool b_iqk_ok, long result[][8],
1040                                                u8 final_candidate, bool btxonly)
1041 {
1042         u32 oldval_1, x, tx1_a, reg;
1043         long y, tx1_c;
1044
1045         if (final_candidate == 0xFF) {
1046                 return;
1047         } else if (b_iqk_ok) {
1048                 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
1049                                           MASKDWORD) >> 22) & 0x3FF;
1050                 x = result[final_candidate][4];
1051                 if ((x & 0x00000200) != 0)
1052                         x = x | 0xFFFFFC00;
1053                 tx1_a = (x * oldval_1) >> 8;
1054                 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a);
1055                 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(27),
1056                               ((x * oldval_1 >> 7) & 0x1));
1057                 y = result[final_candidate][5];
1058                 if ((y & 0x00000200) != 0)
1059                         y = y | 0xFFFFFC00;
1060                 tx1_c = (y * oldval_1) >> 8;
1061                 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000,
1062                               ((tx1_c & 0x3C0) >> 6));
1063                 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000,
1064                               (tx1_c & 0x3F));
1065                 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(25),
1066                               ((y * oldval_1 >> 7) & 0x1));
1067                 if (btxonly)
1068                         return;
1069                 reg = result[final_candidate][6];
1070                 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
1071                 reg = result[final_candidate][7] & 0x3F;
1072                 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg);
1073                 reg = (result[final_candidate][7] >> 6) & 0xF;
1074                 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg);
1075         }
1076 }
1077
1078 static void _rtl92c_phy_save_adda_registers(struct ieee80211_hw *hw,
1079                                             u32 *addareg, u32 *addabackup,
1080                                             u32 registernum)
1081 {
1082         u32 i;
1083
1084         for (i = 0; i < registernum; i++)
1085                 addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);
1086 }
1087
1088 static void _rtl92c_phy_save_mac_registers(struct ieee80211_hw *hw,
1089                                            u32 *macreg, u32 *macbackup)
1090 {
1091         struct rtl_priv *rtlpriv = rtl_priv(hw);
1092         u32 i;
1093
1094         for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1095                 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
1096         macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
1097 }
1098
1099 static void _rtl92c_phy_reload_adda_registers(struct ieee80211_hw *hw,
1100                                               u32 *addareg, u32 *addabackup,
1101                                               u32 regiesternum)
1102 {
1103         u32 i;
1104
1105         for (i = 0; i < regiesternum; i++)
1106                 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]);
1107 }
1108
1109 static void _rtl92c_phy_reload_mac_registers(struct ieee80211_hw *hw,
1110                                              u32 *macreg, u32 *macbackup)
1111 {
1112         struct rtl_priv *rtlpriv = rtl_priv(hw);
1113         u32 i;
1114
1115         for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1116                 rtl_write_byte(rtlpriv, macreg[i], (u8)macbackup[i]);
1117         rtl_write_dword(rtlpriv, macreg[i], macbackup[i]);
1118 }
1119
1120 static void _rtl92c_phy_path_adda_on(struct ieee80211_hw *hw,
1121                                      u32 *addareg, bool is_patha_on, bool is2t)
1122 {
1123         u32 pathOn;
1124         u32 i;
1125
1126         pathOn = is_patha_on ? 0x04db25a4 : 0x0b1b25a4;
1127         if (false == is2t) {
1128                 pathOn = 0x0bdb25a0;
1129                 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0);
1130         } else {
1131                 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathOn);
1132         }
1133
1134         for (i = 1; i < IQK_ADDA_REG_NUM; i++)
1135                 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathOn);
1136 }
1137
1138 static void _rtl92c_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1139                                                 u32 *macreg, u32 *macbackup)
1140 {
1141         struct rtl_priv *rtlpriv = rtl_priv(hw);
1142         u32 i = 0;
1143
1144         rtl_write_byte(rtlpriv, macreg[i], 0x3F);
1145
1146         for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
1147                 rtl_write_byte(rtlpriv, macreg[i],
1148                                (u8)(macbackup[i] & (~BIT(3))));
1149         rtl_write_byte(rtlpriv, macreg[i], (u8)(macbackup[i] & (~BIT(5))));
1150 }
1151
1152 static void _rtl92c_phy_path_a_standby(struct ieee80211_hw *hw)
1153 {
1154         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
1155         rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1156         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1157 }
1158
1159 static void _rtl92c_phy_pi_mode_switch(struct ieee80211_hw *hw, bool pi_mode)
1160 {
1161         u32 mode;
1162
1163         mode = pi_mode ? 0x01000100 : 0x01000000;
1164         rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
1165         rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
1166 }
1167
1168 static bool _rtl92c_phy_simularity_compare(struct ieee80211_hw *hw,
1169                                            long result[][8], u8 c1, u8 c2)
1170 {
1171         u32 i, j, diff, simularity_bitmap, bound;
1172         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1173
1174         u8 final_candidate[2] = { 0xFF, 0xFF };
1175         bool bresult = true, is2t = IS_92C_SERIAL(rtlhal->version);
1176
1177         if (is2t)
1178                 bound = 8;
1179         else
1180                 bound = 4;
1181
1182         simularity_bitmap = 0;
1183
1184         for (i = 0; i < bound; i++) {
1185                 diff = (result[c1][i] > result[c2][i]) ?
1186                     (result[c1][i] - result[c2][i]) :
1187                     (result[c2][i] - result[c1][i]);
1188
1189                 if (diff > MAX_TOLERANCE) {
1190                         if ((i == 2 || i == 6) && !simularity_bitmap) {
1191                                 if (result[c1][i] + result[c1][i + 1] == 0)
1192                                         final_candidate[(i / 4)] = c2;
1193                                 else if (result[c2][i] + result[c2][i + 1] == 0)
1194                                         final_candidate[(i / 4)] = c1;
1195                                 else
1196                                         simularity_bitmap = simularity_bitmap |
1197                                             (1 << i);
1198                         } else
1199                                 simularity_bitmap =
1200                                     simularity_bitmap | (1 << i);
1201                 }
1202         }
1203
1204         if (simularity_bitmap == 0) {
1205                 for (i = 0; i < (bound / 4); i++) {
1206                         if (final_candidate[i] != 0xFF) {
1207                                 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
1208                                         result[3][j] =
1209                                             result[final_candidate[i]][j];
1210                                 bresult = false;
1211                         }
1212                 }
1213                 return bresult;
1214         } else if (!(simularity_bitmap & 0x0F)) {
1215                 for (i = 0; i < 4; i++)
1216                         result[3][i] = result[c1][i];
1217                 return false;
1218         } else if (!(simularity_bitmap & 0xF0) && is2t) {
1219                 for (i = 4; i < 8; i++)
1220                         result[3][i] = result[c1][i];
1221                 return false;
1222         } else {
1223                 return false;
1224         }
1225 }
1226
1227 static void _rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw,
1228                                      long result[][8], u8 t, bool is2t)
1229 {
1230         struct rtl_priv *rtlpriv = rtl_priv(hw);
1231         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1232         u32 i;
1233         u8 patha_ok, pathb_ok;
1234         u32 adda_reg[IQK_ADDA_REG_NUM] = {
1235                 0x85c, 0xe6c, 0xe70, 0xe74,
1236                 0xe78, 0xe7c, 0xe80, 0xe84,
1237                 0xe88, 0xe8c, 0xed0, 0xed4,
1238                 0xed8, 0xedc, 0xee0, 0xeec
1239         };
1240         u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1241                 0x522, 0x550, 0x551, 0x040
1242         };
1243         const u32 retrycount = 2;
1244         u32 bbvalue;
1245
1246         if (t == 0) {
1247                 bbvalue = rtl_get_bbreg(hw, 0x800, MASKDWORD);
1248
1249                 _rtl92c_phy_save_adda_registers(hw, adda_reg,
1250                                                 rtlphy->adda_backup, 16);
1251                 _rtl92c_phy_save_mac_registers(hw, iqk_mac_reg,
1252                                                rtlphy->iqk_mac_backup);
1253         }
1254         _rtl92c_phy_path_adda_on(hw, adda_reg, true, is2t);
1255         if (t == 0) {
1256                 rtlphy->rfpi_enable =
1257                    (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
1258                                      BIT(8));
1259         }
1260
1261         if (!rtlphy->rfpi_enable)
1262                 _rtl92c_phy_pi_mode_switch(hw, true);
1263         if (t == 0) {
1264                 rtlphy->reg_c04 = rtl_get_bbreg(hw, 0xc04, MASKDWORD);
1265                 rtlphy->reg_c08 = rtl_get_bbreg(hw, 0xc08, MASKDWORD);
1266                 rtlphy->reg_874 = rtl_get_bbreg(hw, 0x874, MASKDWORD);
1267         }
1268         rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600);
1269         rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4);
1270         rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000);
1271         if (is2t) {
1272                 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1273                 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000);
1274         }
1275         _rtl92c_phy_mac_setting_calibration(hw, iqk_mac_reg,
1276                                             rtlphy->iqk_mac_backup);
1277         rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x00080000);
1278         if (is2t)
1279                 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x00080000);
1280         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1281         rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
1282         rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
1283         for (i = 0; i < retrycount; i++) {
1284                 patha_ok = _rtl92c_phy_path_a_iqk(hw, is2t);
1285                 if (patha_ok == 0x03) {
1286                         result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1287                                         0x3FF0000) >> 16;
1288                         result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1289                                         0x3FF0000) >> 16;
1290                         result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
1291                                         0x3FF0000) >> 16;
1292                         result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
1293                                         0x3FF0000) >> 16;
1294                         break;
1295                 } else if (i == (retrycount - 1) && patha_ok == 0x01)
1296
1297                         result[t][0] = (rtl_get_bbreg(hw, 0xe94,
1298                                                       MASKDWORD) & 0x3FF0000) >>
1299                             16;
1300                 result[t][1] =
1301                     (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 0x3FF0000) >> 16;
1302
1303         }
1304
1305         if (is2t) {
1306                 _rtl92c_phy_path_a_standby(hw);
1307                 _rtl92c_phy_path_adda_on(hw, adda_reg, false, is2t);
1308                 for (i = 0; i < retrycount; i++) {
1309                         pathb_ok = _rtl92c_phy_path_b_iqk(hw);
1310                         if (pathb_ok == 0x03) {
1311                                 result[t][4] = (rtl_get_bbreg(hw,
1312                                                               0xeb4,
1313                                                               MASKDWORD) &
1314                                                 0x3FF0000) >> 16;
1315                                 result[t][5] =
1316                                     (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1317                                      0x3FF0000) >> 16;
1318                                 result[t][6] =
1319                                     (rtl_get_bbreg(hw, 0xec4, MASKDWORD) &
1320                                      0x3FF0000) >> 16;
1321                                 result[t][7] =
1322                                     (rtl_get_bbreg(hw, 0xecc, MASKDWORD) &
1323                                      0x3FF0000) >> 16;
1324                                 break;
1325                         } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1326                                 result[t][4] = (rtl_get_bbreg(hw,
1327                                                               0xeb4,
1328                                                               MASKDWORD) &
1329                                                 0x3FF0000) >> 16;
1330                         }
1331                         result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1332                                         0x3FF0000) >> 16;
1333                 }
1334         }
1335         rtl_set_bbreg(hw, 0xc04, MASKDWORD, rtlphy->reg_c04);
1336         rtl_set_bbreg(hw, 0x874, MASKDWORD, rtlphy->reg_874);
1337         rtl_set_bbreg(hw, 0xc08, MASKDWORD, rtlphy->reg_c08);
1338         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
1339         rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3);
1340         if (is2t)
1341                 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3);
1342         if (t != 0) {
1343                 if (!rtlphy->rfpi_enable)
1344                         _rtl92c_phy_pi_mode_switch(hw, false);
1345                 _rtl92c_phy_reload_adda_registers(hw, adda_reg,
1346                                                   rtlphy->adda_backup, 16);
1347                 _rtl92c_phy_reload_mac_registers(hw, iqk_mac_reg,
1348                                                  rtlphy->iqk_mac_backup);
1349         }
1350 }
1351
1352 static void _rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw,
1353                                      s8 delta, bool is2t)
1354 {
1355 }
1356
1357 static void _rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw,
1358                                           bool bmain, bool is2t)
1359 {
1360         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1361
1362         if (is_hal_stop(rtlhal)) {
1363                 rtl_set_bbreg(hw, REG_LEDCFG0, BIT(23), 0x01);
1364                 rtl_set_bbreg(hw, rFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
1365         }
1366         if (is2t) {
1367                 if (bmain)
1368                         rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1369                                       BIT(5) | BIT(6), 0x1);
1370                 else
1371                         rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1372                                       BIT(5) | BIT(6), 0x2);
1373         } else {
1374                 if (bmain)
1375                         rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x2);
1376                 else
1377                         rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x1);
1378         }
1379 }
1380
1381 #undef IQK_ADDA_REG_NUM
1382 #undef IQK_DELAY_TIME
1383
1384 void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery)
1385 {
1386         struct rtl_priv *rtlpriv = rtl_priv(hw);
1387         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1388         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1389
1390         long result[4][8];
1391         u8 i, final_candidate;
1392         bool b_patha_ok, b_pathb_ok;
1393         long reg_e94, reg_e9c, reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4,
1394             reg_ecc, reg_tmp = 0;
1395         bool is12simular, is13simular, is23simular;
1396         u32 iqk_bb_reg[10] = {
1397                 ROFDM0_XARXIQIMBALANCE,
1398                 ROFDM0_XBRXIQIMBALANCE,
1399                 ROFDM0_ECCATHRESHOLD,
1400                 ROFDM0_AGCRSSITABLE,
1401                 ROFDM0_XATXIQIMBALANCE,
1402                 ROFDM0_XBTXIQIMBALANCE,
1403                 ROFDM0_XCTXIQIMBALANCE,
1404                 ROFDM0_XCTXAFE,
1405                 ROFDM0_XDTXAFE,
1406                 ROFDM0_RXIQEXTANTA
1407         };
1408
1409         if (b_recovery) {
1410                 _rtl92c_phy_reload_adda_registers(hw,
1411                                                   iqk_bb_reg,
1412                                                   rtlphy->iqk_bb_backup, 10);
1413                 return;
1414         }
1415         for (i = 0; i < 8; i++) {
1416                 result[0][i] = 0;
1417                 result[1][i] = 0;
1418                 result[2][i] = 0;
1419                 result[3][i] = 0;
1420         }
1421         final_candidate = 0xff;
1422         b_patha_ok = false;
1423         b_pathb_ok = false;
1424         is12simular = false;
1425         is23simular = false;
1426         is13simular = false;
1427         for (i = 0; i < 3; i++) {
1428                 if (IS_92C_SERIAL(rtlhal->version))
1429                         _rtl92c_phy_iq_calibrate(hw, result, i, true);
1430                 else
1431                         _rtl92c_phy_iq_calibrate(hw, result, i, false);
1432                 if (i == 1) {
1433                         is12simular = _rtl92c_phy_simularity_compare(hw,
1434                                                                      result, 0,
1435                                                                      1);
1436                         if (is12simular) {
1437                                 final_candidate = 0;
1438                                 break;
1439                         }
1440                 }
1441                 if (i == 2) {
1442                         is13simular = _rtl92c_phy_simularity_compare(hw,
1443                                                                      result, 0,
1444                                                                      2);
1445                         if (is13simular) {
1446                                 final_candidate = 0;
1447                                 break;
1448                         }
1449                         is23simular = _rtl92c_phy_simularity_compare(hw,
1450                                                                      result, 1,
1451                                                                      2);
1452                         if (is23simular)
1453                                 final_candidate = 1;
1454                         else {
1455                                 for (i = 0; i < 8; i++)
1456                                         reg_tmp += result[3][i];
1457
1458                                 if (reg_tmp != 0)
1459                                         final_candidate = 3;
1460                                 else
1461                                         final_candidate = 0xFF;
1462                         }
1463                 }
1464         }
1465         for (i = 0; i < 4; i++) {
1466                 reg_e94 = result[i][0];
1467                 reg_e9c = result[i][1];
1468                 reg_ea4 = result[i][2];
1469                 reg_eac = result[i][3];
1470                 reg_eb4 = result[i][4];
1471                 reg_ebc = result[i][5];
1472                 reg_ec4 = result[i][6];
1473                 reg_ecc = result[i][7];
1474         }
1475         if (final_candidate != 0xff) {
1476                 rtlphy->reg_e94 = reg_e94 = result[final_candidate][0];
1477                 rtlphy->reg_e9c = reg_e9c = result[final_candidate][1];
1478                 reg_ea4 = result[final_candidate][2];
1479                 reg_eac = result[final_candidate][3];
1480                 rtlphy->reg_eb4 = reg_eb4 = result[final_candidate][4];
1481                 rtlphy->reg_ebc = reg_ebc = result[final_candidate][5];
1482                 reg_ec4 = result[final_candidate][6];
1483                 reg_ecc = result[final_candidate][7];
1484                 b_patha_ok = true;
1485                 b_pathb_ok = true;
1486         } else {
1487                 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100;
1488                 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0;
1489         }
1490         if (reg_e94 != 0) /*&&(reg_ea4 != 0) */
1491                 _rtl92c_phy_path_a_fill_iqk_matrix(hw, b_patha_ok, result,
1492                                                    final_candidate,
1493                                                    (reg_ea4 == 0));
1494         if (IS_92C_SERIAL(rtlhal->version)) {
1495                 if (reg_eb4 != 0) /*&&(reg_ec4 != 0) */
1496                         _rtl92c_phy_path_b_fill_iqk_matrix(hw, b_pathb_ok,
1497                                                            result,
1498                                                            final_candidate,
1499                                                            (reg_ec4 == 0));
1500         }
1501         _rtl92c_phy_save_adda_registers(hw, iqk_bb_reg,
1502                                         rtlphy->iqk_bb_backup, 10);
1503 }
1504 EXPORT_SYMBOL(rtl92c_phy_iq_calibrate);
1505
1506 void rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw)
1507 {
1508         struct rtl_priv *rtlpriv = rtl_priv(hw);
1509         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1510
1511         if (IS_92C_SERIAL(rtlhal->version))
1512                 rtlpriv->cfg->ops->phy_lc_calibrate(hw, true);
1513         else
1514                 rtlpriv->cfg->ops->phy_lc_calibrate(hw, false);
1515 }
1516 EXPORT_SYMBOL(rtl92c_phy_lc_calibrate);
1517
1518 void rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta)
1519 {
1520         struct rtl_priv *rtlpriv = rtl_priv(hw);
1521         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1522         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1523
1524         if (rtlphy->apk_done)
1525                 return;
1526         if (IS_92C_SERIAL(rtlhal->version))
1527                 _rtl92c_phy_ap_calibrate(hw, delta, true);
1528         else
1529                 _rtl92c_phy_ap_calibrate(hw, delta, false);
1530 }
1531 EXPORT_SYMBOL(rtl92c_phy_ap_calibrate);
1532
1533 void rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
1534 {
1535         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1536
1537         if (IS_92C_SERIAL(rtlhal->version))
1538                 _rtl92c_phy_set_rfpath_switch(hw, bmain, true);
1539         else
1540                 _rtl92c_phy_set_rfpath_switch(hw, bmain, false);
1541 }
1542 EXPORT_SYMBOL(rtl92c_phy_set_rfpath_switch);
1543
1544 bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
1545 {
1546         struct rtl_priv *rtlpriv = rtl_priv(hw);
1547         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1548         bool postprocessing = false;
1549
1550         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1551                  "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
1552                   iotype, rtlphy->set_io_inprogress);
1553         do {
1554                 switch (iotype) {
1555                 case IO_CMD_RESUME_DM_BY_SCAN:
1556                         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1557                                  "[IO CMD] Resume DM after scan.\n");
1558                         postprocessing = true;
1559                         break;
1560                 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
1561                         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1562                                  "[IO CMD] Pause DM before scan.\n");
1563                         postprocessing = true;
1564                         break;
1565                 default:
1566                         RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1567                                  "switch case %#x not processed\n", iotype);
1568                         break;
1569                 }
1570         } while (false);
1571         if (postprocessing && !rtlphy->set_io_inprogress) {
1572                 rtlphy->set_io_inprogress = true;
1573                 rtlphy->current_io_type = iotype;
1574         } else {
1575                 return false;
1576         }
1577         rtl92c_phy_set_io(hw);
1578         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "IO Type(%#x)\n", iotype);
1579         return true;
1580 }
1581 EXPORT_SYMBOL(rtl92c_phy_set_io_cmd);
1582
1583 void rtl92c_phy_set_io(struct ieee80211_hw *hw)
1584 {
1585         struct rtl_priv *rtlpriv = rtl_priv(hw);
1586         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1587         struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
1588
1589         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1590                  "--->Cmd(%#x), set_io_inprogress(%d)\n",
1591                   rtlphy->current_io_type, rtlphy->set_io_inprogress);
1592         switch (rtlphy->current_io_type) {
1593         case IO_CMD_RESUME_DM_BY_SCAN:
1594                 dm_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1;
1595                 rtl92c_dm_write_dig(hw);
1596                 rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
1597                 break;
1598         case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
1599                 rtlphy->initgain_backup.xaagccore1 = dm_digtable->cur_igvalue;
1600                 dm_digtable->cur_igvalue = 0x17;
1601                 rtl92c_dm_write_dig(hw);
1602                 break;
1603         default:
1604                 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1605                          "switch case %#x not processed\n",
1606                          rtlphy->current_io_type);
1607                 break;
1608         }
1609         rtlphy->set_io_inprogress = false;
1610         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1611                  "(%#x)\n", rtlphy->current_io_type);
1612 }
1613 EXPORT_SYMBOL(rtl92c_phy_set_io);
1614
1615 void rtl92ce_phy_set_rf_on(struct ieee80211_hw *hw)
1616 {
1617         struct rtl_priv *rtlpriv = rtl_priv(hw);
1618
1619         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
1620         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1621         rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
1622         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1623         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1624         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1625 }
1626 EXPORT_SYMBOL(rtl92ce_phy_set_rf_on);
1627
1628 void _rtl92c_phy_set_rf_sleep(struct ieee80211_hw *hw)
1629 {
1630         u32 u4b_tmp;
1631         u8 delay = 5;
1632         struct rtl_priv *rtlpriv = rtl_priv(hw);
1633
1634         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1635         rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1636         rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1637         u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
1638         while (u4b_tmp != 0 && delay > 0) {
1639                 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
1640                 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1641                 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1642                 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
1643                 delay--;
1644         }
1645         if (delay == 0) {
1646                 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
1647                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1648                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1649                 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1650                 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
1651                          "Switch RF timeout !!!.\n");
1652                 return;
1653         }
1654         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1655         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
1656 }
1657 EXPORT_SYMBOL(_rtl92c_phy_set_rf_sleep);