drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2013  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #include "../wifi.h"
  27 #include "../efuse.h"
  28 #include "../base.h"
  29 #include "../regd.h"
  30 #include "../cam.h"
  31 #include "../ps.h"
  32 #include "../pci.h"
  33 #include "../pwrseqcmd.h"
  34 #include "reg.h"
  35 #include "def.h"
  36 #include "phy.h"
  37 #include "dm.h"
  38 #include "fw.h"
  39 #include "led.h"
  40 #include "hw.h"
  41 #include "pwrseq.h"
  42
  43 #define LLT_CONFIG              5
  44
  45 static void _rtl88ee_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
  46                                       u8 set_bits, u8 clear_bits)
  47 {
  48         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  49         struct rtl_priv *rtlpriv = rtl_priv(hw);
  50
  51         rtlpci->reg_bcn_ctrl_val |= set_bits;
  52         rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
  53
  54         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
  55 }
  56
  57 static void _rtl88ee_stop_tx_beacon(struct ieee80211_hw *hw)
  58 {
  59         struct rtl_priv *rtlpriv = rtl_priv(hw);
  60         u8 tmp1byte;
  61
  62         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  63         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
  64         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
  65         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  66         tmp1byte &= ~(BIT(0));
  67         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  68 }
  69
  70 static void _rtl88ee_resume_tx_beacon(struct ieee80211_hw *hw)
  71 {
  72         struct rtl_priv *rtlpriv = rtl_priv(hw);
  73         u8 tmp1byte;
  74
  75         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  76         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
  77         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
  78         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  79         tmp1byte |= BIT(0);
  80         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  81 }
  82
  83 static void _rtl88ee_enable_bcn_sub_func(struct ieee80211_hw *hw)
  84 {
  85         _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(1));
  86 }
  87
  88 static void _rtl88ee_return_beacon_queue_skb(struct ieee80211_hw *hw)
  89 {
  90         struct rtl_priv *rtlpriv = rtl_priv(hw);
  91         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  92         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
  93         unsigned long flags;
  94
  95         spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
  96         while (skb_queue_len(&ring->queue)) {
  97                 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
  98                 struct sk_buff *skb = __skb_dequeue(&ring->queue);
  99
 100                 pci_unmap_single(rtlpci->pdev,
 101                                  rtlpriv->cfg->ops->get_desc(
 102                                  (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
 103                                  skb->len, PCI_DMA_TODEVICE);
 104                 kfree_skb(skb);
 105                 ring->idx = (ring->idx + 1) % ring->entries;
 106         }
 107         spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
 108 }
 109
 110 static void _rtl88ee_disable_bcn_sub_func(struct ieee80211_hw *hw)
 111 {
 112         _rtl88ee_set_bcn_ctrl_reg(hw, BIT(1), 0);
 113 }
 114
 115 static void _rtl88ee_set_fw_clock_on(struct ieee80211_hw *hw,
 116                                      u8 rpwm_val, bool b_need_turn_off_ckk)
 117 {
 118         struct rtl_priv *rtlpriv = rtl_priv(hw);
 119         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 120         bool b_support_remote_wake_up;
 121         u32 count = 0, isr_regaddr, content;
 122         bool schedule_timer = b_need_turn_off_ckk;
 123         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
 124                                         (u8 *)(&b_support_remote_wake_up));
 125
 126         if (!rtlhal->fw_ready)
 127                 return;
 128         if (!rtlpriv->psc.fw_current_inpsmode)
 129                 return;
 130
 131         while (1) {
 132                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 133                 if (rtlhal->fw_clk_change_in_progress) {
 134                         while (rtlhal->fw_clk_change_in_progress) {
 135                                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 136                                 count++;
 137                                 udelay(100);
 138                                 if (count > 1000)
 139                                         return;
 140                                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 141                         }
 142                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 143                 } else {
 144                         rtlhal->fw_clk_change_in_progress = false;
 145                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 146                         break;
 147                 }
 148         }
 149
 150         if (IS_IN_LOW_POWER_STATE_88E(rtlhal->fw_ps_state)) {
 151                 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val);
 152                 if (FW_PS_IS_ACK(rpwm_val)) {
 153                         isr_regaddr = REG_HISR;
 154                         content = rtl_read_dword(rtlpriv, isr_regaddr);
 155                         while (!(content & IMR_CPWM) && (count < 500)) {
 156                                 udelay(50);
 157                                 count++;
 158                                 content = rtl_read_dword(rtlpriv, isr_regaddr);
 159                         }
 160
 161                         if (content & IMR_CPWM) {
 162                                 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
 163                                 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_88E;
 164                                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
 165                                          "Receive CPWM INT!!! Set pHalData->FwPSState = %X\n",
 166                                          rtlhal->fw_ps_state);
 167                         }
 168                 }
 169
 170                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 171                 rtlhal->fw_clk_change_in_progress = false;
 172                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 173                 if (schedule_timer) {
 174                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 175                                   jiffies + MSECS(10));
 176                 }
 177
 178         } else  {
 179                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 180                 rtlhal->fw_clk_change_in_progress = false;
 181                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 182         }
 183 }
 184
 185 static void _rtl88ee_set_fw_clock_off(struct ieee80211_hw *hw,
 186                                       u8 rpwm_val)
 187 {
 188         struct rtl_priv *rtlpriv = rtl_priv(hw);
 189         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 190         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 191         struct rtl8192_tx_ring *ring;
 192         enum rf_pwrstate rtstate;
 193         bool schedule_timer = false;
 194         u8 queue;
 195
 196         if (!rtlhal->fw_ready)
 197                 return;
 198         if (!rtlpriv->psc.fw_current_inpsmode)
 199                 return;
 200         if (!rtlhal->allow_sw_to_change_hwclc)
 201                 return;
 202         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
 203         if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
 204                 return;
 205
 206         for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
 207                 ring = &rtlpci->tx_ring[queue];
 208                 if (skb_queue_len(&ring->queue)) {
 209                         schedule_timer = true;
 210                         break;
 211                 }
 212         }
 213
 214         if (schedule_timer) {
 215                 mod_timer(&rtlpriv->works.fw_clockoff_timer,
 216                           jiffies + MSECS(10));
 217                 return;
 218         }
 219
 220         if (FW_PS_STATE(rtlhal->fw_ps_state) !=
 221             FW_PS_STATE_RF_OFF_LOW_PWR_88E) {
 222                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 223                 if (!rtlhal->fw_clk_change_in_progress) {
 224                         rtlhal->fw_clk_change_in_progress = true;
 225                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 226                         rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
 227                         rtl_write_word(rtlpriv, REG_HISR, 0x0100);
 228                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 229                                                       &rpwm_val);
 230                         spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 231                         rtlhal->fw_clk_change_in_progress = false;
 232                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 233                 } else {
 234                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 235                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 236                                   jiffies + MSECS(10));
 237                 }
 238         }
 239 }
 240
 241 static void _rtl88ee_set_fw_ps_rf_on(struct ieee80211_hw *hw)
 242 {
 243         u8 rpwm_val = 0;
 244
 245         rpwm_val |= (FW_PS_STATE_RF_OFF_88E | FW_PS_ACK);
 246         _rtl88ee_set_fw_clock_on(hw, rpwm_val, true);
 247 }
 248
 249 static void _rtl88ee_set_fw_ps_rf_off_low_power(struct ieee80211_hw *hw)
 250 {
 251         u8 rpwm_val = 0;
 252         rpwm_val |= FW_PS_STATE_RF_OFF_LOW_PWR_88E;
 253         _rtl88ee_set_fw_clock_off(hw, rpwm_val);
 254 }
 255 void rtl88ee_fw_clk_off_timer_callback(unsigned long data)
 256 {
 257         struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
 258
 259         _rtl88ee_set_fw_ps_rf_off_low_power(hw);
 260 }
 261
 262 static void _rtl88ee_fwlps_leave(struct ieee80211_hw *hw)
 263 {
 264         struct rtl_priv *rtlpriv = rtl_priv(hw);
 265         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 266         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 267         bool fw_current_inps = false;
 268         u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
 269
 270         if (ppsc->low_power_enable) {
 271                 rpwm_val = (FW_PS_STATE_ALL_ON_88E|FW_PS_ACK);/* RF on */
 272                 _rtl88ee_set_fw_clock_on(hw, rpwm_val, false);
 273                 rtlhal->allow_sw_to_change_hwclc = false;
 274                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 275                                               &fw_pwrmode);
 276                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 277                                               (u8 *)(&fw_current_inps));
 278         } else {
 279                 rpwm_val = FW_PS_STATE_ALL_ON_88E;      /* RF on */
 280                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val);
 281                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 282                                               &fw_pwrmode);
 283                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 284                                               (u8 *)(&fw_current_inps));
 285         }
 286 }
 287
 288 static void _rtl88ee_fwlps_enter(struct ieee80211_hw *hw)
 289 {
 290         struct rtl_priv *rtlpriv = rtl_priv(hw);
 291         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 292         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 293         bool fw_current_inps = true;
 294         u8 rpwm_val;
 295
 296         if (ppsc->low_power_enable) {
 297                 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_88E;      /* RF off */
 298                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 299                                               (u8 *)(&fw_current_inps));
 300                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 301                                               &ppsc->fwctrl_psmode);
 302                 rtlhal->allow_sw_to_change_hwclc = true;
 303                 _rtl88ee_set_fw_clock_off(hw, rpwm_val);
 304         } else {
 305                 rpwm_val = FW_PS_STATE_RF_OFF_88E;      /* RF off */
 306                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 307                                               (u8 *)(&fw_current_inps));
 308                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 309                                               &ppsc->fwctrl_psmode);
 310                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val);
 311         }
 312 }
 313
 314 void rtl88ee_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 315 {
 316         struct rtl_priv *rtlpriv = rtl_priv(hw);
 317         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 318         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 319
 320         switch (variable) {
 321         case HW_VAR_RCR:
 322                 *((u32 *)(val)) = rtlpci->receive_config;
 323                 break;
 324         case HW_VAR_RF_STATE:
 325                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
 326                 break;
 327         case HW_VAR_FWLPS_RF_ON:{
 328                 enum rf_pwrstate rfstate;
 329                 u32 val_rcr;
 330
 331                 rtlpriv->cfg->ops->get_hw_reg(hw,
 332                                               HW_VAR_RF_STATE,
 333                                               (u8 *)(&rfstate));
 334                 if (rfstate == ERFOFF) {
 335                         *((bool *)(val)) = true;
 336                 } else {
 337                         val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
 338                         val_rcr &= 0x00070000;
 339                         if (val_rcr)
 340                                 *((bool *)(val)) = false;
 341                         else
 342                                 *((bool *)(val)) = true;
 343                 }
 344                 break; }
 345         case HW_VAR_FW_PSMODE_STATUS:
 346                 *((bool *)(val)) = ppsc->fw_current_inpsmode;
 347                 break;
 348         case HW_VAR_CORRECT_TSF:{
 349                 u64 tsf;
 350                 u32 *ptsf_low = (u32 *)&tsf;
 351                 u32 *ptsf_high = ((u32 *)&tsf) + 1;
 352
 353                 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
 354                 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
 355
 356                 *((u64 *)(val)) = tsf;
 357                 break; }
 358         case HAL_DEF_WOWLAN:
 359                 break;
 360         default:
 361                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 362                          "switch case %#x not processed\n", variable);
 363                 break;
 364         }
 365 }
 366
 367 void rtl88ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 368 {
 369         struct rtl_priv *rtlpriv = rtl_priv(hw);
 370         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 371         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 372         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 373         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 374         u8 idx;
 375
 376         switch (variable) {
 377         case HW_VAR_ETHER_ADDR:
 378                 for (idx = 0; idx < ETH_ALEN; idx++) {
 379                         rtl_write_byte(rtlpriv, (REG_MACID + idx),
 380                                        val[idx]);
 381                 }
 382                 break;
 383         case HW_VAR_BASIC_RATE:{
 384                 u16 b_rate_cfg = ((u16 *)val)[0];
 385                 u8 rate_index = 0;
 386                 b_rate_cfg = b_rate_cfg & 0x15f;
 387                 b_rate_cfg |= 0x01;
 388                 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
 389                 rtl_write_byte(rtlpriv, REG_RRSR + 1,
 390                                (b_rate_cfg >> 8) & 0xff);
 391                 while (b_rate_cfg > 0x1) {
 392                         b_rate_cfg = (b_rate_cfg >> 1);
 393                         rate_index++;
 394                 }
 395                 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
 396                                rate_index);
 397                 break;
 398                 }
 399         case HW_VAR_BSSID:
 400                 for (idx = 0; idx < ETH_ALEN; idx++) {
 401                         rtl_write_byte(rtlpriv, (REG_BSSID + idx),
 402                                        val[idx]);
 403                 }
 404                 break;
 405         case HW_VAR_SIFS:
 406                 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
 407                 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
 408
 409                 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
 410                 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
 411
 412                 if (!mac->ht_enable)
 413                         rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 414                                        0x0e0e);
 415                 else
 416                         rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 417                                        *((u16 *)val));
 418                 break;
 419         case HW_VAR_SLOT_TIME:{
 420                 u8 e_aci;
 421
 422                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 423                          "HW_VAR_SLOT_TIME %x\n", val[0]);
 424
 425                 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
 426
 427                 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 428                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
 429                                                       &e_aci);
 430                 }
 431                 break;
 432                 }
 433         case HW_VAR_ACK_PREAMBLE:{
 434                 u8 reg_tmp;
 435                 u8 short_preamble = (bool)*val;
 436                 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2);
 437                 if (short_preamble) {
 438                         reg_tmp |= 0x02;
 439                         rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL +
 440                                        2, reg_tmp);
 441                 } else {
 442                         reg_tmp |= 0xFD;
 443                         rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL +
 444                                        2, reg_tmp);
 445                 }
 446                 break; }
 447         case HW_VAR_WPA_CONFIG:
 448                 rtl_write_byte(rtlpriv, REG_SECCFG, *val);
 449                 break;
 450         case HW_VAR_AMPDU_MIN_SPACE:{
 451                 u8 min_spacing_to_set;
 452                 u8 sec_min_space;
 453
 454                 min_spacing_to_set = *val;
 455                 if (min_spacing_to_set <= 7) {
 456                         sec_min_space = 0;
 457
 458                         if (min_spacing_to_set < sec_min_space)
 459                                 min_spacing_to_set = sec_min_space;
 460
 461                         mac->min_space_cfg = ((mac->min_space_cfg &
 462                                                0xf8) |
 463                                               min_spacing_to_set);
 464
 465                         *val = min_spacing_to_set;
 466
 467                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 468                                  "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 469                                   mac->min_space_cfg);
 470
 471                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 472                                        mac->min_space_cfg);
 473                 }
 474                 break; }
 475         case HW_VAR_SHORTGI_DENSITY:{
 476                 u8 density_to_set;
 477
 478                 density_to_set = *val;
 479                 mac->min_space_cfg |= (density_to_set << 3);
 480
 481                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 482                          "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 483                           mac->min_space_cfg);
 484
 485                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 486                                mac->min_space_cfg);
 487                 break;
 488                 }
 489         case HW_VAR_AMPDU_FACTOR:{
 490                 u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 };
 491                 u8 factor_toset;
 492                 u8 *p_regtoset = NULL;
 493                 u8 index = 0;
 494
 495                 p_regtoset = regtoset_normal;
 496
 497                 factor_toset = *val;
 498                 if (factor_toset <= 3) {
 499                         factor_toset = (1 << (factor_toset + 2));
 500                         if (factor_toset > 0xf)
 501                                 factor_toset = 0xf;
 502
 503                         for (index = 0; index < 4; index++) {
 504                                 if ((p_regtoset[index] & 0xf0) >
 505                                     (factor_toset << 4))
 506                                         p_regtoset[index] =
 507                                             (p_regtoset[index] & 0x0f) |
 508                                             (factor_toset << 4);
 509
 510                                 if ((p_regtoset[index] & 0x0f) >
 511                                     factor_toset)
 512                                         p_regtoset[index] =
 513                                             (p_regtoset[index] & 0xf0) |
 514                                             (factor_toset);
 515
 516                                 rtl_write_byte(rtlpriv,
 517                                                (REG_AGGLEN_LMT + index),
 518                                                p_regtoset[index]);
 519
 520                         }
 521
 522                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 523                                  "Set HW_VAR_AMPDU_FACTOR: %#x\n",
 524                                   factor_toset);
 525                 }
 526                 break; }
 527         case HW_VAR_AC_PARAM:{
 528                 u8 e_aci = *val;
 529                 rtl88e_dm_init_edca_turbo(hw);
 530
 531                 if (rtlpci->acm_method != EACMWAY2_SW)
 532                         rtlpriv->cfg->ops->set_hw_reg(hw,
 533                                                       HW_VAR_ACM_CTRL,
 534                                                       &e_aci);
 535                 break; }
 536         case HW_VAR_ACM_CTRL:{
 537                 u8 e_aci = *val;
 538                 union aci_aifsn *p_aci_aifsn =
 539                     (union aci_aifsn *)(&(mac->ac[0].aifs));
 540                 u8 acm = p_aci_aifsn->f.acm;
 541                 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
 542
 543                 acm_ctrl = acm_ctrl |
 544                            ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
 545
 546                 if (acm) {
 547                         switch (e_aci) {
 548                         case AC0_BE:
 549                                 acm_ctrl |= ACMHW_BEQEN;
 550                                 break;
 551                         case AC2_VI:
 552                                 acm_ctrl |= ACMHW_VIQEN;
 553                                 break;
 554                         case AC3_VO:
 555                                 acm_ctrl |= ACMHW_VOQEN;
 556                                 break;
 557                         default:
 558                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 559                                          "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
 560                                          acm);
 561                                 break;
 562                         }
 563                 } else {
 564                         switch (e_aci) {
 565                         case AC0_BE:
 566                                 acm_ctrl &= (~ACMHW_BEQEN);
 567                                 break;
 568                         case AC2_VI:
 569                                 acm_ctrl &= (~ACMHW_VIQEN);
 570                                 break;
 571                         case AC3_VO:
 572                                 acm_ctrl &= (~ACMHW_VOQEN);
 573                                 break;
 574                         default:
 575                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 576                                          "switch case %#x not processed\n",
 577                                          e_aci);
 578                                 break;
 579                         }
 580                 }
 581
 582                 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 583                          "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
 584                          acm_ctrl);
 585                 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
 586                 break; }
 587         case HW_VAR_RCR:
 588                 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
 589                 rtlpci->receive_config = ((u32 *)(val))[0];
 590                 break;
 591         case HW_VAR_RETRY_LIMIT:{
 592                 u8 retry_limit = *val;
 593
 594                 rtl_write_word(rtlpriv, REG_RL,
 595                                retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 596                                retry_limit << RETRY_LIMIT_LONG_SHIFT);
 597                 break; }
 598         case HW_VAR_DUAL_TSF_RST:
 599                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
 600                 break;
 601         case HW_VAR_EFUSE_BYTES:
 602                 rtlefuse->efuse_usedbytes = *((u16 *)val);
 603                 break;
 604         case HW_VAR_EFUSE_USAGE:
 605                 rtlefuse->efuse_usedpercentage = *val;
 606                 break;
 607         case HW_VAR_IO_CMD:
 608                 rtl88e_phy_set_io_cmd(hw, (*(enum io_type *)val));
 609                 break;
 610         case HW_VAR_SET_RPWM:{
 611                 u8 rpwm_val;
 612
 613                 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
 614                 udelay(1);
 615
 616                 if (rpwm_val & BIT(7)) {
 617                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val);
 618                 } else {
 619                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val | BIT(7));
 620                 }
 621                 break; }
 622         case HW_VAR_H2C_FW_PWRMODE:
 623                 rtl88e_set_fw_pwrmode_cmd(hw, *val);
 624                 break;
 625         case HW_VAR_FW_PSMODE_STATUS:
 626                 ppsc->fw_current_inpsmode = *((bool *)val);
 627                 break;
 628         case HW_VAR_RESUME_CLK_ON:
 629                 _rtl88ee_set_fw_ps_rf_on(hw);
 630                 break;
 631         case HW_VAR_FW_LPS_ACTION:{
 632                 bool enter_fwlps = *((bool *)val);
 633
 634                 if (enter_fwlps)
 635                         _rtl88ee_fwlps_enter(hw);
 636                  else
 637                         _rtl88ee_fwlps_leave(hw);
 638
 639                  break; }
 640         case HW_VAR_H2C_FW_JOINBSSRPT:{
 641                 u8 mstatus = *val;
 642                 u8 tmp_regcr, tmp_reg422, bcnvalid_reg;
 643                 u8 count = 0, dlbcn_count = 0;
 644                 bool b_recover = false;
 645
 646                 if (mstatus == RT_MEDIA_CONNECT) {
 647                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
 648                                                       NULL);
 649
 650                         tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 651                         rtl_write_byte(rtlpriv, REG_CR + 1,
 652                                        (tmp_regcr | BIT(0)));
 653
 654                         _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
 655                         _rtl88ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
 656
 657                         tmp_reg422 =
 658                             rtl_read_byte(rtlpriv,
 659                                           REG_FWHW_TXQ_CTRL + 2);
 660                         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
 661                                        tmp_reg422 & (~BIT(6)));
 662                         if (tmp_reg422 & BIT(6))
 663                                 b_recover = true;
 664
 665                         do {
 666                                 bcnvalid_reg = rtl_read_byte(rtlpriv,
 667                                                              REG_TDECTRL+2);
 668                                 rtl_write_byte(rtlpriv, REG_TDECTRL+2,
 669                                                (bcnvalid_reg | BIT(0)));
 670                                 _rtl88ee_return_beacon_queue_skb(hw);
 671
 672                                 rtl88e_set_fw_rsvdpagepkt(hw, 0);
 673                                 bcnvalid_reg = rtl_read_byte(rtlpriv,
 674                                                              REG_TDECTRL+2);
 675                                 count = 0;
 676                                 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
 677                                         count++;
 678                                         udelay(10);
 679                                         bcnvalid_reg =
 680                                           rtl_read_byte(rtlpriv, REG_TDECTRL+2);
 681                                 }
 682                                 dlbcn_count++;
 683                         } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
 684
 685                         if (bcnvalid_reg & BIT(0))
 686                                 rtl_write_byte(rtlpriv, REG_TDECTRL+2, BIT(0));
 687
 688                         _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
 689                         _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
 690
 691                         if (b_recover) {
 692                                 rtl_write_byte(rtlpriv,
 693                                                REG_FWHW_TXQ_CTRL + 2,
 694                                                tmp_reg422);
 695                         }
 696
 697                         rtl_write_byte(rtlpriv, REG_CR + 1,
 698                                        (tmp_regcr & ~(BIT(0))));
 699                 }
 700                 rtl88e_set_fw_joinbss_report_cmd(hw, (*(u8 *)val));
 701                 break; }
 702         case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
 703                 rtl88e_set_p2p_ps_offload_cmd(hw, *val);
 704                 break;
 705         case HW_VAR_AID:{
 706                 u16 u2btmp;
 707
 708                 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
 709                 u2btmp &= 0xC000;
 710                 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
 711                                mac->assoc_id));
 712                 break; }
 713         case HW_VAR_CORRECT_TSF:{
 714                 u8 btype_ibss = *val;
 715
 716                 if (btype_ibss)
 717                         _rtl88ee_stop_tx_beacon(hw);
 718
 719                 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
 720
 721                 rtl_write_dword(rtlpriv, REG_TSFTR,
 722                                 (u32)(mac->tsf & 0xffffffff));
 723                 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
 724                                 (u32)((mac->tsf >> 32) & 0xffffffff));
 725
 726                 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
 727
 728                 if (btype_ibss)
 729                         _rtl88ee_resume_tx_beacon(hw);
 730                 break; }
 731         case HW_VAR_KEEP_ALIVE: {
 732                 u8 array[2];
 733
 734                 array[0] = 0xff;
 735                 array[1] = *((u8 *)val);
 736                 rtl88e_fill_h2c_cmd(hw, H2C_88E_KEEP_ALIVE_CTRL,
 737                                     2, array);
 738                 break; }
 739         default:
 740                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 741                          "switch case %#x not processed\n", variable);
 742                 break;
 743         }
 744 }
 745
 746 static bool _rtl88ee_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
 747 {
 748         struct rtl_priv *rtlpriv = rtl_priv(hw);
 749         bool status = true;
 750         long count = 0;
 751         u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
 752                     _LLT_OP(_LLT_WRITE_ACCESS);
 753
 754         rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
 755
 756         do {
 757                 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
 758                 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
 759                         break;
 760
 761                 if (count > POLLING_LLT_THRESHOLD) {
 762                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 763                                  "Failed to polling write LLT done at address %d!\n",
 764                                  address);
 765                         status = false;
 766                         break;
 767                 }
 768         } while (++count);
 769
 770         return status;
 771 }
 772
 773 static bool _rtl88ee_llt_table_init(struct ieee80211_hw *hw)
 774 {
 775         struct rtl_priv *rtlpriv = rtl_priv(hw);
 776         unsigned short i;
 777         u8 txpktbuf_bndy;
 778         u8 maxpage;
 779         bool status;
 780
 781         maxpage = 0xAF;
 782         txpktbuf_bndy = 0xAB;
 783
 784         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x01);
 785         rtl_write_dword(rtlpriv, REG_RQPN, 0x80730d29);
 786
 787         /*0x2600   MaxRxBuff=10k-max(TxReportSize(64*8), WOLPattern(16*24)) */
 788         rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x25FF0000 | txpktbuf_bndy));
 789         rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
 790
 791         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 792         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 793
 794         rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
 795         rtl_write_byte(rtlpriv, REG_PBP, 0x11);
 796         rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
 797
 798         for (i = 0; i < (txpktbuf_bndy - 1); i++) {
 799                 status = _rtl88ee_llt_write(hw, i, i + 1);
 800                 if (true != status)
 801                         return status;
 802         }
 803
 804         status = _rtl88ee_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
 805         if (true != status)
 806                 return status;
 807
 808         for (i = txpktbuf_bndy; i < maxpage; i++) {
 809                 status = _rtl88ee_llt_write(hw, i, (i + 1));
 810                 if (true != status)
 811                         return status;
 812         }
 813
 814         status = _rtl88ee_llt_write(hw, maxpage, txpktbuf_bndy);
 815         if (true != status)
 816                 return status;
 817
 818         return true;
 819 }
 820
 821 static void _rtl88ee_gen_refresh_led_state(struct ieee80211_hw *hw)
 822 {
 823         struct rtl_priv *rtlpriv = rtl_priv(hw);
 824         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 825         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 826         struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
 827
 828         if (rtlpriv->rtlhal.up_first_time)
 829                 return;
 830
 831         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 832                 rtl88ee_sw_led_on(hw, pLed0);
 833         else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
 834                 rtl88ee_sw_led_on(hw, pLed0);
 835         else
 836                 rtl88ee_sw_led_off(hw, pLed0);
 837 }
 838
 839 static bool _rtl88ee_init_mac(struct ieee80211_hw *hw)
 840 {
 841         struct rtl_priv *rtlpriv = rtl_priv(hw);
 842         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 843         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 844
 845         u8 bytetmp;
 846         u16 wordtmp;
 847
 848         /*Disable XTAL OUTPUT for power saving. YJ,add,111206. */
 849         bytetmp = rtl_read_byte(rtlpriv, REG_XCK_OUT_CTRL) & (~BIT(0));
 850         rtl_write_byte(rtlpriv, REG_XCK_OUT_CTRL, bytetmp);
 851         /*Auto Power Down to CHIP-off State*/
 852         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
 853         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
 854
 855         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
 856         /* HW Power on sequence */
 857         if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
 858                                       PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
 859                                       RTL8188EE_NIC_ENABLE_FLOW)) {
 860                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 861                          "init MAC Fail as rtl_hal_pwrseqcmdparsing\n");
 862                 return false;
 863         }
 864
 865         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
 866         rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
 867
 868         bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG+2);
 869         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+2, bytetmp|BIT(2));
 870
 871         bytetmp = rtl_read_byte(rtlpriv, REG_WATCH_DOG+1);
 872         rtl_write_byte(rtlpriv, REG_WATCH_DOG+1, bytetmp|BIT(7));
 873
 874         bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL_EXT+1);
 875         rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL_EXT+1, bytetmp|BIT(1));
 876
 877         bytetmp = rtl_read_byte(rtlpriv, REG_TX_RPT_CTRL);
 878         rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL, bytetmp|BIT(1)|BIT(0));
 879         rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL+1, 2);
 880         rtl_write_word(rtlpriv, REG_TX_RPT_TIME, 0xcdf0);
 881
 882         /*Add for wake up online*/
 883         bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
 884
 885         rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp|BIT(3));
 886         bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG+1);
 887         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+1, (bytetmp & (~BIT(4))));
 888         rtl_write_byte(rtlpriv, 0x367, 0x80);
 889
 890         rtl_write_word(rtlpriv, REG_CR, 0x2ff);
 891         rtl_write_byte(rtlpriv, REG_CR+1, 0x06);
 892         rtl_write_byte(rtlpriv, MSR, 0x00);
 893
 894         if (!rtlhal->mac_func_enable) {
 895                 if (_rtl88ee_llt_table_init(hw) == false) {
 896                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 897                                  "LLT table init fail\n");
 898                         return false;
 899                 }
 900         }
 901         rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
 902         rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
 903
 904         wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
 905         wordtmp &= 0xf;
 906         wordtmp |= 0xE771;
 907         rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
 908
 909         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
 910         rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xffff);
 911         rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
 912
 913         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
 914                         ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
 915                         DMA_BIT_MASK(32));
 916         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
 917                         (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
 918                         DMA_BIT_MASK(32));
 919         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
 920                         (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
 921         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
 922                         (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
 923         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
 924                         (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
 925         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
 926                         (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
 927         rtl_write_dword(rtlpriv, REG_HQ_DESA,
 928                         (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
 929                         DMA_BIT_MASK(32));
 930         rtl_write_dword(rtlpriv, REG_RX_DESA,
 931                         (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
 932                         DMA_BIT_MASK(32));
 933
 934         /* if we want to support 64 bit DMA, we should set it here,
 935          * but now we do not support 64 bit DMA
 936          */
 937         rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
 938
 939         rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
 940         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0);/*Enable RX DMA */
 941
 942         if (rtlhal->earlymode_enable) {/*Early mode enable*/
 943                 bytetmp = rtl_read_byte(rtlpriv, REG_EARLY_MODE_CONTROL);
 944                 bytetmp |= 0x1f;
 945                 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, bytetmp);
 946                 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL+3, 0x81);
 947         }
 948         _rtl88ee_gen_refresh_led_state(hw);
 949         return true;
 950 }
 951
 952 static void _rtl88ee_hw_configure(struct ieee80211_hw *hw)
 953 {
 954         struct rtl_priv *rtlpriv = rtl_priv(hw);
 955         u8 reg_bw_opmode;
 956         u32 reg_ratr, reg_prsr;
 957
 958         reg_bw_opmode = BW_OPMODE_20MHZ;
 959         reg_ratr = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
 960             RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
 961         reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 962
 963         rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
 964         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
 965 }
 966
 967 static void _rtl88ee_enable_aspm_back_door(struct ieee80211_hw *hw)
 968 {
 969         struct rtl_priv *rtlpriv = rtl_priv(hw);
 970         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 971         u8 tmp1byte = 0;
 972         u32 tmp4byte = 0, count = 0;
 973
 974         rtl_write_word(rtlpriv, 0x354, 0x8104);
 975         rtl_write_word(rtlpriv, 0x358, 0x24);
 976
 977         rtl_write_word(rtlpriv, 0x350, 0x70c);
 978         rtl_write_byte(rtlpriv, 0x352, 0x2);
 979         tmp1byte = rtl_read_byte(rtlpriv, 0x352);
 980         count = 0;
 981         while (tmp1byte && count < 20) {
 982                 udelay(10);
 983                 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
 984                 count++;
 985         }
 986         if (0 == tmp1byte) {
 987                 tmp4byte = rtl_read_dword(rtlpriv, 0x34c);
 988                 rtl_write_dword(rtlpriv, 0x348, tmp4byte|BIT(31));
 989                 rtl_write_word(rtlpriv, 0x350, 0xf70c);
 990                 rtl_write_byte(rtlpriv, 0x352, 0x1);
 991         }
 992
 993         tmp1byte = rtl_read_byte(rtlpriv, 0x352);
 994         count = 0;
 995         while (tmp1byte && count < 20) {
 996                 udelay(10);
 997                 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
 998                 count++;
 999         }
1000
1001         rtl_write_word(rtlpriv, 0x350, 0x718);
1002         rtl_write_byte(rtlpriv, 0x352, 0x2);
1003         tmp1byte = rtl_read_byte(rtlpriv, 0x352);
1004         count = 0;
1005         while (tmp1byte && count < 20) {
1006                 udelay(10);
1007                 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
1008                 count++;
1009         }
1010
1011         if (ppsc->support_backdoor || (0 == tmp1byte)) {
1012                 tmp4byte = rtl_read_dword(rtlpriv, 0x34c);
1013                 rtl_write_dword(rtlpriv, 0x348, tmp4byte|BIT(11)|BIT(12));
1014                 rtl_write_word(rtlpriv, 0x350, 0xf718);
1015                 rtl_write_byte(rtlpriv, 0x352, 0x1);
1016         }
1017
1018         tmp1byte = rtl_read_byte(rtlpriv, 0x352);
1019         count = 0;
1020         while (tmp1byte && count < 20) {
1021                 udelay(10);
1022                 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
1023                 count++;
1024         }
1025 }
1026
1027 void rtl88ee_enable_hw_security_config(struct ieee80211_hw *hw)
1028 {
1029         struct rtl_priv *rtlpriv = rtl_priv(hw);
1030         u8 sec_reg_value;
1031
1032         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1033                  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1034                   rtlpriv->sec.pairwise_enc_algorithm,
1035                   rtlpriv->sec.group_enc_algorithm);
1036
1037         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1038                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1039                          "not open hw encryption\n");
1040                 return;
1041         }
1042
1043         sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1044
1045         if (rtlpriv->sec.use_defaultkey) {
1046                 sec_reg_value |= SCR_TXUSEDK;
1047                 sec_reg_value |= SCR_RXUSEDK;
1048         }
1049
1050         sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1051
1052         rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1053
1054         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1055                  "The SECR-value %x\n", sec_reg_value);
1056
1057         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1058 }
1059
1060 int rtl88ee_hw_init(struct ieee80211_hw *hw)
1061 {
1062         struct rtl_priv *rtlpriv = rtl_priv(hw);
1063         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1064         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1065         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1066         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1067         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1068         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1069         bool rtstatus = true;
1070         int err = 0;
1071         u8 tmp_u1b, u1byte;
1072         unsigned long flags;
1073
1074         rtlpriv->rtlhal.being_init_adapter = true;
1075         /* As this function can take a very long time (up to 350 ms)
1076          * and can be called with irqs disabled, reenable the irqs
1077          * to let the other devices continue being serviced.
1078          *
1079          * It is safe doing so since our own interrupts will only be enabled
1080          * in a subsequent step.
1081          */
1082         local_save_flags(flags);
1083         local_irq_enable();
1084         rtlhal->fw_ready = false;
1085
1086         rtlpriv->intf_ops->disable_aspm(hw);
1087
1088         tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CLKR+1);
1089         u1byte = rtl_read_byte(rtlpriv, REG_CR);
1090         if ((tmp_u1b & BIT(3)) && (u1byte != 0 && u1byte != 0xEA)) {
1091                 rtlhal->mac_func_enable = true;
1092         } else {
1093                 rtlhal->mac_func_enable = false;
1094                 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_88E;
1095         }
1096
1097         rtstatus = _rtl88ee_init_mac(hw);
1098         if (rtstatus != true) {
1099                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
1100                 err = 1;
1101                 goto exit;
1102         }
1103
1104         err = rtl88e_download_fw(hw, false);
1105         if (err) {
1106                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1107                          "Failed to download FW. Init HW without FW now..\n");
1108                 err = 1;
1109                 goto exit;
1110         }
1111         rtlhal->fw_ready = true;
1112         /*fw related variable initialize */
1113         rtlhal->last_hmeboxnum = 0;
1114         rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_88E;
1115         rtlhal->fw_clk_change_in_progress = false;
1116         rtlhal->allow_sw_to_change_hwclc = false;
1117         ppsc->fw_current_inpsmode = false;
1118
1119         rtl88e_phy_mac_config(hw);
1120         /* because last function modify RCR, so we update
1121          * rcr var here, or TP will unstable for receive_config
1122          * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
1123          * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1124          */
1125         rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1126         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
1127
1128         rtl88e_phy_bb_config(hw);
1129         rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1130         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1131
1132         rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1133         rtl88e_phy_rf_config(hw);
1134
1135         rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1136                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1137         rtlphy->rfreg_chnlval[0] = rtlphy->rfreg_chnlval[0] & 0xfff00fff;
1138
1139         _rtl88ee_hw_configure(hw);
1140         rtl_cam_reset_all_entry(hw);
1141         rtl88ee_enable_hw_security_config(hw);
1142
1143         rtlhal->mac_func_enable = true;
1144         ppsc->rfpwr_state = ERFON;
1145
1146         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1147         _rtl88ee_enable_aspm_back_door(hw);
1148         rtlpriv->intf_ops->enable_aspm(hw);
1149
1150         if (ppsc->rfpwr_state == ERFON) {
1151                 if ((rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV) ||
1152                     ((rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) &&
1153                      (rtlhal->oem_id == RT_CID_819X_HP))) {
1154                         rtl88e_phy_set_rfpath_switch(hw, true);
1155                         rtlpriv->dm.fat_table.rx_idle_ant = MAIN_ANT;
1156                 } else {
1157                         rtl88e_phy_set_rfpath_switch(hw, false);
1158                         rtlpriv->dm.fat_table.rx_idle_ant = AUX_ANT;
1159                 }
1160                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rx idle ant %s\n",
1161                          (rtlpriv->dm.fat_table.rx_idle_ant == MAIN_ANT) ?
1162                          ("MAIN_ANT") : ("AUX_ANT"));
1163
1164                 if (rtlphy->iqk_initialized) {
1165                         rtl88e_phy_iq_calibrate(hw, true);
1166                 } else {
1167                         rtl88e_phy_iq_calibrate(hw, false);
1168                         rtlphy->iqk_initialized = true;
1169                 }
1170
1171                 rtl88e_dm_check_txpower_tracking(hw);
1172                 rtl88e_phy_lc_calibrate(hw);
1173         }
1174
1175         tmp_u1b = efuse_read_1byte(hw, 0x1FA);
1176         if (!(tmp_u1b & BIT(0))) {
1177                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
1178                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path A\n");
1179         }
1180
1181         if (!(tmp_u1b & BIT(4))) {
1182                 tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
1183                 tmp_u1b &= 0x0F;
1184                 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
1185                 udelay(10);
1186                 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
1187                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "under 1.5V\n");
1188         }
1189         rtl_write_byte(rtlpriv, REG_NAV_CTRL+2,  ((30000+127)/128));
1190         rtl88e_dm_init(hw);
1191 exit:
1192         local_irq_restore(flags);
1193         rtlpriv->rtlhal.being_init_adapter = false;
1194         return err;
1195 }
1196
1197 static enum version_8188e _rtl88ee_read_chip_version(struct ieee80211_hw *hw)
1198 {
1199         struct rtl_priv *rtlpriv = rtl_priv(hw);
1200         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1201         enum version_8188e version = VERSION_UNKNOWN;
1202         u32 value32;
1203
1204         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1205         if (value32 & TRP_VAUX_EN) {
1206                 version = (enum version_8188e) VERSION_TEST_CHIP_88E;
1207         } else {
1208                 version = NORMAL_CHIP;
1209                 version = version | ((value32 & TYPE_ID) ? RF_TYPE_2T2R : 0);
1210                 version = version | ((value32 & VENDOR_ID) ?
1211                           CHIP_VENDOR_UMC : 0);
1212         }
1213
1214         rtlphy->rf_type = RF_1T1R;
1215         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1216                  "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1217                  "RF_2T2R" : "RF_1T1R");
1218
1219         return version;
1220 }
1221
1222 static int _rtl88ee_set_media_status(struct ieee80211_hw *hw,
1223                                      enum nl80211_iftype type)
1224 {
1225         struct rtl_priv *rtlpriv = rtl_priv(hw);
1226         u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc;
1227         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1228         u8 mode = MSR_NOLINK;
1229
1230         switch (type) {
1231         case NL80211_IFTYPE_UNSPECIFIED:
1232                 mode = MSR_NOLINK;
1233                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1234                          "Set Network type to NO LINK!\n");
1235                 break;
1236         case NL80211_IFTYPE_ADHOC:
1237         case NL80211_IFTYPE_MESH_POINT:
1238                 mode = MSR_ADHOC;
1239                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1240                          "Set Network type to Ad Hoc!\n");
1241                 break;
1242         case NL80211_IFTYPE_STATION:
1243                 mode = MSR_INFRA;
1244                 ledaction = LED_CTL_LINK;
1245                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1246                          "Set Network type to STA!\n");
1247                 break;
1248         case NL80211_IFTYPE_AP:
1249                 mode = MSR_AP;
1250                 ledaction = LED_CTL_LINK;
1251                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1252                          "Set Network type to AP!\n");
1253                 break;
1254         default:
1255                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1256                          "Network type %d not support!\n", type);
1257                 return 1;
1258                 break;
1259         }
1260
1261         /* MSR_INFRA == Link in infrastructure network;
1262          * MSR_ADHOC == Link in ad hoc network;
1263          * Therefore, check link state is necessary.
1264          *
1265          * MSR_AP == AP mode; link state is not cared here.
1266          */
1267         if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1268                 mode = MSR_NOLINK;
1269                 ledaction = LED_CTL_NO_LINK;
1270         }
1271
1272         if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1273                 _rtl88ee_stop_tx_beacon(hw);
1274                 _rtl88ee_enable_bcn_sub_func(hw);
1275         } else if (mode == MSR_ADHOC || mode == MSR_AP) {
1276                 _rtl88ee_resume_tx_beacon(hw);
1277                 _rtl88ee_disable_bcn_sub_func(hw);
1278         } else {
1279                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1280                          "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1281                          mode);
1282         }
1283
1284         rtl_write_byte(rtlpriv, MSR, bt_msr | mode);
1285         rtlpriv->cfg->ops->led_control(hw, ledaction);
1286         if (mode == MSR_AP)
1287                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1288         else
1289                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1290         return 0;
1291 }
1292
1293 void rtl88ee_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1294 {
1295         struct rtl_priv *rtlpriv = rtl_priv(hw);
1296         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1297         u32 reg_rcr = rtlpci->receive_config;
1298
1299         if (rtlpriv->psc.rfpwr_state != ERFON)
1300                 return;
1301
1302         if (check_bssid == true) {
1303                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1304                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1305                                               (u8 *)(&reg_rcr));
1306                 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
1307         } else if (check_bssid == false) {
1308                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1309                 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
1310                 rtlpriv->cfg->ops->set_hw_reg(hw,
1311                         HW_VAR_RCR, (u8 *)(&reg_rcr));
1312         }
1313
1314 }
1315
1316 int rtl88ee_set_network_type(struct ieee80211_hw *hw,
1317                              enum nl80211_iftype type)
1318 {
1319         struct rtl_priv *rtlpriv = rtl_priv(hw);
1320
1321         if (_rtl88ee_set_media_status(hw, type))
1322                 return -EOPNOTSUPP;
1323
1324         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1325                 if (type != NL80211_IFTYPE_AP &&
1326                     type != NL80211_IFTYPE_MESH_POINT)
1327                         rtl88ee_set_check_bssid(hw, true);
1328         } else {
1329                 rtl88ee_set_check_bssid(hw, false);
1330         }
1331
1332         return 0;
1333 }
1334
1335 /* don't set REG_EDCA_BE_PARAM here
1336  * because mac80211 will send pkt when scan
1337  */
1338 void rtl88ee_set_qos(struct ieee80211_hw *hw, int aci)
1339 {
1340         struct rtl_priv *rtlpriv = rtl_priv(hw);
1341         rtl88e_dm_init_edca_turbo(hw);
1342         switch (aci) {
1343         case AC1_BK:
1344                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1345                 break;
1346         case AC0_BE:
1347                 break;
1348         case AC2_VI:
1349                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1350                 break;
1351         case AC3_VO:
1352                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1353                 break;
1354         default:
1355                 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1356                 break;
1357         }
1358 }
1359
1360 void rtl88ee_enable_interrupt(struct ieee80211_hw *hw)
1361 {
1362         struct rtl_priv *rtlpriv = rtl_priv(hw);
1363         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1364
1365         rtl_write_dword(rtlpriv, REG_HIMR,
1366                         rtlpci->irq_mask[0] & 0xFFFFFFFF);
1367         rtl_write_dword(rtlpriv, REG_HIMRE,
1368                         rtlpci->irq_mask[1] & 0xFFFFFFFF);
1369         rtlpci->irq_enabled = true;
1370         /* there are some C2H CMDs have been sent
1371          * before system interrupt is enabled, e.g., C2H, CPWM.
1372          * So we need to clear all C2H events that FW has notified,
1373          * otherwise FW won't schedule any commands anymore.
1374          */
1375         rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0);
1376         /*enable system interrupt*/
1377         rtl_write_dword(rtlpriv, REG_HSIMR,
1378                         rtlpci->sys_irq_mask & 0xFFFFFFFF);
1379 }
1380
1381 void rtl88ee_disable_interrupt(struct ieee80211_hw *hw)
1382 {
1383         struct rtl_priv *rtlpriv = rtl_priv(hw);
1384         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1385
1386         rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
1387         rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
1388         rtlpci->irq_enabled = false;
1389         /*synchronize_irq(rtlpci->pdev->irq);*/
1390 }
1391
1392 static void _rtl88ee_poweroff_adapter(struct ieee80211_hw *hw)
1393 {
1394         struct rtl_priv *rtlpriv = rtl_priv(hw);
1395         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1396         u8 u1b_tmp;
1397         u32 count = 0;
1398         rtlhal->mac_func_enable = false;
1399         rtlpriv->intf_ops->enable_aspm(hw);
1400
1401         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "POWER OFF adapter\n");
1402         u1b_tmp = rtl_read_byte(rtlpriv, REG_TX_RPT_CTRL);
1403         rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL, u1b_tmp & (~BIT(1)));
1404
1405         u1b_tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1406         while (!(u1b_tmp & BIT(1)) && (count++ < 100)) {
1407                 udelay(10);
1408                 u1b_tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1409                 count++;
1410         }
1411         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0xFF);
1412
1413         rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1414                                  PWR_INTF_PCI_MSK,
1415                                  RTL8188EE_NIC_LPS_ENTER_FLOW);
1416
1417         rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1418
1419         if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready)
1420                 rtl88e_firmware_selfreset(hw);
1421
1422         u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1423         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2))));
1424         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1425
1426         u1b_tmp = rtl_read_byte(rtlpriv, REG_32K_CTRL);
1427         rtl_write_byte(rtlpriv, REG_32K_CTRL, (u1b_tmp & (~BIT(0))));
1428
1429         rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1430                                  PWR_INTF_PCI_MSK, RTL8188EE_NIC_DISABLE_FLOW);
1431
1432         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);
1433         rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp & (~BIT(3))));
1434         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);
1435         rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp | BIT(3)));
1436
1437         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1438
1439         u1b_tmp = rtl_read_byte(rtlpriv, GPIO_IN);
1440         rtl_write_byte(rtlpriv, GPIO_OUT, u1b_tmp);
1441         rtl_write_byte(rtlpriv, GPIO_IO_SEL, 0x7F);
1442
1443         u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
1444         rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL, (u1b_tmp << 4) | u1b_tmp);
1445         u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL+1);
1446         rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL+1, u1b_tmp | 0x0F);
1447
1448         rtl_write_dword(rtlpriv, REG_GPIO_IO_SEL_2+2, 0x00080808);
1449 }
1450
1451 void rtl88ee_card_disable(struct ieee80211_hw *hw)
1452 {
1453         struct rtl_priv *rtlpriv = rtl_priv(hw);
1454         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1455         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1456         enum nl80211_iftype opmode;
1457
1458         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "RTL8188ee card disable\n");
1459
1460         mac->link_state = MAC80211_NOLINK;
1461         opmode = NL80211_IFTYPE_UNSPECIFIED;
1462
1463         _rtl88ee_set_media_status(hw, opmode);
1464
1465         if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1466             ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1467                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1468
1469         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1470         _rtl88ee_poweroff_adapter(hw);
1471
1472         /* after power off we should do iqk again */
1473         rtlpriv->phy.iqk_initialized = false;
1474 }
1475
1476 void rtl88ee_interrupt_recognized(struct ieee80211_hw *hw,
1477                                   u32 *p_inta, u32 *p_intb)
1478 {
1479         struct rtl_priv *rtlpriv = rtl_priv(hw);
1480         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1481
1482         *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1483         rtl_write_dword(rtlpriv, ISR, *p_inta);
1484
1485         *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1486         rtl_write_dword(rtlpriv, REG_HISRE, *p_intb);
1487
1488 }
1489
1490 void rtl88ee_set_beacon_related_registers(struct ieee80211_hw *hw)
1491 {
1492         struct rtl_priv *rtlpriv = rtl_priv(hw);
1493         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1494         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1495         u16 bcn_interval, atim_window;
1496
1497         bcn_interval = mac->beacon_interval;
1498         atim_window = 2;        /*FIX MERGE */
1499         rtl88ee_disable_interrupt(hw);
1500         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1501         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1502         rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1503         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1504         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1505         rtl_write_byte(rtlpriv, 0x606, 0x30);
1506         rtlpci->reg_bcn_ctrl_val |= BIT(3);
1507         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
1508         /*rtl88ee_enable_interrupt(hw);*/
1509 }
1510
1511 void rtl88ee_set_beacon_interval(struct ieee80211_hw *hw)
1512 {
1513         struct rtl_priv *rtlpriv = rtl_priv(hw);
1514         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1515         u16 bcn_interval = mac->beacon_interval;
1516
1517         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1518                  "beacon_interval:%d\n", bcn_interval);
1519         /*rtl88ee_disable_interrupt(hw);*/
1520         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1521         /*rtl88ee_enable_interrupt(hw);*/
1522 }
1523
1524 void rtl88ee_update_interrupt_mask(struct ieee80211_hw *hw,
1525                                    u32 add_msr, u32 rm_msr)
1526 {
1527         struct rtl_priv *rtlpriv = rtl_priv(hw);
1528         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1529
1530         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1531                  "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
1532
1533         if (add_msr)
1534                 rtlpci->irq_mask[0] |= add_msr;
1535         if (rm_msr)
1536                 rtlpci->irq_mask[0] &= (~rm_msr);
1537         rtl88ee_disable_interrupt(hw);
1538         rtl88ee_enable_interrupt(hw);
1539 }
1540
1541 static u8 _rtl88e_get_chnl_group(u8 chnl)
1542 {
1543         u8 group = 0;
1544
1545         if (chnl < 3)
1546                 group = 0;
1547         else if (chnl < 6)
1548                 group = 1;
1549         else if (chnl < 9)
1550                 group = 2;
1551         else if (chnl < 12)
1552                 group = 3;
1553         else if (chnl < 14)
1554                 group = 4;
1555         else if (chnl == 14)
1556                 group = 5;
1557
1558         return group;
1559 }
1560
1561 static void set_24g_base(struct txpower_info_2g *pwrinfo24g, u32 rfpath)
1562 {
1563         int group, txcnt;
1564
1565         for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1566                 pwrinfo24g->index_cck_base[rfpath][group] = 0x2D;
1567                 pwrinfo24g->index_bw40_base[rfpath][group] = 0x2D;
1568         }
1569         for (txcnt = 0; txcnt < MAX_TX_COUNT; txcnt++) {
1570                 if (txcnt == 0) {
1571                         pwrinfo24g->bw20_diff[rfpath][0] = 0x02;
1572                         pwrinfo24g->ofdm_diff[rfpath][0] = 0x04;
1573                 } else {
1574                         pwrinfo24g->bw20_diff[rfpath][txcnt] = 0xFE;
1575                         pwrinfo24g->bw40_diff[rfpath][txcnt] = 0xFE;
1576                         pwrinfo24g->cck_diff[rfpath][txcnt] =   0xFE;
1577                         pwrinfo24g->ofdm_diff[rfpath][txcnt] = 0xFE;
1578                 }
1579         }
1580 }
1581
1582 static void read_power_value_fromprom(struct ieee80211_hw *hw,
1583                                       struct txpower_info_2g *pwrinfo24g,
1584                                       struct txpower_info_5g *pwrinfo5g,
1585                                       bool autoload_fail, u8 *hwinfo)
1586 {
1587         struct rtl_priv *rtlpriv = rtl_priv(hw);
1588         u32 rfpath, eeaddr = EEPROM_TX_PWR_INX, group, txcnt = 0;
1589
1590         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1591                  "hal_ReadPowerValueFromPROM88E():PROMContent[0x%x]=0x%x\n",
1592                  (eeaddr+1), hwinfo[eeaddr+1]);
1593         if (0xFF == hwinfo[eeaddr+1])  /*YJ,add,120316*/
1594                 autoload_fail = true;
1595
1596         if (autoload_fail) {
1597                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1598                          "auto load fail : Use Default value!\n");
1599                 for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) {
1600                         /* 2.4G default value */
1601                         set_24g_base(pwrinfo24g, rfpath);
1602                 }
1603                 return;
1604         }
1605
1606         for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) {
1607                 /*2.4G default value*/
1608                 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1609                         pwrinfo24g->index_cck_base[rfpath][group] =
1610                           hwinfo[eeaddr++];
1611                         if (pwrinfo24g->index_cck_base[rfpath][group] == 0xFF)
1612                                 pwrinfo24g->index_cck_base[rfpath][group] =
1613                                   0x2D;
1614                 }
1615                 for (group = 0 ; group < MAX_CHNL_GROUP_24G-1; group++) {
1616                         pwrinfo24g->index_bw40_base[rfpath][group] =
1617                                 hwinfo[eeaddr++];
1618                         if (pwrinfo24g->index_bw40_base[rfpath][group] == 0xFF)
1619                                 pwrinfo24g->index_bw40_base[rfpath][group] =
1620                                         0x2D;
1621                 }
1622                 pwrinfo24g->bw40_diff[rfpath][0] = 0;
1623                 if (hwinfo[eeaddr] == 0xFF) {
1624                         pwrinfo24g->bw20_diff[rfpath][0] = 0x02;
1625                 } else {
1626                         pwrinfo24g->bw20_diff[rfpath][0] =
1627                                 (hwinfo[eeaddr]&0xf0)>>4;
1628                         /*bit sign number to 8 bit sign number*/
1629                         if (pwrinfo24g->bw20_diff[rfpath][0] & BIT(3))
1630                                 pwrinfo24g->bw20_diff[rfpath][0] |= 0xF0;
1631                 }
1632
1633                 if (hwinfo[eeaddr] == 0xFF) {
1634                         pwrinfo24g->ofdm_diff[rfpath][0] = 0x04;
1635                 } else {
1636                         pwrinfo24g->ofdm_diff[rfpath][0] =
1637                                 (hwinfo[eeaddr]&0x0f);
1638                                 /*bit sign number to 8 bit sign number*/
1639                         if (pwrinfo24g->ofdm_diff[rfpath][0] & BIT(3))
1640                                 pwrinfo24g->ofdm_diff[rfpath][0] |= 0xF0;
1641                 }
1642                 pwrinfo24g->cck_diff[rfpath][0] = 0;
1643                 eeaddr++;
1644                 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) {
1645                         if (hwinfo[eeaddr] == 0xFF) {
1646                                 pwrinfo24g->bw40_diff[rfpath][txcnt] = 0xFE;
1647                         } else {
1648                                 pwrinfo24g->bw40_diff[rfpath][txcnt] =
1649                                   (hwinfo[eeaddr]&0xf0)>>4;
1650                                 if (pwrinfo24g->bw40_diff[rfpath][txcnt] &
1651                                     BIT(3))
1652                                         pwrinfo24g->bw40_diff[rfpath][txcnt] |=
1653                                           0xF0;
1654                         }
1655
1656                         if (hwinfo[eeaddr] == 0xFF) {
1657                                 pwrinfo24g->bw20_diff[rfpath][txcnt] =
1658                                         0xFE;
1659                         } else {
1660                                 pwrinfo24g->bw20_diff[rfpath][txcnt] =
1661                                   (hwinfo[eeaddr]&0x0f);
1662                                 if (pwrinfo24g->bw20_diff[rfpath][txcnt] &
1663                                     BIT(3))
1664                                         pwrinfo24g->bw20_diff[rfpath][txcnt] |=
1665                                           0xF0;
1666                         }
1667                         eeaddr++;
1668
1669                         if (hwinfo[eeaddr] == 0xFF) {
1670                                 pwrinfo24g->ofdm_diff[rfpath][txcnt] = 0xFE;
1671                         } else {
1672                                 pwrinfo24g->ofdm_diff[rfpath][txcnt] =
1673                                   (hwinfo[eeaddr]&0xf0)>>4;
1674                                 if (pwrinfo24g->ofdm_diff[rfpath][txcnt] &
1675                                     BIT(3))
1676                                         pwrinfo24g->ofdm_diff[rfpath][txcnt] |=
1677                                           0xF0;
1678                         }
1679
1680                         if (hwinfo[eeaddr] == 0xFF) {
1681                                 pwrinfo24g->cck_diff[rfpath][txcnt] =   0xFE;
1682                         } else {
1683                                 pwrinfo24g->cck_diff[rfpath][txcnt] =
1684                                   (hwinfo[eeaddr]&0x0f);
1685                                 if (pwrinfo24g->cck_diff[rfpath][txcnt] &
1686                                     BIT(3))
1687                                         pwrinfo24g->cck_diff[rfpath][txcnt] |=
1688                                           0xF0;
1689                         }
1690                         eeaddr++;
1691                 }
1692
1693                 /*5G default value*/
1694                 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) {
1695                         pwrinfo5g->index_bw40_base[rfpath][group] =
1696                                 hwinfo[eeaddr++];
1697                         if (pwrinfo5g->index_bw40_base[rfpath][group] == 0xFF)
1698                                 pwrinfo5g->index_bw40_base[rfpath][group] =
1699                                   0xFE;
1700                 }
1701
1702                 pwrinfo5g->bw40_diff[rfpath][0] = 0;
1703
1704                 if (hwinfo[eeaddr] == 0xFF) {
1705                         pwrinfo5g->bw20_diff[rfpath][0] = 0;
1706                 } else {
1707                         pwrinfo5g->bw20_diff[rfpath][0] =
1708                           (hwinfo[eeaddr]&0xf0)>>4;
1709                         if (pwrinfo5g->bw20_diff[rfpath][0] & BIT(3))
1710                                 pwrinfo5g->bw20_diff[rfpath][0] |= 0xF0;
1711                 }
1712
1713                 if (hwinfo[eeaddr] == 0xFF) {
1714                         pwrinfo5g->ofdm_diff[rfpath][0] = 0x04;
1715                 } else {
1716                         pwrinfo5g->ofdm_diff[rfpath][0] = (hwinfo[eeaddr]&0x0f);
1717                         if (pwrinfo5g->ofdm_diff[rfpath][0] & BIT(3))
1718                                 pwrinfo5g->ofdm_diff[rfpath][0] |= 0xF0;
1719                 }
1720                 eeaddr++;
1721                 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) {
1722                         if (hwinfo[eeaddr] == 0xFF) {
1723                                 pwrinfo5g->bw40_diff[rfpath][txcnt] =   0xFE;
1724                         } else {
1725                                 pwrinfo5g->bw40_diff[rfpath][txcnt] =
1726                                   (hwinfo[eeaddr]&0xf0)>>4;
1727                                 if (pwrinfo5g->bw40_diff[rfpath][txcnt] &
1728                                     BIT(3))
1729                                         pwrinfo5g->bw40_diff[rfpath][txcnt] |=
1730                                           0xF0;
1731                         }
1732
1733                         if (hwinfo[eeaddr] == 0xFF) {
1734                                 pwrinfo5g->bw20_diff[rfpath][txcnt] =   0xFE;
1735                         } else {
1736                                 pwrinfo5g->bw20_diff[rfpath][txcnt] =
1737                                   (hwinfo[eeaddr]&0x0f);
1738                                 if (pwrinfo5g->bw20_diff[rfpath][txcnt] &
1739                                     BIT(3))
1740                                         pwrinfo5g->bw20_diff[rfpath][txcnt] |=
1741                                           0xF0;
1742                         }
1743                         eeaddr++;
1744                 }
1745
1746                 if (hwinfo[eeaddr] == 0xFF) {
1747                         pwrinfo5g->ofdm_diff[rfpath][1] = 0xFE;
1748                         pwrinfo5g->ofdm_diff[rfpath][2] = 0xFE;
1749                 } else {
1750                         pwrinfo5g->ofdm_diff[rfpath][1] =
1751                                         (hwinfo[eeaddr]&0xf0)>>4;
1752                         pwrinfo5g->ofdm_diff[rfpath][2] =
1753                                         (hwinfo[eeaddr]&0x0f);
1754                 }
1755                 eeaddr++;
1756
1757                 if (hwinfo[eeaddr] == 0xFF)
1758                         pwrinfo5g->ofdm_diff[rfpath][3] = 0xFE;
1759                 else
1760                         pwrinfo5g->ofdm_diff[rfpath][3] = (hwinfo[eeaddr]&0x0f);
1761                 eeaddr++;
1762
1763                 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) {
1764                         if (pwrinfo5g->ofdm_diff[rfpath][txcnt] == 0xFF)
1765                                 pwrinfo5g->ofdm_diff[rfpath][txcnt] =   0xFE;
1766                         else if (pwrinfo5g->ofdm_diff[rfpath][txcnt] & BIT(3))
1767                                 pwrinfo5g->ofdm_diff[rfpath][txcnt] |= 0xF0;
1768                 }
1769         }
1770 }
1771
1772 static void _rtl88ee_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1773                                                  bool autoload_fail,
1774                                                  u8 *hwinfo)
1775 {
1776         struct rtl_priv *rtlpriv = rtl_priv(hw);
1777         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1778         struct txpower_info_2g pwrinfo24g;
1779         struct txpower_info_5g pwrinfo5g;
1780         u8 rf_path, index;
1781         u8 i;
1782
1783         read_power_value_fromprom(hw, &pwrinfo24g,
1784                                   &pwrinfo5g, autoload_fail, hwinfo);
1785
1786         for (rf_path = 0; rf_path < 2; rf_path++) {
1787                 for (i = 0; i < 14; i++) {
1788                         index = _rtl88e_get_chnl_group(i+1);
1789
1790                         rtlefuse->txpwrlevel_cck[rf_path][i] =
1791                                 pwrinfo24g.index_cck_base[rf_path][index];
1792                         rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1793                                 pwrinfo24g.index_bw40_base[rf_path][index];
1794                         rtlefuse->txpwr_ht20diff[rf_path][i] =
1795                                 pwrinfo24g.bw20_diff[rf_path][0];
1796                         rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
1797                                 pwrinfo24g.ofdm_diff[rf_path][0];
1798                 }
1799
1800                 for (i = 0; i < 14; i++) {
1801                         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1802                                 "RF(%d)-Ch(%d) [CCK / HT40_1S ] = [0x%x / 0x%x ]\n",
1803                                 rf_path, i,
1804                                 rtlefuse->txpwrlevel_cck[rf_path][i],
1805                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i]);
1806                 }
1807         }
1808
1809         if (!autoload_fail)
1810                 rtlefuse->eeprom_thermalmeter =
1811                         hwinfo[EEPROM_THERMAL_METER_88E];
1812         else
1813                 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1814
1815         if (rtlefuse->eeprom_thermalmeter == 0xff || autoload_fail) {
1816                 rtlefuse->apk_thermalmeterignore = true;
1817                 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1818         }
1819
1820         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1821         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1822                 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1823
1824         if (!autoload_fail) {
1825                 rtlefuse->eeprom_regulatory =
1826                         hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0x07;/*bit0~2*/
1827                 if (hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
1828                         rtlefuse->eeprom_regulatory = 0;
1829         } else {
1830                 rtlefuse->eeprom_regulatory = 0;
1831         }
1832         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1833                 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1834 }
1835
1836 static void _rtl88ee_read_adapter_info(struct ieee80211_hw *hw)
1837 {
1838         struct rtl_priv *rtlpriv = rtl_priv(hw);
1839         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1840         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1841         int params[] = {RTL8188E_EEPROM_ID, EEPROM_VID, EEPROM_DID,
1842                         EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
1843                         EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
1844                         COUNTRY_CODE_WORLD_WIDE_13};
1845         u8 *hwinfo;
1846
1847         hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
1848         if (!hwinfo)
1849                 return;
1850
1851         if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
1852                 goto exit;
1853
1854         if (rtlefuse->eeprom_oemid == 0xFF)
1855                 rtlefuse->eeprom_oemid = 0;
1856
1857         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1858                  "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
1859         /* set channel plan from efuse */
1860         rtlefuse->channel_plan = rtlefuse->eeprom_channelplan;
1861         /*tx power*/
1862         _rtl88ee_read_txpower_info_from_hwpg(hw,
1863                                              rtlefuse->autoload_failflag,
1864                                              hwinfo);
1865         rtlefuse->txpwr_fromeprom = true;
1866
1867         rtl8188ee_read_bt_coexist_info_from_hwpg(hw,
1868                                                  rtlefuse->autoload_failflag,
1869                                                  hwinfo);
1870
1871         /*board type*/
1872         rtlefuse->board_type =
1873                 ((hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0xE0) >> 5);
1874         rtlhal->board_type = rtlefuse->board_type;
1875         /*Wake on wlan*/
1876         rtlefuse->wowlan_enable =
1877                 ((hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & 0x40) >> 6);
1878         /*parse xtal*/
1879         rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_88E];
1880         if (hwinfo[EEPROM_XTAL_88E])
1881                 rtlefuse->crystalcap = 0x20;
1882         /*antenna diversity*/
1883         rtlefuse->antenna_div_cfg =
1884                 (hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0x18) >> 3;
1885         if (hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
1886                 rtlefuse->antenna_div_cfg = 0;
1887         if (rtlpriv->btcoexist.eeprom_bt_coexist != 0 &&
1888             rtlpriv->btcoexist.eeprom_bt_ant_num == ANT_X1)
1889                 rtlefuse->antenna_div_cfg = 0;
1890
1891         rtlefuse->antenna_div_type = hwinfo[EEPROM_RF_ANTENNA_OPT_88E];
1892         if (rtlefuse->antenna_div_type == 0xFF)
1893                 rtlefuse->antenna_div_type = 0x01;
1894         if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV ||
1895                 rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)
1896                 rtlefuse->antenna_div_cfg = 1;
1897
1898         if (rtlhal->oem_id == RT_CID_DEFAULT) {
1899                 switch (rtlefuse->eeprom_oemid) {
1900                 case EEPROM_CID_DEFAULT:
1901                         if (rtlefuse->eeprom_did == 0x8179) {
1902                                 if (rtlefuse->eeprom_svid == 0x1025) {
1903                                         rtlhal->oem_id = RT_CID_819X_ACER;
1904                                 } else if ((rtlefuse->eeprom_svid == 0x10EC &&
1905                                      rtlefuse->eeprom_smid == 0x0179) ||
1906                                      (rtlefuse->eeprom_svid == 0x17AA &&
1907                                      rtlefuse->eeprom_smid == 0x0179)) {
1908                                         rtlhal->oem_id = RT_CID_819X_LENOVO;
1909                                 } else if (rtlefuse->eeprom_svid == 0x103c &&
1910                                            rtlefuse->eeprom_smid == 0x197d) {
1911                                         rtlhal->oem_id = RT_CID_819X_HP;
1912                                 } else {
1913                                         rtlhal->oem_id = RT_CID_DEFAULT;
1914                                 }
1915                         } else {
1916                                 rtlhal->oem_id = RT_CID_DEFAULT;
1917                         }
1918                         break;
1919                 case EEPROM_CID_TOSHIBA:
1920                         rtlhal->oem_id = RT_CID_TOSHIBA;
1921                         break;
1922                 case EEPROM_CID_QMI:
1923                         rtlhal->oem_id = RT_CID_819X_QMI;
1924                         break;
1925                 case EEPROM_CID_WHQL:
1926                 default:
1927                         rtlhal->oem_id = RT_CID_DEFAULT;
1928                         break;
1929
1930                 }
1931         }
1932 exit:
1933         kfree(hwinfo);
1934 }
1935
1936 static void _rtl88ee_hal_customized_behavior(struct ieee80211_hw *hw)
1937 {
1938         struct rtl_priv *rtlpriv = rtl_priv(hw);
1939         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1940         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1941
1942         pcipriv->ledctl.led_opendrain = true;
1943
1944         switch (rtlhal->oem_id) {
1945         case RT_CID_819X_HP:
1946                 pcipriv->ledctl.led_opendrain = true;
1947                 break;
1948         case RT_CID_819X_LENOVO:
1949         case RT_CID_DEFAULT:
1950         case RT_CID_TOSHIBA:
1951         case RT_CID_CCX:
1952         case RT_CID_819X_ACER:
1953         case RT_CID_WHQL:
1954         default:
1955                 break;
1956         }
1957         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1958                  "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
1959 }
1960
1961 void rtl88ee_read_eeprom_info(struct ieee80211_hw *hw)
1962 {
1963         struct rtl_priv *rtlpriv = rtl_priv(hw);
1964         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1965         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1966         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1967         u8 tmp_u1b;
1968
1969         rtlhal->version = _rtl88ee_read_chip_version(hw);
1970         if (get_rf_type(rtlphy) == RF_1T1R)
1971                 rtlpriv->dm.rfpath_rxenable[0] = true;
1972         else
1973                 rtlpriv->dm.rfpath_rxenable[0] =
1974                     rtlpriv->dm.rfpath_rxenable[1] = true;
1975         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
1976                                                 rtlhal->version);
1977         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1978         if (tmp_u1b & BIT(4)) {
1979                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1980                 rtlefuse->epromtype = EEPROM_93C46;
1981         } else {
1982                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1983                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1984         }
1985         if (tmp_u1b & BIT(5)) {
1986                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1987                 rtlefuse->autoload_failflag = false;
1988                 _rtl88ee_read_adapter_info(hw);
1989         } else {
1990                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
1991         }
1992         _rtl88ee_hal_customized_behavior(hw);
1993 }
1994
1995 static void rtl88ee_update_hal_rate_table(struct ieee80211_hw *hw,
1996                 struct ieee80211_sta *sta)
1997 {
1998         struct rtl_priv *rtlpriv = rtl_priv(hw);
1999         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2000         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2001         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2002         u32 ratr_value;
2003         u8 ratr_index = 0;
2004         u8 b_nmode = mac->ht_enable;
2005         /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/
2006         u16 shortgi_rate;
2007         u32 tmp_ratr_value;
2008         u8 curtxbw_40mhz = mac->bw_40;
2009         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2010                                 1 : 0;
2011         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2012                                 1 : 0;
2013         enum wireless_mode wirelessmode = mac->mode;
2014         u32 ratr_mask;
2015
2016         if (rtlhal->current_bandtype == BAND_ON_5G)
2017                 ratr_value = sta->supp_rates[1] << 4;
2018         else
2019                 ratr_value = sta->supp_rates[0];
2020         if (mac->opmode == NL80211_IFTYPE_ADHOC)
2021                 ratr_value = 0xfff;
2022         ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2023                        sta->ht_cap.mcs.rx_mask[0] << 12);
2024         switch (wirelessmode) {
2025         case WIRELESS_MODE_B:
2026                 if (ratr_value & 0x0000000c)
2027                         ratr_value &= 0x0000000d;
2028                 else
2029                         ratr_value &= 0x0000000f;
2030                 break;
2031         case WIRELESS_MODE_G:
2032                 ratr_value &= 0x00000FF5;
2033                 break;
2034         case WIRELESS_MODE_N_24G:
2035         case WIRELESS_MODE_N_5G:
2036                 b_nmode = 1;
2037                 if (get_rf_type(rtlphy) == RF_1T2R ||
2038                     get_rf_type(rtlphy) == RF_1T1R)
2039                         ratr_mask = 0x000ff005;
2040                 else
2041                         ratr_mask = 0x0f0ff005;
2042
2043                 ratr_value &= ratr_mask;
2044                 break;
2045         default:
2046                 if (rtlphy->rf_type == RF_1T2R)
2047                         ratr_value &= 0x000ff0ff;
2048                 else
2049                         ratr_value &= 0x0f0ff0ff;
2050
2051                 break;
2052         }
2053
2054         if ((rtlpriv->btcoexist.bt_coexistence) &&
2055             (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
2056             (rtlpriv->btcoexist.bt_cur_state) &&
2057             (rtlpriv->btcoexist.bt_ant_isolation) &&
2058             ((rtlpriv->btcoexist.bt_service == BT_SCO) ||
2059              (rtlpriv->btcoexist.bt_service == BT_BUSY)))
2060                 ratr_value &= 0x0fffcfc0;
2061         else
2062                 ratr_value &= 0x0FFFFFFF;
2063
2064         if (b_nmode &&
2065             ((curtxbw_40mhz && curshortgi_40mhz) ||
2066              (!curtxbw_40mhz && curshortgi_20mhz))) {
2067                 ratr_value |= 0x10000000;
2068                 tmp_ratr_value = (ratr_value >> 12);
2069
2070                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2071                         if ((1 << shortgi_rate) & tmp_ratr_value)
2072                                 break;
2073                 }
2074
2075                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2076                     (shortgi_rate << 4) | (shortgi_rate);
2077         }
2078
2079         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
2080
2081         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2082                  "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
2083 }
2084
2085 static void rtl88ee_update_hal_rate_mask(struct ieee80211_hw *hw,
2086                 struct ieee80211_sta *sta, u8 rssi_level)
2087 {
2088         struct rtl_priv *rtlpriv = rtl_priv(hw);
2089         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2090         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2091         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2092         struct rtl_sta_info *sta_entry = NULL;
2093         u32 ratr_bitmap;
2094         u8 ratr_index;
2095         u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
2096                                 ? 1 : 0;
2097         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2098                                 1 : 0;
2099         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2100                                 1 : 0;
2101         enum wireless_mode wirelessmode = 0;
2102         bool b_shortgi = false;
2103         u8 rate_mask[5];
2104         u8 macid = 0;
2105         /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/
2106
2107         sta_entry = (struct rtl_sta_info *)sta->drv_priv;
2108         wirelessmode = sta_entry->wireless_mode;
2109         if (mac->opmode == NL80211_IFTYPE_STATION ||
2110                 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2111                 curtxbw_40mhz = mac->bw_40;
2112         else if (mac->opmode == NL80211_IFTYPE_AP ||
2113                 mac->opmode == NL80211_IFTYPE_ADHOC)
2114                 macid = sta->aid + 1;
2115
2116         if (rtlhal->current_bandtype == BAND_ON_5G)
2117                 ratr_bitmap = sta->supp_rates[1] << 4;
2118         else
2119                 ratr_bitmap = sta->supp_rates[0];
2120         if (mac->opmode == NL80211_IFTYPE_ADHOC)
2121                 ratr_bitmap = 0xfff;
2122         ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2123                         sta->ht_cap.mcs.rx_mask[0] << 12);
2124         switch (wirelessmode) {
2125         case WIRELESS_MODE_B:
2126                 ratr_index = RATR_INX_WIRELESS_B;
2127                 if (ratr_bitmap & 0x0000000c)
2128                         ratr_bitmap &= 0x0000000d;
2129                 else
2130                         ratr_bitmap &= 0x0000000f;
2131                 break;
2132         case WIRELESS_MODE_G:
2133                 ratr_index = RATR_INX_WIRELESS_GB;
2134
2135                 if (rssi_level == 1)
2136                         ratr_bitmap &= 0x00000f00;
2137                 else if (rssi_level == 2)
2138                         ratr_bitmap &= 0x00000ff0;
2139                 else
2140                         ratr_bitmap &= 0x00000ff5;
2141                 break;
2142         case WIRELESS_MODE_N_24G:
2143         case WIRELESS_MODE_N_5G:
2144                 ratr_index = RATR_INX_WIRELESS_NGB;
2145                 if (rtlphy->rf_type == RF_1T2R ||
2146                     rtlphy->rf_type == RF_1T1R) {
2147                         if (curtxbw_40mhz) {
2148                                 if (rssi_level == 1)
2149                                         ratr_bitmap &= 0x000f0000;
2150                                 else if (rssi_level == 2)
2151                                         ratr_bitmap &= 0x000ff000;
2152                                 else
2153                                         ratr_bitmap &= 0x000ff015;
2154                         } else {
2155                                 if (rssi_level == 1)
2156                                         ratr_bitmap &= 0x000f0000;
2157                                 else if (rssi_level == 2)
2158                                         ratr_bitmap &= 0x000ff000;
2159                                 else
2160                                         ratr_bitmap &= 0x000ff005;
2161                         }
2162                 } else {
2163                         if (curtxbw_40mhz) {
2164                                 if (rssi_level == 1)
2165                                         ratr_bitmap &= 0x0f8f0000;
2166                                 else if (rssi_level == 2)
2167                                         ratr_bitmap &= 0x0f8ff000;
2168                                 else
2169                                         ratr_bitmap &= 0x0f8ff015;
2170                         } else {
2171                                 if (rssi_level == 1)
2172                                         ratr_bitmap &= 0x0f8f0000;
2173                                 else if (rssi_level == 2)
2174                                         ratr_bitmap &= 0x0f8ff000;
2175                                 else
2176                                         ratr_bitmap &= 0x0f8ff005;
2177                         }
2178                 }
2179                 /*}*/
2180
2181                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2182                     (!curtxbw_40mhz && curshortgi_20mhz)) {
2183
2184                         if (macid == 0)
2185                                 b_shortgi = true;
2186                         else if (macid == 1)
2187                                 b_shortgi = false;
2188                 }
2189                 break;
2190         default:
2191                 ratr_index = RATR_INX_WIRELESS_NGB;
2192
2193                 if (rtlphy->rf_type == RF_1T2R)
2194                         ratr_bitmap &= 0x000ff0ff;
2195                 else
2196                         ratr_bitmap &= 0x0f0ff0ff;
2197                 break;
2198         }
2199         sta_entry->ratr_index = ratr_index;
2200
2201         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2202                  "ratr_bitmap :%x\n", ratr_bitmap);
2203         *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2204                              (ratr_index << 28);
2205         rate_mask[4] = macid | (b_shortgi ? 0x20 : 0x00) | 0x80;
2206         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2207                  "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x\n",
2208                  ratr_index, ratr_bitmap,
2209                  rate_mask[0], rate_mask[1],
2210                  rate_mask[2], rate_mask[3],
2211                  rate_mask[4]);
2212         rtl88e_fill_h2c_cmd(hw, H2C_88E_RA_MASK, 5, rate_mask);
2213         _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
2214 }
2215
2216 void rtl88ee_update_hal_rate_tbl(struct ieee80211_hw *hw,
2217                 struct ieee80211_sta *sta, u8 rssi_level)
2218 {
2219         struct rtl_priv *rtlpriv = rtl_priv(hw);
2220
2221         if (rtlpriv->dm.useramask)
2222                 rtl88ee_update_hal_rate_mask(hw, sta, rssi_level);
2223         else
2224                 rtl88ee_update_hal_rate_table(hw, sta);
2225 }
2226
2227 void rtl88ee_update_channel_access_setting(struct ieee80211_hw *hw)
2228 {
2229         struct rtl_priv *rtlpriv = rtl_priv(hw);
2230         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2231         u16 sifs_timer;
2232
2233         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, &mac->slot_time);
2234         if (!mac->ht_enable)
2235                 sifs_timer = 0x0a0a;
2236         else
2237                 sifs_timer = 0x0e0e;
2238         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2239 }
2240
2241 bool rtl88ee_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2242 {
2243         struct rtl_priv *rtlpriv = rtl_priv(hw);
2244         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2245         enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
2246         u32 u4tmp;
2247         bool b_actuallyset = false;
2248
2249         if (rtlpriv->rtlhal.being_init_adapter)
2250                 return false;
2251
2252         if (ppsc->swrf_processing)
2253                 return false;
2254
2255         spin_lock(&rtlpriv->locks.rf_ps_lock);
2256         if (ppsc->rfchange_inprogress) {
2257                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2258                 return false;
2259         } else {
2260                 ppsc->rfchange_inprogress = true;
2261                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2262         }
2263
2264         cur_rfstate = ppsc->rfpwr_state;
2265
2266         u4tmp = rtl_read_dword(rtlpriv, REG_GPIO_OUTPUT);
2267         e_rfpowerstate_toset = (u4tmp & BIT(31)) ? ERFON : ERFOFF;
2268
2269         if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) {
2270                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2271                          "GPIOChangeRF  - HW Radio ON, RF ON\n");
2272
2273                 e_rfpowerstate_toset = ERFON;
2274                 ppsc->hwradiooff = false;
2275                 b_actuallyset = true;
2276         } else if ((!ppsc->hwradiooff) &&
2277                    (e_rfpowerstate_toset == ERFOFF)) {
2278                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2279                          "GPIOChangeRF  - HW Radio OFF, RF OFF\n");
2280
2281                 e_rfpowerstate_toset = ERFOFF;
2282                 ppsc->hwradiooff = true;
2283                 b_actuallyset = true;
2284         }
2285
2286         if (b_actuallyset) {
2287                 spin_lock(&rtlpriv->locks.rf_ps_lock);
2288                 ppsc->rfchange_inprogress = false;
2289                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2290         } else {
2291                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2292                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2293
2294                 spin_lock(&rtlpriv->locks.rf_ps_lock);
2295                 ppsc->rfchange_inprogress = false;
2296                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2297         }
2298
2299         *valid = 1;
2300         return !ppsc->hwradiooff;
2301
2302 }
2303
2304 void rtl88ee_set_key(struct ieee80211_hw *hw, u32 key_index,
2305                      u8 *p_macaddr, bool is_group, u8 enc_algo,
2306                      bool is_wepkey, bool clear_all)
2307 {
2308         struct rtl_priv *rtlpriv = rtl_priv(hw);
2309         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2310         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2311         u8 *macaddr = p_macaddr;
2312         u32 entry_id = 0;
2313         bool is_pairwise = false;
2314         static u8 cam_const_addr[4][6] = {
2315                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2316                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2317                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2318                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2319         };
2320         static u8 cam_const_broad[] = {
2321                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2322         };
2323
2324         if (clear_all) {
2325                 u8 idx = 0;
2326                 u8 cam_offset = 0;
2327                 u8 clear_number = 5;
2328
2329                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2330
2331                 for (idx = 0; idx < clear_number; idx++) {
2332                         rtl_cam_mark_invalid(hw, cam_offset + idx);
2333                         rtl_cam_empty_entry(hw, cam_offset + idx);
2334
2335                         if (idx < 5) {
2336                                 memset(rtlpriv->sec.key_buf[idx], 0,
2337                                        MAX_KEY_LEN);
2338                                 rtlpriv->sec.key_len[idx] = 0;
2339                         }
2340                 }
2341
2342         } else {
2343                 switch (enc_algo) {
2344                 case WEP40_ENCRYPTION:
2345                         enc_algo = CAM_WEP40;
2346                         break;
2347                 case WEP104_ENCRYPTION:
2348                         enc_algo = CAM_WEP104;
2349                         break;
2350                 case TKIP_ENCRYPTION:
2351                         enc_algo = CAM_TKIP;
2352                         break;
2353                 case AESCCMP_ENCRYPTION:
2354                         enc_algo = CAM_AES;
2355                         break;
2356                 default:
2357                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2358                                  "switch case %#x not processed\n", enc_algo);
2359                         enc_algo = CAM_TKIP;
2360                         break;
2361                 }
2362
2363                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2364                         macaddr = cam_const_addr[key_index];
2365                         entry_id = key_index;
2366                 } else {
2367                         if (is_group) {
2368                                 macaddr = cam_const_broad;
2369                                 entry_id = key_index;
2370                         } else {
2371                                 if (mac->opmode == NL80211_IFTYPE_AP ||
2372                                     mac->opmode == NL80211_IFTYPE_MESH_POINT) {
2373                                         entry_id =
2374                                           rtl_cam_get_free_entry(hw, p_macaddr);
2375                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
2376                                                 RT_TRACE(rtlpriv, COMP_SEC,
2377                                                          DBG_EMERG,
2378                                                          "Can not find free hw security cam entry\n");
2379                                                 return;
2380                                         }
2381                                 } else {
2382                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
2383                                 }
2384                                 key_index = PAIRWISE_KEYIDX;
2385                                 is_pairwise = true;
2386                         }
2387                 }
2388
2389                 if (rtlpriv->sec.key_len[key_index] == 0) {
2390                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2391                                  "delete one entry, entry_id is %d\n",
2392                                  entry_id);
2393                         if (mac->opmode == NL80211_IFTYPE_AP ||
2394                                 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2395                                 rtl_cam_del_entry(hw, p_macaddr);
2396                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2397                 } else {
2398                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2399                                  "add one entry\n");
2400                         if (is_pairwise) {
2401                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2402                                          "set Pairwise key\n");
2403
2404                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2405                                                       entry_id, enc_algo,
2406                                                       CAM_CONFIG_NO_USEDK,
2407                                                       rtlpriv->sec.key_buf[key_index]);
2408                         } else {
2409                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2410                                          "set group key\n");
2411
2412                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2413                                         rtl_cam_add_one_entry(hw,
2414                                                         rtlefuse->dev_addr,
2415                                                         PAIRWISE_KEYIDX,
2416                                                         CAM_PAIRWISE_KEY_POSITION,
2417                                                         enc_algo,
2418                                                         CAM_CONFIG_NO_USEDK,
2419                                                         rtlpriv->sec.key_buf
2420                                                         [entry_id]);
2421                                 }
2422
2423                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2424                                                       entry_id, enc_algo,
2425                                                       CAM_CONFIG_NO_USEDK,
2426                                                       rtlpriv->sec.key_buf[entry_id]);
2427                         }
2428
2429                 }
2430         }
2431 }
2432
2433 static void rtl8188ee_bt_var_init(struct ieee80211_hw *hw)
2434 {
2435         struct rtl_priv *rtlpriv = rtl_priv(hw);
2436
2437         rtlpriv->btcoexist.bt_coexistence =
2438                 rtlpriv->btcoexist.eeprom_bt_coexist;
2439         rtlpriv->btcoexist.bt_ant_num = rtlpriv->btcoexist.eeprom_bt_ant_num;
2440         rtlpriv->btcoexist.bt_coexist_type = rtlpriv->btcoexist.eeprom_bt_type;
2441
2442         if (rtlpriv->btcoexist.reg_bt_iso == 2)
2443                 rtlpriv->btcoexist.bt_ant_isolation =
2444                                 rtlpriv->btcoexist.eeprom_bt_ant_isol;
2445         else
2446                 rtlpriv->btcoexist.bt_ant_isolation =
2447                                 rtlpriv->btcoexist.reg_bt_iso;
2448
2449         rtlpriv->btcoexist.bt_radio_shared_type =
2450                 rtlpriv->btcoexist.eeprom_bt_radio_shared;
2451
2452         if (rtlpriv->btcoexist.bt_coexistence) {
2453                 if (rtlpriv->btcoexist.reg_bt_sco == 1)
2454                         rtlpriv->btcoexist.bt_service = BT_OTHER_ACTION;
2455                 else if (rtlpriv->btcoexist.reg_bt_sco == 2)
2456                         rtlpriv->btcoexist.bt_service = BT_SCO;
2457                 else if (rtlpriv->btcoexist.reg_bt_sco == 4)
2458                         rtlpriv->btcoexist.bt_service = BT_BUSY;
2459                 else if (rtlpriv->btcoexist.reg_bt_sco == 5)
2460                         rtlpriv->btcoexist.bt_service = BT_OTHERBUSY;
2461                 else
2462                         rtlpriv->btcoexist.bt_service = BT_IDLE;
2463
2464                 rtlpriv->btcoexist.bt_edca_ul = 0;
2465                 rtlpriv->btcoexist.bt_edca_dl = 0;
2466                 rtlpriv->btcoexist.bt_rssi_state = 0xff;
2467         }
2468 }
2469
2470 void rtl8188ee_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2471                                               bool auto_load_fail, u8 *hwinfo)
2472 {
2473         struct rtl_priv *rtlpriv = rtl_priv(hw);
2474         u8 value;
2475
2476         if (!auto_load_fail) {
2477                 rtlpriv->btcoexist.eeprom_bt_coexist =
2478                         ((hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & 0xe0) >> 5);
2479                 if (hwinfo[EEPROM_RF_FEATURE_OPTION_88E] == 0xFF)
2480                         rtlpriv->btcoexist.eeprom_bt_coexist  = 0;
2481                 value = hwinfo[EEPROM_RF_BT_SETTING_88E];
2482                 rtlpriv->btcoexist.eeprom_bt_type = ((value & 0xe) >> 1);
2483                 rtlpriv->btcoexist.eeprom_bt_ant_num = (value & 0x1);
2484                 rtlpriv->btcoexist.eeprom_bt_ant_isol = ((value & 0x10) >> 4);
2485                 rtlpriv->btcoexist.eeprom_bt_radio_shared =
2486                                  ((value & 0x20) >> 5);
2487         } else {
2488                 rtlpriv->btcoexist.eeprom_bt_coexist = 0;
2489                 rtlpriv->btcoexist.eeprom_bt_type = BT_2WIRE;
2490                 rtlpriv->btcoexist.eeprom_bt_ant_num = ANT_X2;
2491                 rtlpriv->btcoexist.eeprom_bt_ant_isol = 0;
2492                 rtlpriv->btcoexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;
2493         }
2494
2495         rtl8188ee_bt_var_init(hw);
2496 }
2497
2498 void rtl8188ee_bt_reg_init(struct ieee80211_hw *hw)
2499 {
2500         struct rtl_priv *rtlpriv = rtl_priv(hw);
2501
2502         /* 0:Low, 1:High, 2:From Efuse. */
2503         rtlpriv->btcoexist.reg_bt_iso = 2;
2504         /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2505         rtlpriv->btcoexist.reg_bt_sco = 3;
2506         /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2507         rtlpriv->btcoexist.reg_bt_sco = 0;
2508 }
2509
2510 void rtl8188ee_bt_hw_init(struct ieee80211_hw *hw)
2511 {
2512         struct rtl_priv *rtlpriv = rtl_priv(hw);
2513         struct rtl_phy *rtlphy = &rtlpriv->phy;
2514         u8 u1_tmp;
2515
2516         if (rtlpriv->btcoexist.bt_coexistence &&
2517             ((rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) ||
2518               rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC8)) {
2519                 if (rtlpriv->btcoexist.bt_ant_isolation)
2520                         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
2521
2522                 u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) &
2523                          BIT_OFFSET_LEN_MASK_32(0, 1);
2524                 u1_tmp = u1_tmp |
2525                          ((rtlpriv->btcoexist.bt_ant_isolation == 1) ?
2526                          0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
2527                          ((rtlpriv->btcoexist.bt_service == BT_SCO) ?
2528                          0 : BIT_OFFSET_LEN_MASK_32(2, 1));
2529                 rtl_write_byte(rtlpriv, 0x4fd, u1_tmp);
2530
2531                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
2532                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040);
2533                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010);
2534
2535                 /* Config to 1T1R. */
2536                 if (rtlphy->rf_type == RF_1T1R) {
2537                         u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE);
2538                         u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2539                         rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp);
2540
2541                         u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE);
2542                         u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2543                         rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp);
2544                 }
2545         }
2546 }
2547
2548 void rtl88ee_suspend(struct ieee80211_hw *hw)
2549 {
2550 }
2551
2552 void rtl88ee_resume(struct ieee80211_hw *hw)
2553 {
2554 }