drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * RTL8XXXU mac80211 USB driver - 8723b specific subdriver
   4  *
   5  * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
   6  *
   7  * Portions, notably calibration code:
   8  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   9  *
  10  * This driver was written as a replacement for the vendor provided
  11  * rtl8723au driver. As the Realtek 8xxx chips are very similar in
  12  * their programming interface, I have started adding support for
  13  * additional 8xxx chips like the 8192cu, 8188cus, etc.
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/kernel.h>
  18 #include <linux/sched.h>
  19 #include <linux/errno.h>
  20 #include <linux/slab.h>
  21 #include <linux/module.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/list.h>
  24 #include <linux/usb.h>
  25 #include <linux/netdevice.h>
  26 #include <linux/etherdevice.h>
  27 #include <linux/ethtool.h>
  28 #include <linux/wireless.h>
  29 #include <linux/firmware.h>
  30 #include <linux/moduleparam.h>
  31 #include <net/mac80211.h>
  32 #include "rtl8xxxu.h"
  33 #include "rtl8xxxu_regs.h"
  34
  35 static struct rtl8xxxu_reg8val rtl8723b_mac_init_table[] = {
  36         {0x02f, 0x30}, {0x035, 0x00}, {0x039, 0x08}, {0x04e, 0xe0},
  37         {0x064, 0x00}, {0x067, 0x20}, {0x428, 0x0a}, {0x429, 0x10},
  38         {0x430, 0x00}, {0x431, 0x00},
  39         {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
  40         {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
  41         {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
  42         {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
  43         {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
  44         {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
  45         {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
  46         {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
  47         {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
  48         {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
  49         {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
  50         {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
  51         {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
  52         {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
  53         {0x516, 0x0a}, {0x525, 0x4f},
  54         {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50},
  55         {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
  56         {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff},
  57         {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff},
  58         {0x638, 0x50}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
  59         {0x63f, 0x0e}, {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00},
  60         {0x652, 0xc8}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
  61         {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
  62         {0x70a, 0x65}, {0x70b, 0x87}, {0x765, 0x18}, {0x76e, 0x04},
  63         {0xffff, 0xff},
  64 };
  65
  66 static struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table[] = {
  67         {0x800, 0x80040000}, {0x804, 0x00000003},
  68         {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
  69         {0x810, 0x10001331}, {0x814, 0x020c3d10},
  70         {0x818, 0x02200385}, {0x81c, 0x00000000},
  71         {0x820, 0x01000100}, {0x824, 0x00190204},
  72         {0x828, 0x00000000}, {0x82c, 0x00000000},
  73         {0x830, 0x00000000}, {0x834, 0x00000000},
  74         {0x838, 0x00000000}, {0x83c, 0x00000000},
  75         {0x840, 0x00010000}, {0x844, 0x00000000},
  76         {0x848, 0x00000000}, {0x84c, 0x00000000},
  77         {0x850, 0x00000000}, {0x854, 0x00000000},
  78         {0x858, 0x569a11a9}, {0x85c, 0x01000014},
  79         {0x860, 0x66f60110}, {0x864, 0x061f0649},
  80         {0x868, 0x00000000}, {0x86c, 0x27272700},
  81         {0x870, 0x07000760}, {0x874, 0x25004000},
  82         {0x878, 0x00000808}, {0x87c, 0x00000000},
  83         {0x880, 0xb0000c1c}, {0x884, 0x00000001},
  84         {0x888, 0x00000000}, {0x88c, 0xccc000c0},
  85         {0x890, 0x00000800}, {0x894, 0xfffffffe},
  86         {0x898, 0x40302010}, {0x89c, 0x00706050},
  87         {0x900, 0x00000000}, {0x904, 0x00000023},
  88         {0x908, 0x00000000}, {0x90c, 0x81121111},
  89         {0x910, 0x00000002}, {0x914, 0x00000201},
  90         {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c},
  91         {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f},
  92         {0xa10, 0x9500bb78}, {0xa14, 0x1114d028},
  93         {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
  94         {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
  95         {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
  96         {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
  97         {0xa78, 0x00000900}, {0xa7c, 0x225b0606},
  98         {0xa80, 0x21806490}, {0xb2c, 0x00000000},
  99         {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
 100         {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
 101         {0xc10, 0x08800000}, {0xc14, 0x40000100},
 102         {0xc18, 0x08800000}, {0xc1c, 0x40000100},
 103         {0xc20, 0x00000000}, {0xc24, 0x00000000},
 104         {0xc28, 0x00000000}, {0xc2c, 0x00000000},
 105         {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
 106         {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
 107         {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
 108         {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
 109         {0xc50, 0x69553420}, {0xc54, 0x43bc0094},
 110         {0xc58, 0x00013149}, {0xc5c, 0x00250492},
 111         {0xc60, 0x00000000}, {0xc64, 0x7112848b},
 112         {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
 113         {0xc70, 0x2c7f000d}, {0xc74, 0x020610db},
 114         {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
 115         {0xc80, 0x390000e4}, {0xc84, 0x20f60000},
 116         {0xc88, 0x40000100}, {0xc8c, 0x20200000},
 117         {0xc90, 0x00020e1a}, {0xc94, 0x00000000},
 118         {0xc98, 0x00020e1a}, {0xc9c, 0x00007f7f},
 119         {0xca0, 0x00000000}, {0xca4, 0x000300a0},
 120         {0xca8, 0x00000000}, {0xcac, 0x00000000},
 121         {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
 122         {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
 123         {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
 124         {0xcc8, 0x00000000}, {0xccc, 0x00000000},
 125         {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
 126         {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
 127         {0xce0, 0x00222222}, {0xce4, 0x00000000},
 128         {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
 129         {0xd00, 0x00000740}, {0xd04, 0x40020401},
 130         {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
 131         {0xd10, 0xa0633333}, {0xd14, 0x3333bc53},
 132         {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975},
 133         {0xd30, 0x00000000}, {0xd34, 0x80608000},
 134         {0xd38, 0x00000000}, {0xd3c, 0x00127353},
 135         {0xd40, 0x00000000}, {0xd44, 0x00000000},
 136         {0xd48, 0x00000000}, {0xd4c, 0x00000000},
 137         {0xd50, 0x6437140a}, {0xd54, 0x00000000},
 138         {0xd58, 0x00000282}, {0xd5c, 0x30032064},
 139         {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
 140         {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
 141         {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
 142         {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d},
 143         {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d},
 144         {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d},
 145         {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d},
 146         {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
 147         {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
 148         {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
 149         {0xe44, 0x01004800}, {0xe48, 0xfb000000},
 150         {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
 151         {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
 152         {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
 153         {0xe68, 0x001b2556}, {0xe6c, 0x00c00096},
 154         {0xe70, 0x00c00096}, {0xe74, 0x01000056},
 155         {0xe78, 0x01000014}, {0xe7c, 0x01000056},
 156         {0xe80, 0x01000014}, {0xe84, 0x00c00096},
 157         {0xe88, 0x01000056}, {0xe8c, 0x00c00096},
 158         {0xed0, 0x00c00096}, {0xed4, 0x00c00096},
 159         {0xed8, 0x00c00096}, {0xedc, 0x000000d6},
 160         {0xee0, 0x000000d6}, {0xeec, 0x01c00016},
 161         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 162         {0xf00, 0x00000300},
 163         {0x820, 0x01000100}, {0x800, 0x83040000},
 164         {0xffff, 0xffffffff},
 165 };
 166
 167 static struct rtl8xxxu_reg32val rtl8xxx_agc_8723bu_table[] = {
 168         {0xc78, 0xfd000001}, {0xc78, 0xfc010001},
 169         {0xc78, 0xfb020001}, {0xc78, 0xfa030001},
 170         {0xc78, 0xf9040001}, {0xc78, 0xf8050001},
 171         {0xc78, 0xf7060001}, {0xc78, 0xf6070001},
 172         {0xc78, 0xf5080001}, {0xc78, 0xf4090001},
 173         {0xc78, 0xf30a0001}, {0xc78, 0xf20b0001},
 174         {0xc78, 0xf10c0001}, {0xc78, 0xf00d0001},
 175         {0xc78, 0xef0e0001}, {0xc78, 0xee0f0001},
 176         {0xc78, 0xed100001}, {0xc78, 0xec110001},
 177         {0xc78, 0xeb120001}, {0xc78, 0xea130001},
 178         {0xc78, 0xe9140001}, {0xc78, 0xe8150001},
 179         {0xc78, 0xe7160001}, {0xc78, 0xe6170001},
 180         {0xc78, 0xe5180001}, {0xc78, 0xe4190001},
 181         {0xc78, 0xe31a0001}, {0xc78, 0xa51b0001},
 182         {0xc78, 0xa41c0001}, {0xc78, 0xa31d0001},
 183         {0xc78, 0x671e0001}, {0xc78, 0x661f0001},
 184         {0xc78, 0x65200001}, {0xc78, 0x64210001},
 185         {0xc78, 0x63220001}, {0xc78, 0x4a230001},
 186         {0xc78, 0x49240001}, {0xc78, 0x48250001},
 187         {0xc78, 0x47260001}, {0xc78, 0x46270001},
 188         {0xc78, 0x45280001}, {0xc78, 0x44290001},
 189         {0xc78, 0x432a0001}, {0xc78, 0x422b0001},
 190         {0xc78, 0x292c0001}, {0xc78, 0x282d0001},
 191         {0xc78, 0x272e0001}, {0xc78, 0x262f0001},
 192         {0xc78, 0x0a300001}, {0xc78, 0x09310001},
 193         {0xc78, 0x08320001}, {0xc78, 0x07330001},
 194         {0xc78, 0x06340001}, {0xc78, 0x05350001},
 195         {0xc78, 0x04360001}, {0xc78, 0x03370001},
 196         {0xc78, 0x02380001}, {0xc78, 0x01390001},
 197         {0xc78, 0x013a0001}, {0xc78, 0x013b0001},
 198         {0xc78, 0x013c0001}, {0xc78, 0x013d0001},
 199         {0xc78, 0x013e0001}, {0xc78, 0x013f0001},
 200         {0xc78, 0xfc400001}, {0xc78, 0xfb410001},
 201         {0xc78, 0xfa420001}, {0xc78, 0xf9430001},
 202         {0xc78, 0xf8440001}, {0xc78, 0xf7450001},
 203         {0xc78, 0xf6460001}, {0xc78, 0xf5470001},
 204         {0xc78, 0xf4480001}, {0xc78, 0xf3490001},
 205         {0xc78, 0xf24a0001}, {0xc78, 0xf14b0001},
 206         {0xc78, 0xf04c0001}, {0xc78, 0xef4d0001},
 207         {0xc78, 0xee4e0001}, {0xc78, 0xed4f0001},
 208         {0xc78, 0xec500001}, {0xc78, 0xeb510001},
 209         {0xc78, 0xea520001}, {0xc78, 0xe9530001},
 210         {0xc78, 0xe8540001}, {0xc78, 0xe7550001},
 211         {0xc78, 0xe6560001}, {0xc78, 0xe5570001},
 212         {0xc78, 0xe4580001}, {0xc78, 0xe3590001},
 213         {0xc78, 0xa65a0001}, {0xc78, 0xa55b0001},
 214         {0xc78, 0xa45c0001}, {0xc78, 0xa35d0001},
 215         {0xc78, 0x675e0001}, {0xc78, 0x665f0001},
 216         {0xc78, 0x65600001}, {0xc78, 0x64610001},
 217         {0xc78, 0x63620001}, {0xc78, 0x62630001},
 218         {0xc78, 0x61640001}, {0xc78, 0x48650001},
 219         {0xc78, 0x47660001}, {0xc78, 0x46670001},
 220         {0xc78, 0x45680001}, {0xc78, 0x44690001},
 221         {0xc78, 0x436a0001}, {0xc78, 0x426b0001},
 222         {0xc78, 0x286c0001}, {0xc78, 0x276d0001},
 223         {0xc78, 0x266e0001}, {0xc78, 0x256f0001},
 224         {0xc78, 0x24700001}, {0xc78, 0x09710001},
 225         {0xc78, 0x08720001}, {0xc78, 0x07730001},
 226         {0xc78, 0x06740001}, {0xc78, 0x05750001},
 227         {0xc78, 0x04760001}, {0xc78, 0x03770001},
 228         {0xc78, 0x02780001}, {0xc78, 0x01790001},
 229         {0xc78, 0x017a0001}, {0xc78, 0x017b0001},
 230         {0xc78, 0x017c0001}, {0xc78, 0x017d0001},
 231         {0xc78, 0x017e0001}, {0xc78, 0x017f0001},
 232         {0xc50, 0x69553422},
 233         {0xc50, 0x69553420},
 234         {0x824, 0x00390204},
 235         {0xffff, 0xffffffff}
 236 };
 237
 238 static struct rtl8xxxu_rfregval rtl8723bu_radioa_1t_init_table[] = {
 239         {0x00, 0x00010000}, {0xb0, 0x000dffe0},
 240         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 241         {0xfe, 0x00000000}, {0xb1, 0x00000018},
 242         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 243         {0xfe, 0x00000000}, {0xb2, 0x00084c00},
 244         {0xb5, 0x0000d2cc}, {0xb6, 0x000925aa},
 245         {0xb7, 0x00000010}, {0xb8, 0x0000907f},
 246         {0x5c, 0x00000002}, {0x7c, 0x00000002},
 247         {0x7e, 0x00000005}, {0x8b, 0x0006fc00},
 248         {0xb0, 0x000ff9f0}, {0x1c, 0x000739d2},
 249         {0x1e, 0x00000000}, {0xdf, 0x00000780},
 250         {0x50, 0x00067435},
 251         /*
 252          * The 8723bu vendor driver indicates that bit 8 should be set in
 253          * 0x51 for package types TFBGA90, TFBGA80, and TFBGA79. However
 254          * they never actually check the package type - and just default
 255          * to not setting it.
 256          */
 257         {0x51, 0x0006b04e},
 258         {0x52, 0x000007d2}, {0x53, 0x00000000},
 259         {0x54, 0x00050400}, {0x55, 0x0004026e},
 260         {0xdd, 0x0000004c}, {0x70, 0x00067435},
 261         /*
 262          * 0x71 has same package type condition as for register 0x51
 263          */
 264         {0x71, 0x0006b04e},
 265         {0x72, 0x000007d2}, {0x73, 0x00000000},
 266         {0x74, 0x00050400}, {0x75, 0x0004026e},
 267         {0xef, 0x00000100}, {0x34, 0x0000add7},
 268         {0x35, 0x00005c00}, {0x34, 0x00009dd4},
 269         {0x35, 0x00005000}, {0x34, 0x00008dd1},
 270         {0x35, 0x00004400}, {0x34, 0x00007dce},
 271         {0x35, 0x00003800}, {0x34, 0x00006cd1},
 272         {0x35, 0x00004400}, {0x34, 0x00005cce},
 273         {0x35, 0x00003800}, {0x34, 0x000048ce},
 274         {0x35, 0x00004400}, {0x34, 0x000034ce},
 275         {0x35, 0x00003800}, {0x34, 0x00002451},
 276         {0x35, 0x00004400}, {0x34, 0x0000144e},
 277         {0x35, 0x00003800}, {0x34, 0x00000051},
 278         {0x35, 0x00004400}, {0xef, 0x00000000},
 279         {0xef, 0x00000100}, {0xed, 0x00000010},
 280         {0x44, 0x0000add7}, {0x44, 0x00009dd4},
 281         {0x44, 0x00008dd1}, {0x44, 0x00007dce},
 282         {0x44, 0x00006cc1}, {0x44, 0x00005cce},
 283         {0x44, 0x000044d1}, {0x44, 0x000034ce},
 284         {0x44, 0x00002451}, {0x44, 0x0000144e},
 285         {0x44, 0x00000051}, {0xef, 0x00000000},
 286         {0xed, 0x00000000}, {0x7f, 0x00020080},
 287         {0xef, 0x00002000}, {0x3b, 0x000380ef},
 288         {0x3b, 0x000302fe}, {0x3b, 0x00028ce6},
 289         {0x3b, 0x000200bc}, {0x3b, 0x000188a5},
 290         {0x3b, 0x00010fbc}, {0x3b, 0x00008f71},
 291         {0x3b, 0x00000900}, {0xef, 0x00000000},
 292         {0xed, 0x00000001}, {0x40, 0x000380ef},
 293         {0x40, 0x000302fe}, {0x40, 0x00028ce6},
 294         {0x40, 0x000200bc}, {0x40, 0x000188a5},
 295         {0x40, 0x00010fbc}, {0x40, 0x00008f71},
 296         {0x40, 0x00000900}, {0xed, 0x00000000},
 297         {0x82, 0x00080000}, {0x83, 0x00008000},
 298         {0x84, 0x00048d80}, {0x85, 0x00068000},
 299         {0xa2, 0x00080000}, {0xa3, 0x00008000},
 300         {0xa4, 0x00048d80}, {0xa5, 0x00068000},
 301         {0xed, 0x00000002}, {0xef, 0x00000002},
 302         {0x56, 0x00000032}, {0x76, 0x00000032},
 303         {0x01, 0x00000780},
 304         {0xff, 0xffffffff}
 305 };
 306
 307 static void rtl8723bu_write_btreg(struct rtl8xxxu_priv *priv, u8 reg, u8 data)
 308 {
 309         struct h2c_cmd h2c;
 310         int reqnum = 0;
 311
 312         memset(&h2c, 0, sizeof(struct h2c_cmd));
 313         h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER;
 314         h2c.bt_mp_oper.operreq = 0 | (reqnum << 4);
 315         h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE;
 316         h2c.bt_mp_oper.data = data;
 317         rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper));
 318
 319         reqnum++;
 320         memset(&h2c, 0, sizeof(struct h2c_cmd));
 321         h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER;
 322         h2c.bt_mp_oper.operreq = 0 | (reqnum << 4);
 323         h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE;
 324         h2c.bt_mp_oper.addr = reg;
 325         rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper));
 326 }
 327
 328 static void rtl8723bu_reset_8051(struct rtl8xxxu_priv *priv)
 329 {
 330         u8 val8;
 331         u16 sys_func;
 332
 333         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
 334         val8 &= ~BIT(1);
 335         rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
 336
 337         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
 338         val8 &= ~BIT(0);
 339         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
 340
 341         sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
 342         sys_func &= ~SYS_FUNC_CPU_ENABLE;
 343         rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
 344
 345         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
 346         val8 &= ~BIT(1);
 347         rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
 348
 349         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
 350         val8 |= BIT(0);
 351         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
 352
 353         sys_func |= SYS_FUNC_CPU_ENABLE;
 354         rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
 355 }
 356
 357 static void
 358 rtl8723b_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
 359 {
 360         u32 val32, ofdm, mcs;
 361         u8 cck, ofdmbase, mcsbase;
 362         int group, tx_idx;
 363
 364         tx_idx = 0;
 365         group = rtl8xxxu_gen2_channel_to_group(channel);
 366
 367         cck = priv->cck_tx_power_index_B[group];
 368         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
 369         val32 &= 0xffff00ff;
 370         val32 |= (cck << 8);
 371         rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
 372
 373         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
 374         val32 &= 0xff;
 375         val32 |= ((cck << 8) | (cck << 16) | (cck << 24));
 376         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
 377
 378         ofdmbase = priv->ht40_1s_tx_power_index_B[group];
 379         ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b;
 380         ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24;
 381
 382         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm);
 383         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm);
 384
 385         mcsbase = priv->ht40_1s_tx_power_index_B[group];
 386         if (ht40)
 387                 mcsbase += priv->ht40_tx_power_diff[tx_idx++].b;
 388         else
 389                 mcsbase += priv->ht20_tx_power_diff[tx_idx++].b;
 390         mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24;
 391
 392         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs);
 393         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs);
 394 }
 395
 396 static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv *priv)
 397 {
 398         struct rtl8723bu_efuse *efuse = &priv->efuse_wifi.efuse8723bu;
 399         int i;
 400
 401         if (efuse->rtl_id != cpu_to_le16(0x8129))
 402                 return -EINVAL;
 403
 404         ether_addr_copy(priv->mac_addr, efuse->mac_addr);
 405
 406         memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base,
 407                sizeof(efuse->tx_power_index_A.cck_base));
 408         memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base,
 409                sizeof(efuse->tx_power_index_B.cck_base));
 410
 411         memcpy(priv->ht40_1s_tx_power_index_A,
 412                efuse->tx_power_index_A.ht40_base,
 413                sizeof(efuse->tx_power_index_A.ht40_base));
 414         memcpy(priv->ht40_1s_tx_power_index_B,
 415                efuse->tx_power_index_B.ht40_base,
 416                sizeof(efuse->tx_power_index_B.ht40_base));
 417
 418         priv->ofdm_tx_power_diff[0].a =
 419                 efuse->tx_power_index_A.ht20_ofdm_1s_diff.a;
 420         priv->ofdm_tx_power_diff[0].b =
 421                 efuse->tx_power_index_B.ht20_ofdm_1s_diff.a;
 422
 423         priv->ht20_tx_power_diff[0].a =
 424                 efuse->tx_power_index_A.ht20_ofdm_1s_diff.b;
 425         priv->ht20_tx_power_diff[0].b =
 426                 efuse->tx_power_index_B.ht20_ofdm_1s_diff.b;
 427
 428         priv->ht40_tx_power_diff[0].a = 0;
 429         priv->ht40_tx_power_diff[0].b = 0;
 430
 431         for (i = 1; i < RTL8723B_TX_COUNT; i++) {
 432                 priv->ofdm_tx_power_diff[i].a =
 433                         efuse->tx_power_index_A.pwr_diff[i - 1].ofdm;
 434                 priv->ofdm_tx_power_diff[i].b =
 435                         efuse->tx_power_index_B.pwr_diff[i - 1].ofdm;
 436
 437                 priv->ht20_tx_power_diff[i].a =
 438                         efuse->tx_power_index_A.pwr_diff[i - 1].ht20;
 439                 priv->ht20_tx_power_diff[i].b =
 440                         efuse->tx_power_index_B.pwr_diff[i - 1].ht20;
 441
 442                 priv->ht40_tx_power_diff[i].a =
 443                         efuse->tx_power_index_A.pwr_diff[i - 1].ht40;
 444                 priv->ht40_tx_power_diff[i].b =
 445                         efuse->tx_power_index_B.pwr_diff[i - 1].ht40;
 446         }
 447
 448         priv->has_xtalk = 1;
 449         priv->xtalk = priv->efuse_wifi.efuse8723bu.xtal_k & 0x3f;
 450
 451         dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name);
 452         dev_info(&priv->udev->dev, "Product: %.41s\n", efuse->device_name);
 453
 454         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
 455                 int i;
 456                 unsigned char *raw = priv->efuse_wifi.raw;
 457
 458                 dev_info(&priv->udev->dev,
 459                          "%s: dumping efuse (0x%02zx bytes):\n",
 460                          __func__, sizeof(struct rtl8723bu_efuse));
 461                 for (i = 0; i < sizeof(struct rtl8723bu_efuse); i += 8)
 462                         dev_info(&priv->udev->dev, "%02x: %8ph\n", i, &raw[i]);
 463         }
 464
 465         return 0;
 466 }
 467
 468 static int rtl8723bu_load_firmware(struct rtl8xxxu_priv *priv)
 469 {
 470         char *fw_name;
 471         int ret;
 472
 473         if (priv->enable_bluetooth)
 474                 fw_name = "/*(DEBLOBBED)*/";
 475         else
 476                 fw_name = "/*(DEBLOBBED)*/";
 477
 478         ret = rtl8xxxu_load_firmware(priv, fw_name);
 479         return ret;
 480 }
 481
 482 static void rtl8723bu_init_phy_bb(struct rtl8xxxu_priv *priv)
 483 {
 484         u8 val8;
 485         u16 val16;
 486
 487         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
 488         val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_DIO_RF;
 489         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
 490
 491         rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
 492
 493         /* 6. 0x1f[7:0] = 0x07 */
 494         val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
 495         rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
 496
 497         /* Why? */
 498         rtl8xxxu_write8(priv, REG_SYS_FUNC, 0xe3);
 499         rtl8xxxu_write8(priv, REG_AFE_XTAL_CTRL + 1, 0x80);
 500         rtl8xxxu_init_phy_regs(priv, rtl8723b_phy_1t_init_table);
 501
 502         rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8723bu_table);
 503 }
 504
 505 static int rtl8723bu_init_phy_rf(struct rtl8xxxu_priv *priv)
 506 {
 507         int ret;
 508
 509         ret = rtl8xxxu_init_phy_rf(priv, rtl8723bu_radioa_1t_init_table, RF_A);
 510         /*
 511          * PHY LCK
 512          */
 513         rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdfbe0);
 514         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, 0x8c01);
 515         msleep(200);
 516         rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdffe0);
 517
 518         return ret;
 519 }
 520
 521 static void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv)
 522 {
 523         u32 val32;
 524
 525         val32 = rtl8xxxu_read32(priv, REG_PAD_CTRL1);
 526         val32 &= ~(BIT(20) | BIT(24));
 527         rtl8xxxu_write32(priv, REG_PAD_CTRL1, val32);
 528
 529         val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
 530         val32 &= ~BIT(4);
 531         rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
 532
 533         val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
 534         val32 |= BIT(3);
 535         rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
 536
 537         val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
 538         val32 |= BIT(24);
 539         rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
 540
 541         val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
 542         val32 &= ~BIT(23);
 543         rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
 544
 545         val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER);
 546         val32 |= (BIT(0) | BIT(1));
 547         rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32);
 548
 549         val32 = rtl8xxxu_read32(priv, REG_RFE_CTRL_ANTA_SRC);
 550         val32 &= 0xffffff00;
 551         val32 |= 0x77;
 552         rtl8xxxu_write32(priv, REG_RFE_CTRL_ANTA_SRC, val32);
 553
 554         val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
 555         val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
 556         rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
 557 }
 558
 559 static int rtl8723bu_iqk_path_a(struct rtl8xxxu_priv *priv)
 560 {
 561         u32 reg_eac, reg_e94, reg_e9c, path_sel, val32;
 562         int result = 0;
 563
 564         path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
 565
 566         /*
 567          * Leave IQK mode
 568          */
 569         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
 570         val32 &= 0x000000ff;
 571         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
 572
 573         /*
 574          * Enable path A PA in TX IQK mode
 575          */
 576         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
 577         val32 |= 0x80000;
 578         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
 579         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000);
 580         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0003f);
 581         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xc7f87);
 582
 583         /*
 584          * Tx IQK setting
 585          */
 586         rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
 587         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
 588
 589         /* path-A IQK setting */
 590         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
 591         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
 592         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
 593         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
 594
 595         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ea);
 596         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
 597         rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
 598         rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
 599
 600         /* LO calibration setting */
 601         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911);
 602
 603         /*
 604          * Enter IQK mode
 605          */
 606         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
 607         val32 &= 0x000000ff;
 608         val32 |= 0x80800000;
 609         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
 610
 611         /*
 612          * The vendor driver indicates the USB module is always using
 613          * S0S1 path 1 for the 8723bu. This may be different for 8192eu
 614          */
 615         if (priv->rf_paths > 1)
 616                 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
 617         else
 618                 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
 619
 620         /*
 621          * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
 622          * No trace of this in the 8192eu or 8188eu vendor drivers.
 623          */
 624         rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
 625
 626         /* One shot, path A LOK & IQK */
 627         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
 628         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
 629
 630         mdelay(1);
 631
 632         /* Restore Ant Path */
 633         rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
 634 #ifdef RTL8723BU_BT
 635         /* GNT_BT = 1 */
 636         rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
 637 #endif
 638
 639         /*
 640          * Leave IQK mode
 641          */
 642         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
 643         val32 &= 0x000000ff;
 644         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
 645
 646         /* Check failed */
 647         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
 648         reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
 649         reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
 650
 651         val32 = (reg_e9c >> 16) & 0x3ff;
 652         if (val32 & 0x200)
 653                 val32 = 0x400 - val32;
 654
 655         if (!(reg_eac & BIT(28)) &&
 656             ((reg_e94 & 0x03ff0000) != 0x01420000) &&
 657             ((reg_e9c & 0x03ff0000) != 0x00420000) &&
 658             ((reg_e94 & 0x03ff0000)  < 0x01100000) &&
 659             ((reg_e94 & 0x03ff0000)  > 0x00f00000) &&
 660             val32 < 0xf)
 661                 result |= 0x01;
 662         else    /* If TX not OK, ignore RX */
 663                 goto out;
 664
 665 out:
 666         return result;
 667 }
 668
 669 static int rtl8723bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv)
 670 {
 671         u32 reg_ea4, reg_eac, reg_e94, reg_e9c, path_sel, val32;
 672         int result = 0;
 673
 674         path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
 675
 676         /*
 677          * Leave IQK mode
 678          */
 679         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
 680         val32 &= 0x000000ff;
 681         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
 682
 683         /*
 684          * Enable path A PA in TX IQK mode
 685          */
 686         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
 687         val32 |= 0x80000;
 688         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
 689         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
 690         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
 691         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
 692
 693         /*
 694          * Tx IQK setting
 695          */
 696         rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
 697         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
 698
 699         /* path-A IQK setting */
 700         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
 701         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
 702         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
 703         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
 704
 705         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160ff0);
 706         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
 707         rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
 708         rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
 709
 710         /* LO calibration setting */
 711         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
 712
 713         /*
 714          * Enter IQK mode
 715          */
 716         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
 717         val32 &= 0x000000ff;
 718         val32 |= 0x80800000;
 719         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
 720
 721         /*
 722          * The vendor driver indicates the USB module is always using
 723          * S0S1 path 1 for the 8723bu. This may be different for 8192eu
 724          */
 725         if (priv->rf_paths > 1)
 726                 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
 727         else
 728                 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
 729
 730         /*
 731          * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
 732          * No trace of this in the 8192eu or 8188eu vendor drivers.
 733          */
 734         rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
 735
 736         /* One shot, path A LOK & IQK */
 737         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
 738         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
 739
 740         mdelay(1);
 741
 742         /* Restore Ant Path */
 743         rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
 744 #ifdef RTL8723BU_BT
 745         /* GNT_BT = 1 */
 746         rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
 747 #endif
 748
 749         /*
 750          * Leave IQK mode
 751          */
 752         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
 753         val32 &= 0x000000ff;
 754         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
 755
 756         /* Check failed */
 757         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
 758         reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
 759         reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
 760
 761         val32 = (reg_e9c >> 16) & 0x3ff;
 762         if (val32 & 0x200)
 763                 val32 = 0x400 - val32;
 764
 765         if (!(reg_eac & BIT(28)) &&
 766             ((reg_e94 & 0x03ff0000) != 0x01420000) &&
 767             ((reg_e9c & 0x03ff0000) != 0x00420000) &&
 768             ((reg_e94 & 0x03ff0000)  < 0x01100000) &&
 769             ((reg_e94 & 0x03ff0000)  > 0x00f00000) &&
 770             val32 < 0xf)
 771                 result |= 0x01;
 772         else    /* If TX not OK, ignore RX */
 773                 goto out;
 774
 775         val32 = 0x80007c00 | (reg_e94 &0x3ff0000) |
 776                 ((reg_e9c & 0x3ff0000) >> 16);
 777         rtl8xxxu_write32(priv, REG_TX_IQK, val32);
 778
 779         /*
 780          * Modify RX IQK mode
 781          */
 782         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
 783         val32 &= 0x000000ff;
 784         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
 785         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
 786         val32 |= 0x80000;
 787         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
 788         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
 789         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
 790         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7d77);
 791
 792         /*
 793          * PA, PAD setting
 794          */
 795         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0xf80);
 796         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, 0x4021f);
 797
 798         /*
 799          * RX IQK setting
 800          */
 801         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
 802
 803         /* path-A IQK setting */
 804         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
 805         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c);
 806         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
 807         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
 808
 809         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82110000);
 810         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x2816001f);
 811         rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
 812         rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
 813
 814         /* LO calibration setting */
 815         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a8d1);
 816
 817         /*
 818          * Enter IQK mode
 819          */
 820         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
 821         val32 &= 0x000000ff;
 822         val32 |= 0x80800000;
 823         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
 824
 825         if (priv->rf_paths > 1)
 826                 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
 827         else
 828                 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
 829
 830         /*
 831          * Disable BT
 832          */
 833         rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
 834
 835         /* One shot, path A LOK & IQK */
 836         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
 837         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
 838
 839         mdelay(1);
 840
 841         /* Restore Ant Path */
 842         rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
 843 #ifdef RTL8723BU_BT
 844         /* GNT_BT = 1 */
 845         rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
 846 #endif
 847
 848         /*
 849          * Leave IQK mode
 850          */
 851         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
 852         val32 &= 0x000000ff;
 853         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
 854
 855         /* Check failed */
 856         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
 857         reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
 858
 859         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x780);
 860
 861         val32 = (reg_eac >> 16) & 0x3ff;
 862         if (val32 & 0x200)
 863                 val32 = 0x400 - val32;
 864
 865         if (!(reg_eac & BIT(27)) &&
 866             ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
 867             ((reg_eac & 0x03ff0000) != 0x00360000) &&
 868             ((reg_ea4 & 0x03ff0000)  < 0x01100000) &&
 869             ((reg_ea4 & 0x03ff0000)  > 0x00f00000) &&
 870             val32 < 0xf)
 871                 result |= 0x02;
 872         else    /* If TX not OK, ignore RX */
 873                 goto out;
 874 out:
 875         return result;
 876 }
 877
 878 static void rtl8723bu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
 879                                       int result[][8], int t)
 880 {
 881         struct device *dev = &priv->udev->dev;
 882         u32 i, val32;
 883         int path_a_ok /*, path_b_ok */;
 884         int retry = 2;
 885         const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
 886                 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
 887                 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
 888                 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
 889                 REG_TX_OFDM_BBON, REG_TX_TO_RX,
 890                 REG_TX_TO_TX, REG_RX_CCK,
 891                 REG_RX_OFDM, REG_RX_WAIT_RIFS,
 892                 REG_RX_TO_RX, REG_STANDBY,
 893                 REG_SLEEP, REG_PMPD_ANAEN
 894         };
 895         const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
 896                 REG_TXPAUSE, REG_BEACON_CTRL,
 897                 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
 898         };
 899         const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
 900                 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
 901                 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
 902                 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
 903                 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
 904         };
 905         u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff;
 906         u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff;
 907
 908         /*
 909          * Note: IQ calibration must be performed after loading
 910          *       PHY_REG.txt , and radio_a, radio_b.txt
 911          */
 912
 913         if (t == 0) {
 914                 /* Save ADDA parameters, turn Path A ADDA on */
 915                 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
 916                                    RTL8XXXU_ADDA_REGS);
 917                 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
 918                 rtl8xxxu_save_regs(priv, iqk_bb_regs,
 919                                    priv->bb_backup, RTL8XXXU_BB_REGS);
 920         }
 921
 922         rtl8xxxu_path_adda_on(priv, adda_regs, true);
 923
 924         /* MAC settings */
 925         rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
 926
 927         val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
 928         val32 |= 0x0f000000;
 929         rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
 930
 931         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
 932         rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
 933         rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
 934
 935         /*
 936          * RX IQ calibration setting for 8723B D cut large current issue
 937          * when leaving IPS
 938          */
 939         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
 940         val32 &= 0x000000ff;
 941         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
 942
 943         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
 944         val32 |= 0x80000;
 945         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
 946
 947         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
 948         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
 949         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
 950
 951         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
 952         val32 |= 0x20;
 953         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
 954
 955         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_43, 0x60fbd);
 956
 957         for (i = 0; i < retry; i++) {
 958                 path_a_ok = rtl8723bu_iqk_path_a(priv);
 959                 if (path_a_ok == 0x01) {
 960                         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
 961                         val32 &= 0x000000ff;
 962                         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
 963
 964                         val32 = rtl8xxxu_read32(priv,
 965                                                 REG_TX_POWER_BEFORE_IQK_A);
 966                         result[t][0] = (val32 >> 16) & 0x3ff;
 967                         val32 = rtl8xxxu_read32(priv,
 968                                                 REG_TX_POWER_AFTER_IQK_A);
 969                         result[t][1] = (val32 >> 16) & 0x3ff;
 970
 971                         break;
 972                 }
 973         }
 974
 975         if (!path_a_ok)
 976                 dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__);
 977
 978         for (i = 0; i < retry; i++) {
 979                 path_a_ok = rtl8723bu_rx_iqk_path_a(priv);
 980                 if (path_a_ok == 0x03) {
 981                         val32 = rtl8xxxu_read32(priv,
 982                                                 REG_RX_POWER_BEFORE_IQK_A_2);
 983                         result[t][2] = (val32 >> 16) & 0x3ff;
 984                         val32 = rtl8xxxu_read32(priv,
 985                                                 REG_RX_POWER_AFTER_IQK_A_2);
 986                         result[t][3] = (val32 >> 16) & 0x3ff;
 987
 988                         break;
 989                 }
 990         }
 991
 992         if (!path_a_ok)
 993                 dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__);
 994
 995         if (priv->tx_paths > 1) {
 996 #if 1
 997                 dev_warn(dev, "%s: Path B not supported\n", __func__);
 998 #else
 999
1000                 /*
1001                  * Path A into standby
1002                  */
1003                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
1004                 val32 &= 0x000000ff;
1005                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
1006                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000);
1007
1008                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
1009                 val32 &= 0x000000ff;
1010                 val32 |= 0x80800000;
1011                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
1012
1013                 /* Turn Path B ADDA on */
1014                 rtl8xxxu_path_adda_on(priv, adda_regs, false);
1015
1016                 for (i = 0; i < retry; i++) {
1017                         path_b_ok = rtl8xxxu_iqk_path_b(priv);
1018                         if (path_b_ok == 0x03) {
1019                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
1020                                 result[t][4] = (val32 >> 16) & 0x3ff;
1021                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
1022                                 result[t][5] = (val32 >> 16) & 0x3ff;
1023                                 break;
1024                         }
1025                 }
1026
1027                 if (!path_b_ok)
1028                         dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
1029
1030                 for (i = 0; i < retry; i++) {
1031                         path_b_ok = rtl8723bu_rx_iqk_path_b(priv);
1032                         if (path_a_ok == 0x03) {
1033                                 val32 = rtl8xxxu_read32(priv,
1034                                                         REG_RX_POWER_BEFORE_IQK_B_2);
1035                                 result[t][6] = (val32 >> 16) & 0x3ff;
1036                                 val32 = rtl8xxxu_read32(priv,
1037                                                         REG_RX_POWER_AFTER_IQK_B_2);
1038                                 result[t][7] = (val32 >> 16) & 0x3ff;
1039                                 break;
1040                         }
1041                 }
1042
1043                 if (!path_b_ok)
1044                         dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__);
1045 #endif
1046         }
1047
1048         /* Back to BB mode, load original value */
1049         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
1050         val32 &= 0x000000ff;
1051         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
1052
1053         if (t) {
1054                 /* Reload ADDA power saving parameters */
1055                 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
1056                                       RTL8XXXU_ADDA_REGS);
1057
1058                 /* Reload MAC parameters */
1059                 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
1060
1061                 /* Reload BB parameters */
1062                 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
1063                                       priv->bb_backup, RTL8XXXU_BB_REGS);
1064
1065                 /* Restore RX initial gain */
1066                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
1067                 val32 &= 0xffffff00;
1068                 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50);
1069                 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc);
1070
1071                 if (priv->tx_paths > 1) {
1072                         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1);
1073                         val32 &= 0xffffff00;
1074                         rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
1075                                          val32 | 0x50);
1076                         rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
1077                                          val32 | xb_agc);
1078                 }
1079
1080                 /* Load 0xe30 IQC default value */
1081                 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
1082                 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
1083         }
1084 }
1085
1086 static void rtl8723bu_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
1087 {
1088         struct device *dev = &priv->udev->dev;
1089         int result[4][8];       /* last is final result */
1090         int i, candidate;
1091         bool path_a_ok, path_b_ok;
1092         u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
1093         u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
1094         u32 val32, bt_control;
1095         s32 reg_tmp = 0;
1096         bool simu;
1097
1098         rtl8xxxu_gen2_prepare_calibrate(priv, 1);
1099
1100         memset(result, 0, sizeof(result));
1101         candidate = -1;
1102
1103         path_a_ok = false;
1104         path_b_ok = false;
1105
1106         bt_control = rtl8xxxu_read32(priv, REG_BT_CONTROL_8723BU);
1107
1108         for (i = 0; i < 3; i++) {
1109                 rtl8723bu_phy_iqcalibrate(priv, result, i);
1110
1111                 if (i == 1) {
1112                         simu = rtl8xxxu_gen2_simularity_compare(priv,
1113                                                                 result, 0, 1);
1114                         if (simu) {
1115                                 candidate = 0;
1116                                 break;
1117                         }
1118                 }
1119
1120                 if (i == 2) {
1121                         simu = rtl8xxxu_gen2_simularity_compare(priv,
1122                                                                 result, 0, 2);
1123                         if (simu) {
1124                                 candidate = 0;
1125                                 break;
1126                         }
1127
1128                         simu = rtl8xxxu_gen2_simularity_compare(priv,
1129                                                                 result, 1, 2);
1130                         if (simu) {
1131                                 candidate = 1;
1132                         } else {
1133                                 for (i = 0; i < 8; i++)
1134                                         reg_tmp += result[3][i];
1135
1136                                 if (reg_tmp)
1137                                         candidate = 3;
1138                                 else
1139                                         candidate = -1;
1140                         }
1141                 }
1142         }
1143
1144         for (i = 0; i < 4; i++) {
1145                 reg_e94 = result[i][0];
1146                 reg_e9c = result[i][1];
1147                 reg_ea4 = result[i][2];
1148                 reg_eac = result[i][3];
1149                 reg_eb4 = result[i][4];
1150                 reg_ebc = result[i][5];
1151                 reg_ec4 = result[i][6];
1152                 reg_ecc = result[i][7];
1153         }
1154
1155         if (candidate >= 0) {
1156                 reg_e94 = result[candidate][0];
1157                 priv->rege94 =  reg_e94;
1158                 reg_e9c = result[candidate][1];
1159                 priv->rege9c = reg_e9c;
1160                 reg_ea4 = result[candidate][2];
1161                 reg_eac = result[candidate][3];
1162                 reg_eb4 = result[candidate][4];
1163                 priv->regeb4 = reg_eb4;
1164                 reg_ebc = result[candidate][5];
1165                 priv->regebc = reg_ebc;
1166                 reg_ec4 = result[candidate][6];
1167                 reg_ecc = result[candidate][7];
1168                 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
1169                 dev_dbg(dev,
1170                         "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n",
1171                         __func__, reg_e94, reg_e9c,
1172                         reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
1173                 path_a_ok = true;
1174                 path_b_ok = true;
1175         } else {
1176                 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
1177                 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
1178         }
1179
1180         if (reg_e94 && candidate >= 0)
1181                 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
1182                                            candidate, (reg_ea4 == 0));
1183
1184         if (priv->tx_paths > 1 && reg_eb4)
1185                 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
1186                                            candidate, (reg_ec4 == 0));
1187
1188         rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg,
1189                            priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
1190
1191         rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, bt_control);
1192
1193         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
1194         val32 |= 0x80000;
1195         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
1196         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x18000);
1197         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
1198         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xe6177);
1199         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
1200         val32 |= 0x20;
1201         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
1202         rtl8xxxu_write_rfreg(priv, RF_A, 0x43, 0x300bd);
1203
1204         if (priv->rf_paths > 1)
1205                 dev_dbg(dev, "%s: 8723BU 2T not supported\n", __func__);
1206
1207         rtl8xxxu_gen2_prepare_calibrate(priv, 0);
1208 }
1209
1210 static int rtl8723bu_active_to_emu(struct rtl8xxxu_priv *priv)
1211 {
1212         u8 val8;
1213         u16 val16;
1214         u32 val32;
1215         int count, ret = 0;
1216
1217         /* Turn off RF */
1218         rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
1219
1220         /* Enable rising edge triggering interrupt */
1221         val16 = rtl8xxxu_read16(priv, REG_GPIO_INTM);
1222         val16 &= ~GPIO_INTM_EDGE_TRIG_IRQ;
1223         rtl8xxxu_write16(priv, REG_GPIO_INTM, val16);
1224
1225         /* Release WLON reset 0x04[16]= 1*/
1226         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1227         val32 |= APS_FSMCO_WLON_RESET;
1228         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
1229
1230         /* 0x0005[1] = 1 turn off MAC by HW state machine*/
1231         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1232         val8 |= BIT(1);
1233         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1234
1235         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
1236                 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1237                 if ((val8 & BIT(1)) == 0)
1238                         break;
1239                 udelay(10);
1240         }
1241
1242         if (!count) {
1243                 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
1244                          __func__);
1245                 ret = -EBUSY;
1246                 goto exit;
1247         }
1248
1249         /* Enable BT control XTAL setting */
1250         val8 = rtl8xxxu_read8(priv, REG_AFE_MISC);
1251         val8 &= ~AFE_MISC_WL_XTAL_CTRL;
1252         rtl8xxxu_write8(priv, REG_AFE_MISC, val8);
1253
1254         /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
1255         val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
1256         val8 |= SYS_ISO_ANALOG_IPS;
1257         rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
1258
1259         /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
1260         val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
1261         val8 &= ~LDOA15_ENABLE;
1262         rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
1263
1264 exit:
1265         return ret;
1266 }
1267
1268 static int rtl8723b_emu_to_active(struct rtl8xxxu_priv *priv)
1269 {
1270         u8 val8;
1271         u32 val32;
1272         int count, ret = 0;
1273
1274         /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface */
1275         val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
1276         val8 |= LDOA15_ENABLE;
1277         rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
1278
1279         /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
1280         val8 = rtl8xxxu_read8(priv, 0x0067);
1281         val8 &= ~BIT(4);
1282         rtl8xxxu_write8(priv, 0x0067, val8);
1283
1284         mdelay(1);
1285
1286         /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
1287         val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
1288         val8 &= ~SYS_ISO_ANALOG_IPS;
1289         rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
1290
1291         /* Disable SW LPS 0x04[10]= 0 */
1292         val32 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
1293         val32 &= ~APS_FSMCO_SW_LPS;
1294         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
1295
1296         /* Wait until 0x04[17] = 1 power ready */
1297         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
1298                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1299                 if (val32 & BIT(17))
1300                         break;
1301
1302                 udelay(10);
1303         }
1304
1305         if (!count) {
1306                 ret = -EBUSY;
1307                 goto exit;
1308         }
1309
1310         /* We should be able to optimize the following three entries into one */
1311
1312         /* Release WLON reset 0x04[16]= 1*/
1313         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1314         val32 |= APS_FSMCO_WLON_RESET;
1315         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
1316
1317         /* Disable HWPDN 0x04[15]= 0*/
1318         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1319         val32 &= ~APS_FSMCO_HW_POWERDOWN;
1320         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
1321
1322         /* Disable WL suspend*/
1323         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1324         val32 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE);
1325         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
1326
1327         /* Set, then poll until 0 */
1328         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1329         val32 |= APS_FSMCO_MAC_ENABLE;
1330         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
1331
1332         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
1333                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1334                 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
1335                         ret = 0;
1336                         break;
1337                 }
1338                 udelay(10);
1339         }
1340
1341         if (!count) {
1342                 ret = -EBUSY;
1343                 goto exit;
1344         }
1345
1346         /* Enable WL control XTAL setting */
1347         val8 = rtl8xxxu_read8(priv, REG_AFE_MISC);
1348         val8 |= AFE_MISC_WL_XTAL_CTRL;
1349         rtl8xxxu_write8(priv, REG_AFE_MISC, val8);
1350
1351         /* Enable falling edge triggering interrupt */
1352         val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 1);
1353         val8 |= BIT(1);
1354         rtl8xxxu_write8(priv, REG_GPIO_INTM + 1, val8);
1355
1356         /* Enable GPIO9 interrupt mode */
1357         val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2 + 1);
1358         val8 |= BIT(1);
1359         rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2 + 1, val8);
1360
1361         /* Enable GPIO9 input mode */
1362         val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2);
1363         val8 &= ~BIT(1);
1364         rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2, val8);
1365
1366         /* Enable HSISR GPIO[C:0] interrupt */
1367         val8 = rtl8xxxu_read8(priv, REG_HSIMR);
1368         val8 |= BIT(0);
1369         rtl8xxxu_write8(priv, REG_HSIMR, val8);
1370
1371         /* Enable HSISR GPIO9 interrupt */
1372         val8 = rtl8xxxu_read8(priv, REG_HSIMR + 2);
1373         val8 |= BIT(1);
1374         rtl8xxxu_write8(priv, REG_HSIMR + 2, val8);
1375
1376         val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL);
1377         val8 |= MULTI_WIFI_HW_ROF_EN;
1378         rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL, val8);
1379
1380         /* For GPIO9 internal pull high setting BIT(14) */
1381         val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL + 1);
1382         val8 |= BIT(6);
1383         rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL + 1, val8);
1384
1385 exit:
1386         return ret;
1387 }
1388
1389 static int rtl8723bu_power_on(struct rtl8xxxu_priv *priv)
1390 {
1391         u8 val8;
1392         u16 val16;
1393         u32 val32;
1394         int ret;
1395
1396         rtl8xxxu_disabled_to_emu(priv);
1397
1398         ret = rtl8723b_emu_to_active(priv);
1399         if (ret)
1400                 goto exit;
1401
1402         /*
1403          * Enable MAC DMA/WMAC/SCHEDULE/SEC block
1404          * Set CR bit10 to enable 32k calibration.
1405          */
1406         val16 = rtl8xxxu_read16(priv, REG_CR);
1407         val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
1408                   CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
1409                   CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
1410                   CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
1411                   CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
1412         rtl8xxxu_write16(priv, REG_CR, val16);
1413
1414         /*
1415          * BT coexist power on settings. This is identical for 1 and 2
1416          * antenna parts.
1417          */
1418         rtl8xxxu_write8(priv, REG_PAD_CTRL1 + 3, 0x20);
1419
1420         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1421         val16 |= SYS_FUNC_BBRSTB | SYS_FUNC_BB_GLB_RSTN;
1422         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
1423
1424         rtl8xxxu_write8(priv, REG_BT_CONTROL_8723BU + 1, 0x18);
1425         rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04);
1426         rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
1427         /* Antenna inverse */
1428         rtl8xxxu_write8(priv, 0xfe08, 0x01);
1429
1430         val16 = rtl8xxxu_read16(priv, REG_PWR_DATA);
1431         val16 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
1432         rtl8xxxu_write16(priv, REG_PWR_DATA, val16);
1433
1434         val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
1435         val32 |= LEDCFG0_DPDT_SELECT;
1436         rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
1437
1438         val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
1439         val8 &= ~PAD_CTRL1_SW_DPDT_SEL_DATA;
1440         rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
1441 exit:
1442         return ret;
1443 }
1444
1445 static void rtl8723bu_power_off(struct rtl8xxxu_priv *priv)
1446 {
1447         u8 val8;
1448         u16 val16;
1449
1450         rtl8xxxu_flush_fifo(priv);
1451
1452         /*
1453          * Disable TX report timer
1454          */
1455         val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
1456         val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE;
1457         rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
1458
1459         rtl8xxxu_write8(priv, REG_CR, 0x0000);
1460
1461         rtl8xxxu_active_to_lps(priv);
1462
1463         /* Reset Firmware if running in RAM */
1464         if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
1465                 rtl8xxxu_firmware_self_reset(priv);
1466
1467         /* Reset MCU */
1468         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1469         val16 &= ~SYS_FUNC_CPU_ENABLE;
1470         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
1471
1472         /* Reset MCU ready status */
1473         rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
1474
1475         rtl8723bu_active_to_emu(priv);
1476
1477         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1478         val8 |= BIT(3); /* APS_FSMCO_HW_SUSPEND */
1479         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1480
1481         /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
1482         val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
1483         val8 |= BIT(0);
1484         rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
1485 }
1486
1487 static void rtl8723b_enable_rf(struct rtl8xxxu_priv *priv)
1488 {
1489         struct h2c_cmd h2c;
1490         u32 val32;
1491         u8 val8;
1492
1493         val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA);
1494         val32 |= (BIT(22) | BIT(23));
1495         rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32);
1496
1497         /*
1498          * No indication anywhere as to what 0x0790 does. The 2 antenna
1499          * vendor code preserves bits 6-7 here.
1500          */
1501         rtl8xxxu_write8(priv, 0x0790, 0x05);
1502         /*
1503          * 0x0778 seems to be related to enabling the number of antennas
1504          * In the vendor driver halbtc8723b2ant_InitHwConfig() sets it
1505          * to 0x03, while halbtc8723b1ant_InitHwConfig() sets it to 0x01
1506          */
1507         rtl8xxxu_write8(priv, 0x0778, 0x01);
1508
1509         val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);
1510         val8 |= BIT(5);
1511         rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);
1512
1513         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_IQADJ_G1, 0x780);
1514
1515         rtl8723bu_write_btreg(priv, 0x3c, 0x15); /* BT TRx Mask on */
1516
1517         /*
1518          * Set BT grant to low
1519          */
1520         memset(&h2c, 0, sizeof(struct h2c_cmd));
1521         h2c.bt_grant.cmd = H2C_8723B_BT_GRANT;
1522         h2c.bt_grant.data = 0;
1523         rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_grant));
1524
1525         /*
1526          * WLAN action by PTA
1527          */
1528         rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x0c);
1529
1530         /*
1531          * BT select S0/S1 controlled by WiFi
1532          */
1533         val8 = rtl8xxxu_read8(priv, 0x0067);
1534         val8 |= BIT(5);
1535         rtl8xxxu_write8(priv, 0x0067, val8);
1536
1537         val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
1538         val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
1539         rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
1540
1541         /*
1542          * Bits 6/7 are marked in/out ... but for what?
1543          */
1544         rtl8xxxu_write8(priv, 0x0974, 0xff);
1545
1546         val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER);
1547         val32 |= (BIT(0) | BIT(1));
1548         rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32);
1549
1550         rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77);
1551
1552         val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
1553         val32 &= ~BIT(24);
1554         val32 |= BIT(23);
1555         rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
1556
1557         /*
1558          * Fix external switch Main->S1, Aux->S0
1559          */
1560         val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
1561         val8 &= ~BIT(0);
1562         rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
1563
1564         memset(&h2c, 0, sizeof(struct h2c_cmd));
1565         h2c.ant_sel_rsv.cmd = H2C_8723B_ANT_SEL_RSV;
1566         h2c.ant_sel_rsv.ant_inverse = 1;
1567         h2c.ant_sel_rsv.int_switch_type = 0;
1568         rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.ant_sel_rsv));
1569
1570         /*
1571          * Different settings per different antenna position.
1572          *      Antenna Position:   | Normal   Inverse
1573          * --------------------------------------------------
1574          * Antenna switch to BT:    |  0x280,   0x00
1575          * Antenna switch to WiFi:  |  0x0,     0x280
1576          * Antenna switch to PTA:   |  0x200,   0x80
1577          */
1578         rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x80);
1579
1580         /*
1581          * Software control, antenna at WiFi side
1582          */
1583 #ifdef NEED_PS_TDMA
1584         rtl8723bu_set_ps_tdma(priv, 0x08, 0x00, 0x00, 0x00, 0x00);
1585 #endif
1586
1587         rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555);
1588         rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555);
1589         rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
1590         rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
1591
1592         memset(&h2c, 0, sizeof(struct h2c_cmd));
1593         h2c.bt_info.cmd = H2C_8723B_BT_INFO;
1594         h2c.bt_info.data = BIT(0);
1595         rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_info));
1596
1597         memset(&h2c, 0, sizeof(struct h2c_cmd));
1598         h2c.ignore_wlan.cmd = H2C_8723B_BT_IGNORE_WLANACT;
1599         h2c.ignore_wlan.data = 0;
1600         rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.ignore_wlan));
1601 }
1602
1603 static void rtl8723bu_init_aggregation(struct rtl8xxxu_priv *priv)
1604 {
1605         u32 agg_rx;
1606         u8 agg_ctrl;
1607
1608         /*
1609          * For now simply disable RX aggregation
1610          */
1611         agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL);
1612         agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN;
1613
1614         agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH);
1615         agg_rx &= ~RXDMA_USB_AGG_ENABLE;
1616         agg_rx &= ~0xff0f;
1617
1618         rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
1619         rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx);
1620 }
1621
1622 static void rtl8723bu_init_statistics(struct rtl8xxxu_priv *priv)
1623 {
1624         u32 val32;
1625
1626         /* Time duration for NHM unit: 4us, 0x2710=40ms */
1627         rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0x2710);
1628         rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff);
1629         rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff52);
1630         rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff);
1631         /* TH8 */
1632         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
1633         val32 |= 0xff;
1634         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
1635         /* Enable CCK */
1636         val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B);
1637         val32 |= BIT(8) | BIT(9) | BIT(10);
1638         rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32);
1639         /* Max power amongst all RX antennas */
1640         val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC);
1641         val32 |= BIT(7);
1642         rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32);
1643 }
1644
1645 struct rtl8xxxu_fileops rtl8723bu_fops = {
1646         .parse_efuse = rtl8723bu_parse_efuse,
1647         .load_firmware = rtl8723bu_load_firmware,
1648         .power_on = rtl8723bu_power_on,
1649         .power_off = rtl8723bu_power_off,
1650         .reset_8051 = rtl8723bu_reset_8051,
1651         .llt_init = rtl8xxxu_auto_llt_table,
1652         .init_phy_bb = rtl8723bu_init_phy_bb,
1653         .init_phy_rf = rtl8723bu_init_phy_rf,
1654         .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection,
1655         .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate,
1656         .config_channel = rtl8xxxu_gen2_config_channel,
1657         .parse_rx_desc = rtl8xxxu_parse_rxdesc24,
1658         .init_aggregation = rtl8723bu_init_aggregation,
1659         .init_statistics = rtl8723bu_init_statistics,
1660         .enable_rf = rtl8723b_enable_rf,
1661         .disable_rf = rtl8xxxu_gen2_disable_rf,
1662         .usb_quirks = rtl8xxxu_gen2_usb_quirks,
1663         .set_tx_power = rtl8723b_set_tx_power,
1664         .update_rate_mask = rtl8xxxu_gen2_update_rate_mask,
1665         .report_connect = rtl8xxxu_gen2_report_connect,
1666         .fill_txdesc = rtl8xxxu_fill_txdesc_v2,
1667         .writeN_block_size = 1024,
1668         .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40),
1669         .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24),
1670         .has_s0s1 = 1,
1671         .has_tx_report = 1,
1672         .gen2_thermal_meter = 1,
1673         .needs_full_init = 1,
1674         .adda_1t_init = 0x01c00014,
1675         .adda_1t_path_on = 0x01c00014,
1676         .adda_2t_path_on_a = 0x01c00014,
1677         .adda_2t_path_on_b = 0x01c00014,
1678         .trxff_boundary = 0x3f7f,
1679         .pbp_rx = PBP_PAGE_SIZE_256,
1680         .pbp_tx = PBP_PAGE_SIZE_256,
1681         .mactable = rtl8723b_mac_init_table,
1682         .total_page_num = TX_TOTAL_PAGE_NUM_8723B,
1683         .page_num_hi = TX_PAGE_NUM_HI_PQ_8723B,
1684         .page_num_lo = TX_PAGE_NUM_LO_PQ_8723B,
1685         .page_num_norm = TX_PAGE_NUM_NORM_PQ_8723B,
1686 };