2 * Copyright (c) 2014 - 2016 Jes Sorensen <Jes.Sorensen@redhat.com>
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * Register definitions taken from original Realtek rtl8723au driver
16 #include <asm/byteorder.h>
18 #define RTL8XXXU_DEBUG_REG_WRITE 0x01
19 #define RTL8XXXU_DEBUG_REG_READ 0x02
20 #define RTL8XXXU_DEBUG_RFREG_WRITE 0x04
21 #define RTL8XXXU_DEBUG_RFREG_READ 0x08
22 #define RTL8XXXU_DEBUG_CHANNEL 0x10
23 #define RTL8XXXU_DEBUG_TX 0x20
24 #define RTL8XXXU_DEBUG_TX_DUMP 0x40
25 #define RTL8XXXU_DEBUG_RX 0x80
26 #define RTL8XXXU_DEBUG_RX_DUMP 0x100
27 #define RTL8XXXU_DEBUG_USB 0x200
28 #define RTL8XXXU_DEBUG_KEY 0x400
29 #define RTL8XXXU_DEBUG_H2C 0x800
30 #define RTL8XXXU_DEBUG_ACTION 0x1000
31 #define RTL8XXXU_DEBUG_EFUSE 0x2000
33 #define RTW_USB_CONTROL_MSG_TIMEOUT 500
34 #define RTL8XXXU_MAX_REG_POLL 500
35 #define USB_INTR_CONTENT_LENGTH 56
37 #define RTL8XXXU_OUT_ENDPOINTS 4
39 #define REALTEK_USB_READ 0xc0
40 #define REALTEK_USB_WRITE 0x40
41 #define REALTEK_USB_CMD_REQ 0x05
42 #define REALTEK_USB_CMD_IDX 0x00
44 #define TX_TOTAL_PAGE_NUM 0xf8
45 #define TX_TOTAL_PAGE_NUM_8192E 0xf3
46 /* (HPQ + LPQ + NPQ + PUBQ) = TX_TOTAL_PAGE_NUM */
47 #define TX_PAGE_NUM_PUBQ 0xe7
48 #define TX_PAGE_NUM_HI_PQ 0x0c
49 #define TX_PAGE_NUM_LO_PQ 0x02
50 #define TX_PAGE_NUM_NORM_PQ 0x02
52 #define TX_PAGE_NUM_PUBQ_8192E 0xe7
53 #define TX_PAGE_NUM_HI_PQ_8192E 0x08
54 #define TX_PAGE_NUM_LO_PQ_8192E 0x0c
55 #define TX_PAGE_NUM_NORM_PQ_8192E 0x00
57 #define RTL_FW_PAGE_SIZE 4096
58 #define RTL8XXXU_FIRMWARE_POLL_MAX 1000
60 #define RTL8723A_CHANNEL_GROUPS 3
61 #define RTL8723A_MAX_RF_PATHS 2
62 #define RTL8723B_CHANNEL_GROUPS 6
63 #define RTL8723B_TX_COUNT 4
64 #define RTL8723B_MAX_RF_PATHS 4
65 #define RTL8XXXU_MAX_CHANNEL_GROUPS 6
66 #define RF6052_MAX_TX_PWR 0x3f
68 #define EFUSE_MAP_LEN 512
69 #define EFUSE_MAX_SECTION_8723A 64
70 #define EFUSE_REAL_CONTENT_LEN_8723A 512
71 #define EFUSE_BT_MAP_LEN_8723A 1024
72 #define EFUSE_MAX_WORD_UNIT 4
74 enum rtl8xxxu_rtl_chip {
98 enum rtl8xxxu_rx_type {
104 struct rtl8xxxu_rxdesc16 {
105 #ifdef __LITTLE_ENDIAN
240 struct rtl8xxxu_rxdesc24 {
241 #ifdef __LITTLE_ENDIAN
263 u32 a1fit:4; /* 16 */
278 u32 rx_is_qos:1; /* 16 */
291 u32 usb_agg_pktnum:8; /* 16 */
347 u32 usb_agg_pktnum:8;
348 u32 dummy3_1:2; /* 16 */
365 struct rtl8xxxu_txdesc32 {
379 struct rtl8xxxu_txdesc40 {
395 /* CCK Rates, TxHT = 0 */
396 #define DESC_RATE_1M 0x00
397 #define DESC_RATE_2M 0x01
398 #define DESC_RATE_5_5M 0x02
399 #define DESC_RATE_11M 0x03
401 /* OFDM Rates, TxHT = 0 */
402 #define DESC_RATE_6M 0x04
403 #define DESC_RATE_9M 0x05
404 #define DESC_RATE_12M 0x06
405 #define DESC_RATE_18M 0x07
406 #define DESC_RATE_24M 0x08
407 #define DESC_RATE_36M 0x09
408 #define DESC_RATE_48M 0x0a
409 #define DESC_RATE_54M 0x0b
411 /* MCS Rates, TxHT = 1 */
412 #define DESC_RATE_MCS0 0x0c
413 #define DESC_RATE_MCS1 0x0d
414 #define DESC_RATE_MCS2 0x0e
415 #define DESC_RATE_MCS3 0x0f
416 #define DESC_RATE_MCS4 0x10
417 #define DESC_RATE_MCS5 0x11
418 #define DESC_RATE_MCS6 0x12
419 #define DESC_RATE_MCS7 0x13
420 #define DESC_RATE_MCS8 0x14
421 #define DESC_RATE_MCS9 0x15
422 #define DESC_RATE_MCS10 0x16
423 #define DESC_RATE_MCS11 0x17
424 #define DESC_RATE_MCS12 0x18
425 #define DESC_RATE_MCS13 0x19
426 #define DESC_RATE_MCS14 0x1a
427 #define DESC_RATE_MCS15 0x1b
428 #define DESC_RATE_MCS15_SG 0x1c
429 #define DESC_RATE_MCS32 0x20
431 #define TXDESC_OFFSET_SZ 0
432 #define TXDESC_OFFSET_SHT 16
434 #define TXDESC_BMC BIT(24)
435 #define TXDESC_LSG BIT(26)
436 #define TXDESC_FSG BIT(27)
437 #define TXDESC_OWN BIT(31)
439 #define TXDESC_BROADMULTICAST BIT(0)
440 #define TXDESC_HTC BIT(1)
441 #define TXDESC_LAST_SEGMENT BIT(2)
442 #define TXDESC_FIRST_SEGMENT BIT(3)
443 #define TXDESC_LINIP BIT(4)
444 #define TXDESC_NO_ACM BIT(5)
445 #define TXDESC_GF BIT(6)
446 #define TXDESC_OWN BIT(7)
451 * Bits 0-7 differ dependent on chip generation. For 8723au bits 5/6 are
452 * aggregation enable and break respectively. For 8723bu, bits 0-7 are macid.
454 #define TXDESC_PKT_OFFSET_SZ 0
455 #define TXDESC32_AGG_ENABLE BIT(5)
456 #define TXDESC32_AGG_BREAK BIT(6)
457 #define TXDESC40_MACID_SHIFT 0
458 #define TXDESC40_MACID_MASK 0x00f0
459 #define TXDESC_QUEUE_SHIFT 8
460 #define TXDESC_QUEUE_MASK 0x1f00
461 #define TXDESC_QUEUE_BK 0x2
462 #define TXDESC_QUEUE_BE 0x0
463 #define TXDESC_QUEUE_VI 0x5
464 #define TXDESC_QUEUE_VO 0x7
465 #define TXDESC_QUEUE_BEACON 0x10
466 #define TXDESC_QUEUE_HIGH 0x11
467 #define TXDESC_QUEUE_MGNT 0x12
468 #define TXDESC_QUEUE_CMD 0x13
469 #define TXDESC_QUEUE_MAX (TXDESC_QUEUE_CMD + 1)
470 #define TXDESC40_RDG_NAV_EXT BIT(13)
471 #define TXDESC40_LSIG_TXOP_ENABLE BIT(14)
472 #define TXDESC40_PIFS BIT(15)
474 #define DESC_RATE_ID_SHIFT 16
475 #define DESC_RATE_ID_MASK 0xf
476 #define TXDESC_NAVUSEHDR BIT(20)
477 #define TXDESC_SEC_RC4 0x00400000
478 #define TXDESC_SEC_AES 0x00c00000
479 #define TXDESC_PKT_OFFSET_SHIFT 26
480 #define TXDESC_AGG_EN BIT(29)
481 #define TXDESC_HWPC BIT(31)
484 #define TXDESC40_PAID_SHIFT 0
485 #define TXDESC40_PAID_MASK 0x1ff
486 #define TXDESC40_CCA_RTS_SHIFT 10
487 #define TXDESC40_CCA_RTS_MASK 0xc00
488 #define TXDESC40_AGG_ENABLE BIT(12)
489 #define TXDESC40_RDG_ENABLE BIT(13)
490 #define TXDESC40_AGG_BREAK BIT(16)
491 #define TXDESC40_MORE_FRAG BIT(17)
492 #define TXDESC40_RAW BIT(18)
493 #define TXDESC32_ACK_REPORT BIT(19)
494 #define TXDESC40_SPE_RPT BIT(19)
495 #define TXDESC_AMPDU_DENSITY_SHIFT 20
496 #define TXDESC40_BT_INT BIT(23)
497 #define TXDESC40_GID_SHIFT 24
500 #define TXDESC40_USE_DRIVER_RATE BIT(8)
501 #define TXDESC40_CTS_SELF_ENABLE BIT(11)
502 #define TXDESC40_RTS_CTS_ENABLE BIT(12)
503 #define TXDESC40_HW_RTS_ENABLE BIT(13)
504 #define TXDESC32_SEQ_SHIFT 16
505 #define TXDESC32_SEQ_MASK 0x0fff0000
508 #define TXDESC32_RTS_RATE_SHIFT 0
509 #define TXDESC32_RTS_RATE_MASK 0x3f
510 #define TXDESC32_QOS BIT(6)
511 #define TXDESC32_HW_SEQ_ENABLE BIT(7)
512 #define TXDESC32_USE_DRIVER_RATE BIT(8)
513 #define TXDESC_DISABLE_DATA_FB BIT(10)
514 #define TXDESC32_CTS_SELF_ENABLE BIT(11)
515 #define TXDESC32_RTS_CTS_ENABLE BIT(12)
516 #define TXDESC32_HW_RTS_ENABLE BIT(13)
517 #define TXDESC_PRIME_CH_OFF_LOWER BIT(20)
518 #define TXDESC_PRIME_CH_OFF_UPPER BIT(21)
519 #define TXDESC32_SHORT_PREAMBLE BIT(24)
520 #define TXDESC_DATA_BW BIT(25)
521 #define TXDESC_RTS_DATA_BW BIT(27)
522 #define TXDESC_RTS_PRIME_CH_OFF_LOWER BIT(28)
523 #define TXDESC_RTS_PRIME_CH_OFF_UPPER BIT(29)
524 #define TXDESC40_DATA_RATE_FB_SHIFT 8
525 #define TXDESC40_DATA_RATE_FB_MASK 0x00001f00
526 #define TXDESC40_RETRY_LIMIT_ENABLE BIT(17)
527 #define TXDESC40_RETRY_LIMIT_SHIFT 18
528 #define TXDESC40_RETRY_LIMIT_MASK 0x00fc0000
529 #define TXDESC40_RTS_RATE_SHIFT 24
530 #define TXDESC40_RTS_RATE_MASK 0x3f000000
533 #define TXDESC40_SHORT_PREAMBLE BIT(4)
534 #define TXDESC32_SHORT_GI BIT(6)
535 #define TXDESC_CCX_TAG BIT(7)
536 #define TXDESC32_RETRY_LIMIT_ENABLE BIT(17)
537 #define TXDESC32_RETRY_LIMIT_SHIFT 18
538 #define TXDESC32_RETRY_LIMIT_MASK 0x00fc0000
541 #define TXDESC_MAX_AGG_SHIFT 11
544 #define TXDESC40_HW_SEQ_ENABLE BIT(15)
547 #define TXDESC40_SEQ_SHIFT 12
548 #define TXDESC40_SEQ_MASK 0x00fff000
550 struct phy_rx_agc_info {
551 #ifdef __LITTLE_ENDIAN
558 struct rtl8723au_phy_stats {
559 struct phy_rx_agc_info path_agc[RTL8723A_MAX_RF_PATHS];
560 u8 ch_corr[RTL8723A_MAX_RF_PATHS];
561 u8 cck_sig_qual_ofdm_pwdb_all;
562 u8 cck_agc_rpt_ofdm_cfosho_a;
563 u8 cck_rpt_b_ofdm_cfosho_b;
565 u8 noise_power_db_msb;
566 u8 path_cfotail[RTL8723A_MAX_RF_PATHS];
567 u8 pcts_mask[RTL8723A_MAX_RF_PATHS];
568 s8 stream_rxevm[RTL8723A_MAX_RF_PATHS];
569 u8 path_rxsnr[RTL8723A_MAX_RF_PATHS];
570 u8 noise_power_db_lsb;
572 u8 stream_csi[RTL8723A_MAX_RF_PATHS];
573 u8 stream_target_csi[RTL8723A_MAX_RF_PATHS];
577 #ifdef __LITTLE_ENDIAN
578 u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */
583 u8 antenna_select_b:1;
585 #else /* _BIG_ENDIAN_ */
587 u8 antenna_select_b:1;
592 u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */
599 #define RTL8XXXU_ADDA_REGS 16
600 #define RTL8XXXU_MAC_REGS 4
601 #define RTL8XXXU_BB_REGS 9
603 struct rtl8xxxu_firmware_header {
604 __le16 signature; /* 92C0: test chip; 92C,
608 u8 category; /* AP/NIC and USB/PCI */
611 __le16 major_version; /* FW Version */
612 u8 minor_version; /* FW Subversion, default 0x00 */
615 u8 month; /* Release time Month field */
616 u8 date; /* Release time Date field */
617 u8 hour; /* Release time Hour field */
618 u8 minute; /* Release time Minute field */
620 __le16 ramcodesize; /* Size of RAM code */
623 __le32 svn_idx; /* SVN entry index */
633 * 8723au/8192cu/8188ru required base power index offset tables.
635 struct rtl8xxxu_power_base {
658 * The 8723au has 3 channel groups: 1-3, 4-9, and 10-14
660 struct rtl8723au_idx {
661 #ifdef __LITTLE_ENDIAN
668 } __attribute__((packed));
670 struct rtl8723au_efuse {
673 u8 cck_tx_power_index_A[3]; /* 0x10 */
674 u8 cck_tx_power_index_B[3];
675 u8 ht40_1s_tx_power_index_A[3]; /* 0x16 */
676 u8 ht40_1s_tx_power_index_B[3];
678 * The following entries are half-bytes split as:
679 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed
681 struct rtl8723au_idx ht20_tx_power_index_diff[3];
682 struct rtl8723au_idx ofdm_tx_power_index_diff[3];
683 struct rtl8723au_idx ht40_max_power_offset[3];
684 struct rtl8723au_idx ht20_max_power_offset[3];
685 u8 channel_plan; /* 0x28 */
693 u8 version /* 0x30 */;
694 u8 customer_id_major;
695 u8 customer_id_minor;
697 u8 chipset; /* 0x34 */
703 u8 mac_addr[ETH_ALEN]; /* 0xc6 */
707 u8 device_name[0x29]; /* 0xd7 */
710 struct rtl8192cu_efuse {
719 __le16 smid; /* 0x10 */
721 u8 mac_addr[ETH_ALEN]; /* 0x16 */
725 u8 device_name[0x14]; /* 0x28 */
726 u8 res4[0x1e]; /* 0x3c */
727 u8 cck_tx_power_index_A[3]; /* 0x5a */
728 u8 cck_tx_power_index_B[3];
729 u8 ht40_1s_tx_power_index_A[3]; /* 0x60 */
730 u8 ht40_1s_tx_power_index_B[3];
732 * The following entries are half-bytes split as:
733 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed
735 struct rtl8723au_idx ht40_2s_tx_power_index_diff[3];
736 struct rtl8723au_idx ht20_tx_power_index_diff[3]; /* 0x69 */
737 struct rtl8723au_idx ofdm_tx_power_index_diff[3];
738 struct rtl8723au_idx ht40_max_power_offset[3]; /* 0x6f */
739 struct rtl8723au_idx ht20_max_power_offset[3];
740 u8 channel_plan; /* 0x75 */
743 u8 thermal_meter; /* xtal_k */ /* 0x78 */
748 u8 res5[1]; /* 0x7d */
753 struct rtl8723bu_pwr_idx {
754 #ifdef __LITTLE_ENDIAN
765 } __attribute__((packed));
767 struct rtl8723bu_efuse_tx_power {
770 struct rtl8723au_idx ht20_ofdm_1s_diff;
771 struct rtl8723bu_pwr_idx pwr_diff[3];
772 u8 dummy5g[24]; /* max channel group (14) + power diff offset (10) */
775 struct rtl8723bu_efuse {
778 struct rtl8723bu_efuse_tx_power tx_power_index_A; /* 0x10 */
779 struct rtl8723bu_efuse_tx_power tx_power_index_B; /* 0x3a */
780 struct rtl8723bu_efuse_tx_power tx_power_index_C; /* 0x64 */
781 struct rtl8723bu_efuse_tx_power tx_power_index_D; /* 0x8e */
782 u8 channel_plan; /* 0xb8 */
786 u8 pa_type; /* 0xbc */
787 u8 lna_type_2g; /* 0xbd */
790 u8 rf_feature_option;
793 u8 eeprom_customer_id;
795 u8 tx_pwr_calibrate_rate;
796 u8 rf_antenna_option; /* 0xc9 */
799 u8 usb_optional_function;
802 u8 serial[0x0b]; /* 0xf5 */
807 u8 mac_addr[ETH_ALEN]; /* 0x107 */
809 u8 vendor_name[0x07];
811 u8 device_name[0x14];
813 u8 package_type; /* 0x1fb */
817 struct rtl8192eu_efuse_tx_power {
820 struct rtl8723au_idx ht20_ofdm_1s_diff;
821 struct rtl8723bu_pwr_idx pwr_diff[3];
822 u8 dummy5g[24]; /* max channel group (14) + power diff offset (10) */
825 struct rtl8192eu_efuse {
828 struct rtl8192eu_efuse_tx_power tx_power_index_A; /* 0x10 */
829 struct rtl8192eu_efuse_tx_power tx_power_index_B; /* 0x3a */
831 u8 channel_plan; /* 0xb8 */
835 u8 pa_type; /* 0xbc */
836 u8 lna_type_2g; /* 0xbd */
838 u8 lna_type_5g; /* 0xbf */
841 u8 rf_feature_option;
844 u8 eeprom_customer_id;
846 u8 rf_antenna_option; /* 0xc9 */
852 u8 usb_optional_function;
854 u8 mac_addr[ETH_ALEN]; /* 0xd7 */
858 u8 device_name[0x0b]; /* 0xe8 */
860 u8 serial[0x0b]; /* 0xf5 */
862 u8 unknown[0x0d]; /* 0x130 */
866 struct rtl8xxxu_reg8val {
871 struct rtl8xxxu_reg32val {
876 struct rtl8xxxu_rfregval {
881 enum rtl8xxxu_rfpath {
886 struct rtl8xxxu_rfregs {
895 #define H2C_MAX_MBOX 4
896 #define H2C_EXT BIT(7)
897 #define H2C_JOIN_BSS_DISCONNECT 0
898 #define H2C_JOIN_BSS_CONNECT 1
901 * H2C (firmware) commands differ between the older generation chips
902 * 8188[cr]u, 819[12]cu, and 8723au, and the more recent chips 8723bu,
903 * 8192[de]u, 8192eu, and 8812.
906 H2C_SET_POWER_MODE = 1,
907 H2C_JOIN_BSS_REPORT = 2,
909 H2C_SET_RATE_MASK = (6 | H2C_EXT),
916 H2C_8723B_RSVD_PAGE = 0x00,
917 H2C_8723B_MEDIA_STATUS_RPT = 0x01,
918 H2C_8723B_SCAN_ENABLE = 0x02,
919 H2C_8723B_KEEP_ALIVE = 0x03,
920 H2C_8723B_DISCON_DECISION = 0x04,
921 H2C_8723B_PSD_OFFLOAD = 0x05,
922 H2C_8723B_AP_OFFLOAD = 0x08,
923 H2C_8723B_BCN_RSVDPAGE = 0x09,
924 H2C_8723B_PROBERSP_RSVDPAGE = 0x0A,
925 H2C_8723B_FCS_RSVDPAGE = 0x10,
926 H2C_8723B_FCS_INFO = 0x11,
927 H2C_8723B_AP_WOW_GPIO_CTRL = 0x13,
930 * PoweSave Class: 001
932 H2C_8723B_SET_PWR_MODE = 0x20,
933 H2C_8723B_PS_TUNING_PARA = 0x21,
934 H2C_8723B_PS_TUNING_PARA2 = 0x22,
935 H2C_8723B_P2P_LPS_PARAM = 0x23,
936 H2C_8723B_P2P_PS_OFFLOAD = 0x24,
937 H2C_8723B_PS_SCAN_ENABLE = 0x25,
938 H2C_8723B_SAP_PS_ = 0x26,
939 H2C_8723B_INACTIVE_PS_ = 0x27,
940 H2C_8723B_FWLPS_IN_IPS_ = 0x28,
943 * Dynamic Mechanism Class: 010
945 H2C_8723B_MACID_CFG_RAID = 0x40,
946 H2C_8723B_TXBF = 0x41,
947 H2C_8723B_RSSI_SETTING = 0x42,
948 H2C_8723B_AP_REQ_TXRPT = 0x43,
949 H2C_8723B_INIT_RATE_COLLECT = 0x44,
954 H2C_8723B_B_TYPE_TDMA = 0x60,
955 H2C_8723B_BT_INFO = 0x61,
956 H2C_8723B_FORCE_BT_TXPWR = 0x62,
957 H2C_8723B_BT_IGNORE_WLANACT = 0x63,
958 H2C_8723B_DAC_SWING_VALUE = 0x64,
959 H2C_8723B_ANT_SEL_RSV = 0x65,
960 H2C_8723B_WL_OPMODE = 0x66,
961 H2C_8723B_BT_MP_OPER = 0x67,
962 H2C_8723B_BT_CONTROL = 0x68,
963 H2C_8723B_BT_WIFI_CTRL = 0x69,
964 H2C_8723B_BT_FW_PATCH = 0x6a,
965 H2C_8723B_BT_WLAN_CALIBRATION = 0x6d,
966 H2C_8723B_BT_GRANT = 0x6e,
971 H2C_8723B_WOWLAN = 0x80,
972 H2C_8723B_REMOTE_WAKE_CTRL = 0x81,
973 H2C_8723B_AOAC_GLOBAL_INFO = 0x82,
974 H2C_8723B_AOAC_RSVD_PAGE = 0x83,
975 H2C_8723B_AOAC_RSVD_PAGE2 = 0x84,
976 H2C_8723B_D0_SCAN_OFFLOAD_CTRL = 0x85,
977 H2C_8723B_D0_SCAN_OFFLOAD_INFO = 0x86,
978 H2C_8723B_CHNL_SWITCH_OFFLOAD = 0x87,
980 H2C_8723B_RESET_TSF = 0xC0,
1013 } __packed media_status_rpt;
1025 * [4:5] - VHT enable
1034 } __packed b_macid_cfg;
1042 } __packed b_type_dma;
1053 } __packed bt_mp_oper;
1057 } __packed bt_wlan_calibration;
1061 } __packed ignore_wlan;
1066 } __packed ant_sel_rsv;
1070 } __packed bt_grant;
1074 enum c2h_evt_8723b {
1075 C2H_8723B_DEBUG = 0,
1077 C2H_8723B_AP_RPT_RSP = 2,
1078 C2H_8723B_CCX_TX_RPT = 3,
1079 C2H_8723B_BT_RSSI = 4,
1080 C2H_8723B_BT_OP_MODE = 5,
1081 C2H_8723B_EXT_RA_RPT = 6,
1082 C2H_8723B_BT_INFO = 9,
1083 C2H_8723B_HW_INFO_EXCH = 0x0a,
1084 C2H_8723B_BT_MP_INFO = 0x0b,
1085 C2H_8723B_RA_REPORT = 0x0c,
1086 C2H_8723B_FW_DEBUG = 0xff,
1089 enum bt_info_src_8723b {
1090 BT_INFO_SRC_8723B_WIFI_FW = 0x0,
1091 BT_INFO_SRC_8723B_BT_RSP = 0x1,
1092 BT_INFO_SRC_8723B_BT_ACTIVE_SEND = 0x2,
1095 enum bt_mp_oper_opcode_8723b {
1096 BT_MP_OP_GET_BT_VERSION = 0x00,
1097 BT_MP_OP_RESET = 0x01,
1098 BT_MP_OP_TEST_CTRL = 0x02,
1099 BT_MP_OP_SET_BT_MODE = 0x03,
1100 BT_MP_OP_SET_CHNL_TX_GAIN = 0x04,
1101 BT_MP_OP_SET_PKT_TYPE_LEN = 0x05,
1102 BT_MP_OP_SET_PKT_CNT_L_PL_TYPE = 0x06,
1103 BT_MP_OP_SET_PKT_CNT_H_PKT_INTV = 0x07,
1104 BT_MP_OP_SET_PKT_HEADER = 0x08,
1105 BT_MP_OP_SET_WHITENCOEFF = 0x09,
1106 BT_MP_OP_SET_BD_ADDR_L = 0x0a,
1107 BT_MP_OP_SET_BD_ADDR_H = 0x0b,
1108 BT_MP_OP_WRITE_REG_ADDR = 0x0c,
1109 BT_MP_OP_WRITE_REG_VALUE = 0x0d,
1110 BT_MP_OP_GET_BT_STATUS = 0x0e,
1111 BT_MP_OP_GET_BD_ADDR_L = 0x0f,
1112 BT_MP_OP_GET_BD_ADDR_H = 0x10,
1113 BT_MP_OP_READ_REG = 0x11,
1114 BT_MP_OP_SET_TARGET_BD_ADDR_L = 0x12,
1115 BT_MP_OP_SET_TARGET_BD_ADDR_H = 0x13,
1116 BT_MP_OP_SET_TX_POWER_CALIBRATION = 0x14,
1117 BT_MP_OP_GET_RX_PKT_CNT_L = 0x15,
1118 BT_MP_OP_GET_RX_PKT_CNT_H = 0x16,
1119 BT_MP_OP_GET_RX_ERROR_BITS_L = 0x17,
1120 BT_MP_OP_GET_RX_ERROR_BITS_H = 0x18,
1121 BT_MP_OP_GET_RSSI = 0x19,
1122 BT_MP_OP_GET_CFO_HDR_QUALITY_L = 0x1a,
1123 BT_MP_OP_GET_CFO_HDR_QUALITY_H = 0x1b,
1124 BT_MP_OP_GET_TARGET_BD_ADDR_L = 0x1c,
1125 BT_MP_OP_GET_TARGET_BD_ADDR_H = 0x1d,
1126 BT_MP_OP_GET_AFH_MAP_L = 0x1e,
1127 BT_MP_OP_GET_AFH_MAP_M = 0x1f,
1128 BT_MP_OP_GET_AFH_MAP_H = 0x20,
1129 BT_MP_OP_GET_AFH_STATUS = 0x21,
1130 BT_MP_OP_SET_TRACKING_INTERVAL = 0x22,
1131 BT_MP_OP_SET_THERMAL_METER = 0x23,
1132 BT_MP_OP_ENABLE_CFO_TRACKING = 0x24,
1135 struct rtl8723bu_c2h {
1149 } __packed bt_mp_info;
1151 u8 response_source:4;
1183 } __packed ra_report;
1187 struct rtl8xxxu_fileops;
1189 struct rtl8xxxu_priv {
1190 struct ieee80211_hw *hw;
1191 struct usb_device *udev;
1192 struct rtl8xxxu_fileops *fops;
1194 spinlock_t tx_urb_lock;
1195 struct list_head tx_urb_free_list;
1196 int tx_urb_free_count;
1199 spinlock_t rx_urb_lock;
1200 struct list_head rx_urb_pending_list;
1201 int rx_urb_pending_count;
1203 struct work_struct rx_urb_wq;
1205 u8 mac_addr[ETH_ALEN];
1207 char chip_vendor[8];
1208 u8 cck_tx_power_index_A[RTL8XXXU_MAX_CHANNEL_GROUPS];
1209 u8 cck_tx_power_index_B[RTL8XXXU_MAX_CHANNEL_GROUPS];
1210 u8 ht40_1s_tx_power_index_A[RTL8XXXU_MAX_CHANNEL_GROUPS];
1211 u8 ht40_1s_tx_power_index_B[RTL8XXXU_MAX_CHANNEL_GROUPS];
1213 * The following entries are half-bytes split as:
1214 * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed
1216 struct rtl8723au_idx ht40_2s_tx_power_index_diff[
1217 RTL8723A_CHANNEL_GROUPS];
1218 struct rtl8723au_idx ht20_tx_power_index_diff[RTL8723A_CHANNEL_GROUPS];
1219 struct rtl8723au_idx ofdm_tx_power_index_diff[RTL8723A_CHANNEL_GROUPS];
1220 struct rtl8723au_idx ht40_max_power_offset[RTL8723A_CHANNEL_GROUPS];
1221 struct rtl8723au_idx ht20_max_power_offset[RTL8723A_CHANNEL_GROUPS];
1223 * Newer generation chips only keep power diffs per TX count,
1224 * not per channel group.
1226 struct rtl8723au_idx ofdm_tx_power_diff[RTL8723B_TX_COUNT];
1227 struct rtl8723au_idx ht20_tx_power_diff[RTL8723B_TX_COUNT];
1228 struct rtl8723au_idx ht40_tx_power_diff[RTL8723B_TX_COUNT];
1229 struct rtl8xxxu_power_base *power_base;
1232 u32 is_multi_func:1;
1234 u32 has_bluetooth:1;
1235 u32 enable_bluetooth:1;
1240 u32 has_polarity_ctrl:1;
1243 u32 usb_interrupts:1;
1244 u32 ep_tx_high_queue:1;
1245 u32 ep_tx_normal_queue:1;
1246 u32 ep_tx_low_queue:1;
1249 unsigned int pipe_interrupt;
1250 unsigned int pipe_in;
1251 unsigned int pipe_out[TXDESC_QUEUE_MAX];
1252 u8 out_ep[RTL8XXXU_OUT_ENDPOINTS];
1264 struct mutex h2c_mutex;
1266 struct usb_anchor rx_anchor;
1267 struct usb_anchor tx_anchor;
1268 struct usb_anchor int_anchor;
1269 struct rtl8xxxu_firmware_header *fw_data;
1271 struct mutex usb_buf_mutex;
1278 u8 raw[EFUSE_MAP_LEN];
1279 struct rtl8723au_efuse efuse8723;
1280 struct rtl8723bu_efuse efuse8723bu;
1281 struct rtl8192cu_efuse efuse8192;
1282 struct rtl8192eu_efuse efuse8192eu;
1284 u32 adda_backup[RTL8XXXU_ADDA_REGS];
1285 u32 mac_backup[RTL8XXXU_MAC_REGS];
1286 u32 bb_backup[RTL8XXXU_BB_REGS];
1287 u32 bb_recovery_backup[RTL8XXXU_BB_REGS];
1288 enum rtl8xxxu_rtl_chip rtl_chip;
1291 u8 int_buf[USB_INTR_CONTENT_LENGTH];
1294 struct rtl8xxxu_rx_urb {
1296 struct ieee80211_hw *hw;
1297 struct list_head list;
1300 struct rtl8xxxu_tx_urb {
1302 struct ieee80211_hw *hw;
1303 struct list_head list;
1306 struct rtl8xxxu_fileops {
1307 int (*parse_efuse) (struct rtl8xxxu_priv *priv);
1308 int (*load_firmware) (struct rtl8xxxu_priv *priv);
1309 int (*power_on) (struct rtl8xxxu_priv *priv);
1310 void (*power_off) (struct rtl8xxxu_priv *priv);
1311 void (*reset_8051) (struct rtl8xxxu_priv *priv);
1312 int (*llt_init) (struct rtl8xxxu_priv *priv, u8 last_tx_page);
1313 void (*init_phy_bb) (struct rtl8xxxu_priv *priv);
1314 int (*init_phy_rf) (struct rtl8xxxu_priv *priv);
1315 void (*phy_init_antenna_selection) (struct rtl8xxxu_priv *priv);
1316 void (*phy_iq_calibrate) (struct rtl8xxxu_priv *priv);
1317 void (*config_channel) (struct ieee80211_hw *hw);
1318 int (*parse_rx_desc) (struct rtl8xxxu_priv *priv, struct sk_buff *skb,
1319 struct ieee80211_rx_status *rx_status);
1320 void (*init_aggregation) (struct rtl8xxxu_priv *priv);
1321 void (*init_statistics) (struct rtl8xxxu_priv *priv);
1322 void (*enable_rf) (struct rtl8xxxu_priv *priv);
1323 void (*disable_rf) (struct rtl8xxxu_priv *priv);
1324 void (*usb_quirks) (struct rtl8xxxu_priv *priv);
1325 void (*set_tx_power) (struct rtl8xxxu_priv *priv, int channel,
1327 void (*update_rate_mask) (struct rtl8xxxu_priv *priv,
1328 u32 ramask, int sgi);
1329 void (*report_connect) (struct rtl8xxxu_priv *priv,
1330 u8 macid, bool connect);
1331 int writeN_block_size;
1336 u32 adda_1t_path_on;
1337 u32 adda_2t_path_on_a;
1338 u32 adda_2t_path_on_b;
1342 struct rtl8xxxu_reg8val *mactable;
1349 extern int rtl8xxxu_debug;
1351 extern struct rtl8xxxu_reg8val rtl8xxxu_gen1_mac_init_table[];
1352 extern const u32 rtl8xxxu_iqk_phy_iq_bb_reg[];
1353 u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr);
1354 u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr);
1355 u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr);
1356 int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val);
1357 int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val);
1358 int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val);
1359 u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
1360 enum rtl8xxxu_rfpath path, u8 reg);
1361 int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
1362 enum rtl8xxxu_rfpath path, u8 reg, u32 data);
1363 void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
1364 u32 *backup, int count);
1365 void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
1366 u32 *backup, int count);
1367 void rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv,
1368 const u32 *reg, u32 *backup);
1369 void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
1370 const u32 *reg, u32 *backup);
1371 void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
1373 void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
1374 const u32 *regs, u32 *backup);
1375 void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok,
1376 int result[][8], int candidate, bool tx_only);
1377 void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok,
1378 int result[][8], int candidate, bool tx_only);
1379 int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
1380 struct rtl8xxxu_rfregval *table,
1381 enum rtl8xxxu_rfpath path);
1382 int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
1383 struct rtl8xxxu_reg32val *array);
1384 int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name);
1385 void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv);
1386 void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv);
1387 void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv);
1388 int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page);
1389 void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start);
1390 int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv);
1391 int rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv,
1392 struct h2c_cmd *h2c, int len);
1393 int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv);
1394 void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv);
1395 int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page);
1396 void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv);
1397 void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv);
1398 void rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv,
1399 int channel, bool ht40);
1400 void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw);
1401 void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw);
1402 void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv);
1403 void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv);
1404 void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
1405 u32 ramask, int sgi);
1406 void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv,
1407 u32 ramask, int sgi);
1408 void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv,
1409 u8 macid, bool connect);
1410 void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv,
1411 u8 macid, bool connect);
1412 void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv);
1413 void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv);
1414 void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv);
1415 int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb,
1416 struct ieee80211_rx_status *rx_status);
1417 int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb,
1418 struct ieee80211_rx_status *rx_status);
1419 int rtl8xxxu_gen2_channel_to_group(int channel);
1420 bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv,
1421 int result[][8], int c1, int c2);
1423 extern struct rtl8xxxu_fileops rtl8192cu_fops;
1424 extern struct rtl8xxxu_fileops rtl8192eu_fops;
1425 extern struct rtl8xxxu_fileops rtl8723au_fops;
1426 extern struct rtl8xxxu_fileops rtl8723bu_fops;