drivers/net/wireless/p54/net2280.h

   1 #ifndef NET2280_H
   2 #define NET2280_H
   3 /*
   4  * NetChip 2280 high/full speed USB device controller.
   5  * Unlike many such controllers, this one talks PCI.
   6  */
   7
   8 /*
   9  * Copyright (C) 2002 NetChip Technology, Inc. (http://www.netchip.com)
  10  * Copyright (C) 2003 David Brownell
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, see <http://www.gnu.org/licenses/>.
  24  */
  25
  26 /*-------------------------------------------------------------------------*/
  27
  28 /* NET2280 MEMORY MAPPED REGISTERS
  29  *
  30  * The register layout came from the chip documentation, and the bit
  31  * number definitions were extracted from chip specification.
  32  *
  33  * Use the shift operator ('<<') to build bit masks, with readl/writel
  34  * to access the registers through PCI.
  35  */
  36
  37 /* main registers, BAR0 + 0x0000 */
  38 struct net2280_regs {
  39         /* offset 0x0000 */
  40         __le32                  devinit;
  41 #define LOCAL_CLOCK_FREQUENCY                                   8
  42 #define FORCE_PCI_RESET                                         7
  43 #define PCI_ID                                                  6
  44 #define PCI_ENABLE                                              5
  45 #define FIFO_SOFT_RESET                                         4
  46 #define CFG_SOFT_RESET                                          3
  47 #define PCI_SOFT_RESET                                          2
  48 #define USB_SOFT_RESET                                          1
  49 #define M8051_RESET                                             0
  50         __le32                  eectl;
  51 #define EEPROM_ADDRESS_WIDTH                                    23
  52 #define EEPROM_CHIP_SELECT_ACTIVE                               22
  53 #define EEPROM_PRESENT                                          21
  54 #define EEPROM_VALID                                            20
  55 #define EEPROM_BUSY                                             19
  56 #define EEPROM_CHIP_SELECT_ENABLE                               18
  57 #define EEPROM_BYTE_READ_START                                  17
  58 #define EEPROM_BYTE_WRITE_START                                 16
  59 #define EEPROM_READ_DATA                                        8
  60 #define EEPROM_WRITE_DATA                                       0
  61         __le32                  eeclkfreq;
  62         u32                     _unused0;
  63         /* offset 0x0010 */
  64
  65         __le32                  pciirqenb0;     /* interrupt PCI master ... */
  66 #define SETUP_PACKET_INTERRUPT_ENABLE                           7
  67 #define ENDPOINT_F_INTERRUPT_ENABLE                             6
  68 #define ENDPOINT_E_INTERRUPT_ENABLE                             5
  69 #define ENDPOINT_D_INTERRUPT_ENABLE                             4
  70 #define ENDPOINT_C_INTERRUPT_ENABLE                             3
  71 #define ENDPOINT_B_INTERRUPT_ENABLE                             2
  72 #define ENDPOINT_A_INTERRUPT_ENABLE                             1
  73 #define ENDPOINT_0_INTERRUPT_ENABLE                             0
  74         __le32                  pciirqenb1;
  75 #define PCI_INTERRUPT_ENABLE                                    31
  76 #define POWER_STATE_CHANGE_INTERRUPT_ENABLE                     27
  77 #define PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE                    26
  78 #define PCI_PARITY_ERROR_INTERRUPT_ENABLE                       25
  79 #define PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE              20
  80 #define PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE              19
  81 #define PCI_TARGET_ABORT_ASSERTED_INTERRUPT_ENABLE              18
  82 #define PCI_RETRY_ABORT_INTERRUPT_ENABLE                        17
  83 #define PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE                  16
  84 #define GPIO_INTERRUPT_ENABLE                                   13
  85 #define DMA_D_INTERRUPT_ENABLE                                  12
  86 #define DMA_C_INTERRUPT_ENABLE                                  11
  87 #define DMA_B_INTERRUPT_ENABLE                                  10
  88 #define DMA_A_INTERRUPT_ENABLE                                  9
  89 #define EEPROM_DONE_INTERRUPT_ENABLE                            8
  90 #define VBUS_INTERRUPT_ENABLE                                   7
  91 #define CONTROL_STATUS_INTERRUPT_ENABLE                         6
  92 #define ROOT_PORT_RESET_INTERRUPT_ENABLE                        4
  93 #define SUSPEND_REQUEST_INTERRUPT_ENABLE                        3
  94 #define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE                 2
  95 #define RESUME_INTERRUPT_ENABLE                                 1
  96 #define SOF_INTERRUPT_ENABLE                                    0
  97         __le32                  cpu_irqenb0;    /* ... or onboard 8051 */
  98 #define SETUP_PACKET_INTERRUPT_ENABLE                           7
  99 #define ENDPOINT_F_INTERRUPT_ENABLE                             6
 100 #define ENDPOINT_E_INTERRUPT_ENABLE                             5
 101 #define ENDPOINT_D_INTERRUPT_ENABLE                             4
 102 #define ENDPOINT_C_INTERRUPT_ENABLE                             3
 103 #define ENDPOINT_B_INTERRUPT_ENABLE                             2
 104 #define ENDPOINT_A_INTERRUPT_ENABLE                             1
 105 #define ENDPOINT_0_INTERRUPT_ENABLE                             0
 106         __le32                  cpu_irqenb1;
 107 #define CPU_INTERRUPT_ENABLE                                    31
 108 #define POWER_STATE_CHANGE_INTERRUPT_ENABLE                     27
 109 #define PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE                    26
 110 #define PCI_PARITY_ERROR_INTERRUPT_ENABLE                       25
 111 #define PCI_INTA_INTERRUPT_ENABLE                               24
 112 #define PCI_PME_INTERRUPT_ENABLE                                23
 113 #define PCI_SERR_INTERRUPT_ENABLE                               22
 114 #define PCI_PERR_INTERRUPT_ENABLE                               21
 115 #define PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE              20
 116 #define PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE              19
 117 #define PCI_RETRY_ABORT_INTERRUPT_ENABLE                        17
 118 #define PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE                  16
 119 #define GPIO_INTERRUPT_ENABLE                                   13
 120 #define DMA_D_INTERRUPT_ENABLE                                  12
 121 #define DMA_C_INTERRUPT_ENABLE                                  11
 122 #define DMA_B_INTERRUPT_ENABLE                                  10
 123 #define DMA_A_INTERRUPT_ENABLE                                  9
 124 #define EEPROM_DONE_INTERRUPT_ENABLE                            8
 125 #define VBUS_INTERRUPT_ENABLE                                   7
 126 #define CONTROL_STATUS_INTERRUPT_ENABLE                         6
 127 #define ROOT_PORT_RESET_INTERRUPT_ENABLE                        4
 128 #define SUSPEND_REQUEST_INTERRUPT_ENABLE                        3
 129 #define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE                 2
 130 #define RESUME_INTERRUPT_ENABLE                                 1
 131 #define SOF_INTERRUPT_ENABLE                                    0
 132
 133         /* offset 0x0020 */
 134         u32                     _unused1;
 135         __le32                  usbirqenb1;
 136 #define USB_INTERRUPT_ENABLE                                    31
 137 #define POWER_STATE_CHANGE_INTERRUPT_ENABLE                     27
 138 #define PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE                    26
 139 #define PCI_PARITY_ERROR_INTERRUPT_ENABLE                       25
 140 #define PCI_INTA_INTERRUPT_ENABLE                               24
 141 #define PCI_PME_INTERRUPT_ENABLE                                23
 142 #define PCI_SERR_INTERRUPT_ENABLE                               22
 143 #define PCI_PERR_INTERRUPT_ENABLE                               21
 144 #define PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE              20
 145 #define PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE              19
 146 #define PCI_RETRY_ABORT_INTERRUPT_ENABLE                        17
 147 #define PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE                  16
 148 #define GPIO_INTERRUPT_ENABLE                                   13
 149 #define DMA_D_INTERRUPT_ENABLE                                  12
 150 #define DMA_C_INTERRUPT_ENABLE                                  11
 151 #define DMA_B_INTERRUPT_ENABLE                                  10
 152 #define DMA_A_INTERRUPT_ENABLE                                  9
 153 #define EEPROM_DONE_INTERRUPT_ENABLE                            8
 154 #define VBUS_INTERRUPT_ENABLE                                   7
 155 #define CONTROL_STATUS_INTERRUPT_ENABLE                         6
 156 #define ROOT_PORT_RESET_INTERRUPT_ENABLE                        4
 157 #define SUSPEND_REQUEST_INTERRUPT_ENABLE                        3
 158 #define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE                 2
 159 #define RESUME_INTERRUPT_ENABLE                                 1
 160 #define SOF_INTERRUPT_ENABLE                                    0
 161         __le32                  irqstat0;
 162 #define INTA_ASSERTED                                           12
 163 #define SETUP_PACKET_INTERRUPT                                  7
 164 #define ENDPOINT_F_INTERRUPT                                    6
 165 #define ENDPOINT_E_INTERRUPT                                    5
 166 #define ENDPOINT_D_INTERRUPT                                    4
 167 #define ENDPOINT_C_INTERRUPT                                    3
 168 #define ENDPOINT_B_INTERRUPT                                    2
 169 #define ENDPOINT_A_INTERRUPT                                    1
 170 #define ENDPOINT_0_INTERRUPT                                    0
 171         __le32                  irqstat1;
 172 #define POWER_STATE_CHANGE_INTERRUPT                            27
 173 #define PCI_ARBITER_TIMEOUT_INTERRUPT                           26
 174 #define PCI_PARITY_ERROR_INTERRUPT                              25
 175 #define PCI_INTA_INTERRUPT                                      24
 176 #define PCI_PME_INTERRUPT                                       23
 177 #define PCI_SERR_INTERRUPT                                      22
 178 #define PCI_PERR_INTERRUPT                                      21
 179 #define PCI_MASTER_ABORT_RECEIVED_INTERRUPT                     20
 180 #define PCI_TARGET_ABORT_RECEIVED_INTERRUPT                     19
 181 #define PCI_RETRY_ABORT_INTERRUPT                               17
 182 #define PCI_MASTER_CYCLE_DONE_INTERRUPT                         16
 183 #define GPIO_INTERRUPT                                          13
 184 #define DMA_D_INTERRUPT                                         12
 185 #define DMA_C_INTERRUPT                                         11
 186 #define DMA_B_INTERRUPT                                         10
 187 #define DMA_A_INTERRUPT                                         9
 188 #define EEPROM_DONE_INTERRUPT                                   8
 189 #define VBUS_INTERRUPT                                          7
 190 #define CONTROL_STATUS_INTERRUPT                                6
 191 #define ROOT_PORT_RESET_INTERRUPT                               4
 192 #define SUSPEND_REQUEST_INTERRUPT                               3
 193 #define SUSPEND_REQUEST_CHANGE_INTERRUPT                        2
 194 #define RESUME_INTERRUPT                                        1
 195 #define SOF_INTERRUPT                                           0
 196         /* offset 0x0030 */
 197         __le32                  idxaddr;
 198         __le32                  idxdata;
 199         __le32                  fifoctl;
 200 #define PCI_BASE2_RANGE                                         16
 201 #define IGNORE_FIFO_AVAILABILITY                                3
 202 #define PCI_BASE2_SELECT                                        2
 203 #define FIFO_CONFIGURATION_SELECT                               0
 204         u32                     _unused2;
 205         /* offset 0x0040 */
 206         __le32                  memaddr;
 207 #define START                                                   28
 208 #define DIRECTION                                               27
 209 #define FIFO_DIAGNOSTIC_SELECT                                  24
 210 #define MEMORY_ADDRESS                                          0
 211         __le32                  memdata0;
 212         __le32                  memdata1;
 213         u32                     _unused3;
 214         /* offset 0x0050 */
 215         __le32                  gpioctl;
 216 #define GPIO3_LED_SELECT                                        12
 217 #define GPIO3_INTERRUPT_ENABLE                                  11
 218 #define GPIO2_INTERRUPT_ENABLE                                  10
 219 #define GPIO1_INTERRUPT_ENABLE                                  9
 220 #define GPIO0_INTERRUPT_ENABLE                                  8
 221 #define GPIO3_OUTPUT_ENABLE                                     7
 222 #define GPIO2_OUTPUT_ENABLE                                     6
 223 #define GPIO1_OUTPUT_ENABLE                                     5
 224 #define GPIO0_OUTPUT_ENABLE                                     4
 225 #define GPIO3_DATA                                              3
 226 #define GPIO2_DATA                                              2
 227 #define GPIO1_DATA                                              1
 228 #define GPIO0_DATA                                              0
 229         __le32                  gpiostat;
 230 #define GPIO3_INTERRUPT                                         3
 231 #define GPIO2_INTERRUPT                                         2
 232 #define GPIO1_INTERRUPT                                         1
 233 #define GPIO0_INTERRUPT                                         0
 234 } __packed;
 235
 236 /* usb control, BAR0 + 0x0080 */
 237 struct net2280_usb_regs {
 238         /* offset 0x0080 */
 239         __le32                  stdrsp;
 240 #define STALL_UNSUPPORTED_REQUESTS                              31
 241 #define SET_TEST_MODE                                           16
 242 #define GET_OTHER_SPEED_CONFIGURATION                           15
 243 #define GET_DEVICE_QUALIFIER                                    14
 244 #define SET_ADDRESS                                             13
 245 #define ENDPOINT_SET_CLEAR_HALT                                 12
 246 #define DEVICE_SET_CLEAR_DEVICE_REMOTE_WAKEUP                   11
 247 #define GET_STRING_DESCRIPTOR_2                                 10
 248 #define GET_STRING_DESCRIPTOR_1                                 9
 249 #define GET_STRING_DESCRIPTOR_0                                 8
 250 #define GET_SET_INTERFACE                                       6
 251 #define GET_SET_CONFIGURATION                                   5
 252 #define GET_CONFIGURATION_DESCRIPTOR                            4
 253 #define GET_DEVICE_DESCRIPTOR                                   3
 254 #define GET_ENDPOINT_STATUS                                     2
 255 #define GET_INTERFACE_STATUS                                    1
 256 #define GET_DEVICE_STATUS                                       0
 257         __le32                  prodvendid;
 258 #define     PRODUCT_ID                                          16
 259 #define     VENDOR_ID                                           0
 260         __le32                  relnum;
 261         __le32                  usbctl;
 262 #define SERIAL_NUMBER_INDEX                                     16
 263 #define PRODUCT_ID_STRING_ENABLE                                13
 264 #define VENDOR_ID_STRING_ENABLE                                 12
 265 #define USB_ROOT_PORT_WAKEUP_ENABLE                             11
 266 #define VBUS_PIN                                                10
 267 #define TIMED_DISCONNECT                                        9
 268 #define SUSPEND_IMMEDIATELY                                     7
 269 #define SELF_POWERED_USB_DEVICE                                 6
 270 #define REMOTE_WAKEUP_SUPPORT                                   5
 271 #define PME_POLARITY                                            4
 272 #define USB_DETECT_ENABLE                                       3
 273 #define PME_WAKEUP_ENABLE                                       2
 274 #define DEVICE_REMOTE_WAKEUP_ENABLE                             1
 275 #define SELF_POWERED_STATUS                                     0
 276         /* offset 0x0090 */
 277         __le32                  usbstat;
 278 #define HIGH_SPEED                                              7
 279 #define FULL_SPEED                                              6
 280 #define GENERATE_RESUME                                         5
 281 #define GENERATE_DEVICE_REMOTE_WAKEUP                           4
 282         __le32                  xcvrdiag;
 283 #define FORCE_HIGH_SPEED_MODE                                   31
 284 #define FORCE_FULL_SPEED_MODE                                   30
 285 #define USB_TEST_MODE                                           24
 286 #define LINE_STATE                                              16
 287 #define TRANSCEIVER_OPERATION_MODE                              2
 288 #define TRANSCEIVER_SELECT                                      1
 289 #define TERMINATION_SELECT                                      0
 290         __le32                  setup0123;
 291         __le32                  setup4567;
 292         /* offset 0x0090 */
 293         u32                     _unused0;
 294         __le32                  ouraddr;
 295 #define FORCE_IMMEDIATE                                         7
 296 #define OUR_USB_ADDRESS                                         0
 297         __le32                  ourconfig;
 298 } __packed;
 299
 300 /* pci control, BAR0 + 0x0100 */
 301 struct net2280_pci_regs {
 302         /* offset 0x0100 */
 303         __le32                  pcimstctl;
 304 #define PCI_ARBITER_PARK_SELECT                                 13
 305 #define PCI_MULTI LEVEL_ARBITER                                 12
 306 #define PCI_RETRY_ABORT_ENABLE                                  11
 307 #define DMA_MEMORY_WRITE_AND_INVALIDATE_ENABLE                  10
 308 #define DMA_READ_MULTIPLE_ENABLE                                9
 309 #define DMA_READ_LINE_ENABLE                                    8
 310 #define PCI_MASTER_COMMAND_SELECT                               6
 311 #define         MEM_READ_OR_WRITE                               0
 312 #define         IO_READ_OR_WRITE                                1
 313 #define         CFG_READ_OR_WRITE                               2
 314 #define PCI_MASTER_START                                        5
 315 #define PCI_MASTER_READ_WRITE                                   4
 316 #define         PCI_MASTER_WRITE                                0
 317 #define         PCI_MASTER_READ                                 1
 318 #define PCI_MASTER_BYTE_WRITE_ENABLES                           0
 319         __le32                  pcimstaddr;
 320         __le32                  pcimstdata;
 321         __le32                  pcimststat;
 322 #define PCI_ARBITER_CLEAR                                       2
 323 #define PCI_EXTERNAL_ARBITER                                    1
 324 #define PCI_HOST_MODE                                           0
 325 } __packed;
 326
 327 /* dma control, BAR0 + 0x0180 ... array of four structs like this,
 328  * for channels 0..3.  see also struct net2280_dma:  descriptor
 329  * that can be loaded into some of these registers.
 330  */
 331 struct net2280_dma_regs {       /* [11.7] */
 332         /* offset 0x0180, 0x01a0, 0x01c0, 0x01e0, */
 333         __le32                  dmactl;
 334 #define DMA_SCATTER_GATHER_DONE_INTERRUPT_ENABLE                25
 335 #define DMA_CLEAR_COUNT_ENABLE                                  21
 336 #define DESCRIPTOR_POLLING_RATE                                 19
 337 #define         POLL_CONTINUOUS                                 0
 338 #define         POLL_1_USEC                                     1
 339 #define         POLL_100_USEC                                   2
 340 #define         POLL_1_MSEC                                     3
 341 #define DMA_VALID_BIT_POLLING_ENABLE                            18
 342 #define DMA_VALID_BIT_ENABLE                                    17
 343 #define DMA_SCATTER_GATHER_ENABLE                               16
 344 #define DMA_OUT_AUTO_START_ENABLE                               4
 345 #define DMA_PREEMPT_ENABLE                                      3
 346 #define DMA_FIFO_VALIDATE                                       2
 347 #define DMA_ENABLE                                              1
 348 #define DMA_ADDRESS_HOLD                                        0
 349         __le32                  dmastat;
 350 #define DMA_SCATTER_GATHER_DONE_INTERRUPT                       25
 351 #define DMA_TRANSACTION_DONE_INTERRUPT                          24
 352 #define DMA_ABORT                                               1
 353 #define DMA_START                                               0
 354         u32                     _unused0[2];
 355         /* offset 0x0190, 0x01b0, 0x01d0, 0x01f0, */
 356         __le32                  dmacount;
 357 #define VALID_BIT                                               31
 358 #define DMA_DIRECTION                                           30
 359 #define DMA_DONE_INTERRUPT_ENABLE                               29
 360 #define END_OF_CHAIN                                            28
 361 #define DMA_BYTE_COUNT_MASK                                     ((1<<24)-1)
 362 #define DMA_BYTE_COUNT                                          0
 363         __le32                  dmaaddr;
 364         __le32                  dmadesc;
 365         u32                     _unused1;
 366 } __packed;
 367
 368 /* dedicated endpoint registers, BAR0 + 0x0200 */
 369
 370 struct net2280_dep_regs {       /* [11.8] */
 371         /* offset 0x0200, 0x0210, 0x220, 0x230, 0x240 */
 372         __le32                  dep_cfg;
 373         /* offset 0x0204, 0x0214, 0x224, 0x234, 0x244 */
 374         __le32                  dep_rsp;
 375         u32                     _unused[2];
 376 } __packed;
 377
 378 /* configurable endpoint registers, BAR0 + 0x0300 ... array of seven structs
 379  * like this, for ep0 then the configurable endpoints A..F
 380  * ep0 reserved for control; E and F have only 64 bytes of fifo
 381  */
 382 struct net2280_ep_regs {        /* [11.9] */
 383         /* offset 0x0300, 0x0320, 0x0340, 0x0360, 0x0380, 0x03a0, 0x03c0 */
 384         __le32                  ep_cfg;
 385 #define ENDPOINT_BYTE_COUNT                                     16
 386 #define ENDPOINT_ENABLE                                         10
 387 #define ENDPOINT_TYPE                                           8
 388 #define ENDPOINT_DIRECTION                                      7
 389 #define ENDPOINT_NUMBER                                         0
 390         __le32                  ep_rsp;
 391 #define SET_NAK_OUT_PACKETS                                     15
 392 #define SET_EP_HIDE_STATUS_PHASE                                14
 393 #define SET_EP_FORCE_CRC_ERROR                                  13
 394 #define SET_INTERRUPT_MODE                                      12
 395 #define SET_CONTROL_STATUS_PHASE_HANDSHAKE                      11
 396 #define SET_NAK_OUT_PACKETS_MODE                                10
 397 #define SET_ENDPOINT_TOGGLE                                     9
 398 #define SET_ENDPOINT_HALT                                       8
 399 #define CLEAR_NAK_OUT_PACKETS                                   7
 400 #define CLEAR_EP_HIDE_STATUS_PHASE                              6
 401 #define CLEAR_EP_FORCE_CRC_ERROR                                5
 402 #define CLEAR_INTERRUPT_MODE                                    4
 403 #define CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE                    3
 404 #define CLEAR_NAK_OUT_PACKETS_MODE                              2
 405 #define CLEAR_ENDPOINT_TOGGLE                                   1
 406 #define CLEAR_ENDPOINT_HALT                                     0
 407         __le32                  ep_irqenb;
 408 #define SHORT_PACKET_OUT_DONE_INTERRUPT_ENABLE                  6
 409 #define SHORT_PACKET_TRANSFERRED_INTERRUPT_ENABLE               5
 410 #define DATA_PACKET_RECEIVED_INTERRUPT_ENABLE                   3
 411 #define DATA_PACKET_TRANSMITTED_INTERRUPT_ENABLE                2
 412 #define DATA_OUT_PING_TOKEN_INTERRUPT_ENABLE                    1
 413 #define DATA_IN_TOKEN_INTERRUPT_ENABLE                          0
 414         __le32                  ep_stat;
 415 #define FIFO_VALID_COUNT                                        24
 416 #define HIGH_BANDWIDTH_OUT_TRANSACTION_PID                      22
 417 #define TIMEOUT                                                 21
 418 #define USB_STALL_SENT                                          20
 419 #define USB_IN_NAK_SENT                                         19
 420 #define USB_IN_ACK_RCVD                                         18
 421 #define USB_OUT_PING_NAK_SENT                                   17
 422 #define USB_OUT_ACK_SENT                                        16
 423 #define FIFO_OVERFLOW                                           13
 424 #define FIFO_UNDERFLOW                                          12
 425 #define FIFO_FULL                                               11
 426 #define FIFO_EMPTY                                              10
 427 #define FIFO_FLUSH                                              9
 428 #define SHORT_PACKET_OUT_DONE_INTERRUPT                         6
 429 #define SHORT_PACKET_TRANSFERRED_INTERRUPT                      5
 430 #define NAK_OUT_PACKETS                                         4
 431 #define DATA_PACKET_RECEIVED_INTERRUPT                          3
 432 #define DATA_PACKET_TRANSMITTED_INTERRUPT                       2
 433 #define DATA_OUT_PING_TOKEN_INTERRUPT                           1
 434 #define DATA_IN_TOKEN_INTERRUPT                                 0
 435         /* offset 0x0310, 0x0330, 0x0350, 0x0370, 0x0390, 0x03b0, 0x03d0 */
 436         __le32                  ep_avail;
 437         __le32                  ep_data;
 438         u32                     _unused0[2];
 439 } __packed;
 440
 441 struct net2280_reg_write {
 442         __le16 port;
 443         __le32 addr;
 444         __le32 val;
 445 } __packed;
 446
 447 struct net2280_reg_read {
 448         __le16 port;
 449         __le32 addr;
 450 } __packed;
 451 #endif /* NET2280_H */