drivers/net/wireless/iwlwifi/pcie/trans.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
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  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but
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  20  * along with this program; if not, write to the Free Software
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  44  *    the documentation and/or other materials provided with the
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  47  *    contributors may be used to endorse or promote products derived
  48  *    from this software without specific prior written permission.
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  50  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  52  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  55  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  56  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  57  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  58  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  59  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 #include <linux/pci.h>
  64 #include <linux/pci-aspm.h>
  65 #include <linux/interrupt.h>
  66 #include <linux/debugfs.h>
  67 #include <linux/sched.h>
  68 #include <linux/bitops.h>
  69 #include <linux/gfp.h>
  70
  71 #include "iwl-drv.h"
  72 #include "iwl-trans.h"
  73 #include "iwl-csr.h"
  74 #include "iwl-prph.h"
  75 #include "iwl-agn-hw.h"
  76 #include "internal.h"
  77
  78 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
  79 {
  80         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
  81                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
  82                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  83                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
  84         else
  85                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
  86                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  87                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
  88 }
  89
  90 /* PCI registers */
  91 #define PCI_CFG_RETRY_TIMEOUT   0x041
  92
  93 static void iwl_pcie_apm_config(struct iwl_trans *trans)
  94 {
  95         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  96         u16 lctl;
  97         u16 cap;
  98
  99         /*
 100          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 101          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 102          * If so (likely), disable L0S, so device moves directly L0->L1;
 103          *    costs negligible amount of power savings.
 104          * If not (unlikely), enable L0S, so there is at least some
 105          *    power savings, even without L1.
 106          */
 107         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 108         if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
 109                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 110         else
 111                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 112         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 113
 114         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
 115         trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
 116         dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
 117                  (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
 118                  trans->ltr_enabled ? "En" : "Dis");
 119 }
 120
 121 /*
 122  * Start up NIC's basic functionality after it has been reset
 123  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 124  * NOTE:  This does not load uCode nor start the embedded processor
 125  */
 126 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 127 {
 128         int ret = 0;
 129         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 130
 131         /*
 132          * Use "set_bit" below rather than "write", to preserve any hardware
 133          * bits already set by default after reset.
 134          */
 135
 136         /* Disable L0S exit timer (platform NMI Work/Around) */
 137         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 138                     CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 139
 140         /*
 141          * Disable L0s without affecting L1;
 142          *  don't wait for ICH L0s (ICH bug W/A)
 143          */
 144         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 145                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 146
 147         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 148         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 149
 150         /*
 151          * Enable HAP INTA (interrupt from management bus) to
 152          * wake device's PCI Express link L1a -> L0s
 153          */
 154         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 155                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 156
 157         iwl_pcie_apm_config(trans);
 158
 159         /* Configure analog phase-lock-loop before activating to D0A */
 160         if (trans->cfg->base_params->pll_cfg_val)
 161                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 162                             trans->cfg->base_params->pll_cfg_val);
 163
 164         /*
 165          * Set "initialization complete" bit to move adapter from
 166          * D0U* --> D0A* (powered-up active) state.
 167          */
 168         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 169
 170         /*
 171          * Wait for clock stabilization; once stabilized, access to
 172          * device-internal resources is supported, e.g. iwl_write_prph()
 173          * and accesses to uCode SRAM.
 174          */
 175         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 176                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 177                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 178         if (ret < 0) {
 179                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 180                 goto out;
 181         }
 182
 183         if (trans->cfg->host_interrupt_operation_mode) {
 184                 /*
 185                  * This is a bit of an abuse - This is needed for 7260 / 3160
 186                  * only check host_interrupt_operation_mode even if this is
 187                  * not related to host_interrupt_operation_mode.
 188                  *
 189                  * Enable the oscillator to count wake up time for L1 exit. This
 190                  * consumes slightly more power (100uA) - but allows to be sure
 191                  * that we wake up from L1 on time.
 192                  *
 193                  * This looks weird: read twice the same register, discard the
 194                  * value, set a bit, and yet again, read that same register
 195                  * just to discard the value. But that's the way the hardware
 196                  * seems to like it.
 197                  */
 198                 iwl_read_prph(trans, OSC_CLK);
 199                 iwl_read_prph(trans, OSC_CLK);
 200                 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
 201                 iwl_read_prph(trans, OSC_CLK);
 202                 iwl_read_prph(trans, OSC_CLK);
 203         }
 204
 205         /*
 206          * Enable DMA clock and wait for it to stabilize.
 207          *
 208          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
 209          * do not disable clocks.  This preserves any hardware bits already
 210          * set by default in "CLK_CTRL_REG" after reset.
 211          */
 212         iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 213         udelay(20);
 214
 215         /* Disable L1-Active */
 216         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 217                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 218
 219         /* Clear the interrupt in APMG if the NIC is in RFKILL */
 220         iwl_write_prph(trans, APMG_RTC_INT_STT_REG, APMG_RTC_INT_STT_RFKILL);
 221
 222         set_bit(STATUS_DEVICE_ENABLED, &trans->status);
 223
 224 out:
 225         return ret;
 226 }
 227
 228 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 229 {
 230         int ret = 0;
 231
 232         /* stop device's busmaster DMA activity */
 233         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 234
 235         ret = iwl_poll_bit(trans, CSR_RESET,
 236                            CSR_RESET_REG_FLAG_MASTER_DISABLED,
 237                            CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 238         if (ret)
 239                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 240
 241         IWL_DEBUG_INFO(trans, "stop master\n");
 242
 243         return ret;
 244 }
 245
 246 static void iwl_pcie_apm_stop(struct iwl_trans *trans)
 247 {
 248         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 249
 250         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
 251
 252         /* Stop device's DMA activity */
 253         iwl_pcie_apm_stop_master(trans);
 254
 255         /* Reset the entire device */
 256         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 257
 258         udelay(10);
 259
 260         /*
 261          * Clear "initialization complete" bit to move adapter from
 262          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 263          */
 264         iwl_clear_bit(trans, CSR_GP_CNTRL,
 265                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 266 }
 267
 268 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 269 {
 270         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 271
 272         /* nic_init */
 273         spin_lock(&trans_pcie->irq_lock);
 274         iwl_pcie_apm_init(trans);
 275
 276         spin_unlock(&trans_pcie->irq_lock);
 277
 278         iwl_pcie_set_pwr(trans, false);
 279
 280         iwl_op_mode_nic_config(trans->op_mode);
 281
 282         /* Allocate the RX queue, or reset if it is already allocated */
 283         iwl_pcie_rx_init(trans);
 284
 285         /* Allocate or reset and init all Tx and Command queues */
 286         if (iwl_pcie_tx_init(trans))
 287                 return -ENOMEM;
 288
 289         if (trans->cfg->base_params->shadow_reg_enable) {
 290                 /* enable shadow regs in HW */
 291                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 292                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 293         }
 294
 295         return 0;
 296 }
 297
 298 #define HW_READY_TIMEOUT (50)
 299
 300 /* Note: returns poll_bit return value, which is >= 0 if success */
 301 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 302 {
 303         int ret;
 304
 305         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 306                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 307
 308         /* See if we got it */
 309         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 310                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 311                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 312                            HW_READY_TIMEOUT);
 313
 314         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 315         return ret;
 316 }
 317
 318 /* Note: returns standard 0/-ERROR code */
 319 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 320 {
 321         int ret;
 322         int t = 0;
 323         int iter;
 324
 325         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 326
 327         ret = iwl_pcie_set_hw_ready(trans);
 328         /* If the card is ready, exit 0 */
 329         if (ret >= 0)
 330                 return 0;
 331
 332         for (iter = 0; iter < 10; iter++) {
 333                 /* If HW is not ready, prepare the conditions to check again */
 334                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 335                             CSR_HW_IF_CONFIG_REG_PREPARE);
 336
 337                 do {
 338                         ret = iwl_pcie_set_hw_ready(trans);
 339                         if (ret >= 0)
 340                                 return 0;
 341
 342                         usleep_range(200, 1000);
 343                         t += 200;
 344                 } while (t < 150000);
 345                 msleep(25);
 346         }
 347
 348         IWL_DEBUG_INFO(trans, "got NIC after %d iterations\n", iter);
 349
 350         return ret;
 351 }
 352
 353 /*
 354  * ucode
 355  */
 356 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
 357                                    dma_addr_t phy_addr, u32 byte_cnt)
 358 {
 359         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 360         int ret;
 361
 362         trans_pcie->ucode_write_complete = false;
 363
 364         iwl_write_direct32(trans,
 365                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 366                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 367
 368         iwl_write_direct32(trans,
 369                            FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 370                            dst_addr);
 371
 372         iwl_write_direct32(trans,
 373                            FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 374                            phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 375
 376         iwl_write_direct32(trans,
 377                            FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 378                            (iwl_get_dma_hi_addr(phy_addr)
 379                                 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 380
 381         iwl_write_direct32(trans,
 382                            FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 383                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 384                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 385                            FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 386
 387         iwl_write_direct32(trans,
 388                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 389                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE    |
 390                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 391                            FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 392
 393         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 394                                  trans_pcie->ucode_write_complete, 5 * HZ);
 395         if (!ret) {
 396                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 397                 return -ETIMEDOUT;
 398         }
 399
 400         return 0;
 401 }
 402
 403 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 404                             const struct fw_desc *section)
 405 {
 406         u8 *v_addr;
 407         dma_addr_t p_addr;
 408         u32 offset, chunk_sz = section->len;
 409         int ret = 0;
 410
 411         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 412                      section_num);
 413
 414         v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
 415                                     GFP_KERNEL | __GFP_NOWARN);
 416         if (!v_addr) {
 417                 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
 418                 chunk_sz = PAGE_SIZE;
 419                 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
 420                                             &p_addr, GFP_KERNEL);
 421                 if (!v_addr)
 422                         return -ENOMEM;
 423         }
 424
 425         for (offset = 0; offset < section->len; offset += chunk_sz) {
 426                 u32 copy_size;
 427
 428                 copy_size = min_t(u32, chunk_sz, section->len - offset);
 429
 430                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 431                 ret = iwl_pcie_load_firmware_chunk(trans,
 432                                                    section->offset + offset,
 433                                                    p_addr, copy_size);
 434                 if (ret) {
 435                         IWL_ERR(trans,
 436                                 "Could not load the [%d] uCode section\n",
 437                                 section_num);
 438                         break;
 439                 }
 440         }
 441
 442         dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
 443         return ret;
 444 }
 445
 446 static int iwl_pcie_secure_set(struct iwl_trans *trans, int cpu)
 447 {
 448         int shift_param;
 449         u32 address;
 450         int ret = 0;
 451
 452         if (cpu == 1) {
 453                 shift_param = 0;
 454                 address = CSR_SECURE_BOOT_CPU1_STATUS_ADDR;
 455         } else {
 456                 shift_param = 16;
 457                 address = CSR_SECURE_BOOT_CPU2_STATUS_ADDR;
 458         }
 459
 460         /* set CPU to started */
 461         iwl_trans_set_bits_mask(trans,
 462                                 CSR_UCODE_LOAD_STATUS_ADDR,
 463                                 CSR_CPU_STATUS_LOADING_STARTED << shift_param,
 464                                 1);
 465
 466         /* set last complete descriptor number */
 467         iwl_trans_set_bits_mask(trans,
 468                                 CSR_UCODE_LOAD_STATUS_ADDR,
 469                                 CSR_CPU_STATUS_NUM_OF_LAST_COMPLETED
 470                                 << shift_param,
 471                                 1);
 472
 473         /* set last loaded block */
 474         iwl_trans_set_bits_mask(trans,
 475                                 CSR_UCODE_LOAD_STATUS_ADDR,
 476                                 CSR_CPU_STATUS_NUM_OF_LAST_LOADED_BLOCK
 477                                 << shift_param,
 478                                 1);
 479
 480         /* image loading complete */
 481         iwl_trans_set_bits_mask(trans,
 482                                 CSR_UCODE_LOAD_STATUS_ADDR,
 483                                 CSR_CPU_STATUS_LOADING_COMPLETED
 484                                 << shift_param,
 485                                 1);
 486
 487         /* set FH_TCSR_0_REG  */
 488         iwl_trans_set_bits_mask(trans, FH_TCSR_0_REG0, 0x00400000, 1);
 489
 490         /* verify image verification started  */
 491         ret = iwl_poll_bit(trans, address,
 492                            CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS,
 493                            CSR_SECURE_BOOT_CPU_STATUS_VERF_STATUS,
 494                            CSR_SECURE_TIME_OUT);
 495         if (ret < 0) {
 496                 IWL_ERR(trans, "secure boot process didn't start\n");
 497                 return ret;
 498         }
 499
 500         /* wait for image verification to complete  */
 501         ret = iwl_poll_bit(trans, address,
 502                            CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED,
 503                            CSR_SECURE_BOOT_CPU_STATUS_VERF_COMPLETED,
 504                            CSR_SECURE_TIME_OUT);
 505
 506         if (ret < 0) {
 507                 IWL_ERR(trans, "Time out on secure boot process\n");
 508                 return ret;
 509         }
 510
 511         return 0;
 512 }
 513
 514 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
 515                                 const struct fw_img *image)
 516 {
 517         int i, ret = 0;
 518
 519         IWL_DEBUG_FW(trans,
 520                      "working with %s image\n",
 521                      image->is_secure ? "Secured" : "Non Secured");
 522         IWL_DEBUG_FW(trans,
 523                      "working with %s CPU\n",
 524                      image->is_dual_cpus ? "Dual" : "Single");
 525
 526         /* configure the ucode to be ready to get the secured image */
 527         if (image->is_secure) {
 528                 /* set secure boot inspector addresses */
 529                 iwl_write32(trans, CSR_SECURE_INSPECTOR_CODE_ADDR, 0);
 530                 iwl_write32(trans, CSR_SECURE_INSPECTOR_DATA_ADDR, 0);
 531
 532                 /* release CPU1 reset if secure inspector image burned in OTP */
 533                 iwl_write32(trans, CSR_RESET, 0);
 534         }
 535
 536         /* load to FW the binary sections of CPU1 */
 537         IWL_DEBUG_INFO(trans, "Loading CPU1\n");
 538         for (i = 0;
 539              i < IWL_UCODE_FIRST_SECTION_OF_SECOND_CPU;
 540              i++) {
 541                 if (!image->sec[i].data)
 542                         break;
 543                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 544                 if (ret)
 545                         return ret;
 546         }
 547
 548         /* configure the ucode to start secure process on CPU1 */
 549         if (image->is_secure) {
 550                 /* config CPU1 to start secure protocol */
 551                 ret = iwl_pcie_secure_set(trans, 1);
 552                 if (ret)
 553                         return ret;
 554         } else {
 555                 /* Remove all resets to allow NIC to operate */
 556                 iwl_write32(trans, CSR_RESET, 0);
 557         }
 558
 559         if (image->is_dual_cpus) {
 560                 /* load to FW the binary sections of CPU2 */
 561                 IWL_DEBUG_INFO(trans, "working w/ DUAL CPUs - Loading CPU2\n");
 562                 for (i = IWL_UCODE_FIRST_SECTION_OF_SECOND_CPU;
 563                         i < IWL_UCODE_SECTION_MAX; i++) {
 564                         if (!image->sec[i].data)
 565                                 break;
 566                         ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 567                         if (ret)
 568                                 return ret;
 569                 }
 570
 571                 if (image->is_secure) {
 572                         /* set CPU2 for secure protocol */
 573                         ret = iwl_pcie_secure_set(trans, 2);
 574                         if (ret)
 575                                 return ret;
 576                 }
 577         }
 578
 579         return 0;
 580 }
 581
 582 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
 583                                    const struct fw_img *fw, bool run_in_rfkill)
 584 {
 585         int ret;
 586         bool hw_rfkill;
 587
 588         /* This may fail if AMT took ownership of the device */
 589         if (iwl_pcie_prepare_card_hw(trans)) {
 590                 IWL_WARN(trans, "Exit HW not ready\n");
 591                 return -EIO;
 592         }
 593
 594         iwl_enable_rfkill_int(trans);
 595
 596         /* If platform's RF_KILL switch is NOT set to KILL */
 597         hw_rfkill = iwl_is_rfkill_set(trans);
 598         if (hw_rfkill)
 599                 set_bit(STATUS_RFKILL, &trans->status);
 600         else
 601                 clear_bit(STATUS_RFKILL, &trans->status);
 602         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 603         if (hw_rfkill && !run_in_rfkill)
 604                 return -ERFKILL;
 605
 606         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 607
 608         ret = iwl_pcie_nic_init(trans);
 609         if (ret) {
 610                 IWL_ERR(trans, "Unable to init nic\n");
 611                 return ret;
 612         }
 613
 614         /* make sure rfkill handshake bits are cleared */
 615         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 616         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
 617                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 618
 619         /* clear (again), then enable host interrupts */
 620         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 621         iwl_enable_interrupts(trans);
 622
 623         /* really make sure rfkill handshake bits are cleared */
 624         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 625         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 626
 627         /* Load the given image to the HW */
 628         return iwl_pcie_load_given_ucode(trans, fw);
 629 }
 630
 631 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
 632 {
 633         iwl_pcie_reset_ict(trans);
 634         iwl_pcie_tx_start(trans, scd_addr);
 635 }
 636
 637 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
 638 {
 639         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 640         bool hw_rfkill, was_hw_rfkill;
 641
 642         was_hw_rfkill = iwl_is_rfkill_set(trans);
 643
 644         /* tell the device to stop sending interrupts */
 645         spin_lock(&trans_pcie->irq_lock);
 646         iwl_disable_interrupts(trans);
 647         spin_unlock(&trans_pcie->irq_lock);
 648
 649         /* device going down, Stop using ICT table */
 650         iwl_pcie_disable_ict(trans);
 651
 652         /*
 653          * If a HW restart happens during firmware loading,
 654          * then the firmware loading might call this function
 655          * and later it might be called again due to the
 656          * restart. So don't process again if the device is
 657          * already dead.
 658          */
 659         if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
 660                 iwl_pcie_tx_stop(trans);
 661                 iwl_pcie_rx_stop(trans);
 662
 663                 /* Power-down device's busmaster DMA clocks */
 664                 iwl_write_prph(trans, APMG_CLK_DIS_REG,
 665                                APMG_CLK_VAL_DMA_CLK_RQT);
 666                 udelay(5);
 667         }
 668
 669         /* Make sure (redundant) we've released our request to stay awake */
 670         iwl_clear_bit(trans, CSR_GP_CNTRL,
 671                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 672
 673         /* Stop the device, and put it in low power state */
 674         iwl_pcie_apm_stop(trans);
 675
 676         /* Upon stop, the APM issues an interrupt if HW RF kill is set.
 677          * Clean again the interrupt here
 678          */
 679         spin_lock(&trans_pcie->irq_lock);
 680         iwl_disable_interrupts(trans);
 681         spin_unlock(&trans_pcie->irq_lock);
 682
 683         /* stop and reset the on-board processor */
 684         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
 685
 686         /* clear all status bits */
 687         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
 688         clear_bit(STATUS_INT_ENABLED, &trans->status);
 689         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
 690         clear_bit(STATUS_TPOWER_PMI, &trans->status);
 691         clear_bit(STATUS_RFKILL, &trans->status);
 692
 693         /*
 694          * Even if we stop the HW, we still want the RF kill
 695          * interrupt
 696          */
 697         iwl_enable_rfkill_int(trans);
 698
 699         /*
 700          * Check again since the RF kill state may have changed while
 701          * all the interrupts were disabled, in this case we couldn't
 702          * receive the RF kill interrupt and update the state in the
 703          * op_mode.
 704          * Don't call the op_mode if the rkfill state hasn't changed.
 705          * This allows the op_mode to call stop_device from the rfkill
 706          * notification without endless recursion. Under very rare
 707          * circumstances, we might have a small recursion if the rfkill
 708          * state changed exactly now while we were called from stop_device.
 709          * This is very unlikely but can happen and is supported.
 710          */
 711         hw_rfkill = iwl_is_rfkill_set(trans);
 712         if (hw_rfkill)
 713                 set_bit(STATUS_RFKILL, &trans->status);
 714         else
 715                 clear_bit(STATUS_RFKILL, &trans->status);
 716         if (hw_rfkill != was_hw_rfkill)
 717                 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 718 }
 719
 720 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
 721 {
 722         iwl_disable_interrupts(trans);
 723
 724         /*
 725          * in testing mode, the host stays awake and the
 726          * hardware won't be reset (not even partially)
 727          */
 728         if (test)
 729                 return;
 730
 731         iwl_pcie_disable_ict(trans);
 732
 733         iwl_clear_bit(trans, CSR_GP_CNTRL,
 734                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 735         iwl_clear_bit(trans, CSR_GP_CNTRL,
 736                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 737
 738         /*
 739          * reset TX queues -- some of their registers reset during S3
 740          * so if we don't reset everything here the D3 image would try
 741          * to execute some invalid memory upon resume
 742          */
 743         iwl_trans_pcie_tx_reset(trans);
 744
 745         iwl_pcie_set_pwr(trans, true);
 746 }
 747
 748 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
 749                                     enum iwl_d3_status *status,
 750                                     bool test)
 751 {
 752         u32 val;
 753         int ret;
 754
 755         if (test) {
 756                 iwl_enable_interrupts(trans);
 757                 *status = IWL_D3_STATUS_ALIVE;
 758                 return 0;
 759         }
 760
 761         iwl_pcie_set_pwr(trans, false);
 762
 763         val = iwl_read32(trans, CSR_RESET);
 764         if (val & CSR_RESET_REG_FLAG_NEVO_RESET) {
 765                 *status = IWL_D3_STATUS_RESET;
 766                 return 0;
 767         }
 768
 769         /*
 770          * Also enables interrupts - none will happen as the device doesn't
 771          * know we're waking it up, only when the opmode actually tells it
 772          * after this call.
 773          */
 774         iwl_pcie_reset_ict(trans);
 775
 776         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 777         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 778
 779         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 780                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 781                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 782                            25000);
 783         if (ret) {
 784                 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
 785                 return ret;
 786         }
 787
 788         iwl_trans_pcie_tx_reset(trans);
 789
 790         ret = iwl_pcie_rx_init(trans);
 791         if (ret) {
 792                 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
 793                 return ret;
 794         }
 795
 796         *status = IWL_D3_STATUS_ALIVE;
 797         return 0;
 798 }
 799
 800 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
 801 {
 802         bool hw_rfkill;
 803         int err;
 804
 805         err = iwl_pcie_prepare_card_hw(trans);
 806         if (err) {
 807                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
 808                 return err;
 809         }
 810
 811         /* Reset the entire device */
 812         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 813
 814         usleep_range(10, 15);
 815
 816         iwl_pcie_apm_init(trans);
 817
 818         /* From now on, the op_mode will be kept updated about RF kill state */
 819         iwl_enable_rfkill_int(trans);
 820
 821         hw_rfkill = iwl_is_rfkill_set(trans);
 822         if (hw_rfkill)
 823                 set_bit(STATUS_RFKILL, &trans->status);
 824         else
 825                 clear_bit(STATUS_RFKILL, &trans->status);
 826         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 827
 828         return 0;
 829 }
 830
 831 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
 832 {
 833         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 834
 835         /* disable interrupts - don't enable HW RF kill interrupt */
 836         spin_lock(&trans_pcie->irq_lock);
 837         iwl_disable_interrupts(trans);
 838         spin_unlock(&trans_pcie->irq_lock);
 839
 840         iwl_pcie_apm_stop(trans);
 841
 842         spin_lock(&trans_pcie->irq_lock);
 843         iwl_disable_interrupts(trans);
 844         spin_unlock(&trans_pcie->irq_lock);
 845
 846         iwl_pcie_disable_ict(trans);
 847 }
 848
 849 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
 850 {
 851         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
 852 }
 853
 854 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
 855 {
 856         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
 857 }
 858
 859 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
 860 {
 861         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
 862 }
 863
 864 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
 865 {
 866         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
 867                                ((reg & 0x000FFFFF) | (3 << 24)));
 868         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
 869 }
 870
 871 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
 872                                       u32 val)
 873 {
 874         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
 875                                ((addr & 0x000FFFFF) | (3 << 24)));
 876         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
 877 }
 878
 879 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
 880                                      const struct iwl_trans_config *trans_cfg)
 881 {
 882         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 883
 884         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
 885         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
 886         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
 887                 trans_pcie->n_no_reclaim_cmds = 0;
 888         else
 889                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
 890         if (trans_pcie->n_no_reclaim_cmds)
 891                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
 892                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
 893
 894         trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
 895         if (trans_pcie->rx_buf_size_8k)
 896                 trans_pcie->rx_page_order = get_order(8 * 1024);
 897         else
 898                 trans_pcie->rx_page_order = get_order(4 * 1024);
 899
 900         trans_pcie->wd_timeout =
 901                 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
 902
 903         trans_pcie->command_names = trans_cfg->command_names;
 904         trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
 905 }
 906
 907 void iwl_trans_pcie_free(struct iwl_trans *trans)
 908 {
 909         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 910
 911         synchronize_irq(trans_pcie->pci_dev->irq);
 912
 913         iwl_pcie_tx_free(trans);
 914         iwl_pcie_rx_free(trans);
 915
 916         free_irq(trans_pcie->pci_dev->irq, trans);
 917         iwl_pcie_free_ict(trans);
 918
 919         pci_disable_msi(trans_pcie->pci_dev);
 920         iounmap(trans_pcie->hw_base);
 921         pci_release_regions(trans_pcie->pci_dev);
 922         pci_disable_device(trans_pcie->pci_dev);
 923         kmem_cache_destroy(trans->dev_cmd_pool);
 924
 925         kfree(trans);
 926 }
 927
 928 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
 929 {
 930         if (state)
 931                 set_bit(STATUS_TPOWER_PMI, &trans->status);
 932         else
 933                 clear_bit(STATUS_TPOWER_PMI, &trans->status);
 934 }
 935
 936 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
 937                                                 unsigned long *flags)
 938 {
 939         int ret;
 940         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 941
 942         spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
 943
 944         if (trans_pcie->cmd_in_flight)
 945                 goto out;
 946
 947         /* this bit wakes up the NIC */
 948         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
 949                                  CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 950
 951         /*
 952          * These bits say the device is running, and should keep running for
 953          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
 954          * but they do not indicate that embedded SRAM is restored yet;
 955          * 3945 and 4965 have volatile SRAM, and must save/restore contents
 956          * to/from host DRAM when sleeping/waking for power-saving.
 957          * Each direction takes approximately 1/4 millisecond; with this
 958          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
 959          * series of register accesses are expected (e.g. reading Event Log),
 960          * to keep device from sleeping.
 961          *
 962          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
 963          * SRAM is okay/restored.  We don't check that here because this call
 964          * is just for hardware register access; but GP1 MAC_SLEEP check is a
 965          * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
 966          *
 967          * 5000 series and later (including 1000 series) have non-volatile SRAM,
 968          * and do not save/restore SRAM when power cycling.
 969          */
 970         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 971                            CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
 972                            (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
 973                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
 974         if (unlikely(ret < 0)) {
 975                 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
 976                 if (!silent) {
 977                         u32 val = iwl_read32(trans, CSR_GP_CNTRL);
 978                         WARN_ONCE(1,
 979                                   "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
 980                                   val);
 981                         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
 982                         return false;
 983                 }
 984         }
 985
 986 out:
 987         /*
 988          * Fool sparse by faking we release the lock - sparse will
 989          * track nic_access anyway.
 990          */
 991         __release(&trans_pcie->reg_lock);
 992         return true;
 993 }
 994
 995 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
 996                                               unsigned long *flags)
 997 {
 998         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 999
1000         lockdep_assert_held(&trans_pcie->reg_lock);
1001
1002         /*
1003          * Fool sparse by faking we acquiring the lock - sparse will
1004          * track nic_access anyway.
1005          */
1006         __acquire(&trans_pcie->reg_lock);
1007
1008         if (trans_pcie->cmd_in_flight)
1009                 goto out;
1010
1011         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1012                                    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1013         /*
1014          * Above we read the CSR_GP_CNTRL register, which will flush
1015          * any previous writes, but we need the write that clears the
1016          * MAC_ACCESS_REQ bit to be performed before any other writes
1017          * scheduled on different CPUs (after we drop reg_lock).
1018          */
1019         mmiowb();
1020 out:
1021         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1022 }
1023
1024 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1025                                    void *buf, int dwords)
1026 {
1027         unsigned long flags;
1028         int offs, ret = 0;
1029         u32 *vals = buf;
1030
1031         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1032                 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1033                 for (offs = 0; offs < dwords; offs++)
1034                         vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1035                 iwl_trans_release_nic_access(trans, &flags);
1036         } else {
1037                 ret = -EBUSY;
1038         }
1039         return ret;
1040 }
1041
1042 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1043                                     const void *buf, int dwords)
1044 {
1045         unsigned long flags;
1046         int offs, ret = 0;
1047         const u32 *vals = buf;
1048
1049         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
1050                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1051                 for (offs = 0; offs < dwords; offs++)
1052                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1053                                     vals ? vals[offs] : 0);
1054                 iwl_trans_release_nic_access(trans, &flags);
1055         } else {
1056                 ret = -EBUSY;
1057         }
1058         return ret;
1059 }
1060
1061 #define IWL_FLUSH_WAIT_MS       2000
1062
1063 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans)
1064 {
1065         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1066         struct iwl_txq *txq;
1067         struct iwl_queue *q;
1068         int cnt;
1069         unsigned long now = jiffies;
1070         u32 scd_sram_addr;
1071         u8 buf[16];
1072         int ret = 0;
1073
1074         /* waiting for all the tx frames complete might take a while */
1075         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1076                 if (cnt == trans_pcie->cmd_queue)
1077                         continue;
1078                 txq = &trans_pcie->txq[cnt];
1079                 q = &txq->q;
1080                 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1081                        now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1082                         msleep(1);
1083
1084                 if (q->read_ptr != q->write_ptr) {
1085                         IWL_ERR(trans,
1086                                 "fail to flush all tx fifo queues Q %d\n", cnt);
1087                         ret = -ETIMEDOUT;
1088                         break;
1089                 }
1090         }
1091
1092         if (!ret)
1093                 return 0;
1094
1095         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
1096                 txq->q.read_ptr, txq->q.write_ptr);
1097
1098         scd_sram_addr = trans_pcie->scd_base_addr +
1099                         SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
1100         iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
1101
1102         iwl_print_hex_error(trans, buf, sizeof(buf));
1103
1104         for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1105                 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1106                         iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1107
1108         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1109                 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1110                 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1111                 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1112                 u32 tbl_dw =
1113                         iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1114                                              SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1115
1116                 if (cnt & 0x1)
1117                         tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1118                 else
1119                         tbl_dw = tbl_dw & 0x0000FFFF;
1120
1121                 IWL_ERR(trans,
1122                         "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1123                         cnt, active ? "" : "in", fifo, tbl_dw,
1124                         iwl_read_prph(trans,
1125                                       SCD_QUEUE_RDPTR(cnt)) & (txq->q.n_bd - 1),
1126                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1127         }
1128
1129         return ret;
1130 }
1131
1132 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1133                                          u32 mask, u32 value)
1134 {
1135         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1136         unsigned long flags;
1137
1138         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1139         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
1140         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1141 }
1142
1143 static const char *get_csr_string(int cmd)
1144 {
1145 #define IWL_CMD(x) case x: return #x
1146         switch (cmd) {
1147         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1148         IWL_CMD(CSR_INT_COALESCING);
1149         IWL_CMD(CSR_INT);
1150         IWL_CMD(CSR_INT_MASK);
1151         IWL_CMD(CSR_FH_INT_STATUS);
1152         IWL_CMD(CSR_GPIO_IN);
1153         IWL_CMD(CSR_RESET);
1154         IWL_CMD(CSR_GP_CNTRL);
1155         IWL_CMD(CSR_HW_REV);
1156         IWL_CMD(CSR_EEPROM_REG);
1157         IWL_CMD(CSR_EEPROM_GP);
1158         IWL_CMD(CSR_OTP_GP_REG);
1159         IWL_CMD(CSR_GIO_REG);
1160         IWL_CMD(CSR_GP_UCODE_REG);
1161         IWL_CMD(CSR_GP_DRIVER_REG);
1162         IWL_CMD(CSR_UCODE_DRV_GP1);
1163         IWL_CMD(CSR_UCODE_DRV_GP2);
1164         IWL_CMD(CSR_LED_REG);
1165         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1166         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1167         IWL_CMD(CSR_ANA_PLL_CFG);
1168         IWL_CMD(CSR_HW_REV_WA_REG);
1169         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1170         default:
1171                 return "UNKNOWN";
1172         }
1173 #undef IWL_CMD
1174 }
1175
1176 void iwl_pcie_dump_csr(struct iwl_trans *trans)
1177 {
1178         int i;
1179         static const u32 csr_tbl[] = {
1180                 CSR_HW_IF_CONFIG_REG,
1181                 CSR_INT_COALESCING,
1182                 CSR_INT,
1183                 CSR_INT_MASK,
1184                 CSR_FH_INT_STATUS,
1185                 CSR_GPIO_IN,
1186                 CSR_RESET,
1187                 CSR_GP_CNTRL,
1188                 CSR_HW_REV,
1189                 CSR_EEPROM_REG,
1190                 CSR_EEPROM_GP,
1191                 CSR_OTP_GP_REG,
1192                 CSR_GIO_REG,
1193                 CSR_GP_UCODE_REG,
1194                 CSR_GP_DRIVER_REG,
1195                 CSR_UCODE_DRV_GP1,
1196                 CSR_UCODE_DRV_GP2,
1197                 CSR_LED_REG,
1198                 CSR_DRAM_INT_TBL_REG,
1199                 CSR_GIO_CHICKEN_BITS,
1200                 CSR_ANA_PLL_CFG,
1201                 CSR_HW_REV_WA_REG,
1202                 CSR_DBG_HPET_MEM_REG
1203         };
1204         IWL_ERR(trans, "CSR values:\n");
1205         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1206                 "CSR_INT_PERIODIC_REG)\n");
1207         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1208                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1209                         get_csr_string(csr_tbl[i]),
1210                         iwl_read32(trans, csr_tbl[i]));
1211         }
1212 }
1213
1214 #ifdef CONFIG_IWLWIFI_DEBUGFS
1215 /* create and remove of files */
1216 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1217         if (!debugfs_create_file(#name, mode, parent, trans,            \
1218                                  &iwl_dbgfs_##name##_ops))              \
1219                 goto err;                                               \
1220 } while (0)
1221
1222 /* file operation */
1223 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1224 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1225         .read = iwl_dbgfs_##name##_read,                                \
1226         .open = simple_open,                                            \
1227         .llseek = generic_file_llseek,                                  \
1228 };
1229
1230 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1231 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1232         .write = iwl_dbgfs_##name##_write,                              \
1233         .open = simple_open,                                            \
1234         .llseek = generic_file_llseek,                                  \
1235 };
1236
1237 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1238 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1239         .write = iwl_dbgfs_##name##_write,                              \
1240         .read = iwl_dbgfs_##name##_read,                                \
1241         .open = simple_open,                                            \
1242         .llseek = generic_file_llseek,                                  \
1243 };
1244
1245 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1246                                        char __user *user_buf,
1247                                        size_t count, loff_t *ppos)
1248 {
1249         struct iwl_trans *trans = file->private_data;
1250         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1251         struct iwl_txq *txq;
1252         struct iwl_queue *q;
1253         char *buf;
1254         int pos = 0;
1255         int cnt;
1256         int ret;
1257         size_t bufsz;
1258
1259         bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1260
1261         if (!trans_pcie->txq)
1262                 return -EAGAIN;
1263
1264         buf = kzalloc(bufsz, GFP_KERNEL);
1265         if (!buf)
1266                 return -ENOMEM;
1267
1268         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1269                 txq = &trans_pcie->txq[cnt];
1270                 q = &txq->q;
1271                 pos += scnprintf(buf + pos, bufsz - pos,
1272                                 "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
1273                                 cnt, q->read_ptr, q->write_ptr,
1274                                 !!test_bit(cnt, trans_pcie->queue_used),
1275                                 !!test_bit(cnt, trans_pcie->queue_stopped));
1276         }
1277         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1278         kfree(buf);
1279         return ret;
1280 }
1281
1282 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1283                                        char __user *user_buf,
1284                                        size_t count, loff_t *ppos)
1285 {
1286         struct iwl_trans *trans = file->private_data;
1287         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1288         struct iwl_rxq *rxq = &trans_pcie->rxq;
1289         char buf[256];
1290         int pos = 0;
1291         const size_t bufsz = sizeof(buf);
1292
1293         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1294                                                 rxq->read);
1295         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1296                                                 rxq->write);
1297         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1298                                                 rxq->free_count);
1299         if (rxq->rb_stts) {
1300                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1301                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1302         } else {
1303                 pos += scnprintf(buf + pos, bufsz - pos,
1304                                         "closed_rb_num: Not Allocated\n");
1305         }
1306         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1307 }
1308
1309 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1310                                         char __user *user_buf,
1311                                         size_t count, loff_t *ppos)
1312 {
1313         struct iwl_trans *trans = file->private_data;
1314         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1315         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1316
1317         int pos = 0;
1318         char *buf;
1319         int bufsz = 24 * 64; /* 24 items * 64 char per item */
1320         ssize_t ret;
1321
1322         buf = kzalloc(bufsz, GFP_KERNEL);
1323         if (!buf)
1324                 return -ENOMEM;
1325
1326         pos += scnprintf(buf + pos, bufsz - pos,
1327                         "Interrupt Statistics Report:\n");
1328
1329         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1330                 isr_stats->hw);
1331         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1332                 isr_stats->sw);
1333         if (isr_stats->sw || isr_stats->hw) {
1334                 pos += scnprintf(buf + pos, bufsz - pos,
1335                         "\tLast Restarting Code:  0x%X\n",
1336                         isr_stats->err_code);
1337         }
1338 #ifdef CONFIG_IWLWIFI_DEBUG
1339         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1340                 isr_stats->sch);
1341         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1342                 isr_stats->alive);
1343 #endif
1344         pos += scnprintf(buf + pos, bufsz - pos,
1345                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1346
1347         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1348                 isr_stats->ctkill);
1349
1350         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1351                 isr_stats->wakeup);
1352
1353         pos += scnprintf(buf + pos, bufsz - pos,
1354                 "Rx command responses:\t\t %u\n", isr_stats->rx);
1355
1356         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1357                 isr_stats->tx);
1358
1359         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1360                 isr_stats->unhandled);
1361
1362         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1363         kfree(buf);
1364         return ret;
1365 }
1366
1367 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1368                                          const char __user *user_buf,
1369                                          size_t count, loff_t *ppos)
1370 {
1371         struct iwl_trans *trans = file->private_data;
1372         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1373         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1374
1375         char buf[8];
1376         int buf_size;
1377         u32 reset_flag;
1378
1379         memset(buf, 0, sizeof(buf));
1380         buf_size = min(count, sizeof(buf) -  1);
1381         if (copy_from_user(buf, user_buf, buf_size))
1382                 return -EFAULT;
1383         if (sscanf(buf, "%x", &reset_flag) != 1)
1384                 return -EFAULT;
1385         if (reset_flag == 0)
1386                 memset(isr_stats, 0, sizeof(*isr_stats));
1387
1388         return count;
1389 }
1390
1391 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1392                                    const char __user *user_buf,
1393                                    size_t count, loff_t *ppos)
1394 {
1395         struct iwl_trans *trans = file->private_data;
1396         char buf[8];
1397         int buf_size;
1398         int csr;
1399
1400         memset(buf, 0, sizeof(buf));
1401         buf_size = min(count, sizeof(buf) -  1);
1402         if (copy_from_user(buf, user_buf, buf_size))
1403                 return -EFAULT;
1404         if (sscanf(buf, "%d", &csr) != 1)
1405                 return -EFAULT;
1406
1407         iwl_pcie_dump_csr(trans);
1408
1409         return count;
1410 }
1411
1412 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1413                                      char __user *user_buf,
1414                                      size_t count, loff_t *ppos)
1415 {
1416         struct iwl_trans *trans = file->private_data;
1417         char *buf = NULL;
1418         int pos = 0;
1419         ssize_t ret = -EFAULT;
1420
1421         ret = pos = iwl_dump_fh(trans, &buf);
1422         if (buf) {
1423                 ret = simple_read_from_buffer(user_buf,
1424                                               count, ppos, buf, pos);
1425                 kfree(buf);
1426         }
1427
1428         return ret;
1429 }
1430
1431 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1432 DEBUGFS_READ_FILE_OPS(fh_reg);
1433 DEBUGFS_READ_FILE_OPS(rx_queue);
1434 DEBUGFS_READ_FILE_OPS(tx_queue);
1435 DEBUGFS_WRITE_FILE_OPS(csr);
1436
1437 /*
1438  * Create the debugfs files and directories
1439  *
1440  */
1441 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1442                                          struct dentry *dir)
1443 {
1444         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1445         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1446         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1447         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1448         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1449         return 0;
1450
1451 err:
1452         IWL_ERR(trans, "failed to create the trans debugfs entry\n");
1453         return -ENOMEM;
1454 }
1455 #else
1456 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1457                                          struct dentry *dir)
1458 {
1459         return 0;
1460 }
1461 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1462
1463 static const struct iwl_trans_ops trans_ops_pcie = {
1464         .start_hw = iwl_trans_pcie_start_hw,
1465         .op_mode_leave = iwl_trans_pcie_op_mode_leave,
1466         .fw_alive = iwl_trans_pcie_fw_alive,
1467         .start_fw = iwl_trans_pcie_start_fw,
1468         .stop_device = iwl_trans_pcie_stop_device,
1469
1470         .d3_suspend = iwl_trans_pcie_d3_suspend,
1471         .d3_resume = iwl_trans_pcie_d3_resume,
1472
1473         .send_cmd = iwl_trans_pcie_send_hcmd,
1474
1475         .tx = iwl_trans_pcie_tx,
1476         .reclaim = iwl_trans_pcie_reclaim,
1477
1478         .txq_disable = iwl_trans_pcie_txq_disable,
1479         .txq_enable = iwl_trans_pcie_txq_enable,
1480
1481         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
1482
1483         .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
1484
1485         .write8 = iwl_trans_pcie_write8,
1486         .write32 = iwl_trans_pcie_write32,
1487         .read32 = iwl_trans_pcie_read32,
1488         .read_prph = iwl_trans_pcie_read_prph,
1489         .write_prph = iwl_trans_pcie_write_prph,
1490         .read_mem = iwl_trans_pcie_read_mem,
1491         .write_mem = iwl_trans_pcie_write_mem,
1492         .configure = iwl_trans_pcie_configure,
1493         .set_pmi = iwl_trans_pcie_set_pmi,
1494         .grab_nic_access = iwl_trans_pcie_grab_nic_access,
1495         .release_nic_access = iwl_trans_pcie_release_nic_access,
1496         .set_bits_mask = iwl_trans_pcie_set_bits_mask,
1497 };
1498
1499 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
1500                                        const struct pci_device_id *ent,
1501                                        const struct iwl_cfg *cfg)
1502 {
1503         struct iwl_trans_pcie *trans_pcie;
1504         struct iwl_trans *trans;
1505         u16 pci_cmd;
1506         int err;
1507
1508         trans = kzalloc(sizeof(struct iwl_trans) +
1509                         sizeof(struct iwl_trans_pcie), GFP_KERNEL);
1510         if (!trans) {
1511                 err = -ENOMEM;
1512                 goto out;
1513         }
1514
1515         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1516
1517         trans->ops = &trans_ops_pcie;
1518         trans->cfg = cfg;
1519         trans_lockdep_init(trans);
1520         trans_pcie->trans = trans;
1521         spin_lock_init(&trans_pcie->irq_lock);
1522         spin_lock_init(&trans_pcie->reg_lock);
1523         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
1524
1525         err = pci_enable_device(pdev);
1526         if (err)
1527                 goto out_no_pci;
1528
1529         if (!cfg->base_params->pcie_l1_allowed) {
1530                 /*
1531                  * W/A - seems to solve weird behavior. We need to remove this
1532                  * if we don't want to stay in L1 all the time. This wastes a
1533                  * lot of power.
1534                  */
1535                 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
1536                                        PCIE_LINK_STATE_L1 |
1537                                        PCIE_LINK_STATE_CLKPM);
1538         }
1539
1540         pci_set_master(pdev);
1541
1542         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
1543         if (!err)
1544                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
1545         if (err) {
1546                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1547                 if (!err)
1548                         err = pci_set_consistent_dma_mask(pdev,
1549                                                           DMA_BIT_MASK(32));
1550                 /* both attempts failed: */
1551                 if (err) {
1552                         dev_err(&pdev->dev, "No suitable DMA available\n");
1553                         goto out_pci_disable_device;
1554                 }
1555         }
1556
1557         err = pci_request_regions(pdev, DRV_NAME);
1558         if (err) {
1559                 dev_err(&pdev->dev, "pci_request_regions failed\n");
1560                 goto out_pci_disable_device;
1561         }
1562
1563         trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
1564         if (!trans_pcie->hw_base) {
1565                 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
1566                 err = -ENODEV;
1567                 goto out_pci_release_regions;
1568         }
1569
1570         /* We disable the RETRY_TIMEOUT register (0x41) to keep
1571          * PCI Tx retries from interfering with C3 CPU state */
1572         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
1573
1574         trans->dev = &pdev->dev;
1575         trans_pcie->pci_dev = pdev;
1576         iwl_disable_interrupts(trans);
1577
1578         err = pci_enable_msi(pdev);
1579         if (err) {
1580                 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
1581                 /* enable rfkill interrupt: hw bug w/a */
1582                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1583                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1584                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1585                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1586                 }
1587         }
1588
1589         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
1590         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
1591         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
1592                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
1593
1594         /* Initialize the wait queue for commands */
1595         init_waitqueue_head(&trans_pcie->wait_command_queue);
1596
1597         snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
1598                  "iwl_cmd_pool:%s", dev_name(trans->dev));
1599
1600         trans->dev_cmd_headroom = 0;
1601         trans->dev_cmd_pool =
1602                 kmem_cache_create(trans->dev_cmd_pool_name,
1603                                   sizeof(struct iwl_device_cmd)
1604                                   + trans->dev_cmd_headroom,
1605                                   sizeof(void *),
1606                                   SLAB_HWCACHE_ALIGN,
1607                                   NULL);
1608
1609         if (!trans->dev_cmd_pool) {
1610                 err = -ENOMEM;
1611                 goto out_pci_disable_msi;
1612         }
1613
1614         if (iwl_pcie_alloc_ict(trans))
1615                 goto out_free_cmd_pool;
1616
1617         err = request_threaded_irq(pdev->irq, iwl_pcie_isr,
1618                                    iwl_pcie_irq_handler,
1619                                    IRQF_SHARED, DRV_NAME, trans);
1620         if (err) {
1621                 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
1622                 goto out_free_ict;
1623         }
1624
1625         trans_pcie->inta_mask = CSR_INI_SET_MASK;
1626
1627         return trans;
1628
1629 out_free_ict:
1630         iwl_pcie_free_ict(trans);
1631 out_free_cmd_pool:
1632         kmem_cache_destroy(trans->dev_cmd_pool);
1633 out_pci_disable_msi:
1634         pci_disable_msi(pdev);
1635 out_pci_release_regions:
1636         pci_release_regions(pdev);
1637 out_pci_disable_device:
1638         pci_disable_device(pdev);
1639 out_no_pci:
1640         kfree(trans);
1641 out:
1642         return ERR_PTR(err);
1643 }