drivers/net/wireless/iwlwifi/pcie/rx.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29 #include <linux/sched.h>
  30 #include <linux/wait.h>
  31 #include <linux/gfp.h>
  32
  33 #include "iwl-prph.h"
  34 #include "iwl-io.h"
  35 #include "internal.h"
  36 #include "iwl-op-mode.h"
  37
  38 /******************************************************************************
  39  *
  40  * RX path functions
  41  *
  42  ******************************************************************************/
  43
  44 /*
  45  * Rx theory of operation
  46  *
  47  * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  48  * each of which point to Receive Buffers to be filled by the NIC.  These get
  49  * used not only for Rx frames, but for any command response or notification
  50  * from the NIC.  The driver and NIC manage the Rx buffers by means
  51  * of indexes into the circular buffer.
  52  *
  53  * Rx Queue Indexes
  54  * The host/firmware share two index registers for managing the Rx buffers.
  55  *
  56  * The READ index maps to the first position that the firmware may be writing
  57  * to -- the driver can read up to (but not including) this position and get
  58  * good data.
  59  * The READ index is managed by the firmware once the card is enabled.
  60  *
  61  * The WRITE index maps to the last position the driver has read from -- the
  62  * position preceding WRITE is the last slot the firmware can place a packet.
  63  *
  64  * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  65  * WRITE = READ.
  66  *
  67  * During initialization, the host sets up the READ queue position to the first
  68  * INDEX position, and WRITE to the last (READ - 1 wrapped)
  69  *
  70  * When the firmware places a packet in a buffer, it will advance the READ index
  71  * and fire the RX interrupt.  The driver can then query the READ index and
  72  * process as many packets as possible, moving the WRITE index forward as it
  73  * resets the Rx queue buffers with new memory.
  74  *
  75  * The management in the driver is as follows:
  76  * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free.  When
  77  *   iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  78  *   to replenish the iwl->rxq->rx_free.
  79  * + In iwl_pcie_rx_replenish (scheduled) if 'processed' != 'read' then the
  80  *   iwl->rxq is replenished and the READ INDEX is updated (updating the
  81  *   'processed' and 'read' driver indexes as well)
  82  * + A received packet is processed and handed to the kernel network stack,
  83  *   detached from the iwl->rxq.  The driver 'processed' index is updated.
  84  * + The Host/Firmware iwl->rxq is replenished at irq thread time from the
  85  *   rx_free list. If there are no allocated buffers in iwl->rxq->rx_free,
  86  *   the READ INDEX is not incremented and iwl->status(RX_STALLED) is set.
  87  *   If there were enough free buffers and RX_STALLED is set it is cleared.
  88  *
  89  *
  90  * Driver sequence:
  91  *
  92  * iwl_rxq_alloc()            Allocates rx_free
  93  * iwl_pcie_rx_replenish()    Replenishes rx_free list from rx_used, and calls
  94  *                            iwl_pcie_rxq_restock
  95  * iwl_pcie_rxq_restock()     Moves available buffers from rx_free into Rx
  96  *                            queue, updates firmware pointers, and updates
  97  *                            the WRITE index.  If insufficient rx_free buffers
  98  *                            are available, schedules iwl_pcie_rx_replenish
  99  *
 100  * -- enable interrupts --
 101  * ISR - iwl_rx()             Detach iwl_rx_mem_buffers from pool up to the
 102  *                            READ INDEX, detaching the SKB from the pool.
 103  *                            Moves the packet buffer from queue to rx_used.
 104  *                            Calls iwl_pcie_rxq_restock to refill any empty
 105  *                            slots.
 106  * ...
 107  *
 108  */
 109
 110 /*
 111  * iwl_rxq_space - Return number of free slots available in queue.
 112  */
 113 static int iwl_rxq_space(const struct iwl_rxq *rxq)
 114 {
 115         /* Make sure RX_QUEUE_SIZE is a power of 2 */
 116         BUILD_BUG_ON(RX_QUEUE_SIZE & (RX_QUEUE_SIZE - 1));
 117
 118         /*
 119          * There can be up to (RX_QUEUE_SIZE - 1) free slots, to avoid ambiguity
 120          * between empty and completely full queues.
 121          * The following is equivalent to modulo by RX_QUEUE_SIZE and is well
 122          * defined for negative dividends.
 123          */
 124         return (rxq->read - rxq->write - 1) & (RX_QUEUE_SIZE - 1);
 125 }
 126
 127 /*
 128  * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
 129  */
 130 static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr)
 131 {
 132         return cpu_to_le32((u32)(dma_addr >> 8));
 133 }
 134
 135 /*
 136  * iwl_pcie_rx_stop - stops the Rx DMA
 137  */
 138 int iwl_pcie_rx_stop(struct iwl_trans *trans)
 139 {
 140         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 141         return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
 142                                    FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
 143 }
 144
 145 /*
 146  * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue
 147  */
 148 static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans)
 149 {
 150         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 151         struct iwl_rxq *rxq = &trans_pcie->rxq;
 152         u32 reg;
 153
 154         lockdep_assert_held(&rxq->lock);
 155
 156         /*
 157          * explicitly wake up the NIC if:
 158          * 1. shadow registers aren't enabled
 159          * 2. there is a chance that the NIC is asleep
 160          */
 161         if (!trans->cfg->base_params->shadow_reg_enable &&
 162             test_bit(STATUS_TPOWER_PMI, &trans->status)) {
 163                 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
 164
 165                 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 166                         IWL_DEBUG_INFO(trans, "Rx queue requesting wakeup, GP1 = 0x%x\n",
 167                                        reg);
 168                         iwl_set_bit(trans, CSR_GP_CNTRL,
 169                                     CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 170                         rxq->need_update = true;
 171                         return;
 172                 }
 173         }
 174
 175         rxq->write_actual = round_down(rxq->write, 8);
 176         iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual);
 177 }
 178
 179 static void iwl_pcie_rxq_check_wrptr(struct iwl_trans *trans)
 180 {
 181         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 182         struct iwl_rxq *rxq = &trans_pcie->rxq;
 183
 184         spin_lock(&rxq->lock);
 185
 186         if (!rxq->need_update)
 187                 goto exit_unlock;
 188
 189         iwl_pcie_rxq_inc_wr_ptr(trans);
 190         rxq->need_update = false;
 191
 192  exit_unlock:
 193         spin_unlock(&rxq->lock);
 194 }
 195
 196 /*
 197  * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool
 198  *
 199  * If there are slots in the RX queue that need to be restocked,
 200  * and we have free pre-allocated buffers, fill the ranks as much
 201  * as we can, pulling from rx_free.
 202  *
 203  * This moves the 'write' index forward to catch up with 'processed', and
 204  * also updates the memory address in the firmware to reference the new
 205  * target buffer.
 206  */
 207 static void iwl_pcie_rxq_restock(struct iwl_trans *trans)
 208 {
 209         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 210         struct iwl_rxq *rxq = &trans_pcie->rxq;
 211         struct iwl_rx_mem_buffer *rxb;
 212
 213         /*
 214          * If the device isn't enabled - not need to try to add buffers...
 215          * This can happen when we stop the device and still have an interrupt
 216          * pending. We stop the APM before we sync the interrupts because we
 217          * have to (see comment there). On the other hand, since the APM is
 218          * stopped, we cannot access the HW (in particular not prph).
 219          * So don't try to restock if the APM has been already stopped.
 220          */
 221         if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 222                 return;
 223
 224         spin_lock(&rxq->lock);
 225         while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) {
 226                 /* The overwritten rxb must be a used one */
 227                 rxb = rxq->queue[rxq->write];
 228                 BUG_ON(rxb && rxb->page);
 229
 230                 /* Get next free Rx buffer, remove from free list */
 231                 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer,
 232                                        list);
 233                 list_del(&rxb->list);
 234
 235                 /* Point to Rx buffer via next RBD in circular buffer */
 236                 rxq->bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma);
 237                 rxq->queue[rxq->write] = rxb;
 238                 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
 239                 rxq->free_count--;
 240         }
 241         spin_unlock(&rxq->lock);
 242         /* If the pre-allocated buffer pool is dropping low, schedule to
 243          * refill it */
 244         if (rxq->free_count <= RX_LOW_WATERMARK)
 245                 schedule_work(&trans_pcie->rx_replenish);
 246
 247         /* If we've added more space for the firmware to place data, tell it.
 248          * Increment device's write pointer in multiples of 8. */
 249         if (rxq->write_actual != (rxq->write & ~0x7)) {
 250                 spin_lock(&rxq->lock);
 251                 iwl_pcie_rxq_inc_wr_ptr(trans);
 252                 spin_unlock(&rxq->lock);
 253         }
 254 }
 255
 256 /*
 257  * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD
 258  *
 259  * A used RBD is an Rx buffer that has been given to the stack. To use it again
 260  * a page must be allocated and the RBD must point to the page. This function
 261  * doesn't change the HW pointer but handles the list of pages that is used by
 262  * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly
 263  * allocated buffers.
 264  */
 265 static void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority)
 266 {
 267         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 268         struct iwl_rxq *rxq = &trans_pcie->rxq;
 269         struct iwl_rx_mem_buffer *rxb;
 270         struct page *page;
 271         gfp_t gfp_mask = priority;
 272
 273         while (1) {
 274                 spin_lock(&rxq->lock);
 275                 if (list_empty(&rxq->rx_used)) {
 276                         spin_unlock(&rxq->lock);
 277                         return;
 278                 }
 279                 spin_unlock(&rxq->lock);
 280
 281                 if (rxq->free_count > RX_LOW_WATERMARK)
 282                         gfp_mask |= __GFP_NOWARN;
 283
 284                 if (trans_pcie->rx_page_order > 0)
 285                         gfp_mask |= __GFP_COMP;
 286
 287                 /* Alloc a new receive buffer */
 288                 page = alloc_pages(gfp_mask, trans_pcie->rx_page_order);
 289                 if (!page) {
 290                         if (net_ratelimit())
 291                                 IWL_DEBUG_INFO(trans, "alloc_pages failed, "
 292                                            "order: %d\n",
 293                                            trans_pcie->rx_page_order);
 294
 295                         if ((rxq->free_count <= RX_LOW_WATERMARK) &&
 296                             net_ratelimit())
 297                                 IWL_CRIT(trans, "Failed to alloc_pages with %s."
 298                                          "Only %u free buffers remaining.\n",
 299                                          priority == GFP_ATOMIC ?
 300                                          "GFP_ATOMIC" : "GFP_KERNEL",
 301                                          rxq->free_count);
 302                         /* We don't reschedule replenish work here -- we will
 303                          * call the restock method and if it still needs
 304                          * more buffers it will schedule replenish */
 305                         return;
 306                 }
 307
 308                 spin_lock(&rxq->lock);
 309
 310                 if (list_empty(&rxq->rx_used)) {
 311                         spin_unlock(&rxq->lock);
 312                         __free_pages(page, trans_pcie->rx_page_order);
 313                         return;
 314                 }
 315                 rxb = list_first_entry(&rxq->rx_used, struct iwl_rx_mem_buffer,
 316                                        list);
 317                 list_del(&rxb->list);
 318                 spin_unlock(&rxq->lock);
 319
 320                 BUG_ON(rxb->page);
 321                 rxb->page = page;
 322                 /* Get physical address of the RB */
 323                 rxb->page_dma =
 324                         dma_map_page(trans->dev, page, 0,
 325                                      PAGE_SIZE << trans_pcie->rx_page_order,
 326                                      DMA_FROM_DEVICE);
 327                 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
 328                         rxb->page = NULL;
 329                         spin_lock(&rxq->lock);
 330                         list_add(&rxb->list, &rxq->rx_used);
 331                         spin_unlock(&rxq->lock);
 332                         __free_pages(page, trans_pcie->rx_page_order);
 333                         return;
 334                 }
 335                 /* dma address must be no more than 36 bits */
 336                 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
 337                 /* and also 256 byte aligned! */
 338                 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
 339
 340                 spin_lock(&rxq->lock);
 341
 342                 list_add_tail(&rxb->list, &rxq->rx_free);
 343                 rxq->free_count++;
 344
 345                 spin_unlock(&rxq->lock);
 346         }
 347 }
 348
 349 static void iwl_pcie_rxq_free_rbs(struct iwl_trans *trans)
 350 {
 351         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 352         struct iwl_rxq *rxq = &trans_pcie->rxq;
 353         int i;
 354
 355         lockdep_assert_held(&rxq->lock);
 356
 357         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
 358                 if (!rxq->pool[i].page)
 359                         continue;
 360                 dma_unmap_page(trans->dev, rxq->pool[i].page_dma,
 361                                PAGE_SIZE << trans_pcie->rx_page_order,
 362                                DMA_FROM_DEVICE);
 363                 __free_pages(rxq->pool[i].page, trans_pcie->rx_page_order);
 364                 rxq->pool[i].page = NULL;
 365         }
 366 }
 367
 368 /*
 369  * iwl_pcie_rx_replenish - Move all used buffers from rx_used to rx_free
 370  *
 371  * When moving to rx_free an page is allocated for the slot.
 372  *
 373  * Also restock the Rx queue via iwl_pcie_rxq_restock.
 374  * This is called as a scheduled work item (except for during initialization)
 375  */
 376 static void iwl_pcie_rx_replenish(struct iwl_trans *trans, gfp_t gfp)
 377 {
 378         iwl_pcie_rxq_alloc_rbs(trans, gfp);
 379
 380         iwl_pcie_rxq_restock(trans);
 381 }
 382
 383 static void iwl_pcie_rx_replenish_work(struct work_struct *data)
 384 {
 385         struct iwl_trans_pcie *trans_pcie =
 386             container_of(data, struct iwl_trans_pcie, rx_replenish);
 387
 388         iwl_pcie_rx_replenish(trans_pcie->trans, GFP_KERNEL);
 389 }
 390
 391 static int iwl_pcie_rx_alloc(struct iwl_trans *trans)
 392 {
 393         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 394         struct iwl_rxq *rxq = &trans_pcie->rxq;
 395         struct device *dev = trans->dev;
 396
 397         memset(&trans_pcie->rxq, 0, sizeof(trans_pcie->rxq));
 398
 399         spin_lock_init(&rxq->lock);
 400
 401         if (WARN_ON(rxq->bd || rxq->rb_stts))
 402                 return -EINVAL;
 403
 404         /* Allocate the circular buffer of Read Buffer Descriptors (RBDs) */
 405         rxq->bd = dma_zalloc_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
 406                                       &rxq->bd_dma, GFP_KERNEL);
 407         if (!rxq->bd)
 408                 goto err_bd;
 409
 410         /*Allocate the driver's pointer to receive buffer status */
 411         rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
 412                                            &rxq->rb_stts_dma, GFP_KERNEL);
 413         if (!rxq->rb_stts)
 414                 goto err_rb_stts;
 415
 416         return 0;
 417
 418 err_rb_stts:
 419         dma_free_coherent(dev, sizeof(__le32) * RX_QUEUE_SIZE,
 420                           rxq->bd, rxq->bd_dma);
 421         rxq->bd_dma = 0;
 422         rxq->bd = NULL;
 423 err_bd:
 424         return -ENOMEM;
 425 }
 426
 427 static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq)
 428 {
 429         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 430         u32 rb_size;
 431         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
 432
 433         if (trans_pcie->rx_buf_size_8k)
 434                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 435         else
 436                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 437
 438         /* Stop Rx DMA */
 439         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 440         /* reset and flush pointers */
 441         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0);
 442         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0);
 443         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RDPTR, 0);
 444
 445         /* Reset driver's Rx queue write index */
 446         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 447
 448         /* Tell device where to find RBD circular buffer in DRAM */
 449         iwl_write_direct32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 450                            (u32)(rxq->bd_dma >> 8));
 451
 452         /* Tell device where in DRAM to update its Rx status */
 453         iwl_write_direct32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
 454                            rxq->rb_stts_dma >> 4);
 455
 456         /* Enable Rx DMA
 457          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
 458          *      the credit mechanism in 5000 HW RX FIFO
 459          * Direct rx interrupts to hosts
 460          * Rx buffer size 4 or 8k
 461          * RB timeout 0x10
 462          * 256 RBDs
 463          */
 464         iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
 465                            FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 466                            FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
 467                            FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 468                            rb_size|
 469                            (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
 470                            (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 471
 472         /* Set interrupt coalescing timer to default (2048 usecs) */
 473         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 474
 475         /* W/A for interrupt coalescing bug in 7260 and 3160 */
 476         if (trans->cfg->host_interrupt_operation_mode)
 477                 iwl_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE);
 478 }
 479
 480 static void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq)
 481 {
 482         int i;
 483
 484         lockdep_assert_held(&rxq->lock);
 485
 486         INIT_LIST_HEAD(&rxq->rx_free);
 487         INIT_LIST_HEAD(&rxq->rx_used);
 488         rxq->free_count = 0;
 489
 490         for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++)
 491                 list_add(&rxq->pool[i].list, &rxq->rx_used);
 492 }
 493
 494 int iwl_pcie_rx_init(struct iwl_trans *trans)
 495 {
 496         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 497         struct iwl_rxq *rxq = &trans_pcie->rxq;
 498         int i, err;
 499
 500         if (!rxq->bd) {
 501                 err = iwl_pcie_rx_alloc(trans);
 502                 if (err)
 503                         return err;
 504         }
 505
 506         spin_lock(&rxq->lock);
 507
 508         INIT_WORK(&trans_pcie->rx_replenish, iwl_pcie_rx_replenish_work);
 509
 510         /* free all first - we might be reconfigured for a different size */
 511         iwl_pcie_rxq_free_rbs(trans);
 512         iwl_pcie_rx_init_rxb_lists(rxq);
 513
 514         for (i = 0; i < RX_QUEUE_SIZE; i++)
 515                 rxq->queue[i] = NULL;
 516
 517         /* Set us so that we have processed and used all buffers, but have
 518          * not restocked the Rx queue with fresh buffers */
 519         rxq->read = rxq->write = 0;
 520         rxq->write_actual = 0;
 521         memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts));
 522         spin_unlock(&rxq->lock);
 523
 524         iwl_pcie_rx_replenish(trans, GFP_KERNEL);
 525
 526         iwl_pcie_rx_hw_init(trans, rxq);
 527
 528         spin_lock(&rxq->lock);
 529         iwl_pcie_rxq_inc_wr_ptr(trans);
 530         spin_unlock(&rxq->lock);
 531
 532         return 0;
 533 }
 534
 535 void iwl_pcie_rx_free(struct iwl_trans *trans)
 536 {
 537         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 538         struct iwl_rxq *rxq = &trans_pcie->rxq;
 539
 540         /*if rxq->bd is NULL, it means that nothing has been allocated,
 541          * exit now */
 542         if (!rxq->bd) {
 543                 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
 544                 return;
 545         }
 546
 547         cancel_work_sync(&trans_pcie->rx_replenish);
 548
 549         spin_lock(&rxq->lock);
 550         iwl_pcie_rxq_free_rbs(trans);
 551         spin_unlock(&rxq->lock);
 552
 553         dma_free_coherent(trans->dev, sizeof(__le32) * RX_QUEUE_SIZE,
 554                           rxq->bd, rxq->bd_dma);
 555         rxq->bd_dma = 0;
 556         rxq->bd = NULL;
 557
 558         if (rxq->rb_stts)
 559                 dma_free_coherent(trans->dev,
 560                                   sizeof(struct iwl_rb_status),
 561                                   rxq->rb_stts, rxq->rb_stts_dma);
 562         else
 563                 IWL_DEBUG_INFO(trans, "Free rxq->rb_stts which is NULL\n");
 564         rxq->rb_stts_dma = 0;
 565         rxq->rb_stts = NULL;
 566 }
 567
 568 static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans,
 569                                 struct iwl_rx_mem_buffer *rxb)
 570 {
 571         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 572         struct iwl_rxq *rxq = &trans_pcie->rxq;
 573         struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
 574         bool page_stolen = false;
 575         int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
 576         u32 offset = 0;
 577
 578         if (WARN_ON(!rxb))
 579                 return;
 580
 581         dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE);
 582
 583         while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) {
 584                 struct iwl_rx_packet *pkt;
 585                 struct iwl_device_cmd *cmd;
 586                 u16 sequence;
 587                 bool reclaim;
 588                 int index, cmd_index, err, len;
 589                 struct iwl_rx_cmd_buffer rxcb = {
 590                         ._offset = offset,
 591                         ._rx_page_order = trans_pcie->rx_page_order,
 592                         ._page = rxb->page,
 593                         ._page_stolen = false,
 594                         .truesize = max_len,
 595                 };
 596
 597                 pkt = rxb_addr(&rxcb);
 598
 599                 if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID))
 600                         break;
 601
 602                 IWL_DEBUG_RX(trans, "cmd at offset %d: %s (0x%.2x)\n",
 603                         rxcb._offset, get_cmd_string(trans_pcie, pkt->hdr.cmd),
 604                         pkt->hdr.cmd);
 605
 606                 len = iwl_rx_packet_len(pkt);
 607                 len += sizeof(u32); /* account for status word */
 608                 trace_iwlwifi_dev_rx(trans->dev, trans, pkt, len);
 609                 trace_iwlwifi_dev_rx_data(trans->dev, trans, pkt, len);
 610
 611                 /* Reclaim a command buffer only if this packet is a response
 612                  *   to a (driver-originated) command.
 613                  * If the packet (e.g. Rx frame) originated from uCode,
 614                  *   there is no command buffer to reclaim.
 615                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
 616                  *   but apparently a few don't get set; catch them here. */
 617                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME);
 618                 if (reclaim) {
 619                         int i;
 620
 621                         for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) {
 622                                 if (trans_pcie->no_reclaim_cmds[i] ==
 623                                                         pkt->hdr.cmd) {
 624                                         reclaim = false;
 625                                         break;
 626                                 }
 627                         }
 628                 }
 629
 630                 sequence = le16_to_cpu(pkt->hdr.sequence);
 631                 index = SEQ_TO_INDEX(sequence);
 632                 cmd_index = get_cmd_index(&txq->q, index);
 633
 634                 if (reclaim)
 635                         cmd = txq->entries[cmd_index].cmd;
 636                 else
 637                         cmd = NULL;
 638
 639                 err = iwl_op_mode_rx(trans->op_mode, &rxcb, cmd);
 640
 641                 if (reclaim) {
 642                         kfree(txq->entries[cmd_index].free_buf);
 643                         txq->entries[cmd_index].free_buf = NULL;
 644                 }
 645
 646                 /*
 647                  * After here, we should always check rxcb._page_stolen,
 648                  * if it is true then one of the handlers took the page.
 649                  */
 650
 651                 if (reclaim) {
 652                         /* Invoke any callbacks, transfer the buffer to caller,
 653                          * and fire off the (possibly) blocking
 654                          * iwl_trans_send_cmd()
 655                          * as we reclaim the driver command queue */
 656                         if (!rxcb._page_stolen)
 657                                 iwl_pcie_hcmd_complete(trans, &rxcb, err);
 658                         else
 659                                 IWL_WARN(trans, "Claim null rxb?\n");
 660                 }
 661
 662                 page_stolen |= rxcb._page_stolen;
 663                 offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN);
 664         }
 665
 666         /* page was stolen from us -- free our reference */
 667         if (page_stolen) {
 668                 __free_pages(rxb->page, trans_pcie->rx_page_order);
 669                 rxb->page = NULL;
 670         }
 671
 672         /* Reuse the page if possible. For notification packets and
 673          * SKBs that fail to Rx correctly, add them back into the
 674          * rx_free list for reuse later. */
 675         if (rxb->page != NULL) {
 676                 rxb->page_dma =
 677                         dma_map_page(trans->dev, rxb->page, 0,
 678                                      PAGE_SIZE << trans_pcie->rx_page_order,
 679                                      DMA_FROM_DEVICE);
 680                 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
 681                         /*
 682                          * free the page(s) as well to not break
 683                          * the invariant that the items on the used
 684                          * list have no page(s)
 685                          */
 686                         __free_pages(rxb->page, trans_pcie->rx_page_order);
 687                         rxb->page = NULL;
 688                         list_add_tail(&rxb->list, &rxq->rx_used);
 689                 } else {
 690                         list_add_tail(&rxb->list, &rxq->rx_free);
 691                         rxq->free_count++;
 692                 }
 693         } else
 694                 list_add_tail(&rxb->list, &rxq->rx_used);
 695 }
 696
 697 /*
 698  * iwl_pcie_rx_handle - Main entry function for receiving responses from fw
 699  */
 700 static void iwl_pcie_rx_handle(struct iwl_trans *trans)
 701 {
 702         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 703         struct iwl_rxq *rxq = &trans_pcie->rxq;
 704         u32 r, i;
 705         u8 fill_rx = 0;
 706         u32 count = 8;
 707         int total_empty;
 708
 709 restart:
 710         spin_lock(&rxq->lock);
 711         /* uCode's read index (stored in shared DRAM) indicates the last Rx
 712          * buffer that the driver may process (last buffer filled by ucode). */
 713         r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
 714         i = rxq->read;
 715
 716         /* Rx interrupt, but nothing sent from uCode */
 717         if (i == r)
 718                 IWL_DEBUG_RX(trans, "HW = SW = %d\n", r);
 719
 720         /* calculate total frames need to be restock after handling RX */
 721         total_empty = r - rxq->write_actual;
 722         if (total_empty < 0)
 723                 total_empty += RX_QUEUE_SIZE;
 724
 725         if (total_empty > (RX_QUEUE_SIZE / 2))
 726                 fill_rx = 1;
 727
 728         while (i != r) {
 729                 struct iwl_rx_mem_buffer *rxb;
 730
 731                 rxb = rxq->queue[i];
 732                 rxq->queue[i] = NULL;
 733
 734                 IWL_DEBUG_RX(trans, "rxbuf: HW = %d, SW = %d (%p)\n",
 735                              r, i, rxb);
 736                 iwl_pcie_rx_handle_rb(trans, rxb);
 737
 738                 i = (i + 1) & RX_QUEUE_MASK;
 739                 /* If there are a lot of unused frames,
 740                  * restock the Rx queue so ucode wont assert. */
 741                 if (fill_rx) {
 742                         count++;
 743                         if (count >= 8) {
 744                                 rxq->read = i;
 745                                 spin_unlock(&rxq->lock);
 746                                 iwl_pcie_rx_replenish(trans, GFP_ATOMIC);
 747                                 count = 0;
 748                                 goto restart;
 749                         }
 750                 }
 751         }
 752
 753         /* Backtrack one entry */
 754         rxq->read = i;
 755         spin_unlock(&rxq->lock);
 756
 757         if (fill_rx)
 758                 iwl_pcie_rx_replenish(trans, GFP_ATOMIC);
 759         else
 760                 iwl_pcie_rxq_restock(trans);
 761
 762         if (trans_pcie->napi.poll)
 763                 napi_gro_flush(&trans_pcie->napi, false);
 764 }
 765
 766 /*
 767  * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card
 768  */
 769 static void iwl_pcie_irq_handle_error(struct iwl_trans *trans)
 770 {
 771         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 772
 773         /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
 774         if (trans->cfg->internal_wimax_coex &&
 775             (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) &
 776                              APMS_CLK_VAL_MRB_FUNC_MODE) ||
 777              (iwl_read_prph(trans, APMG_PS_CTRL_REG) &
 778                             APMG_PS_CTRL_VAL_RESET_REQ))) {
 779                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
 780                 iwl_op_mode_wimax_active(trans->op_mode);
 781                 wake_up(&trans_pcie->wait_command_queue);
 782                 return;
 783         }
 784
 785         iwl_pcie_dump_csr(trans);
 786         iwl_dump_fh(trans, NULL);
 787
 788         local_bh_disable();
 789         /* The STATUS_FW_ERROR bit is set in this function. This must happen
 790          * before we wake up the command caller, to ensure a proper cleanup. */
 791         iwl_trans_fw_error(trans);
 792         local_bh_enable();
 793
 794         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
 795         wake_up(&trans_pcie->wait_command_queue);
 796 }
 797
 798 static u32 iwl_pcie_int_cause_non_ict(struct iwl_trans *trans)
 799 {
 800         u32 inta;
 801
 802         lockdep_assert_held(&IWL_TRANS_GET_PCIE_TRANS(trans)->irq_lock);
 803
 804         trace_iwlwifi_dev_irq(trans->dev);
 805
 806         /* Discover which interrupts are active/pending */
 807         inta = iwl_read32(trans, CSR_INT);
 808
 809         /* the thread will service interrupts and re-enable them */
 810         return inta;
 811 }
 812
 813 /* a device (PCI-E) page is 4096 bytes long */
 814 #define ICT_SHIFT       12
 815 #define ICT_SIZE        (1 << ICT_SHIFT)
 816 #define ICT_COUNT       (ICT_SIZE / sizeof(u32))
 817
 818 /* interrupt handler using ict table, with this interrupt driver will
 819  * stop using INTA register to get device's interrupt, reading this register
 820  * is expensive, device will write interrupts in ICT dram table, increment
 821  * index then will fire interrupt to driver, driver will OR all ICT table
 822  * entries from current index up to table entry with 0 value. the result is
 823  * the interrupt we need to service, driver will set the entries back to 0 and
 824  * set index.
 825  */
 826 static u32 iwl_pcie_int_cause_ict(struct iwl_trans *trans)
 827 {
 828         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 829         u32 inta;
 830         u32 val = 0;
 831         u32 read;
 832
 833         trace_iwlwifi_dev_irq(trans->dev);
 834
 835         /* Ignore interrupt if there's nothing in NIC to service.
 836          * This may be due to IRQ shared with another device,
 837          * or due to sporadic interrupts thrown from our NIC. */
 838         read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
 839         trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read);
 840         if (!read)
 841                 return 0;
 842
 843         /*
 844          * Collect all entries up to the first 0, starting from ict_index;
 845          * note we already read at ict_index.
 846          */
 847         do {
 848                 val |= read;
 849                 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
 850                                 trans_pcie->ict_index, read);
 851                 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
 852                 trans_pcie->ict_index =
 853                         ((trans_pcie->ict_index + 1) & (ICT_COUNT - 1));
 854
 855                 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
 856                 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index,
 857                                            read);
 858         } while (read);
 859
 860         /* We should not get this value, just ignore it. */
 861         if (val == 0xffffffff)
 862                 val = 0;
 863
 864         /*
 865          * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
 866          * (bit 15 before shifting it to 31) to clear when using interrupt
 867          * coalescing. fortunately, bits 18 and 19 stay set when this happens
 868          * so we use them to decide on the real state of the Rx bit.
 869          * In order words, bit 15 is set if bit 18 or bit 19 are set.
 870          */
 871         if (val & 0xC0000)
 872                 val |= 0x8000;
 873
 874         inta = (0xff & val) | ((0xff00 & val) << 16);
 875         return inta;
 876 }
 877
 878 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id)
 879 {
 880         struct iwl_trans *trans = dev_id;
 881         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 882         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
 883         u32 inta = 0;
 884         u32 handled = 0;
 885
 886         lock_map_acquire(&trans->sync_cmd_lockdep_map);
 887
 888         spin_lock(&trans_pcie->irq_lock);
 889
 890         /* dram interrupt table not set yet,
 891          * use legacy interrupt.
 892          */
 893         if (likely(trans_pcie->use_ict))
 894                 inta = iwl_pcie_int_cause_ict(trans);
 895         else
 896                 inta = iwl_pcie_int_cause_non_ict(trans);
 897
 898         if (iwl_have_debug_level(IWL_DL_ISR)) {
 899                 IWL_DEBUG_ISR(trans,
 900                               "ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\n",
 901                               inta, trans_pcie->inta_mask,
 902                               iwl_read32(trans, CSR_INT_MASK),
 903                               iwl_read32(trans, CSR_FH_INT_STATUS));
 904                 if (inta & (~trans_pcie->inta_mask))
 905                         IWL_DEBUG_ISR(trans,
 906                                       "We got a masked interrupt (0x%08x)\n",
 907                                       inta & (~trans_pcie->inta_mask));
 908         }
 909
 910         inta &= trans_pcie->inta_mask;
 911
 912         /*
 913          * Ignore interrupt if there's nothing in NIC to service.
 914          * This may be due to IRQ shared with another device,
 915          * or due to sporadic interrupts thrown from our NIC.
 916          */
 917         if (unlikely(!inta)) {
 918                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
 919                 /*
 920                  * Re-enable interrupts here since we don't
 921                  * have anything to service
 922                  */
 923                 if (test_bit(STATUS_INT_ENABLED, &trans->status))
 924                         iwl_enable_interrupts(trans);
 925                 spin_unlock(&trans_pcie->irq_lock);
 926                 lock_map_release(&trans->sync_cmd_lockdep_map);
 927                 return IRQ_NONE;
 928         }
 929
 930         if (unlikely(inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
 931                 /*
 932                  * Hardware disappeared. It might have
 933                  * already raised an interrupt.
 934                  */
 935                 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
 936                 spin_unlock(&trans_pcie->irq_lock);
 937                 goto out;
 938         }
 939
 940         /* Ack/clear/reset pending uCode interrupts.
 941          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
 942          */
 943         /* There is a hardware bug in the interrupt mask function that some
 944          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
 945          * they are disabled in the CSR_INT_MASK register. Furthermore the
 946          * ICT interrupt handling mechanism has another bug that might cause
 947          * these unmasked interrupts fail to be detected. We workaround the
 948          * hardware bugs here by ACKing all the possible interrupts so that
 949          * interrupt coalescing can still be achieved.
 950          */
 951         iwl_write32(trans, CSR_INT, inta | ~trans_pcie->inta_mask);
 952
 953         if (iwl_have_debug_level(IWL_DL_ISR))
 954                 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n",
 955                               inta, iwl_read32(trans, CSR_INT_MASK));
 956
 957         spin_unlock(&trans_pcie->irq_lock);
 958
 959         /* Now service all interrupt bits discovered above. */
 960         if (inta & CSR_INT_BIT_HW_ERR) {
 961                 IWL_ERR(trans, "Hardware error detected.  Restarting.\n");
 962
 963                 /* Tell the device to stop sending interrupts */
 964                 iwl_disable_interrupts(trans);
 965
 966                 isr_stats->hw++;
 967                 iwl_pcie_irq_handle_error(trans);
 968
 969                 handled |= CSR_INT_BIT_HW_ERR;
 970
 971                 goto out;
 972         }
 973
 974         if (iwl_have_debug_level(IWL_DL_ISR)) {
 975                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
 976                 if (inta & CSR_INT_BIT_SCD) {
 977                         IWL_DEBUG_ISR(trans,
 978                                       "Scheduler finished to transmit the frame/frames.\n");
 979                         isr_stats->sch++;
 980                 }
 981
 982                 /* Alive notification via Rx interrupt will do the real work */
 983                 if (inta & CSR_INT_BIT_ALIVE) {
 984                         IWL_DEBUG_ISR(trans, "Alive interrupt\n");
 985                         isr_stats->alive++;
 986                 }
 987         }
 988
 989         /* Safely ignore these bits for debug checks below */
 990         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
 991
 992         /* HW RF KILL switch toggled */
 993         if (inta & CSR_INT_BIT_RF_KILL) {
 994                 bool hw_rfkill;
 995
 996                 hw_rfkill = iwl_is_rfkill_set(trans);
 997                 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
 998                          hw_rfkill ? "disable radio" : "enable radio");
 999
1000                 isr_stats->rfkill++;
1001
1002                 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1003                 if (hw_rfkill) {
1004                         set_bit(STATUS_RFKILL, &trans->status);
1005                         if (test_and_clear_bit(STATUS_SYNC_HCMD_ACTIVE,
1006                                                &trans->status))
1007                                 IWL_DEBUG_RF_KILL(trans,
1008                                                   "Rfkill while SYNC HCMD in flight\n");
1009                         wake_up(&trans_pcie->wait_command_queue);
1010                 } else {
1011                         clear_bit(STATUS_RFKILL, &trans->status);
1012                 }
1013
1014                 handled |= CSR_INT_BIT_RF_KILL;
1015         }
1016
1017         /* Chip got too hot and stopped itself */
1018         if (inta & CSR_INT_BIT_CT_KILL) {
1019                 IWL_ERR(trans, "Microcode CT kill error detected.\n");
1020                 isr_stats->ctkill++;
1021                 handled |= CSR_INT_BIT_CT_KILL;
1022         }
1023
1024         /* Error detected by uCode */
1025         if (inta & CSR_INT_BIT_SW_ERR) {
1026                 IWL_ERR(trans, "Microcode SW error detected. "
1027                         " Restarting 0x%X.\n", inta);
1028                 isr_stats->sw++;
1029                 iwl_pcie_irq_handle_error(trans);
1030                 handled |= CSR_INT_BIT_SW_ERR;
1031         }
1032
1033         /* uCode wakes up after power-down sleep */
1034         if (inta & CSR_INT_BIT_WAKEUP) {
1035                 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
1036                 iwl_pcie_rxq_check_wrptr(trans);
1037                 iwl_pcie_txq_check_wrptrs(trans);
1038
1039                 isr_stats->wakeup++;
1040
1041                 handled |= CSR_INT_BIT_WAKEUP;
1042         }
1043
1044         /* All uCode command responses, including Tx command responses,
1045          * Rx "responses" (frame-received notification), and other
1046          * notifications from uCode come through here*/
1047         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1048                     CSR_INT_BIT_RX_PERIODIC)) {
1049                 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
1050                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1051                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1052                         iwl_write32(trans, CSR_FH_INT_STATUS,
1053                                         CSR_FH_INT_RX_MASK);
1054                 }
1055                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1056                         handled |= CSR_INT_BIT_RX_PERIODIC;
1057                         iwl_write32(trans,
1058                                 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1059                 }
1060                 /* Sending RX interrupt require many steps to be done in the
1061                  * the device:
1062                  * 1- write interrupt to current index in ICT table.
1063                  * 2- dma RX frame.
1064                  * 3- update RX shared data to indicate last write index.
1065                  * 4- send interrupt.
1066                  * This could lead to RX race, driver could receive RX interrupt
1067                  * but the shared data changes does not reflect this;
1068                  * periodic interrupt will detect any dangling Rx activity.
1069                  */
1070
1071                 /* Disable periodic interrupt; we use it as just a one-shot. */
1072                 iwl_write8(trans, CSR_INT_PERIODIC_REG,
1073                             CSR_INT_PERIODIC_DIS);
1074
1075                 /*
1076                  * Enable periodic interrupt in 8 msec only if we received
1077                  * real RX interrupt (instead of just periodic int), to catch
1078                  * any dangling Rx interrupt.  If it was just the periodic
1079                  * interrupt, there was no dangling Rx activity, and no need
1080                  * to extend the periodic interrupt; one-shot is enough.
1081                  */
1082                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1083                         iwl_write8(trans, CSR_INT_PERIODIC_REG,
1084                                    CSR_INT_PERIODIC_ENA);
1085
1086                 isr_stats->rx++;
1087
1088                 local_bh_disable();
1089                 iwl_pcie_rx_handle(trans);
1090                 local_bh_enable();
1091         }
1092
1093         /* This "Tx" DMA channel is used only for loading uCode */
1094         if (inta & CSR_INT_BIT_FH_TX) {
1095                 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1096                 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
1097                 isr_stats->tx++;
1098                 handled |= CSR_INT_BIT_FH_TX;
1099                 /* Wake up uCode load routine, now that load is complete */
1100                 trans_pcie->ucode_write_complete = true;
1101                 wake_up(&trans_pcie->ucode_write_waitq);
1102         }
1103
1104         if (inta & ~handled) {
1105                 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1106                 isr_stats->unhandled++;
1107         }
1108
1109         if (inta & ~(trans_pcie->inta_mask)) {
1110                 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
1111                          inta & ~trans_pcie->inta_mask);
1112         }
1113
1114         /* Re-enable all interrupts */
1115         /* only Re-enable if disabled by irq */
1116         if (test_bit(STATUS_INT_ENABLED, &trans->status))
1117                 iwl_enable_interrupts(trans);
1118         /* Re-enable RF_KILL if it occurred */
1119         else if (handled & CSR_INT_BIT_RF_KILL)
1120                 iwl_enable_rfkill_int(trans);
1121
1122 out:
1123         lock_map_release(&trans->sync_cmd_lockdep_map);
1124         return IRQ_HANDLED;
1125 }
1126
1127 /******************************************************************************
1128  *
1129  * ICT functions
1130  *
1131  ******************************************************************************/
1132
1133 /* Free dram table */
1134 void iwl_pcie_free_ict(struct iwl_trans *trans)
1135 {
1136         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1137
1138         if (trans_pcie->ict_tbl) {
1139                 dma_free_coherent(trans->dev, ICT_SIZE,
1140                                   trans_pcie->ict_tbl,
1141                                   trans_pcie->ict_tbl_dma);
1142                 trans_pcie->ict_tbl = NULL;
1143                 trans_pcie->ict_tbl_dma = 0;
1144         }
1145 }
1146
1147 /*
1148  * allocate dram shared table, it is an aligned memory
1149  * block of ICT_SIZE.
1150  * also reset all data related to ICT table interrupt.
1151  */
1152 int iwl_pcie_alloc_ict(struct iwl_trans *trans)
1153 {
1154         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1155
1156         trans_pcie->ict_tbl =
1157                 dma_zalloc_coherent(trans->dev, ICT_SIZE,
1158                                    &trans_pcie->ict_tbl_dma,
1159                                    GFP_KERNEL);
1160         if (!trans_pcie->ict_tbl)
1161                 return -ENOMEM;
1162
1163         /* just an API sanity check ... it is guaranteed to be aligned */
1164         if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) {
1165                 iwl_pcie_free_ict(trans);
1166                 return -EINVAL;
1167         }
1168
1169         IWL_DEBUG_ISR(trans, "ict dma addr %Lx ict vir addr %p\n",
1170                       (unsigned long long)trans_pcie->ict_tbl_dma,
1171                       trans_pcie->ict_tbl);
1172
1173         return 0;
1174 }
1175
1176 /* Device is going up inform it about using ICT interrupt table,
1177  * also we need to tell the driver to start using ICT interrupt.
1178  */
1179 void iwl_pcie_reset_ict(struct iwl_trans *trans)
1180 {
1181         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1182         u32 val;
1183
1184         if (!trans_pcie->ict_tbl)
1185                 return;
1186
1187         spin_lock(&trans_pcie->irq_lock);
1188         iwl_disable_interrupts(trans);
1189
1190         memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1191
1192         val = trans_pcie->ict_tbl_dma >> ICT_SHIFT;
1193
1194         val |= CSR_DRAM_INT_TBL_ENABLE;
1195         val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
1196
1197         IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
1198
1199         iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);
1200         trans_pcie->use_ict = true;
1201         trans_pcie->ict_index = 0;
1202         iwl_write32(trans, CSR_INT, trans_pcie->inta_mask);
1203         iwl_enable_interrupts(trans);
1204         spin_unlock(&trans_pcie->irq_lock);
1205 }
1206
1207 /* Device is going down disable ict interrupt usage */
1208 void iwl_pcie_disable_ict(struct iwl_trans *trans)
1209 {
1210         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1211
1212         spin_lock(&trans_pcie->irq_lock);
1213         trans_pcie->use_ict = false;
1214         spin_unlock(&trans_pcie->irq_lock);
1215 }
1216
1217 irqreturn_t iwl_pcie_isr(int irq, void *data)
1218 {
1219         struct iwl_trans *trans = data;
1220
1221         if (!trans)
1222                 return IRQ_NONE;
1223
1224         /* Disable (but don't clear!) interrupts here to avoid
1225          * back-to-back ISRs and sporadic interrupts from our NIC.
1226          * If we have something to service, the tasklet will re-enable ints.
1227          * If we *don't* have something, we'll re-enable before leaving here.
1228          */
1229         iwl_write32(trans, CSR_INT_MASK, 0x00000000);
1230
1231         return IRQ_WAKE_THREAD;
1232 }