drivers/net/wireless/ath/wil6210/txrx_edma.c

   1 /*
   2  * Copyright (c) 2012-2018 The Linux Foundation. All rights reserved.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/etherdevice.h>
  18 #include <linux/moduleparam.h>
  19 #include <linux/prefetch.h>
  20 #include <linux/types.h>
  21 #include <linux/list.h>
  22 #include <linux/ip.h>
  23 #include <linux/ipv6.h>
  24 #include "wil6210.h"
  25 #include "txrx_edma.h"
  26 #include "txrx.h"
  27 #include "trace.h"
  28
  29 #define WIL_EDMA_MAX_DATA_OFFSET (2)
  30 /* RX buffer size must be aligned to 4 bytes */
  31 #define WIL_EDMA_RX_BUF_LEN_DEFAULT (2048)
  32
  33 static void wil_tx_desc_unmap_edma(struct device *dev,
  34                                    union wil_tx_desc *desc,
  35                                    struct wil_ctx *ctx)
  36 {
  37         struct wil_tx_enhanced_desc *d = (struct wil_tx_enhanced_desc *)desc;
  38         dma_addr_t pa = wil_tx_desc_get_addr_edma(&d->dma);
  39         u16 dmalen = le16_to_cpu(d->dma.length);
  40
  41         switch (ctx->mapped_as) {
  42         case wil_mapped_as_single:
  43                 dma_unmap_single(dev, pa, dmalen, DMA_TO_DEVICE);
  44                 break;
  45         case wil_mapped_as_page:
  46                 dma_unmap_page(dev, pa, dmalen, DMA_TO_DEVICE);
  47                 break;
  48         default:
  49                 break;
  50         }
  51 }
  52
  53 static int wil_find_free_sring(struct wil6210_priv *wil)
  54 {
  55         int i;
  56
  57         for (i = 0; i < WIL6210_MAX_STATUS_RINGS; i++) {
  58                 if (!wil->srings[i].va)
  59                         return i;
  60         }
  61
  62         return -EINVAL;
  63 }
  64
  65 static void wil_sring_free(struct wil6210_priv *wil,
  66                            struct wil_status_ring *sring)
  67 {
  68         struct device *dev = wil_to_dev(wil);
  69         size_t sz;
  70
  71         if (!sring || !sring->va)
  72                 return;
  73
  74         sz = sring->elem_size * sring->size;
  75
  76         wil_dbg_misc(wil, "status_ring_free, size(bytes)=%zu, 0x%p:%pad\n",
  77                      sz, sring->va, &sring->pa);
  78
  79         dma_free_coherent(dev, sz, (void *)sring->va, sring->pa);
  80         sring->pa = 0;
  81         sring->va = NULL;
  82 }
  83
  84 static int wil_sring_alloc(struct wil6210_priv *wil,
  85                            struct wil_status_ring *sring)
  86 {
  87         struct device *dev = wil_to_dev(wil);
  88         size_t sz = sring->elem_size * sring->size;
  89
  90         wil_dbg_misc(wil, "status_ring_alloc: size=%zu\n", sz);
  91
  92         if (sz == 0) {
  93                 wil_err(wil, "Cannot allocate a zero size status ring\n");
  94                 return -EINVAL;
  95         }
  96
  97         sring->swhead = 0;
  98
  99         /* Status messages are allocated and initialized to 0. This is necessary
 100          * since DR bit should be initialized to 0.
 101          */
 102         sring->va = dma_zalloc_coherent(dev, sz, &sring->pa, GFP_KERNEL);
 103         if (!sring->va)
 104                 return -ENOMEM;
 105
 106         wil_dbg_misc(wil, "status_ring[%d] 0x%p:%pad\n", sring->size, sring->va,
 107                      &sring->pa);
 108
 109         return 0;
 110 }
 111
 112 static int wil_tx_init_edma(struct wil6210_priv *wil)
 113 {
 114         int ring_id = wil_find_free_sring(wil);
 115         struct wil_status_ring *sring;
 116         int rc;
 117         u16 status_ring_size;
 118
 119         if (wil->tx_status_ring_order < WIL_SRING_SIZE_ORDER_MIN ||
 120             wil->tx_status_ring_order > WIL_SRING_SIZE_ORDER_MAX)
 121                 wil->tx_status_ring_order = WIL_TX_SRING_SIZE_ORDER_DEFAULT;
 122
 123         status_ring_size = 1 << wil->tx_status_ring_order;
 124
 125         wil_dbg_misc(wil, "init TX sring: size=%u, ring_id=%u\n",
 126                      status_ring_size, ring_id);
 127
 128         if (ring_id < 0)
 129                 return ring_id;
 130
 131         /* Allocate Tx status ring. Tx descriptor rings will be
 132          * allocated on WMI connect event
 133          */
 134         sring = &wil->srings[ring_id];
 135
 136         sring->is_rx = false;
 137         sring->size = status_ring_size;
 138         sring->elem_size = sizeof(struct wil_ring_tx_status);
 139         rc = wil_sring_alloc(wil, sring);
 140         if (rc)
 141                 return rc;
 142
 143         rc = wil_wmi_tx_sring_cfg(wil, ring_id);
 144         if (rc)
 145                 goto out_free;
 146
 147         sring->desc_rdy_pol = 1;
 148         wil->tx_sring_idx = ring_id;
 149
 150         return 0;
 151 out_free:
 152         wil_sring_free(wil, sring);
 153         return rc;
 154 }
 155
 156 /**
 157  * Allocate one skb for Rx descriptor RING
 158  */
 159 static int wil_ring_alloc_skb_edma(struct wil6210_priv *wil,
 160                                    struct wil_ring *ring, u32 i)
 161 {
 162         struct device *dev = wil_to_dev(wil);
 163         unsigned int sz = ALIGN(wil->rx_buf_len, 4);
 164         dma_addr_t pa;
 165         u16 buff_id;
 166         struct list_head *active = &wil->rx_buff_mgmt.active;
 167         struct list_head *free = &wil->rx_buff_mgmt.free;
 168         struct wil_rx_buff *rx_buff;
 169         struct wil_rx_buff *buff_arr = wil->rx_buff_mgmt.buff_arr;
 170         struct sk_buff *skb;
 171         struct wil_rx_enhanced_desc dd, *d = &dd;
 172         struct wil_rx_enhanced_desc *_d = (struct wil_rx_enhanced_desc *)
 173                 &ring->va[i].rx.enhanced;
 174
 175         if (unlikely(list_empty(free))) {
 176                 wil->rx_buff_mgmt.free_list_empty_cnt++;
 177                 return -EAGAIN;
 178         }
 179
 180         skb = dev_alloc_skb(sz);
 181         if (unlikely(!skb))
 182                 return -ENOMEM;
 183
 184         skb_put(skb, sz);
 185
 186         /**
 187          * Make sure that the network stack calculates checksum for packets
 188          * which failed the HW checksum calculation
 189          */
 190         skb->ip_summed = CHECKSUM_NONE;
 191
 192         pa = dma_map_single(dev, skb->data, skb->len, DMA_FROM_DEVICE);
 193         if (unlikely(dma_mapping_error(dev, pa))) {
 194                 kfree_skb(skb);
 195                 return -ENOMEM;
 196         }
 197
 198         /* Get the buffer ID - the index of the rx buffer in the buff_arr */
 199         rx_buff = list_first_entry(free, struct wil_rx_buff, list);
 200         buff_id = rx_buff->id;
 201
 202         /* Move a buffer from the free list to the active list */
 203         list_move(&rx_buff->list, active);
 204
 205         buff_arr[buff_id].skb = skb;
 206
 207         wil_desc_set_addr_edma(&d->dma.addr, &d->dma.addr_high_high, pa);
 208         d->dma.length = cpu_to_le16(sz);
 209         d->mac.buff_id = cpu_to_le16(buff_id);
 210         *_d = *d;
 211
 212         /* Save the physical address in skb->cb for later use in dma_unmap */
 213         memcpy(skb->cb, &pa, sizeof(pa));
 214
 215         return 0;
 216 }
 217
 218 static inline
 219 void wil_get_next_rx_status_msg(struct wil_status_ring *sring, void *msg)
 220 {
 221         memcpy(msg, (void *)(sring->va + (sring->elem_size * sring->swhead)),
 222                sring->elem_size);
 223 }
 224
 225 static inline void wil_sring_advance_swhead(struct wil_status_ring *sring)
 226 {
 227         sring->swhead = (sring->swhead + 1) % sring->size;
 228         if (sring->swhead == 0)
 229                 sring->desc_rdy_pol = 1 - sring->desc_rdy_pol;
 230 }
 231
 232 static int wil_rx_refill_edma(struct wil6210_priv *wil)
 233 {
 234         struct wil_ring *ring = &wil->ring_rx;
 235         u32 next_head;
 236         int rc = 0;
 237         ring->swtail = *ring->edma_rx_swtail.va;
 238
 239         for (; next_head = wil_ring_next_head(ring),
 240              (next_head != ring->swtail);
 241              ring->swhead = next_head) {
 242                 rc = wil_ring_alloc_skb_edma(wil, ring, ring->swhead);
 243                 if (unlikely(rc)) {
 244                         if (rc == -EAGAIN)
 245                                 wil_dbg_txrx(wil, "No free buffer ID found\n");
 246                         else
 247                                 wil_err_ratelimited(wil,
 248                                                     "Error %d in refill desc[%d]\n",
 249                                                     rc, ring->swhead);
 250                         break;
 251                 }
 252         }
 253
 254         /* make sure all writes to descriptors (shared memory) are done before
 255          * committing them to HW
 256          */
 257         wmb();
 258
 259         wil_w(wil, ring->hwtail, ring->swhead);
 260
 261         return rc;
 262 }
 263
 264 static void wil_move_all_rx_buff_to_free_list(struct wil6210_priv *wil,
 265                                               struct wil_ring *ring)
 266 {
 267         struct device *dev = wil_to_dev(wil);
 268         struct list_head *active = &wil->rx_buff_mgmt.active;
 269         dma_addr_t pa;
 270
 271         if (!wil->rx_buff_mgmt.buff_arr)
 272                 return;
 273
 274         while (!list_empty(active)) {
 275                 struct wil_rx_buff *rx_buff =
 276                         list_first_entry(active, struct wil_rx_buff, list);
 277                 struct sk_buff *skb = rx_buff->skb;
 278
 279                 if (unlikely(!skb)) {
 280                         wil_err(wil, "No Rx skb at buff_id %d\n", rx_buff->id);
 281                 } else {
 282                         rx_buff->skb = NULL;
 283                         memcpy(&pa, skb->cb, sizeof(pa));
 284                         dma_unmap_single(dev, pa, wil->rx_buf_len,
 285                                          DMA_FROM_DEVICE);
 286                         kfree_skb(skb);
 287                 }
 288
 289                 /* Move the buffer from the active to the free list */
 290                 list_move(&rx_buff->list, &wil->rx_buff_mgmt.free);
 291         }
 292 }
 293
 294 static void wil_free_rx_buff_arr(struct wil6210_priv *wil)
 295 {
 296         struct wil_ring *ring = &wil->ring_rx;
 297
 298         if (!wil->rx_buff_mgmt.buff_arr)
 299                 return;
 300
 301         /* Move all the buffers to the free list in case active list is
 302          * not empty in order to release all SKBs before deleting the array
 303          */
 304         wil_move_all_rx_buff_to_free_list(wil, ring);
 305
 306         kfree(wil->rx_buff_mgmt.buff_arr);
 307         wil->rx_buff_mgmt.buff_arr = NULL;
 308 }
 309
 310 static int wil_init_rx_buff_arr(struct wil6210_priv *wil,
 311                                 size_t size)
 312 {
 313         struct wil_rx_buff *buff_arr;
 314         struct list_head *active = &wil->rx_buff_mgmt.active;
 315         struct list_head *free = &wil->rx_buff_mgmt.free;
 316         int i;
 317
 318         wil->rx_buff_mgmt.buff_arr = kcalloc(size, sizeof(struct wil_rx_buff),
 319                                              GFP_KERNEL);
 320         if (!wil->rx_buff_mgmt.buff_arr)
 321                 return -ENOMEM;
 322
 323         /* Set list heads */
 324         INIT_LIST_HEAD(active);
 325         INIT_LIST_HEAD(free);
 326
 327         /* Linkify the list */
 328         buff_arr = wil->rx_buff_mgmt.buff_arr;
 329         for (i = 0; i < size; i++) {
 330                 list_add(&buff_arr[i].list, free);
 331                 buff_arr[i].id = i;
 332         }
 333
 334         wil->rx_buff_mgmt.size = size;
 335
 336         return 0;
 337 }
 338
 339 static int wil_init_rx_sring(struct wil6210_priv *wil,
 340                              u16 status_ring_size,
 341                              size_t elem_size,
 342                              u16 ring_id)
 343 {
 344         struct wil_status_ring *sring = &wil->srings[ring_id];
 345         int rc;
 346
 347         wil_dbg_misc(wil, "init RX sring: size=%u, ring_id=%u\n", sring->size,
 348                      ring_id);
 349
 350         memset(&sring->rx_data, 0, sizeof(sring->rx_data));
 351
 352         sring->is_rx = true;
 353         sring->size = status_ring_size;
 354         sring->elem_size = elem_size;
 355         rc = wil_sring_alloc(wil, sring);
 356         if (rc)
 357                 return rc;
 358
 359         rc = wil_wmi_rx_sring_add(wil, ring_id);
 360         if (rc)
 361                 goto out_free;
 362
 363         sring->desc_rdy_pol = 1;
 364
 365         return 0;
 366 out_free:
 367         wil_sring_free(wil, sring);
 368         return rc;
 369 }
 370
 371 static int wil_ring_alloc_desc_ring(struct wil6210_priv *wil,
 372                                     struct wil_ring *ring)
 373 {
 374         struct device *dev = wil_to_dev(wil);
 375         size_t sz = ring->size * sizeof(ring->va[0]);
 376
 377         wil_dbg_misc(wil, "alloc_desc_ring:\n");
 378
 379         BUILD_BUG_ON(sizeof(ring->va[0]) != 32);
 380
 381         ring->swhead = 0;
 382         ring->swtail = 0;
 383         ring->ctx = kcalloc(ring->size, sizeof(ring->ctx[0]), GFP_KERNEL);
 384         if (!ring->ctx)
 385                 goto err;
 386
 387         ring->va = dma_zalloc_coherent(dev, sz, &ring->pa, GFP_KERNEL);
 388         if (!ring->va)
 389                 goto err_free_ctx;
 390
 391         if (ring->is_rx) {
 392                 sz = sizeof(*ring->edma_rx_swtail.va);
 393                 ring->edma_rx_swtail.va =
 394                         dma_zalloc_coherent(dev, sz, &ring->edma_rx_swtail.pa,
 395                                             GFP_KERNEL);
 396                 if (!ring->edma_rx_swtail.va)
 397                         goto err_free_va;
 398         }
 399
 400         wil_dbg_misc(wil, "%s ring[%d] 0x%p:%pad 0x%p\n",
 401                      ring->is_rx ? "RX" : "TX",
 402                      ring->size, ring->va, &ring->pa, ring->ctx);
 403
 404         return 0;
 405 err_free_va:
 406         dma_free_coherent(dev, ring->size * sizeof(ring->va[0]),
 407                           (void *)ring->va, ring->pa);
 408         ring->va = NULL;
 409 err_free_ctx:
 410         kfree(ring->ctx);
 411         ring->ctx = NULL;
 412 err:
 413         return -ENOMEM;
 414 }
 415
 416 static void wil_ring_free_edma(struct wil6210_priv *wil, struct wil_ring *ring)
 417 {
 418         struct device *dev = wil_to_dev(wil);
 419         size_t sz;
 420         int ring_index = 0;
 421
 422         if (!ring->va)
 423                 return;
 424
 425         sz = ring->size * sizeof(ring->va[0]);
 426
 427         lockdep_assert_held(&wil->mutex);
 428         if (ring->is_rx) {
 429                 wil_dbg_misc(wil, "free Rx ring [%d] 0x%p:%pad 0x%p\n",
 430                              ring->size, ring->va,
 431                              &ring->pa, ring->ctx);
 432
 433                 wil_move_all_rx_buff_to_free_list(wil, ring);
 434                 goto out;
 435         }
 436
 437         /* TX ring */
 438         ring_index = ring - wil->ring_tx;
 439
 440         wil_dbg_misc(wil, "free Tx ring %d [%d] 0x%p:%pad 0x%p\n",
 441                      ring_index, ring->size, ring->va,
 442                      &ring->pa, ring->ctx);
 443
 444         while (!wil_ring_is_empty(ring)) {
 445                 struct wil_ctx *ctx;
 446
 447                 struct wil_tx_enhanced_desc dd, *d = &dd;
 448                 struct wil_tx_enhanced_desc *_d =
 449                         (struct wil_tx_enhanced_desc *)
 450                         &ring->va[ring->swtail].tx.enhanced;
 451
 452                 ctx = &ring->ctx[ring->swtail];
 453                 if (!ctx) {
 454                         wil_dbg_txrx(wil,
 455                                      "ctx(%d) was already completed\n",
 456                                      ring->swtail);
 457                         ring->swtail = wil_ring_next_tail(ring);
 458                         continue;
 459                 }
 460                 *d = *_d;
 461                 wil_tx_desc_unmap_edma(dev, (union wil_tx_desc *)d, ctx);
 462                 if (ctx->skb)
 463                         dev_kfree_skb_any(ctx->skb);
 464                 ring->swtail = wil_ring_next_tail(ring);
 465         }
 466
 467 out:
 468         dma_free_coherent(dev, sz, (void *)ring->va, ring->pa);
 469         kfree(ring->ctx);
 470         ring->pa = 0;
 471         ring->va = NULL;
 472         ring->ctx = NULL;
 473 }
 474
 475 static int wil_init_rx_desc_ring(struct wil6210_priv *wil, u16 desc_ring_size,
 476                                  int status_ring_id)
 477 {
 478         struct wil_ring *ring = &wil->ring_rx;
 479         int rc;
 480
 481         wil_dbg_misc(wil, "init RX desc ring\n");
 482
 483         ring->size = desc_ring_size;
 484         ring->is_rx = true;
 485         rc = wil_ring_alloc_desc_ring(wil, ring);
 486         if (rc)
 487                 return rc;
 488
 489         rc = wil_wmi_rx_desc_ring_add(wil, status_ring_id);
 490         if (rc)
 491                 goto out_free;
 492
 493         return 0;
 494 out_free:
 495         wil_ring_free_edma(wil, ring);
 496         return rc;
 497 }
 498
 499 static void wil_get_reorder_params_edma(struct wil6210_priv *wil,
 500                                         struct sk_buff *skb, int *tid,
 501                                         int *cid, int *mid, u16 *seq,
 502                                         int *mcast, int *retry)
 503 {
 504         struct wil_rx_status_extended *s = wil_skb_rxstatus(skb);
 505
 506         *tid = wil_rx_status_get_tid(s);
 507         *cid = wil_rx_status_get_cid(s);
 508         *mid = wil_rx_status_get_mid(s);
 509         *seq = le16_to_cpu(wil_rx_status_get_seq(wil, s));
 510         *mcast = wil_rx_status_get_mcast(s);
 511         *retry = wil_rx_status_get_retry(s);
 512 }
 513
 514 static void wil_get_netif_rx_params_edma(struct sk_buff *skb, int *cid,
 515                                          int *security)
 516 {
 517         struct wil_rx_status_extended *s = wil_skb_rxstatus(skb);
 518
 519         *cid = wil_rx_status_get_cid(s);
 520         *security = wil_rx_status_get_security(s);
 521 }
 522
 523 static int wil_rx_crypto_check_edma(struct wil6210_priv *wil,
 524                                     struct sk_buff *skb)
 525 {
 526         struct wil_rx_status_extended *st;
 527         int cid, tid, key_id, mc;
 528         struct wil_sta_info *s;
 529         struct wil_tid_crypto_rx *c;
 530         struct wil_tid_crypto_rx_single *cc;
 531         const u8 *pn;
 532
 533         /* In HW reorder, HW is responsible for crypto check */
 534         if (wil->use_rx_hw_reordering)
 535                 return 0;
 536
 537         st = wil_skb_rxstatus(skb);
 538
 539         cid = wil_rx_status_get_cid(st);
 540         tid = wil_rx_status_get_tid(st);
 541         key_id = wil_rx_status_get_key_id(st);
 542         mc = wil_rx_status_get_mcast(st);
 543         s = &wil->sta[cid];
 544         c = mc ? &s->group_crypto_rx : &s->tid_crypto_rx[tid];
 545         cc = &c->key_id[key_id];
 546         pn = (u8 *)&st->ext.pn_15_0;
 547
 548         if (!cc->key_set) {
 549                 wil_err_ratelimited(wil,
 550                                     "Key missing. CID %d TID %d MCast %d KEY_ID %d\n",
 551                                     cid, tid, mc, key_id);
 552                 return -EINVAL;
 553         }
 554
 555         if (reverse_memcmp(pn, cc->pn, IEEE80211_GCMP_PN_LEN) <= 0) {
 556                 wil_err_ratelimited(wil,
 557                                     "Replay attack. CID %d TID %d MCast %d KEY_ID %d PN %6phN last %6phN\n",
 558                                     cid, tid, mc, key_id, pn, cc->pn);
 559                 return -EINVAL;
 560         }
 561         memcpy(cc->pn, pn, IEEE80211_GCMP_PN_LEN);
 562
 563         return 0;
 564 }
 565
 566 static bool wil_is_rx_idle_edma(struct wil6210_priv *wil)
 567 {
 568         struct wil_status_ring *sring;
 569         struct wil_rx_status_extended msg1;
 570         void *msg = &msg1;
 571         u8 dr_bit;
 572         int i;
 573
 574         for (i = 0; i < wil->num_rx_status_rings; i++) {
 575                 sring = &wil->srings[i];
 576                 if (!sring->va)
 577                         continue;
 578
 579                 wil_get_next_rx_status_msg(sring, msg);
 580                 dr_bit = wil_rx_status_get_desc_rdy_bit(msg);
 581
 582                 /* Check if there are unhandled RX status messages */
 583                 if (dr_bit == sring->desc_rdy_pol)
 584                         return false;
 585         }
 586
 587         return true;
 588 }
 589
 590 static void wil_rx_buf_len_init_edma(struct wil6210_priv *wil)
 591 {
 592         wil->rx_buf_len = rx_large_buf ?
 593                 WIL_MAX_ETH_MTU : WIL_EDMA_RX_BUF_LEN_DEFAULT;
 594 }
 595
 596 static int wil_rx_init_edma(struct wil6210_priv *wil, uint desc_ring_order)
 597 {
 598         u16 status_ring_size, desc_ring_size = 1 << desc_ring_order;
 599         struct wil_ring *ring = &wil->ring_rx;
 600         int rc;
 601         size_t elem_size = wil->use_compressed_rx_status ?
 602                 sizeof(struct wil_rx_status_compressed) :
 603                 sizeof(struct wil_rx_status_extended);
 604         int i;
 605         u16 max_rx_pl_per_desc;
 606
 607         /* In SW reorder one must use extended status messages */
 608         if (wil->use_compressed_rx_status && !wil->use_rx_hw_reordering) {
 609                 wil_err(wil,
 610                         "compressed RX status cannot be used with SW reorder\n");
 611                 return -EINVAL;
 612         }
 613         if (wil->rx_status_ring_order <= desc_ring_order)
 614                 /* make sure sring is larger than desc ring */
 615                 wil->rx_status_ring_order = desc_ring_order + 1;
 616         if (wil->rx_buff_id_count <= desc_ring_size)
 617                 /* make sure we will not run out of buff_ids */
 618                 wil->rx_buff_id_count = desc_ring_size + 512;
 619         if (wil->rx_status_ring_order < WIL_SRING_SIZE_ORDER_MIN ||
 620             wil->rx_status_ring_order > WIL_SRING_SIZE_ORDER_MAX)
 621                 wil->rx_status_ring_order = WIL_RX_SRING_SIZE_ORDER_DEFAULT;
 622
 623         status_ring_size = 1 << wil->rx_status_ring_order;
 624
 625         wil_dbg_misc(wil,
 626                      "rx_init, desc_ring_size=%u, status_ring_size=%u, elem_size=%zu\n",
 627                      desc_ring_size, status_ring_size, elem_size);
 628
 629         wil_rx_buf_len_init_edma(wil);
 630
 631         max_rx_pl_per_desc = ALIGN(wil->rx_buf_len, 4);
 632
 633         /* Use debugfs dbg_num_rx_srings if set, reserve one sring for TX */
 634         if (wil->num_rx_status_rings > WIL6210_MAX_STATUS_RINGS - 1)
 635                 wil->num_rx_status_rings = WIL6210_MAX_STATUS_RINGS - 1;
 636
 637         wil_dbg_misc(wil, "rx_init: allocate %d status rings\n",
 638                      wil->num_rx_status_rings);
 639
 640         rc = wil_wmi_cfg_def_rx_offload(wil, max_rx_pl_per_desc);
 641         if (rc)
 642                 return rc;
 643
 644         /* Allocate status ring */
 645         for (i = 0; i < wil->num_rx_status_rings; i++) {
 646                 int sring_id = wil_find_free_sring(wil);
 647
 648                 if (sring_id < 0) {
 649                         rc = -EFAULT;
 650                         goto err_free_status;
 651                 }
 652                 rc = wil_init_rx_sring(wil, status_ring_size, elem_size,
 653                                        sring_id);
 654                 if (rc)
 655                         goto err_free_status;
 656         }
 657
 658         /* Allocate descriptor ring */
 659         rc = wil_init_rx_desc_ring(wil, desc_ring_size,
 660                                    WIL_DEFAULT_RX_STATUS_RING_ID);
 661         if (rc)
 662                 goto err_free_status;
 663
 664         if (wil->rx_buff_id_count >= status_ring_size) {
 665                 wil_info(wil,
 666                          "rx_buff_id_count %d exceeds sring_size %d. set it to %d\n",
 667                          wil->rx_buff_id_count, status_ring_size,
 668                          status_ring_size - 1);
 669                 wil->rx_buff_id_count = status_ring_size - 1;
 670         }
 671
 672         /* Allocate Rx buffer array */
 673         rc = wil_init_rx_buff_arr(wil, wil->rx_buff_id_count);
 674         if (rc)
 675                 goto err_free_desc;
 676
 677         /* Fill descriptor ring with credits */
 678         rc = wil_rx_refill_edma(wil);
 679         if (rc)
 680                 goto err_free_rx_buff_arr;
 681
 682         return 0;
 683 err_free_rx_buff_arr:
 684         wil_free_rx_buff_arr(wil);
 685 err_free_desc:
 686         wil_ring_free_edma(wil, ring);
 687 err_free_status:
 688         for (i = 0; i < wil->num_rx_status_rings; i++)
 689                 wil_sring_free(wil, &wil->srings[i]);
 690
 691         return rc;
 692 }
 693
 694 static int wil_ring_init_tx_edma(struct wil6210_vif *vif, int ring_id,
 695                                  int size, int cid, int tid)
 696 {
 697         struct wil6210_priv *wil = vif_to_wil(vif);
 698         int rc;
 699         struct wil_ring *ring = &wil->ring_tx[ring_id];
 700         struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_id];
 701
 702         lockdep_assert_held(&wil->mutex);
 703
 704         wil_dbg_misc(wil,
 705                      "init TX ring: ring_id=%u, cid=%u, tid=%u, sring_id=%u\n",
 706                      ring_id, cid, tid, wil->tx_sring_idx);
 707
 708         wil_tx_data_init(txdata);
 709         ring->size = size;
 710         rc = wil_ring_alloc_desc_ring(wil, ring);
 711         if (rc)
 712                 goto out;
 713
 714         wil->ring2cid_tid[ring_id][0] = cid;
 715         wil->ring2cid_tid[ring_id][1] = tid;
 716         if (!vif->privacy)
 717                 txdata->dot1x_open = true;
 718
 719         rc = wil_wmi_tx_desc_ring_add(vif, ring_id, cid, tid);
 720         if (rc) {
 721                 wil_err(wil, "WMI_TX_DESC_RING_ADD_CMD failed\n");
 722                 goto out_free;
 723         }
 724
 725         if (txdata->dot1x_open && agg_wsize >= 0)
 726                 wil_addba_tx_request(wil, ring_id, agg_wsize);
 727
 728         return 0;
 729  out_free:
 730         spin_lock_bh(&txdata->lock);
 731         txdata->dot1x_open = false;
 732         txdata->enabled = 0;
 733         spin_unlock_bh(&txdata->lock);
 734         wil_ring_free_edma(wil, ring);
 735         wil->ring2cid_tid[ring_id][0] = WIL6210_MAX_CID;
 736         wil->ring2cid_tid[ring_id][1] = 0;
 737
 738  out:
 739         return rc;
 740 }
 741
 742 /* This function is used only for RX SW reorder */
 743 static int wil_check_bar(struct wil6210_priv *wil, void *msg, int cid,
 744                          struct sk_buff *skb, struct wil_net_stats *stats)
 745 {
 746         u8 ftype;
 747         u8 fc1;
 748         int mid;
 749         int tid;
 750         u16 seq;
 751         struct wil6210_vif *vif;
 752
 753         ftype = wil_rx_status_get_frame_type(wil, msg);
 754         if (ftype == IEEE80211_FTYPE_DATA)
 755                 return 0;
 756
 757         fc1 = wil_rx_status_get_fc1(wil, msg);
 758         mid = wil_rx_status_get_mid(msg);
 759         tid = wil_rx_status_get_tid(msg);
 760         seq = le16_to_cpu(wil_rx_status_get_seq(wil, msg));
 761         vif = wil->vifs[mid];
 762
 763         if (unlikely(!vif)) {
 764                 wil_dbg_txrx(wil, "RX descriptor with invalid mid %d", mid);
 765                 return -EAGAIN;
 766         }
 767
 768         wil_dbg_txrx(wil,
 769                      "Non-data frame FC[7:0] 0x%02x MID %d CID %d TID %d Seq 0x%03x\n",
 770                      fc1, mid, cid, tid, seq);
 771         if (stats)
 772                 stats->rx_non_data_frame++;
 773         if (wil_is_back_req(fc1)) {
 774                 wil_dbg_txrx(wil,
 775                              "BAR: MID %d CID %d TID %d Seq 0x%03x\n",
 776                              mid, cid, tid, seq);
 777                 wil_rx_bar(wil, vif, cid, tid, seq);
 778         } else {
 779                 u32 sz = wil->use_compressed_rx_status ?
 780                         sizeof(struct wil_rx_status_compressed) :
 781                         sizeof(struct wil_rx_status_extended);
 782
 783                 /* print again all info. One can enable only this
 784                  * without overhead for printing every Rx frame
 785                  */
 786                 wil_dbg_txrx(wil,
 787                              "Unhandled non-data frame FC[7:0] 0x%02x MID %d CID %d TID %d Seq 0x%03x\n",
 788                              fc1, mid, cid, tid, seq);
 789                 wil_hex_dump_txrx("RxS ", DUMP_PREFIX_NONE, 32, 4,
 790                                   (const void *)msg, sz, false);
 791                 wil_hex_dump_txrx("Rx ", DUMP_PREFIX_OFFSET, 16, 1,
 792                                   skb->data, skb_headlen(skb), false);
 793         }
 794
 795         return -EAGAIN;
 796 }
 797
 798 static int wil_rx_error_check_edma(struct wil6210_priv *wil,
 799                                    struct sk_buff *skb,
 800                                    struct wil_net_stats *stats)
 801 {
 802         int error;
 803         int l2_rx_status;
 804         int l3_rx_status;
 805         int l4_rx_status;
 806         void *msg = wil_skb_rxstatus(skb);
 807
 808         error = wil_rx_status_get_error(msg);
 809         if (!error) {
 810                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 811                 return 0;
 812         }
 813
 814         l2_rx_status = wil_rx_status_get_l2_rx_status(msg);
 815         if (l2_rx_status != 0) {
 816                 wil_dbg_txrx(wil, "L2 RX error, l2_rx_status=0x%x\n",
 817                              l2_rx_status);
 818                 /* Due to HW issue, KEY error will trigger a MIC error */
 819                 if (l2_rx_status == WIL_RX_EDMA_ERROR_MIC) {
 820                         wil_err_ratelimited(wil,
 821                                             "L2 MIC/KEY error, dropping packet\n");
 822                         stats->rx_mic_error++;
 823                 }
 824                 if (l2_rx_status == WIL_RX_EDMA_ERROR_KEY) {
 825                         wil_err_ratelimited(wil,
 826                                             "L2 KEY error, dropping packet\n");
 827                         stats->rx_key_error++;
 828                 }
 829                 if (l2_rx_status == WIL_RX_EDMA_ERROR_REPLAY) {
 830                         wil_err_ratelimited(wil,
 831                                             "L2 REPLAY error, dropping packet\n");
 832                         stats->rx_replay++;
 833                 }
 834                 if (l2_rx_status == WIL_RX_EDMA_ERROR_AMSDU) {
 835                         wil_err_ratelimited(wil,
 836                                             "L2 AMSDU error, dropping packet\n");
 837                         stats->rx_amsdu_error++;
 838                 }
 839                 return -EFAULT;
 840         }
 841
 842         l3_rx_status = wil_rx_status_get_l3_rx_status(msg);
 843         l4_rx_status = wil_rx_status_get_l4_rx_status(msg);
 844         if (!l3_rx_status && !l4_rx_status)
 845                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 846         /* If HW reports bad checksum, let IP stack re-check it
 847          * For example, HW don't understand Microsoft IP stack that
 848          * mis-calculates TCP checksum - if it should be 0x0,
 849          * it writes 0xffff in violation of RFC 1624
 850          */
 851         else
 852                 stats->rx_csum_err++;
 853
 854         return 0;
 855 }
 856
 857 static struct sk_buff *wil_sring_reap_rx_edma(struct wil6210_priv *wil,
 858                                               struct wil_status_ring *sring)
 859 {
 860         struct device *dev = wil_to_dev(wil);
 861         struct wil_rx_status_extended msg1;
 862         void *msg = &msg1;
 863         u16 buff_id;
 864         struct sk_buff *skb;
 865         dma_addr_t pa;
 866         struct wil_ring_rx_data *rxdata = &sring->rx_data;
 867         unsigned int sz = ALIGN(wil->rx_buf_len, 4);
 868         struct wil_net_stats *stats = NULL;
 869         u16 dmalen;
 870         int cid;
 871         bool eop, headstolen;
 872         int delta;
 873         u8 dr_bit;
 874         u8 data_offset;
 875         struct wil_rx_status_extended *s;
 876         u16 sring_idx = sring - wil->srings;
 877
 878         BUILD_BUG_ON(sizeof(struct wil_rx_status_extended) > sizeof(skb->cb));
 879
 880 again:
 881         wil_get_next_rx_status_msg(sring, msg);
 882         dr_bit = wil_rx_status_get_desc_rdy_bit(msg);
 883
 884         /* Completed handling all the ready status messages */
 885         if (dr_bit != sring->desc_rdy_pol)
 886                 return NULL;
 887
 888         /* Extract the buffer ID from the status message */
 889         buff_id = le16_to_cpu(wil_rx_status_get_buff_id(msg));
 890         if (unlikely(!wil_val_in_range(buff_id, 0, wil->rx_buff_mgmt.size))) {
 891                 wil_err(wil, "Corrupt buff_id=%d, sring->swhead=%d\n",
 892                         buff_id, sring->swhead);
 893                 wil_sring_advance_swhead(sring);
 894                 goto again;
 895         }
 896
 897         wil_sring_advance_swhead(sring);
 898
 899         /* Extract the SKB from the rx_buff management array */
 900         skb = wil->rx_buff_mgmt.buff_arr[buff_id].skb;
 901         wil->rx_buff_mgmt.buff_arr[buff_id].skb = NULL;
 902         if (!skb) {
 903                 wil_err(wil, "No Rx skb at buff_id %d\n", buff_id);
 904                 /* Move the buffer from the active list to the free list */
 905                 list_move(&wil->rx_buff_mgmt.buff_arr[buff_id].list,
 906                           &wil->rx_buff_mgmt.free);
 907                 goto again;
 908         }
 909
 910         memcpy(&pa, skb->cb, sizeof(pa));
 911         dma_unmap_single(dev, pa, sz, DMA_FROM_DEVICE);
 912         dmalen = le16_to_cpu(wil_rx_status_get_length(msg));
 913
 914         trace_wil6210_rx_status(wil, wil->use_compressed_rx_status, buff_id,
 915                                 msg);
 916         wil_dbg_txrx(wil, "Rx, buff_id=%u, sring_idx=%u, dmalen=%u bytes\n",
 917                      buff_id, sring_idx, dmalen);
 918         wil_hex_dump_txrx("RxS ", DUMP_PREFIX_NONE, 32, 4,
 919                           (const void *)msg, wil->use_compressed_rx_status ?
 920                           sizeof(struct wil_rx_status_compressed) :
 921                           sizeof(struct wil_rx_status_extended), false);
 922
 923         /* Move the buffer from the active list to the free list */
 924         list_move(&wil->rx_buff_mgmt.buff_arr[buff_id].list,
 925                   &wil->rx_buff_mgmt.free);
 926
 927         eop = wil_rx_status_get_eop(msg);
 928
 929         cid = wil_rx_status_get_cid(msg);
 930         if (unlikely(!wil_val_in_range(cid, 0, WIL6210_MAX_CID))) {
 931                 wil_err(wil, "Corrupt cid=%d, sring->swhead=%d\n",
 932                         cid, sring->swhead);
 933                 rxdata->skipping = true;
 934                 goto skipping;
 935         }
 936         stats = &wil->sta[cid].stats;
 937
 938         if (unlikely(skb->len < ETH_HLEN)) {
 939                 wil_dbg_txrx(wil, "Short frame, len = %d\n", skb->len);
 940                 stats->rx_short_frame++;
 941                 rxdata->skipping = true;
 942                 goto skipping;
 943         }
 944
 945         if (unlikely(dmalen > sz)) {
 946                 wil_err(wil, "Rx size too large: %d bytes!\n", dmalen);
 947                 stats->rx_large_frame++;
 948                 rxdata->skipping = true;
 949         }
 950
 951 skipping:
 952         /* skipping indicates if a certain SKB should be dropped.
 953          * It is set in case there is an error on the current SKB or in case
 954          * of RX chaining: as long as we manage to merge the SKBs it will
 955          * be false. once we have a bad SKB or we don't manage to merge SKBs
 956          * it will be set to the !EOP value of the current SKB.
 957          * This guarantees that all the following SKBs until EOP will also
 958          * get dropped.
 959          */
 960         if (unlikely(rxdata->skipping)) {
 961                 kfree_skb(skb);
 962                 if (rxdata->skb) {
 963                         kfree_skb(rxdata->skb);
 964                         rxdata->skb = NULL;
 965                 }
 966                 rxdata->skipping = !eop;
 967                 goto again;
 968         }
 969
 970         skb_trim(skb, dmalen);
 971
 972         prefetch(skb->data);
 973
 974         if (!rxdata->skb) {
 975                 rxdata->skb = skb;
 976         } else {
 977                 if (likely(skb_try_coalesce(rxdata->skb, skb, &headstolen,
 978                                             &delta))) {
 979                         kfree_skb_partial(skb, headstolen);
 980                 } else {
 981                         wil_err(wil, "failed to merge skbs!\n");
 982                         kfree_skb(skb);
 983                         kfree_skb(rxdata->skb);
 984                         rxdata->skb = NULL;
 985                         rxdata->skipping = !eop;
 986                         goto again;
 987                 }
 988         }
 989
 990         if (!eop)
 991                 goto again;
 992
 993         /* reaching here rxdata->skb always contains a full packet */
 994         skb = rxdata->skb;
 995         rxdata->skb = NULL;
 996         rxdata->skipping = false;
 997
 998         if (stats) {
 999                 stats->last_mcs_rx = wil_rx_status_get_mcs(msg);
1000                 if (stats->last_mcs_rx < ARRAY_SIZE(stats->rx_per_mcs))
1001                         stats->rx_per_mcs[stats->last_mcs_rx]++;
1002         }
1003
1004         if (!wil->use_rx_hw_reordering && !wil->use_compressed_rx_status &&
1005             wil_check_bar(wil, msg, cid, skb, stats) == -EAGAIN) {
1006                 kfree_skb(skb);
1007                 goto again;
1008         }
1009
1010         /* Compensate for the HW data alignment according to the status
1011          * message
1012          */
1013         data_offset = wil_rx_status_get_data_offset(msg);
1014         if (data_offset == 0xFF ||
1015             data_offset > WIL_EDMA_MAX_DATA_OFFSET) {
1016                 wil_err(wil, "Unexpected data offset %d\n", data_offset);
1017                 kfree_skb(skb);
1018                 goto again;
1019         }
1020
1021         skb_pull(skb, data_offset);
1022
1023         wil_hex_dump_txrx("Rx ", DUMP_PREFIX_OFFSET, 16, 1,
1024                           skb->data, skb_headlen(skb), false);
1025
1026         /* Has to be done after dma_unmap_single as skb->cb is also
1027          * used for holding the pa
1028          */
1029         s = wil_skb_rxstatus(skb);
1030         memcpy(s, msg, sring->elem_size);
1031
1032         return skb;
1033 }
1034
1035 void wil_rx_handle_edma(struct wil6210_priv *wil, int *quota)
1036 {
1037         struct net_device *ndev;
1038         struct wil_ring *ring = &wil->ring_rx;
1039         struct wil_status_ring *sring;
1040         struct sk_buff *skb;
1041         int i;
1042
1043         if (unlikely(!ring->va)) {
1044                 wil_err(wil, "Rx IRQ while Rx not yet initialized\n");
1045                 return;
1046         }
1047         wil_dbg_txrx(wil, "rx_handle\n");
1048
1049         for (i = 0; i < wil->num_rx_status_rings; i++) {
1050                 sring = &wil->srings[i];
1051                 if (unlikely(!sring->va)) {
1052                         wil_err(wil,
1053                                 "Rx IRQ while Rx status ring %d not yet initialized\n",
1054                                 i);
1055                         continue;
1056                 }
1057
1058                 while ((*quota > 0) &&
1059                        (NULL != (skb =
1060                         wil_sring_reap_rx_edma(wil, sring)))) {
1061                         (*quota)--;
1062                         if (wil->use_rx_hw_reordering) {
1063                                 void *msg = wil_skb_rxstatus(skb);
1064                                 int mid = wil_rx_status_get_mid(msg);
1065                                 struct wil6210_vif *vif = wil->vifs[mid];
1066
1067                                 if (unlikely(!vif)) {
1068                                         wil_dbg_txrx(wil,
1069                                                      "RX desc invalid mid %d",
1070                                                      mid);
1071                                         kfree_skb(skb);
1072                                         continue;
1073                                 }
1074                                 ndev = vif_to_ndev(vif);
1075                                 wil_netif_rx_any(skb, ndev);
1076                         } else {
1077                                 wil_rx_reorder(wil, skb);
1078                         }
1079                 }
1080
1081                 wil_w(wil, sring->hwtail, (sring->swhead - 1) % sring->size);
1082         }
1083
1084         wil_rx_refill_edma(wil);
1085 }
1086
1087 static int wil_tx_desc_map_edma(union wil_tx_desc *desc,
1088                                 dma_addr_t pa,
1089                                 u32 len,
1090                                 int ring_index)
1091 {
1092         struct wil_tx_enhanced_desc *d =
1093                 (struct wil_tx_enhanced_desc *)&desc->enhanced;
1094
1095         memset(d, 0, sizeof(struct wil_tx_enhanced_desc));
1096
1097         wil_desc_set_addr_edma(&d->dma.addr, &d->dma.addr_high_high, pa);
1098
1099         /* 0..6: mac_length; 7:ip_version 0-IP6 1-IP4*/
1100         d->dma.length = cpu_to_le16((u16)len);
1101         d->mac.d[0] = (ring_index << WIL_EDMA_DESC_TX_MAC_CFG_0_QID_POS);
1102         /* translation type:  0 - bypass; 1 - 802.3; 2 - native wifi;
1103          * 3 - eth mode
1104          */
1105         d->mac.d[2] = BIT(MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_POS) |
1106                       (0x3 << MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_POS);
1107
1108         return 0;
1109 }
1110
1111 static inline void
1112 wil_get_next_tx_status_msg(struct wil_status_ring *sring,
1113                            struct wil_ring_tx_status *msg)
1114 {
1115         struct wil_ring_tx_status *_msg = (struct wil_ring_tx_status *)
1116                 (sring->va + (sring->elem_size * sring->swhead));
1117
1118         *msg = *_msg;
1119 }
1120
1121 /**
1122  * Clean up transmitted skb's from the Tx descriptor RING.
1123  * Return number of descriptors cleared.
1124  */
1125 int wil_tx_sring_handler(struct wil6210_priv *wil,
1126                          struct wil_status_ring *sring)
1127 {
1128         struct net_device *ndev;
1129         struct device *dev = wil_to_dev(wil);
1130         struct wil_ring *ring = NULL;
1131         struct wil_ring_tx_data *txdata;
1132         /* Total number of completed descriptors in all descriptor rings */
1133         int desc_cnt = 0;
1134         int cid;
1135         struct wil_net_stats *stats = NULL;
1136         struct wil_tx_enhanced_desc *_d;
1137         unsigned int ring_id;
1138         unsigned int num_descs;
1139         int i;
1140         u8 dr_bit; /* Descriptor Ready bit */
1141         struct wil_ring_tx_status msg;
1142         struct wil6210_vif *vif;
1143         int used_before_complete;
1144         int used_new;
1145
1146         wil_get_next_tx_status_msg(sring, &msg);
1147         dr_bit = msg.desc_ready >> TX_STATUS_DESC_READY_POS;
1148
1149         /* Process completion messages while DR bit has the expected polarity */
1150         while (dr_bit == sring->desc_rdy_pol) {
1151                 num_descs = msg.num_descriptors;
1152                 if (!num_descs) {
1153                         wil_err(wil, "invalid num_descs 0\n");
1154                         goto again;
1155                 }
1156
1157                 /* Find the corresponding descriptor ring */
1158                 ring_id = msg.ring_id;
1159
1160                 if (unlikely(ring_id >= WIL6210_MAX_TX_RINGS)) {
1161                         wil_err(wil, "invalid ring id %d\n", ring_id);
1162                         goto again;
1163                 }
1164                 ring = &wil->ring_tx[ring_id];
1165                 if (unlikely(!ring->va)) {
1166                         wil_err(wil, "Tx irq[%d]: ring not initialized\n",
1167                                 ring_id);
1168                         goto again;
1169                 }
1170                 txdata = &wil->ring_tx_data[ring_id];
1171                 if (unlikely(!txdata->enabled)) {
1172                         wil_info(wil, "Tx irq[%d]: ring disabled\n", ring_id);
1173                         goto again;
1174                 }
1175                 vif = wil->vifs[txdata->mid];
1176                 if (unlikely(!vif)) {
1177                         wil_dbg_txrx(wil, "invalid MID %d for ring %d\n",
1178                                      txdata->mid, ring_id);
1179                         goto again;
1180                 }
1181
1182                 ndev = vif_to_ndev(vif);
1183
1184                 cid = wil->ring2cid_tid[ring_id][0];
1185                 if (cid < WIL6210_MAX_CID)
1186                         stats = &wil->sta[cid].stats;
1187
1188                 wil_dbg_txrx(wil,
1189                              "tx_status: completed desc_ring (%d), num_descs (%d)\n",
1190                              ring_id, num_descs);
1191
1192                 used_before_complete = wil_ring_used_tx(ring);
1193
1194                 for (i = 0 ; i < num_descs; ++i) {
1195                         struct wil_ctx *ctx = &ring->ctx[ring->swtail];
1196                         struct wil_tx_enhanced_desc dd, *d = &dd;
1197                         u16 dmalen;
1198                         struct sk_buff *skb = ctx->skb;
1199
1200                         _d = (struct wil_tx_enhanced_desc *)
1201                                 &ring->va[ring->swtail].tx.enhanced;
1202                         *d = *_d;
1203
1204                         dmalen = le16_to_cpu(d->dma.length);
1205                         trace_wil6210_tx_status(&msg, ring->swtail, dmalen);
1206                         wil_dbg_txrx(wil,
1207                                      "TxC[%2d][%3d] : %d bytes, status 0x%02x\n",
1208                                      ring_id, ring->swtail, dmalen,
1209                                      msg.status);
1210                         wil_hex_dump_txrx("TxS ", DUMP_PREFIX_NONE, 32, 4,
1211                                           (const void *)&msg, sizeof(msg),
1212                                           false);
1213
1214                         wil_tx_desc_unmap_edma(dev,
1215                                                (union wil_tx_desc *)d,
1216                                                ctx);
1217
1218                         if (skb) {
1219                                 if (likely(msg.status == 0)) {
1220                                         ndev->stats.tx_packets++;
1221                                         ndev->stats.tx_bytes += skb->len;
1222                                         if (stats) {
1223                                                 stats->tx_packets++;
1224                                                 stats->tx_bytes += skb->len;
1225
1226                                                 wil_tx_latency_calc(wil, skb,
1227                                                         &wil->sta[cid]);
1228                                         }
1229                                 } else {
1230                                         ndev->stats.tx_errors++;
1231                                         if (stats)
1232                                                 stats->tx_errors++;
1233                                 }
1234                                 wil_consume_skb(skb, msg.status == 0);
1235                         }
1236                         memset(ctx, 0, sizeof(*ctx));
1237                         /* Make sure the ctx is zeroed before updating the tail
1238                          * to prevent a case where wil_tx_ring will see
1239                          * this descriptor as used and handle it before ctx zero
1240                          * is completed.
1241                          */
1242                         wmb();
1243
1244                         ring->swtail = wil_ring_next_tail(ring);
1245
1246                         desc_cnt++;
1247                 }
1248
1249                 /* performance monitoring */
1250                 used_new = wil_ring_used_tx(ring);
1251                 if (wil_val_in_range(wil->ring_idle_trsh,
1252                                      used_new, used_before_complete)) {
1253                         wil_dbg_txrx(wil, "Ring[%2d] idle %d -> %d\n",
1254                                      ring_id, used_before_complete, used_new);
1255                         txdata->last_idle = get_cycles();
1256                 }
1257
1258 again:
1259                 wil_sring_advance_swhead(sring);
1260
1261                 wil_get_next_tx_status_msg(sring, &msg);
1262                 dr_bit = msg.desc_ready >> TX_STATUS_DESC_READY_POS;
1263         }
1264
1265         /* shall we wake net queues? */
1266         if (desc_cnt)
1267                 wil_update_net_queues(wil, vif, NULL, false);
1268
1269         /* Update the HW tail ptr (RD ptr) */
1270         wil_w(wil, sring->hwtail, (sring->swhead - 1) % sring->size);
1271
1272         return desc_cnt;
1273 }
1274
1275 /**
1276  * Sets the descriptor @d up for csum and/or TSO offloading. The corresponding
1277  * @skb is used to obtain the protocol and headers length.
1278  * @tso_desc_type is a descriptor type for TSO: 0 - a header, 1 - first data,
1279  * 2 - middle, 3 - last descriptor.
1280  */
1281 static void wil_tx_desc_offload_setup_tso_edma(struct wil_tx_enhanced_desc *d,
1282                                                int tso_desc_type, bool is_ipv4,
1283                                                int tcp_hdr_len,
1284                                                int skb_net_hdr_len,
1285                                                int mss)
1286 {
1287         /* Number of descriptors */
1288         d->mac.d[2] |= 1;
1289         /* Maximum Segment Size */
1290         d->mac.tso_mss |= cpu_to_le16(mss >> 2);
1291         /* L4 header len: TCP header length */
1292         d->dma.l4_hdr_len |= tcp_hdr_len & DMA_CFG_DESC_TX_0_L4_LENGTH_MSK;
1293         /* EOP, TSO desc type, Segmentation enable,
1294          * Insert IPv4 and TCP / UDP Checksum
1295          */
1296         d->dma.cmd |= BIT(WIL_EDMA_DESC_TX_CFG_EOP_POS) |
1297                       tso_desc_type << WIL_EDMA_DESC_TX_CFG_TSO_DESC_TYPE_POS |
1298                       BIT(WIL_EDMA_DESC_TX_CFG_SEG_EN_POS) |
1299                       BIT(WIL_EDMA_DESC_TX_CFG_INSERT_IP_CHKSUM_POS) |
1300                       BIT(WIL_EDMA_DESC_TX_CFG_INSERT_TCP_CHKSUM_POS);
1301         /* Calculate pseudo-header */
1302         d->dma.w1 |= BIT(WIL_EDMA_DESC_TX_CFG_PSEUDO_HEADER_CALC_EN_POS) |
1303                      BIT(WIL_EDMA_DESC_TX_CFG_L4_TYPE_POS);
1304         /* IP Header Length */
1305         d->dma.ip_length |= skb_net_hdr_len;
1306         /* MAC header length and IP address family*/
1307         d->dma.b11 |= ETH_HLEN |
1308                       is_ipv4 << DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_POS;
1309 }
1310
1311 static int wil_tx_tso_gen_desc(struct wil6210_priv *wil, void *buff_addr,
1312                                int len, uint i, int tso_desc_type,
1313                                skb_frag_t *frag, struct wil_ring *ring,
1314                                struct sk_buff *skb, bool is_ipv4,
1315                                int tcp_hdr_len, int skb_net_hdr_len,
1316                                int mss, int *descs_used)
1317 {
1318         struct device *dev = wil_to_dev(wil);
1319         struct wil_tx_enhanced_desc *_desc = (struct wil_tx_enhanced_desc *)
1320                 &ring->va[i].tx.enhanced;
1321         struct wil_tx_enhanced_desc desc_mem, *d = &desc_mem;
1322         int ring_index = ring - wil->ring_tx;
1323         dma_addr_t pa;
1324
1325         if (len == 0)
1326                 return 0;
1327
1328         if (!frag) {
1329                 pa = dma_map_single(dev, buff_addr, len, DMA_TO_DEVICE);
1330                 ring->ctx[i].mapped_as = wil_mapped_as_single;
1331         } else {
1332                 pa = skb_frag_dma_map(dev, frag, 0, len, DMA_TO_DEVICE);
1333                 ring->ctx[i].mapped_as = wil_mapped_as_page;
1334         }
1335         if (unlikely(dma_mapping_error(dev, pa))) {
1336                 wil_err(wil, "TSO: Skb DMA map error\n");
1337                 return -EINVAL;
1338         }
1339
1340         wil->txrx_ops.tx_desc_map((union wil_tx_desc *)d, pa,
1341                                    len, ring_index);
1342         wil_tx_desc_offload_setup_tso_edma(d, tso_desc_type, is_ipv4,
1343                                            tcp_hdr_len,
1344                                            skb_net_hdr_len, mss);
1345
1346         /* hold reference to skb
1347          * to prevent skb release before accounting
1348          * in case of immediate "tx done"
1349          */
1350         if (tso_desc_type == wil_tso_type_lst)
1351                 ring->ctx[i].skb = skb_get(skb);
1352
1353         wil_hex_dump_txrx("TxD ", DUMP_PREFIX_NONE, 32, 4,
1354                           (const void *)d, sizeof(*d), false);
1355
1356         *_desc = *d;
1357         (*descs_used)++;
1358
1359         return 0;
1360 }
1361
1362 static int __wil_tx_ring_tso_edma(struct wil6210_priv *wil,
1363                                   struct wil6210_vif *vif,
1364                                   struct wil_ring *ring,
1365                                   struct sk_buff *skb)
1366 {
1367         int ring_index = ring - wil->ring_tx;
1368         struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_index];
1369         int nr_frags = skb_shinfo(skb)->nr_frags;
1370         int min_desc_required = nr_frags + 2; /* Headers, Head, Fragments */
1371         int used, avail = wil_ring_avail_tx(ring);
1372         int f, hdrlen, headlen;
1373         int gso_type;
1374         bool is_ipv4;
1375         u32 swhead = ring->swhead;
1376         int descs_used = 0; /* total number of used descriptors */
1377         int rc = -EINVAL;
1378         int tcp_hdr_len;
1379         int skb_net_hdr_len;
1380         int mss = skb_shinfo(skb)->gso_size;
1381
1382         wil_dbg_txrx(wil, "tx_ring_tso: %d bytes to ring %d\n", skb->len,
1383                      ring_index);
1384
1385         if (unlikely(!txdata->enabled))
1386                 return -EINVAL;
1387
1388         if (unlikely(avail < min_desc_required)) {
1389                 wil_err_ratelimited(wil,
1390                                     "TSO: Tx ring[%2d] full. No space for %d fragments\n",
1391                                     ring_index, min_desc_required);
1392                 return -ENOMEM;
1393         }
1394
1395         gso_type = skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV6 | SKB_GSO_TCPV4);
1396         switch (gso_type) {
1397         case SKB_GSO_TCPV4:
1398                 is_ipv4 = true;
1399                 break;
1400         case SKB_GSO_TCPV6:
1401                 is_ipv4 = false;
1402                 break;
1403         default:
1404                 return -EINVAL;
1405         }
1406
1407         if (skb->ip_summed != CHECKSUM_PARTIAL)
1408                 return -EINVAL;
1409
1410         /* tcp header length and skb network header length are fixed for all
1411          * packet's descriptors - read them once here
1412          */
1413         tcp_hdr_len = tcp_hdrlen(skb);
1414         skb_net_hdr_len = skb_network_header_len(skb);
1415
1416         /* First descriptor must contain the header only
1417          * Header Length = MAC header len + IP header len + TCP header len
1418          */
1419         hdrlen = ETH_HLEN + tcp_hdr_len + skb_net_hdr_len;
1420         wil_dbg_txrx(wil, "TSO: process header descriptor, hdrlen %u\n",
1421                      hdrlen);
1422         rc = wil_tx_tso_gen_desc(wil, skb->data, hdrlen, swhead,
1423                                  wil_tso_type_hdr, NULL, ring, skb,
1424                                  is_ipv4, tcp_hdr_len, skb_net_hdr_len,
1425                                  mss, &descs_used);
1426         if (rc)
1427                 return -EINVAL;
1428
1429         /* Second descriptor contains the head */
1430         headlen = skb_headlen(skb) - hdrlen;
1431         wil_dbg_txrx(wil, "TSO: process skb head, headlen %u\n", headlen);
1432         rc = wil_tx_tso_gen_desc(wil, skb->data + hdrlen, headlen,
1433                                  (swhead + descs_used) % ring->size,
1434                                  (nr_frags != 0) ? wil_tso_type_first :
1435                                  wil_tso_type_lst, NULL, ring, skb,
1436                                  is_ipv4, tcp_hdr_len, skb_net_hdr_len,
1437                                  mss, &descs_used);
1438         if (rc)
1439                 goto mem_error;
1440
1441         /* Rest of the descriptors are from the SKB fragments */
1442         for (f = 0; f < nr_frags; f++) {
1443                 skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1444                 int len = frag->size;
1445
1446                 wil_dbg_txrx(wil, "TSO: frag[%d]: len %u, descs_used %d\n", f,
1447                              len, descs_used);
1448
1449                 rc = wil_tx_tso_gen_desc(wil, NULL, len,
1450                                          (swhead + descs_used) % ring->size,
1451                                          (f != nr_frags - 1) ?
1452                                          wil_tso_type_mid : wil_tso_type_lst,
1453                                          frag, ring, skb, is_ipv4,
1454                                          tcp_hdr_len, skb_net_hdr_len,
1455                                          mss, &descs_used);
1456                 if (rc)
1457                         goto mem_error;
1458         }
1459
1460         /* performance monitoring */
1461         used = wil_ring_used_tx(ring);
1462         if (wil_val_in_range(wil->ring_idle_trsh,
1463                              used, used + descs_used)) {
1464                 txdata->idle += get_cycles() - txdata->last_idle;
1465                 wil_dbg_txrx(wil,  "Ring[%2d] not idle %d -> %d\n",
1466                              ring_index, used, used + descs_used);
1467         }
1468
1469         /* advance swhead */
1470         wil_ring_advance_head(ring, descs_used);
1471         wil_dbg_txrx(wil, "TSO: Tx swhead %d -> %d\n", swhead, ring->swhead);
1472
1473         /* make sure all writes to descriptors (shared memory) are done before
1474          * committing them to HW
1475          */
1476         wmb();
1477
1478         if (wil->tx_latency)
1479                 *(ktime_t *)&skb->cb = ktime_get();
1480         else
1481                 memset(skb->cb, 0, sizeof(ktime_t));
1482
1483         wil_w(wil, ring->hwtail, ring->swhead);
1484
1485         return 0;
1486
1487 mem_error:
1488         while (descs_used > 0) {
1489                 struct device *dev = wil_to_dev(wil);
1490                 struct wil_ctx *ctx;
1491                 int i = (swhead + descs_used - 1) % ring->size;
1492                 struct wil_tx_enhanced_desc dd, *d = &dd;
1493                 struct wil_tx_enhanced_desc *_desc =
1494                         (struct wil_tx_enhanced_desc *)
1495                         &ring->va[i].tx.enhanced;
1496
1497                 *d = *_desc;
1498                 ctx = &ring->ctx[i];
1499                 wil_tx_desc_unmap_edma(dev, (union wil_tx_desc *)d, ctx);
1500                 memset(ctx, 0, sizeof(*ctx));
1501                 descs_used--;
1502         }
1503         return rc;
1504 }
1505
1506 static int wil_ring_init_bcast_edma(struct wil6210_vif *vif, int ring_id,
1507                                     int size)
1508 {
1509         struct wil6210_priv *wil = vif_to_wil(vif);
1510         struct wil_ring *ring = &wil->ring_tx[ring_id];
1511         int rc;
1512         struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_id];
1513
1514         wil_dbg_misc(wil, "init bcast: ring_id=%d, sring_id=%d\n",
1515                      ring_id, wil->tx_sring_idx);
1516
1517         lockdep_assert_held(&wil->mutex);
1518
1519         wil_tx_data_init(txdata);
1520         ring->size = size;
1521         ring->is_rx = false;
1522         rc = wil_ring_alloc_desc_ring(wil, ring);
1523         if (rc)
1524                 goto out;
1525
1526         wil->ring2cid_tid[ring_id][0] = WIL6210_MAX_CID; /* CID */
1527         wil->ring2cid_tid[ring_id][1] = 0; /* TID */
1528         if (!vif->privacy)
1529                 txdata->dot1x_open = true;
1530
1531         rc = wil_wmi_bcast_desc_ring_add(vif, ring_id);
1532         if (rc)
1533                 goto out_free;
1534
1535         return 0;
1536
1537  out_free:
1538         spin_lock_bh(&txdata->lock);
1539         txdata->enabled = 0;
1540         txdata->dot1x_open = false;
1541         spin_unlock_bh(&txdata->lock);
1542         wil_ring_free_edma(wil, ring);
1543
1544 out:
1545         return rc;
1546 }
1547
1548 static void wil_tx_fini_edma(struct wil6210_priv *wil)
1549 {
1550         struct wil_status_ring *sring = &wil->srings[wil->tx_sring_idx];
1551
1552         wil_dbg_misc(wil, "free TX sring\n");
1553
1554         wil_sring_free(wil, sring);
1555 }
1556
1557 static void wil_rx_data_free(struct wil_status_ring *sring)
1558 {
1559         if (!sring)
1560                 return;
1561
1562         kfree_skb(sring->rx_data.skb);
1563         sring->rx_data.skb = NULL;
1564 }
1565
1566 static void wil_rx_fini_edma(struct wil6210_priv *wil)
1567 {
1568         struct wil_ring *ring = &wil->ring_rx;
1569         int i;
1570
1571         wil_dbg_misc(wil, "rx_fini_edma\n");
1572
1573         wil_ring_free_edma(wil, ring);
1574
1575         for (i = 0; i < wil->num_rx_status_rings; i++) {
1576                 wil_rx_data_free(&wil->srings[i]);
1577                 wil_sring_free(wil, &wil->srings[i]);
1578         }
1579
1580         wil_free_rx_buff_arr(wil);
1581 }
1582
1583 void wil_init_txrx_ops_edma(struct wil6210_priv *wil)
1584 {
1585         wil->txrx_ops.configure_interrupt_moderation =
1586                 wil_configure_interrupt_moderation_edma;
1587         /* TX ops */
1588         wil->txrx_ops.ring_init_tx = wil_ring_init_tx_edma;
1589         wil->txrx_ops.ring_fini_tx = wil_ring_free_edma;
1590         wil->txrx_ops.ring_init_bcast = wil_ring_init_bcast_edma;
1591         wil->txrx_ops.tx_init = wil_tx_init_edma;
1592         wil->txrx_ops.tx_fini = wil_tx_fini_edma;
1593         wil->txrx_ops.tx_desc_map = wil_tx_desc_map_edma;
1594         wil->txrx_ops.tx_desc_unmap = wil_tx_desc_unmap_edma;
1595         wil->txrx_ops.tx_ring_tso = __wil_tx_ring_tso_edma;
1596         /* RX ops */
1597         wil->txrx_ops.rx_init = wil_rx_init_edma;
1598         wil->txrx_ops.wmi_addba_rx_resp = wmi_addba_rx_resp_edma;
1599         wil->txrx_ops.get_reorder_params = wil_get_reorder_params_edma;
1600         wil->txrx_ops.get_netif_rx_params = wil_get_netif_rx_params_edma;
1601         wil->txrx_ops.rx_crypto_check = wil_rx_crypto_check_edma;
1602         wil->txrx_ops.rx_error_check = wil_rx_error_check_edma;
1603         wil->txrx_ops.is_rx_idle = wil_is_rx_idle_edma;
1604         wil->txrx_ops.rx_fini = wil_rx_fini_edma;
1605 }
1606