drivers/net/wireless/ath/wcn36xx/dxe.c

   1 /*
   2  * Copyright (c) 2013 Eugene Krasnikov <k.eugene.e@gmail.com>
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 /* DXE - DMA transfer engine
  18  * we have 2 channels(High prio and Low prio) for TX and 2 channels for RX.
  19  * through low channels data packets are transfered
  20  * through high channels managment packets are transfered
  21  */
  22
  23 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  24
  25 #include <linux/interrupt.h>
  26 #include <linux/soc/qcom/smem_state.h>
  27 #include "wcn36xx.h"
  28 #include "txrx.h"
  29
  30 void *wcn36xx_dxe_get_next_bd(struct wcn36xx *wcn, bool is_low)
  31 {
  32         struct wcn36xx_dxe_ch *ch = is_low ?
  33                 &wcn->dxe_tx_l_ch :
  34                 &wcn->dxe_tx_h_ch;
  35
  36         return ch->head_blk_ctl->bd_cpu_addr;
  37 }
  38
  39 static void wcn36xx_ccu_write_register(struct wcn36xx *wcn, int addr, int data)
  40 {
  41         wcn36xx_dbg(WCN36XX_DBG_DXE,
  42                     "wcn36xx_ccu_write_register: addr=%x, data=%x\n",
  43                     addr, data);
  44
  45         writel(data, wcn->ccu_base + addr);
  46 }
  47
  48 static void wcn36xx_dxe_write_register(struct wcn36xx *wcn, int addr, int data)
  49 {
  50         wcn36xx_dbg(WCN36XX_DBG_DXE,
  51                     "wcn36xx_dxe_write_register: addr=%x, data=%x\n",
  52                     addr, data);
  53
  54         writel(data, wcn->dxe_base + addr);
  55 }
  56
  57 static void wcn36xx_dxe_read_register(struct wcn36xx *wcn, int addr, int *data)
  58 {
  59         *data = readl(wcn->dxe_base + addr);
  60
  61         wcn36xx_dbg(WCN36XX_DBG_DXE,
  62                     "wcn36xx_dxe_read_register: addr=%x, data=%x\n",
  63                     addr, *data);
  64 }
  65
  66 static void wcn36xx_dxe_free_ctl_block(struct wcn36xx_dxe_ch *ch)
  67 {
  68         struct wcn36xx_dxe_ctl *ctl = ch->head_blk_ctl, *next;
  69         int i;
  70
  71         for (i = 0; i < ch->desc_num && ctl; i++) {
  72                 next = ctl->next;
  73                 kfree(ctl);
  74                 ctl = next;
  75         }
  76 }
  77
  78 static int wcn36xx_dxe_allocate_ctl_block(struct wcn36xx_dxe_ch *ch)
  79 {
  80         struct wcn36xx_dxe_ctl *prev_ctl = NULL;
  81         struct wcn36xx_dxe_ctl *cur_ctl = NULL;
  82         int i;
  83
  84         spin_lock_init(&ch->lock);
  85         for (i = 0; i < ch->desc_num; i++) {
  86                 cur_ctl = kzalloc(sizeof(*cur_ctl), GFP_KERNEL);
  87                 if (!cur_ctl)
  88                         goto out_fail;
  89
  90                 spin_lock_init(&cur_ctl->skb_lock);
  91                 cur_ctl->ctl_blk_order = i;
  92                 if (i == 0) {
  93                         ch->head_blk_ctl = cur_ctl;
  94                         ch->tail_blk_ctl = cur_ctl;
  95                 } else if (ch->desc_num - 1 == i) {
  96                         prev_ctl->next = cur_ctl;
  97                         cur_ctl->next = ch->head_blk_ctl;
  98                 } else {
  99                         prev_ctl->next = cur_ctl;
 100                 }
 101                 prev_ctl = cur_ctl;
 102         }
 103
 104         return 0;
 105
 106 out_fail:
 107         wcn36xx_dxe_free_ctl_block(ch);
 108         return -ENOMEM;
 109 }
 110
 111 int wcn36xx_dxe_alloc_ctl_blks(struct wcn36xx *wcn)
 112 {
 113         int ret;
 114
 115         wcn->dxe_tx_l_ch.ch_type = WCN36XX_DXE_CH_TX_L;
 116         wcn->dxe_tx_h_ch.ch_type = WCN36XX_DXE_CH_TX_H;
 117         wcn->dxe_rx_l_ch.ch_type = WCN36XX_DXE_CH_RX_L;
 118         wcn->dxe_rx_h_ch.ch_type = WCN36XX_DXE_CH_RX_H;
 119
 120         wcn->dxe_tx_l_ch.desc_num = WCN36XX_DXE_CH_DESC_NUMB_TX_L;
 121         wcn->dxe_tx_h_ch.desc_num = WCN36XX_DXE_CH_DESC_NUMB_TX_H;
 122         wcn->dxe_rx_l_ch.desc_num = WCN36XX_DXE_CH_DESC_NUMB_RX_L;
 123         wcn->dxe_rx_h_ch.desc_num = WCN36XX_DXE_CH_DESC_NUMB_RX_H;
 124
 125         wcn->dxe_tx_l_ch.dxe_wq =  WCN36XX_DXE_WQ_TX_L;
 126         wcn->dxe_tx_h_ch.dxe_wq =  WCN36XX_DXE_WQ_TX_H;
 127
 128         wcn->dxe_tx_l_ch.ctrl_bd = WCN36XX_DXE_CTRL_TX_L_BD;
 129         wcn->dxe_tx_h_ch.ctrl_bd = WCN36XX_DXE_CTRL_TX_H_BD;
 130
 131         wcn->dxe_tx_l_ch.ctrl_skb = WCN36XX_DXE_CTRL_TX_L_SKB;
 132         wcn->dxe_tx_h_ch.ctrl_skb = WCN36XX_DXE_CTRL_TX_H_SKB;
 133
 134         wcn->dxe_tx_l_ch.reg_ctrl = WCN36XX_DXE_REG_CTL_TX_L;
 135         wcn->dxe_tx_h_ch.reg_ctrl = WCN36XX_DXE_REG_CTL_TX_H;
 136
 137         wcn->dxe_tx_l_ch.def_ctrl = WCN36XX_DXE_CH_DEFAULT_CTL_TX_L;
 138         wcn->dxe_tx_h_ch.def_ctrl = WCN36XX_DXE_CH_DEFAULT_CTL_TX_H;
 139
 140         /* DXE control block allocation */
 141         ret = wcn36xx_dxe_allocate_ctl_block(&wcn->dxe_tx_l_ch);
 142         if (ret)
 143                 goto out_err;
 144         ret = wcn36xx_dxe_allocate_ctl_block(&wcn->dxe_tx_h_ch);
 145         if (ret)
 146                 goto out_err;
 147         ret = wcn36xx_dxe_allocate_ctl_block(&wcn->dxe_rx_l_ch);
 148         if (ret)
 149                 goto out_err;
 150         ret = wcn36xx_dxe_allocate_ctl_block(&wcn->dxe_rx_h_ch);
 151         if (ret)
 152                 goto out_err;
 153
 154         /* Initialize SMSM state  Clear TX Enable RING EMPTY STATE */
 155         ret = qcom_smem_state_update_bits(wcn->tx_enable_state,
 156                                           WCN36XX_SMSM_WLAN_TX_ENABLE |
 157                                           WCN36XX_SMSM_WLAN_TX_RINGS_EMPTY,
 158                                           WCN36XX_SMSM_WLAN_TX_RINGS_EMPTY);
 159         if (ret)
 160                 goto out_err;
 161
 162         return 0;
 163
 164 out_err:
 165         wcn36xx_err("Failed to allocate DXE control blocks\n");
 166         wcn36xx_dxe_free_ctl_blks(wcn);
 167         return -ENOMEM;
 168 }
 169
 170 void wcn36xx_dxe_free_ctl_blks(struct wcn36xx *wcn)
 171 {
 172         wcn36xx_dxe_free_ctl_block(&wcn->dxe_tx_l_ch);
 173         wcn36xx_dxe_free_ctl_block(&wcn->dxe_tx_h_ch);
 174         wcn36xx_dxe_free_ctl_block(&wcn->dxe_rx_l_ch);
 175         wcn36xx_dxe_free_ctl_block(&wcn->dxe_rx_h_ch);
 176 }
 177
 178 static int wcn36xx_dxe_init_descs(struct device *dev, struct wcn36xx_dxe_ch *wcn_ch)
 179 {
 180         struct wcn36xx_dxe_desc *cur_dxe = NULL;
 181         struct wcn36xx_dxe_desc *prev_dxe = NULL;
 182         struct wcn36xx_dxe_ctl *cur_ctl = NULL;
 183         size_t size;
 184         int i;
 185
 186         size = wcn_ch->desc_num * sizeof(struct wcn36xx_dxe_desc);
 187         wcn_ch->cpu_addr = dma_alloc_coherent(dev, size, &wcn_ch->dma_addr,
 188                                               GFP_KERNEL);
 189         if (!wcn_ch->cpu_addr)
 190                 return -ENOMEM;
 191
 192         memset(wcn_ch->cpu_addr, 0, size);
 193
 194         cur_dxe = (struct wcn36xx_dxe_desc *)wcn_ch->cpu_addr;
 195         cur_ctl = wcn_ch->head_blk_ctl;
 196
 197         for (i = 0; i < wcn_ch->desc_num; i++) {
 198                 cur_ctl->desc = cur_dxe;
 199                 cur_ctl->desc_phy_addr = wcn_ch->dma_addr +
 200                         i * sizeof(struct wcn36xx_dxe_desc);
 201
 202                 switch (wcn_ch->ch_type) {
 203                 case WCN36XX_DXE_CH_TX_L:
 204                         cur_dxe->ctrl = WCN36XX_DXE_CTRL_TX_L;
 205                         cur_dxe->dst_addr_l = WCN36XX_DXE_WQ_TX_L;
 206                         break;
 207                 case WCN36XX_DXE_CH_TX_H:
 208                         cur_dxe->ctrl = WCN36XX_DXE_CTRL_TX_H;
 209                         cur_dxe->dst_addr_l = WCN36XX_DXE_WQ_TX_H;
 210                         break;
 211                 case WCN36XX_DXE_CH_RX_L:
 212                         cur_dxe->ctrl = WCN36XX_DXE_CTRL_RX_L;
 213                         cur_dxe->src_addr_l = WCN36XX_DXE_WQ_RX_L;
 214                         break;
 215                 case WCN36XX_DXE_CH_RX_H:
 216                         cur_dxe->ctrl = WCN36XX_DXE_CTRL_RX_H;
 217                         cur_dxe->src_addr_l = WCN36XX_DXE_WQ_RX_H;
 218                         break;
 219                 }
 220                 if (0 == i) {
 221                         cur_dxe->phy_next_l = 0;
 222                 } else if ((0 < i) && (i < wcn_ch->desc_num - 1)) {
 223                         prev_dxe->phy_next_l =
 224                                 cur_ctl->desc_phy_addr;
 225                 } else if (i == (wcn_ch->desc_num - 1)) {
 226                         prev_dxe->phy_next_l =
 227                                 cur_ctl->desc_phy_addr;
 228                         cur_dxe->phy_next_l =
 229                                 wcn_ch->head_blk_ctl->desc_phy_addr;
 230                 }
 231                 cur_ctl = cur_ctl->next;
 232                 prev_dxe = cur_dxe;
 233                 cur_dxe++;
 234         }
 235
 236         return 0;
 237 }
 238
 239 static void wcn36xx_dxe_init_tx_bd(struct wcn36xx_dxe_ch *ch,
 240                                    struct wcn36xx_dxe_mem_pool *pool)
 241 {
 242         int i, chunk_size = pool->chunk_size;
 243         dma_addr_t bd_phy_addr = pool->phy_addr;
 244         void *bd_cpu_addr = pool->virt_addr;
 245         struct wcn36xx_dxe_ctl *cur = ch->head_blk_ctl;
 246
 247         for (i = 0; i < ch->desc_num; i++) {
 248                 /* Only every second dxe needs a bd pointer,
 249                    the other will point to the skb data */
 250                 if (!(i & 1)) {
 251                         cur->bd_phy_addr = bd_phy_addr;
 252                         cur->bd_cpu_addr = bd_cpu_addr;
 253                         bd_phy_addr += chunk_size;
 254                         bd_cpu_addr += chunk_size;
 255                 } else {
 256                         cur->bd_phy_addr = 0;
 257                         cur->bd_cpu_addr = NULL;
 258                 }
 259                 cur = cur->next;
 260         }
 261 }
 262
 263 static int wcn36xx_dxe_enable_ch_int(struct wcn36xx *wcn, u16 wcn_ch)
 264 {
 265         int reg_data = 0;
 266
 267         wcn36xx_dxe_read_register(wcn,
 268                                   WCN36XX_DXE_INT_MASK_REG,
 269                                   &reg_data);
 270
 271         reg_data |= wcn_ch;
 272
 273         wcn36xx_dxe_write_register(wcn,
 274                                    WCN36XX_DXE_INT_MASK_REG,
 275                                    (int)reg_data);
 276         return 0;
 277 }
 278
 279 static int wcn36xx_dxe_fill_skb(struct device *dev, struct wcn36xx_dxe_ctl *ctl)
 280 {
 281         struct wcn36xx_dxe_desc *dxe = ctl->desc;
 282         struct sk_buff *skb;
 283
 284         skb = alloc_skb(WCN36XX_PKT_SIZE, GFP_ATOMIC);
 285         if (skb == NULL)
 286                 return -ENOMEM;
 287
 288         dxe->dst_addr_l = dma_map_single(dev,
 289                                          skb_tail_pointer(skb),
 290                                          WCN36XX_PKT_SIZE,
 291                                          DMA_FROM_DEVICE);
 292         if (dma_mapping_error(dev, dxe->dst_addr_l)) {
 293                 dev_err(dev, "unable to map skb\n");
 294                 kfree_skb(skb);
 295                 return -ENOMEM;
 296         }
 297         ctl->skb = skb;
 298
 299         return 0;
 300 }
 301
 302 static int wcn36xx_dxe_ch_alloc_skb(struct wcn36xx *wcn,
 303                                     struct wcn36xx_dxe_ch *wcn_ch)
 304 {
 305         int i;
 306         struct wcn36xx_dxe_ctl *cur_ctl = NULL;
 307
 308         cur_ctl = wcn_ch->head_blk_ctl;
 309
 310         for (i = 0; i < wcn_ch->desc_num; i++) {
 311                 wcn36xx_dxe_fill_skb(wcn->dev, cur_ctl);
 312                 cur_ctl = cur_ctl->next;
 313         }
 314
 315         return 0;
 316 }
 317
 318 static void wcn36xx_dxe_ch_free_skbs(struct wcn36xx *wcn,
 319                                      struct wcn36xx_dxe_ch *wcn_ch)
 320 {
 321         struct wcn36xx_dxe_ctl *cur = wcn_ch->head_blk_ctl;
 322         int i;
 323
 324         for (i = 0; i < wcn_ch->desc_num; i++) {
 325                 kfree_skb(cur->skb);
 326                 cur = cur->next;
 327         }
 328 }
 329
 330 void wcn36xx_dxe_tx_ack_ind(struct wcn36xx *wcn, u32 status)
 331 {
 332         struct ieee80211_tx_info *info;
 333         struct sk_buff *skb;
 334         unsigned long flags;
 335
 336         spin_lock_irqsave(&wcn->dxe_lock, flags);
 337         skb = wcn->tx_ack_skb;
 338         wcn->tx_ack_skb = NULL;
 339         spin_unlock_irqrestore(&wcn->dxe_lock, flags);
 340
 341         if (!skb) {
 342                 wcn36xx_warn("Spurious TX complete indication\n");
 343                 return;
 344         }
 345
 346         info = IEEE80211_SKB_CB(skb);
 347
 348         if (status == 1)
 349                 info->flags |= IEEE80211_TX_STAT_ACK;
 350
 351         wcn36xx_dbg(WCN36XX_DBG_DXE, "dxe tx ack status: %d\n", status);
 352
 353         ieee80211_tx_status_irqsafe(wcn->hw, skb);
 354         ieee80211_wake_queues(wcn->hw);
 355 }
 356
 357 static void reap_tx_dxes(struct wcn36xx *wcn, struct wcn36xx_dxe_ch *ch)
 358 {
 359         struct wcn36xx_dxe_ctl *ctl;
 360         struct ieee80211_tx_info *info;
 361         unsigned long flags;
 362
 363         /*
 364          * Make at least one loop of do-while because in case ring is
 365          * completely full head and tail are pointing to the same element
 366          * and while-do will not make any cycles.
 367          */
 368         spin_lock_irqsave(&ch->lock, flags);
 369         ctl = ch->tail_blk_ctl;
 370         do {
 371                 if (ctl->desc->ctrl & WCN36XX_DXE_CTRL_VALID_MASK)
 372                         break;
 373                 if (ctl->skb) {
 374                         dma_unmap_single(wcn->dev, ctl->desc->src_addr_l,
 375                                          ctl->skb->len, DMA_TO_DEVICE);
 376                         info = IEEE80211_SKB_CB(ctl->skb);
 377                         if (!(info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS)) {
 378                                 /* Keep frame until TX status comes */
 379                                 ieee80211_free_txskb(wcn->hw, ctl->skb);
 380                         }
 381                         spin_lock(&ctl->skb_lock);
 382                         if (wcn->queues_stopped) {
 383                                 wcn->queues_stopped = false;
 384                                 ieee80211_wake_queues(wcn->hw);
 385                         }
 386                         spin_unlock(&ctl->skb_lock);
 387
 388                         ctl->skb = NULL;
 389                 }
 390                 ctl = ctl->next;
 391         } while (ctl != ch->head_blk_ctl &&
 392                !(ctl->desc->ctrl & WCN36XX_DXE_CTRL_VALID_MASK));
 393
 394         ch->tail_blk_ctl = ctl;
 395         spin_unlock_irqrestore(&ch->lock, flags);
 396 }
 397
 398 static irqreturn_t wcn36xx_irq_tx_complete(int irq, void *dev)
 399 {
 400         struct wcn36xx *wcn = (struct wcn36xx *)dev;
 401         int int_src, int_reason;
 402
 403         wcn36xx_dxe_read_register(wcn, WCN36XX_DXE_INT_SRC_RAW_REG, &int_src);
 404
 405         if (int_src & WCN36XX_INT_MASK_CHAN_TX_H) {
 406                 wcn36xx_dxe_read_register(wcn,
 407                                           WCN36XX_DXE_CH_STATUS_REG_ADDR_TX_H,
 408                                           &int_reason);
 409
 410                 /* TODO: Check int_reason */
 411
 412                 wcn36xx_dxe_write_register(wcn,
 413                                            WCN36XX_DXE_0_INT_CLR,
 414                                            WCN36XX_INT_MASK_CHAN_TX_H);
 415
 416                 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_0_INT_ED_CLR,
 417                                            WCN36XX_INT_MASK_CHAN_TX_H);
 418                 wcn36xx_dbg(WCN36XX_DBG_DXE, "dxe tx ready high\n");
 419                 reap_tx_dxes(wcn, &wcn->dxe_tx_h_ch);
 420         }
 421
 422         if (int_src & WCN36XX_INT_MASK_CHAN_TX_L) {
 423                 wcn36xx_dxe_read_register(wcn,
 424                                           WCN36XX_DXE_CH_STATUS_REG_ADDR_TX_L,
 425                                           &int_reason);
 426                 /* TODO: Check int_reason */
 427
 428                 wcn36xx_dxe_write_register(wcn,
 429                                            WCN36XX_DXE_0_INT_CLR,
 430                                            WCN36XX_INT_MASK_CHAN_TX_L);
 431
 432                 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_0_INT_ED_CLR,
 433                                            WCN36XX_INT_MASK_CHAN_TX_L);
 434                 wcn36xx_dbg(WCN36XX_DBG_DXE, "dxe tx ready low\n");
 435                 reap_tx_dxes(wcn, &wcn->dxe_tx_l_ch);
 436         }
 437
 438         return IRQ_HANDLED;
 439 }
 440
 441 static irqreturn_t wcn36xx_irq_rx_ready(int irq, void *dev)
 442 {
 443         struct wcn36xx *wcn = (struct wcn36xx *)dev;
 444
 445         disable_irq_nosync(wcn->rx_irq);
 446         wcn36xx_dxe_rx_frame(wcn);
 447         enable_irq(wcn->rx_irq);
 448         return IRQ_HANDLED;
 449 }
 450
 451 static int wcn36xx_dxe_request_irqs(struct wcn36xx *wcn)
 452 {
 453         int ret;
 454
 455         ret = request_irq(wcn->tx_irq, wcn36xx_irq_tx_complete,
 456                           IRQF_TRIGGER_HIGH, "wcn36xx_tx", wcn);
 457         if (ret) {
 458                 wcn36xx_err("failed to alloc tx irq\n");
 459                 goto out_err;
 460         }
 461
 462         ret = request_irq(wcn->rx_irq, wcn36xx_irq_rx_ready, IRQF_TRIGGER_HIGH,
 463                           "wcn36xx_rx", wcn);
 464         if (ret) {
 465                 wcn36xx_err("failed to alloc rx irq\n");
 466                 goto out_txirq;
 467         }
 468
 469         enable_irq_wake(wcn->rx_irq);
 470
 471         return 0;
 472
 473 out_txirq:
 474         free_irq(wcn->tx_irq, wcn);
 475 out_err:
 476         return ret;
 477
 478 }
 479
 480 static int wcn36xx_rx_handle_packets(struct wcn36xx *wcn,
 481                                      struct wcn36xx_dxe_ch *ch)
 482 {
 483         struct wcn36xx_dxe_ctl *ctl = ch->head_blk_ctl;
 484         struct wcn36xx_dxe_desc *dxe = ctl->desc;
 485         dma_addr_t  dma_addr;
 486         struct sk_buff *skb;
 487         int ret = 0, int_mask;
 488         u32 value;
 489
 490         if (ch->ch_type == WCN36XX_DXE_CH_RX_L) {
 491                 value = WCN36XX_DXE_CTRL_RX_L;
 492                 int_mask = WCN36XX_DXE_INT_CH1_MASK;
 493         } else {
 494                 value = WCN36XX_DXE_CTRL_RX_H;
 495                 int_mask = WCN36XX_DXE_INT_CH3_MASK;
 496         }
 497
 498         while (!(dxe->ctrl & WCN36XX_DXE_CTRL_VALID_MASK)) {
 499                 skb = ctl->skb;
 500                 dma_addr = dxe->dst_addr_l;
 501                 ret = wcn36xx_dxe_fill_skb(wcn->dev, ctl);
 502                 if (0 == ret) {
 503                         /* new skb allocation ok. Use the new one and queue
 504                          * the old one to network system.
 505                          */
 506                         dma_unmap_single(wcn->dev, dma_addr, WCN36XX_PKT_SIZE,
 507                                         DMA_FROM_DEVICE);
 508                         wcn36xx_rx_skb(wcn, skb);
 509                 } /* else keep old skb not submitted and use it for rx DMA */
 510
 511                 dxe->ctrl = value;
 512                 ctl = ctl->next;
 513                 dxe = ctl->desc;
 514         }
 515         wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_ENCH_ADDR, int_mask);
 516
 517         ch->head_blk_ctl = ctl;
 518         return 0;
 519 }
 520
 521 void wcn36xx_dxe_rx_frame(struct wcn36xx *wcn)
 522 {
 523         int int_src;
 524
 525         wcn36xx_dxe_read_register(wcn, WCN36XX_DXE_INT_SRC_RAW_REG, &int_src);
 526
 527         /* RX_LOW_PRI */
 528         if (int_src & WCN36XX_DXE_INT_CH1_MASK) {
 529                 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_0_INT_CLR,
 530                                            WCN36XX_DXE_INT_CH1_MASK);
 531                 wcn36xx_rx_handle_packets(wcn, &(wcn->dxe_rx_l_ch));
 532         }
 533
 534         /* RX_HIGH_PRI */
 535         if (int_src & WCN36XX_DXE_INT_CH3_MASK) {
 536                 /* Clean up all the INT within this channel */
 537                 wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_0_INT_CLR,
 538                                            WCN36XX_DXE_INT_CH3_MASK);
 539                 wcn36xx_rx_handle_packets(wcn, &(wcn->dxe_rx_h_ch));
 540         }
 541
 542         if (!int_src)
 543                 wcn36xx_warn("No DXE interrupt pending\n");
 544 }
 545
 546 int wcn36xx_dxe_allocate_mem_pools(struct wcn36xx *wcn)
 547 {
 548         size_t s;
 549         void *cpu_addr;
 550
 551         /* Allocate BD headers for MGMT frames */
 552
 553         /* Where this come from ask QC */
 554         wcn->mgmt_mem_pool.chunk_size = WCN36XX_BD_CHUNK_SIZE +
 555                 16 - (WCN36XX_BD_CHUNK_SIZE % 8);
 556
 557         s = wcn->mgmt_mem_pool.chunk_size * WCN36XX_DXE_CH_DESC_NUMB_TX_H;
 558         cpu_addr = dma_alloc_coherent(wcn->dev, s, &wcn->mgmt_mem_pool.phy_addr,
 559                                       GFP_KERNEL);
 560         if (!cpu_addr)
 561                 goto out_err;
 562
 563         wcn->mgmt_mem_pool.virt_addr = cpu_addr;
 564         memset(cpu_addr, 0, s);
 565
 566         /* Allocate BD headers for DATA frames */
 567
 568         /* Where this come from ask QC */
 569         wcn->data_mem_pool.chunk_size = WCN36XX_BD_CHUNK_SIZE +
 570                 16 - (WCN36XX_BD_CHUNK_SIZE % 8);
 571
 572         s = wcn->data_mem_pool.chunk_size * WCN36XX_DXE_CH_DESC_NUMB_TX_L;
 573         cpu_addr = dma_alloc_coherent(wcn->dev, s, &wcn->data_mem_pool.phy_addr,
 574                                       GFP_KERNEL);
 575         if (!cpu_addr)
 576                 goto out_err;
 577
 578         wcn->data_mem_pool.virt_addr = cpu_addr;
 579         memset(cpu_addr, 0, s);
 580
 581         return 0;
 582
 583 out_err:
 584         wcn36xx_dxe_free_mem_pools(wcn);
 585         wcn36xx_err("Failed to allocate BD mempool\n");
 586         return -ENOMEM;
 587 }
 588
 589 void wcn36xx_dxe_free_mem_pools(struct wcn36xx *wcn)
 590 {
 591         if (wcn->mgmt_mem_pool.virt_addr)
 592                 dma_free_coherent(wcn->dev, wcn->mgmt_mem_pool.chunk_size *
 593                                   WCN36XX_DXE_CH_DESC_NUMB_TX_H,
 594                                   wcn->mgmt_mem_pool.virt_addr,
 595                                   wcn->mgmt_mem_pool.phy_addr);
 596
 597         if (wcn->data_mem_pool.virt_addr) {
 598                 dma_free_coherent(wcn->dev, wcn->data_mem_pool.chunk_size *
 599                                   WCN36XX_DXE_CH_DESC_NUMB_TX_L,
 600                                   wcn->data_mem_pool.virt_addr,
 601                                   wcn->data_mem_pool.phy_addr);
 602         }
 603 }
 604
 605 int wcn36xx_dxe_tx_frame(struct wcn36xx *wcn,
 606                          struct wcn36xx_vif *vif_priv,
 607                          struct sk_buff *skb,
 608                          bool is_low)
 609 {
 610         struct wcn36xx_dxe_ctl *ctl = NULL;
 611         struct wcn36xx_dxe_desc *desc = NULL;
 612         struct wcn36xx_dxe_ch *ch = NULL;
 613         unsigned long flags;
 614         int ret;
 615
 616         ch = is_low ? &wcn->dxe_tx_l_ch : &wcn->dxe_tx_h_ch;
 617
 618         spin_lock_irqsave(&ch->lock, flags);
 619         ctl = ch->head_blk_ctl;
 620
 621         spin_lock(&ctl->next->skb_lock);
 622
 623         /*
 624          * If skb is not null that means that we reached the tail of the ring
 625          * hence ring is full. Stop queues to let mac80211 back off until ring
 626          * has an empty slot again.
 627          */
 628         if (NULL != ctl->next->skb) {
 629                 ieee80211_stop_queues(wcn->hw);
 630                 wcn->queues_stopped = true;
 631                 spin_unlock(&ctl->next->skb_lock);
 632                 spin_unlock_irqrestore(&ch->lock, flags);
 633                 return -EBUSY;
 634         }
 635         spin_unlock(&ctl->next->skb_lock);
 636
 637         ctl->skb = NULL;
 638         desc = ctl->desc;
 639
 640         /* Set source address of the BD we send */
 641         desc->src_addr_l = ctl->bd_phy_addr;
 642
 643         desc->dst_addr_l = ch->dxe_wq;
 644         desc->fr_len = sizeof(struct wcn36xx_tx_bd);
 645         desc->ctrl = ch->ctrl_bd;
 646
 647         wcn36xx_dbg(WCN36XX_DBG_DXE, "DXE TX\n");
 648
 649         wcn36xx_dbg_dump(WCN36XX_DBG_DXE_DUMP, "DESC1 >>> ",
 650                          (char *)desc, sizeof(*desc));
 651         wcn36xx_dbg_dump(WCN36XX_DBG_DXE_DUMP,
 652                          "BD   >>> ", (char *)ctl->bd_cpu_addr,
 653                          sizeof(struct wcn36xx_tx_bd));
 654
 655         /* Set source address of the SKB we send */
 656         ctl = ctl->next;
 657         ctl->skb = skb;
 658         desc = ctl->desc;
 659         if (ctl->bd_cpu_addr) {
 660                 wcn36xx_err("bd_cpu_addr cannot be NULL for skb DXE\n");
 661                 ret = -EINVAL;
 662                 goto unlock;
 663         }
 664
 665         desc->src_addr_l = dma_map_single(wcn->dev,
 666                                           ctl->skb->data,
 667                                           ctl->skb->len,
 668                                           DMA_TO_DEVICE);
 669
 670         desc->dst_addr_l = ch->dxe_wq;
 671         desc->fr_len = ctl->skb->len;
 672
 673         /* set dxe descriptor to VALID */
 674         desc->ctrl = ch->ctrl_skb;
 675
 676         wcn36xx_dbg_dump(WCN36XX_DBG_DXE_DUMP, "DESC2 >>> ",
 677                          (char *)desc, sizeof(*desc));
 678         wcn36xx_dbg_dump(WCN36XX_DBG_DXE_DUMP, "SKB   >>> ",
 679                          (char *)ctl->skb->data, ctl->skb->len);
 680
 681         /* Move the head of the ring to the next empty descriptor */
 682          ch->head_blk_ctl = ctl->next;
 683
 684         /*
 685          * When connected and trying to send data frame chip can be in sleep
 686          * mode and writing to the register will not wake up the chip. Instead
 687          * notify chip about new frame through SMSM bus.
 688          */
 689         if (is_low &&  vif_priv->pw_state == WCN36XX_BMPS) {
 690                 qcom_smem_state_update_bits(wcn->tx_rings_empty_state,
 691                                             WCN36XX_SMSM_WLAN_TX_ENABLE,
 692                                             WCN36XX_SMSM_WLAN_TX_ENABLE);
 693         } else {
 694                 /* indicate End Of Packet and generate interrupt on descriptor
 695                  * done.
 696                  */
 697                 wcn36xx_dxe_write_register(wcn,
 698                         ch->reg_ctrl, ch->def_ctrl);
 699         }
 700
 701         ret = 0;
 702 unlock:
 703         spin_unlock_irqrestore(&ch->lock, flags);
 704         return ret;
 705 }
 706
 707 int wcn36xx_dxe_init(struct wcn36xx *wcn)
 708 {
 709         int reg_data = 0, ret;
 710
 711         reg_data = WCN36XX_DXE_REG_RESET;
 712         wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_REG_CSR_RESET, reg_data);
 713
 714         /* Select channels for rx avail and xfer done interrupts... */
 715         reg_data = (WCN36XX_DXE_INT_CH3_MASK | WCN36XX_DXE_INT_CH1_MASK) << 16 |
 716                     WCN36XX_DXE_INT_CH0_MASK | WCN36XX_DXE_INT_CH4_MASK;
 717         if (wcn->is_pronto)
 718                 wcn36xx_ccu_write_register(wcn, WCN36XX_CCU_DXE_INT_SELECT_PRONTO, reg_data);
 719         else
 720                 wcn36xx_ccu_write_register(wcn, WCN36XX_CCU_DXE_INT_SELECT_RIVA, reg_data);
 721
 722         /***************************************/
 723         /* Init descriptors for TX LOW channel */
 724         /***************************************/
 725         wcn36xx_dxe_init_descs(wcn->dev, &wcn->dxe_tx_l_ch);
 726         wcn36xx_dxe_init_tx_bd(&wcn->dxe_tx_l_ch, &wcn->data_mem_pool);
 727
 728         /* Write channel head to a NEXT register */
 729         wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_L,
 730                 wcn->dxe_tx_l_ch.head_blk_ctl->desc_phy_addr);
 731
 732         /* Program DMA destination addr for TX LOW */
 733         wcn36xx_dxe_write_register(wcn,
 734                 WCN36XX_DXE_CH_DEST_ADDR_TX_L,
 735                 WCN36XX_DXE_WQ_TX_L);
 736
 737         wcn36xx_dxe_read_register(wcn, WCN36XX_DXE_REG_CH_EN, &reg_data);
 738         wcn36xx_dxe_enable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_TX_L);
 739
 740         /***************************************/
 741         /* Init descriptors for TX HIGH channel */
 742         /***************************************/
 743         wcn36xx_dxe_init_descs(wcn->dev, &wcn->dxe_tx_h_ch);
 744         wcn36xx_dxe_init_tx_bd(&wcn->dxe_tx_h_ch, &wcn->mgmt_mem_pool);
 745
 746         /* Write channel head to a NEXT register */
 747         wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_CH_NEXT_DESC_ADDR_TX_H,
 748                 wcn->dxe_tx_h_ch.head_blk_ctl->desc_phy_addr);
 749
 750         /* Program DMA destination addr for TX HIGH */
 751         wcn36xx_dxe_write_register(wcn,
 752                 WCN36XX_DXE_CH_DEST_ADDR_TX_H,
 753                 WCN36XX_DXE_WQ_TX_H);
 754
 755         wcn36xx_dxe_read_register(wcn, WCN36XX_DXE_REG_CH_EN, &reg_data);
 756
 757         /* Enable channel interrupts */
 758         wcn36xx_dxe_enable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_TX_H);
 759
 760         /***************************************/
 761         /* Init descriptors for RX LOW channel */
 762         /***************************************/
 763         wcn36xx_dxe_init_descs(wcn->dev, &wcn->dxe_rx_l_ch);
 764
 765         /* For RX we need to preallocated buffers */
 766         wcn36xx_dxe_ch_alloc_skb(wcn, &wcn->dxe_rx_l_ch);
 767
 768         /* Write channel head to a NEXT register */
 769         wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_L,
 770                 wcn->dxe_rx_l_ch.head_blk_ctl->desc_phy_addr);
 771
 772         /* Write DMA source address */
 773         wcn36xx_dxe_write_register(wcn,
 774                 WCN36XX_DXE_CH_SRC_ADDR_RX_L,
 775                 WCN36XX_DXE_WQ_RX_L);
 776
 777         /* Program preallocated destination address */
 778         wcn36xx_dxe_write_register(wcn,
 779                 WCN36XX_DXE_CH_DEST_ADDR_RX_L,
 780                 wcn->dxe_rx_l_ch.head_blk_ctl->desc->phy_next_l);
 781
 782         /* Enable default control registers */
 783         wcn36xx_dxe_write_register(wcn,
 784                 WCN36XX_DXE_REG_CTL_RX_L,
 785                 WCN36XX_DXE_CH_DEFAULT_CTL_RX_L);
 786
 787         /* Enable channel interrupts */
 788         wcn36xx_dxe_enable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_RX_L);
 789
 790         /***************************************/
 791         /* Init descriptors for RX HIGH channel */
 792         /***************************************/
 793         wcn36xx_dxe_init_descs(wcn->dev, &wcn->dxe_rx_h_ch);
 794
 795         /* For RX we need to prealocat buffers */
 796         wcn36xx_dxe_ch_alloc_skb(wcn, &wcn->dxe_rx_h_ch);
 797
 798         /* Write chanel head to a NEXT register */
 799         wcn36xx_dxe_write_register(wcn, WCN36XX_DXE_CH_NEXT_DESC_ADDR_RX_H,
 800                 wcn->dxe_rx_h_ch.head_blk_ctl->desc_phy_addr);
 801
 802         /* Write DMA source address */
 803         wcn36xx_dxe_write_register(wcn,
 804                 WCN36XX_DXE_CH_SRC_ADDR_RX_H,
 805                 WCN36XX_DXE_WQ_RX_H);
 806
 807         /* Program preallocated destination address */
 808         wcn36xx_dxe_write_register(wcn,
 809                 WCN36XX_DXE_CH_DEST_ADDR_RX_H,
 810                  wcn->dxe_rx_h_ch.head_blk_ctl->desc->phy_next_l);
 811
 812         /* Enable default control registers */
 813         wcn36xx_dxe_write_register(wcn,
 814                 WCN36XX_DXE_REG_CTL_RX_H,
 815                 WCN36XX_DXE_CH_DEFAULT_CTL_RX_H);
 816
 817         /* Enable channel interrupts */
 818         wcn36xx_dxe_enable_ch_int(wcn, WCN36XX_INT_MASK_CHAN_RX_H);
 819
 820         ret = wcn36xx_dxe_request_irqs(wcn);
 821         if (ret < 0)
 822                 goto out_err;
 823
 824         return 0;
 825
 826 out_err:
 827         return ret;
 828 }
 829
 830 void wcn36xx_dxe_deinit(struct wcn36xx *wcn)
 831 {
 832         free_irq(wcn->tx_irq, wcn);
 833         free_irq(wcn->rx_irq, wcn);
 834
 835         if (wcn->tx_ack_skb) {
 836                 ieee80211_tx_status_irqsafe(wcn->hw, wcn->tx_ack_skb);
 837                 wcn->tx_ack_skb = NULL;
 838         }
 839
 840         wcn36xx_dxe_ch_free_skbs(wcn, &wcn->dxe_rx_l_ch);
 841         wcn36xx_dxe_ch_free_skbs(wcn, &wcn->dxe_rx_h_ch);
 842 }