drivers/net/wireless/ath/ath9k/ar9003_hw.c

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "hw.h"
  18 #include "ar9003_mac.h"
  19 #include "ar9003_2p2_initvals.h"
  20 #include "ar9003_buffalo_initvals.h"
  21 #include "ar9485_initvals.h"
  22 #include "ar9340_initvals.h"
  23 #include "ar9330_1p1_initvals.h"
  24 #include "ar9330_1p2_initvals.h"
  25 #include "ar955x_1p0_initvals.h"
  26 #include "ar9580_1p0_initvals.h"
  27 #include "ar9462_2p0_initvals.h"
  28 #include "ar9462_2p1_initvals.h"
  29 #include "ar9565_1p0_initvals.h"
  30 #include "ar9565_1p1_initvals.h"
  31 #include "ar953x_initvals.h"
  32
  33 /* General hardware code for the AR9003 hadware family */
  34
  35 /*
  36  * The AR9003 family uses a new INI format (pre, core, post
  37  * arrays per subsystem). This provides support for the
  38  * AR9003 2.2 chipsets.
  39  */
  40 static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
  41 {
  42         if (AR_SREV_9330_11(ah)) {
  43                 /* mac */
  44                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
  45                                 ar9331_1p1_mac_core);
  46                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
  47                                 ar9331_1p1_mac_postamble);
  48
  49                 /* bb */
  50                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
  51                                 ar9331_1p1_baseband_core);
  52                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
  53                                 ar9331_1p1_baseband_postamble);
  54
  55                 /* radio */
  56                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
  57                                 ar9331_1p1_radio_core);
  58
  59                 /* soc */
  60                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
  61                                 ar9331_1p1_soc_preamble);
  62                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
  63                                 ar9331_1p1_soc_postamble);
  64
  65                 /* rx/tx gain */
  66                 INIT_INI_ARRAY(&ah->iniModesRxGain,
  67                                 ar9331_common_rx_gain_1p1);
  68                 INIT_INI_ARRAY(&ah->iniModesTxGain,
  69                                 ar9331_modes_lowest_ob_db_tx_gain_1p1);
  70
  71                 /* Japan 2484 Mhz CCK */
  72                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
  73                                ar9331_1p1_baseband_core_txfir_coeff_japan_2484);
  74
  75                 /* additional clock settings */
  76                 if (ah->is_clk_25mhz)
  77                         INIT_INI_ARRAY(&ah->iniAdditional,
  78                                         ar9331_1p1_xtal_25M);
  79                 else
  80                         INIT_INI_ARRAY(&ah->iniAdditional,
  81                                         ar9331_1p1_xtal_40M);
  82         } else if (AR_SREV_9330_12(ah)) {
  83                 /* mac */
  84                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
  85                                 ar9331_1p2_mac_core);
  86                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
  87                                 ar9331_1p2_mac_postamble);
  88
  89                 /* bb */
  90                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
  91                                 ar9331_1p2_baseband_core);
  92                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
  93                                 ar9331_1p2_baseband_postamble);
  94
  95                 /* radio */
  96                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
  97                                 ar9331_1p2_radio_core);
  98
  99                 /* soc */
 100                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 101                                 ar9331_1p2_soc_preamble);
 102                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 103                                 ar9331_1p2_soc_postamble);
 104
 105                 /* rx/tx gain */
 106                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 107                                 ar9331_common_rx_gain_1p2);
 108                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 109                                 ar9331_modes_lowest_ob_db_tx_gain_1p2);
 110
 111                 /* Japan 2484 Mhz CCK */
 112                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 113                                ar9331_1p2_baseband_core_txfir_coeff_japan_2484);
 114
 115                 /* additional clock settings */
 116                 if (ah->is_clk_25mhz)
 117                         INIT_INI_ARRAY(&ah->iniAdditional,
 118                                         ar9331_1p2_xtal_25M);
 119                 else
 120                         INIT_INI_ARRAY(&ah->iniAdditional,
 121                                         ar9331_1p2_xtal_40M);
 122         } else if (AR_SREV_9340(ah)) {
 123                 /* mac */
 124                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 125                                 ar9340_1p0_mac_core);
 126                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 127                                 ar9340_1p0_mac_postamble);
 128
 129                 /* bb */
 130                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 131                                 ar9340_1p0_baseband_core);
 132                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 133                                 ar9340_1p0_baseband_postamble);
 134
 135                 /* radio */
 136                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 137                                 ar9340_1p0_radio_core);
 138                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 139                                 ar9340_1p0_radio_postamble);
 140
 141                 /* soc */
 142                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 143                                 ar9340_1p0_soc_preamble);
 144                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 145                                 ar9340_1p0_soc_postamble);
 146
 147                 /* rx/tx gain */
 148                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 149                                 ar9340Common_wo_xlna_rx_gain_table_1p0);
 150                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 151                                 ar9340Modes_high_ob_db_tx_gain_table_1p0);
 152
 153                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 154                                ar9340Modes_fast_clock_1p0);
 155                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 156                                ar9340_1p0_baseband_core_txfir_coeff_japan_2484);
 157                 INIT_INI_ARRAY(&ah->ini_dfs,
 158                                ar9340_1p0_baseband_postamble_dfs_channel);
 159
 160                 if (!ah->is_clk_25mhz)
 161                         INIT_INI_ARRAY(&ah->iniAdditional,
 162                                        ar9340_1p0_radio_core_40M);
 163         } else if (AR_SREV_9485_11_OR_LATER(ah)) {
 164                 /* mac */
 165                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 166                                 ar9485_1_1_mac_core);
 167                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 168                                 ar9485_1_1_mac_postamble);
 169
 170                 /* bb */
 171                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1);
 172                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 173                                 ar9485_1_1_baseband_core);
 174                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 175                                 ar9485_1_1_baseband_postamble);
 176
 177                 /* radio */
 178                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 179                                 ar9485_1_1_radio_core);
 180                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 181                                 ar9485_1_1_radio_postamble);
 182
 183                 /* soc */
 184                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 185                                 ar9485_1_1_soc_preamble);
 186
 187                 /* rx/tx gain */
 188                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 189                                 ar9485Common_wo_xlna_rx_gain_1_1);
 190                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 191                                 ar9485_modes_lowest_ob_db_tx_gain_1_1);
 192
 193                 /* Japan 2484 Mhz CCK */
 194                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 195                                ar9485_1_1_baseband_core_txfir_coeff_japan_2484);
 196
 197                 if (ah->config.no_pll_pwrsave) {
 198                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 199                                        ar9485_1_1_pcie_phy_clkreq_disable_L1);
 200                         INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 201                                        ar9485_1_1_pcie_phy_clkreq_disable_L1);
 202                 } else {
 203                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 204                                        ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
 205                         INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 206                                        ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
 207                 }
 208         } else if (AR_SREV_9462_21(ah)) {
 209                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 210                                ar9462_2p1_mac_core);
 211                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 212                                ar9462_2p1_mac_postamble);
 213                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 214                                ar9462_2p1_baseband_core);
 215                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 216                                ar9462_2p1_baseband_postamble);
 217                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 218                                ar9462_2p1_radio_core);
 219                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 220                                ar9462_2p1_radio_postamble);
 221                 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
 222                                ar9462_2p1_radio_postamble_sys2ant);
 223                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 224                                ar9462_2p1_soc_preamble);
 225                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 226                                ar9462_2p1_soc_postamble);
 227                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 228                                ar9462_2p1_common_rx_gain);
 229                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 230                                ar9462_2p1_modes_fast_clock);
 231                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 232                                ar9462_2p1_baseband_core_txfir_coeff_japan_2484);
 233                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 234                                ar9462_2p1_pciephy_clkreq_disable_L1);
 235                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 236                                ar9462_2p1_pciephy_clkreq_disable_L1);
 237         } else if (AR_SREV_9462_20(ah)) {
 238
 239                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core);
 240                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 241                                 ar9462_2p0_mac_postamble);
 242
 243                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 244                                 ar9462_2p0_baseband_core);
 245                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 246                                 ar9462_2p0_baseband_postamble);
 247
 248                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 249                                 ar9462_2p0_radio_core);
 250                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 251                                 ar9462_2p0_radio_postamble);
 252                 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
 253                                 ar9462_2p0_radio_postamble_sys2ant);
 254
 255                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 256                                 ar9462_2p0_soc_preamble);
 257                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 258                                 ar9462_2p0_soc_postamble);
 259
 260                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 261                                 ar9462_2p0_common_rx_gain);
 262
 263                 /* Awake -> Sleep Setting */
 264                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 265                                ar9462_2p0_pciephy_clkreq_disable_L1);
 266                 /* Sleep -> Awake Setting */
 267                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 268                                ar9462_2p0_pciephy_clkreq_disable_L1);
 269
 270                 /* Fast clock modal settings */
 271                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 272                                 ar9462_2p0_modes_fast_clock);
 273
 274                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 275                                ar9462_2p0_baseband_core_txfir_coeff_japan_2484);
 276         } else if (AR_SREV_9550(ah)) {
 277                 /* mac */
 278                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 279                                 ar955x_1p0_mac_core);
 280                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 281                                 ar955x_1p0_mac_postamble);
 282
 283                 /* bb */
 284                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 285                                 ar955x_1p0_baseband_core);
 286                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 287                                 ar955x_1p0_baseband_postamble);
 288
 289                 /* radio */
 290                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 291                                 ar955x_1p0_radio_core);
 292                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 293                                 ar955x_1p0_radio_postamble);
 294
 295                 /* soc */
 296                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 297                                 ar955x_1p0_soc_preamble);
 298                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 299                                 ar955x_1p0_soc_postamble);
 300
 301                 /* rx/tx gain */
 302                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 303                         ar955x_1p0_common_wo_xlna_rx_gain_table);
 304                 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 305                         ar955x_1p0_common_wo_xlna_rx_gain_bounds);
 306                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 307                                 ar955x_1p0_modes_xpa_tx_gain_table);
 308
 309                 /* Fast clock modal settings */
 310                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 311                                 ar955x_1p0_modes_fast_clock);
 312         } else if (AR_SREV_9531(ah)) {
 313                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 314                                qca953x_1p0_mac_core);
 315                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 316                                qca953x_1p0_mac_postamble);
 317                 if (AR_SREV_9531_20(ah)) {
 318                         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 319                                        qca953x_2p0_baseband_core);
 320                         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 321                                        qca953x_2p0_baseband_postamble);
 322                 } else {
 323                         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 324                                        qca953x_1p0_baseband_core);
 325                         INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 326                                        qca953x_1p0_baseband_postamble);
 327                 }
 328                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 329                                qca953x_1p0_radio_core);
 330                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 331                                qca953x_1p0_radio_postamble);
 332                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 333                                qca953x_1p0_soc_preamble);
 334                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 335                                qca953x_1p0_soc_postamble);
 336                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 337                                qca953x_1p0_common_wo_xlna_rx_gain_table);
 338                 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 339                                qca953x_1p0_common_wo_xlna_rx_gain_bounds);
 340                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 341                                qca953x_1p0_modes_no_xpa_tx_gain_table);
 342                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 343                                qca953x_1p0_modes_fast_clock);
 344         } else if (AR_SREV_9580(ah)) {
 345                 /* mac */
 346                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 347                                 ar9580_1p0_mac_core);
 348                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 349                                 ar9580_1p0_mac_postamble);
 350
 351                 /* bb */
 352                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 353                                 ar9580_1p0_baseband_core);
 354                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 355                                 ar9580_1p0_baseband_postamble);
 356
 357                 /* radio */
 358                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 359                                 ar9580_1p0_radio_core);
 360                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 361                                 ar9580_1p0_radio_postamble);
 362
 363                 /* soc */
 364                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 365                                 ar9580_1p0_soc_preamble);
 366                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 367                                 ar9580_1p0_soc_postamble);
 368
 369                 /* rx/tx gain */
 370                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 371                                 ar9580_1p0_rx_gain_table);
 372                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 373                                 ar9580_1p0_low_ob_db_tx_gain_table);
 374
 375                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 376                                ar9580_1p0_modes_fast_clock);
 377                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 378                                ar9580_1p0_baseband_core_txfir_coeff_japan_2484);
 379                 INIT_INI_ARRAY(&ah->ini_dfs,
 380                                ar9580_1p0_baseband_postamble_dfs_channel);
 381         } else if (AR_SREV_9565_11_OR_LATER(ah)) {
 382                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 383                                ar9565_1p1_mac_core);
 384                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 385                                ar9565_1p1_mac_postamble);
 386
 387                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 388                                ar9565_1p1_baseband_core);
 389                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 390                                ar9565_1p1_baseband_postamble);
 391
 392                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 393                                ar9565_1p1_radio_core);
 394                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 395                                ar9565_1p1_radio_postamble);
 396
 397                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 398                                ar9565_1p1_soc_preamble);
 399                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 400                                ar9565_1p1_soc_postamble);
 401
 402                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 403                                ar9565_1p1_Common_rx_gain_table);
 404                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 405                                ar9565_1p1_Modes_lowest_ob_db_tx_gain_table);
 406
 407                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 408                                ar9565_1p1_pciephy_clkreq_disable_L1);
 409                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 410                                ar9565_1p1_pciephy_clkreq_disable_L1);
 411
 412                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 413                                 ar9565_1p1_modes_fast_clock);
 414                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 415                                ar9565_1p1_baseband_core_txfir_coeff_japan_2484);
 416         } else if (AR_SREV_9565(ah)) {
 417                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 418                                ar9565_1p0_mac_core);
 419                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 420                                ar9565_1p0_mac_postamble);
 421
 422                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 423                                ar9565_1p0_baseband_core);
 424                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 425                                ar9565_1p0_baseband_postamble);
 426
 427                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 428                                ar9565_1p0_radio_core);
 429                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 430                                ar9565_1p0_radio_postamble);
 431
 432                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 433                                ar9565_1p0_soc_preamble);
 434                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 435                                ar9565_1p0_soc_postamble);
 436
 437                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 438                                ar9565_1p0_Common_rx_gain_table);
 439                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 440                                ar9565_1p0_Modes_lowest_ob_db_tx_gain_table);
 441
 442                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 443                                ar9565_1p0_pciephy_clkreq_disable_L1);
 444                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 445                                ar9565_1p0_pciephy_clkreq_disable_L1);
 446
 447                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 448                                 ar9565_1p0_modes_fast_clock);
 449                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 450                                ar9565_1p0_baseband_core_txfir_coeff_japan_2484);
 451         } else {
 452                 /* mac */
 453                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 454                                 ar9300_2p2_mac_core);
 455                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 456                                 ar9300_2p2_mac_postamble);
 457
 458                 /* bb */
 459                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 460                                 ar9300_2p2_baseband_core);
 461                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 462                                 ar9300_2p2_baseband_postamble);
 463
 464                 /* radio */
 465                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 466                                 ar9300_2p2_radio_core);
 467                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 468                                 ar9300_2p2_radio_postamble);
 469
 470                 /* soc */
 471                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 472                                 ar9300_2p2_soc_preamble);
 473                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 474                                 ar9300_2p2_soc_postamble);
 475
 476                 /* rx/tx gain */
 477                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 478                                 ar9300Common_rx_gain_table_2p2);
 479                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 480                                 ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
 481
 482                 /* Load PCIE SERDES settings from INI */
 483
 484                 /* Awake Setting */
 485
 486                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 487                                 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
 488
 489                 /* Sleep Setting */
 490
 491                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 492                                 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
 493
 494                 /* Fast clock modal settings */
 495                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 496                                ar9300Modes_fast_clock_2p2);
 497                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 498                                ar9300_2p2_baseband_core_txfir_coeff_japan_2484);
 499                 INIT_INI_ARRAY(&ah->ini_dfs,
 500                                ar9300_2p2_baseband_postamble_dfs_channel);
 501         }
 502 }
 503
 504 static void ar9003_tx_gain_table_mode0(struct ath_hw *ah)
 505 {
 506         if (AR_SREV_9330_12(ah))
 507                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 508                         ar9331_modes_lowest_ob_db_tx_gain_1p2);
 509         else if (AR_SREV_9330_11(ah))
 510                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 511                         ar9331_modes_lowest_ob_db_tx_gain_1p1);
 512         else if (AR_SREV_9340(ah))
 513                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 514                         ar9340Modes_lowest_ob_db_tx_gain_table_1p0);
 515         else if (AR_SREV_9485_11_OR_LATER(ah))
 516                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 517                         ar9485_modes_lowest_ob_db_tx_gain_1_1);
 518         else if (AR_SREV_9550(ah))
 519                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 520                         ar955x_1p0_modes_xpa_tx_gain_table);
 521         else if (AR_SREV_9531(ah))
 522                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 523                         qca953x_1p0_modes_xpa_tx_gain_table);
 524         else if (AR_SREV_9580(ah))
 525                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 526                         ar9580_1p0_lowest_ob_db_tx_gain_table);
 527         else if (AR_SREV_9462_21(ah))
 528                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 529                         ar9462_2p1_modes_low_ob_db_tx_gain);
 530         else if (AR_SREV_9462_20(ah))
 531                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 532                         ar9462_2p0_modes_low_ob_db_tx_gain);
 533         else if (AR_SREV_9565_11(ah))
 534                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 535                                ar9565_1p1_modes_low_ob_db_tx_gain_table);
 536         else if (AR_SREV_9565(ah))
 537                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 538                                ar9565_1p0_modes_low_ob_db_tx_gain_table);
 539         else
 540                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 541                         ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
 542 }
 543
 544 static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)
 545 {
 546         if (AR_SREV_9330_12(ah))
 547                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 548                         ar9331_modes_high_ob_db_tx_gain_1p2);
 549         else if (AR_SREV_9330_11(ah))
 550                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 551                         ar9331_modes_high_ob_db_tx_gain_1p1);
 552         else if (AR_SREV_9340(ah))
 553                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 554                         ar9340Modes_high_ob_db_tx_gain_table_1p0);
 555         else if (AR_SREV_9485_11_OR_LATER(ah))
 556                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 557                         ar9485Modes_high_ob_db_tx_gain_1_1);
 558         else if (AR_SREV_9580(ah))
 559                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 560                         ar9580_1p0_high_ob_db_tx_gain_table);
 561         else if (AR_SREV_9550(ah))
 562                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 563                         ar955x_1p0_modes_no_xpa_tx_gain_table);
 564         else if (AR_SREV_9531(ah)) {
 565                 if (AR_SREV_9531_11(ah))
 566                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 567                                        qca953x_1p1_modes_no_xpa_tx_gain_table);
 568                 else
 569                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 570                                        qca953x_1p0_modes_no_xpa_tx_gain_table);
 571         } else if (AR_SREV_9462_21(ah))
 572                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 573                         ar9462_2p1_modes_high_ob_db_tx_gain);
 574         else if (AR_SREV_9462_20(ah))
 575                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 576                         ar9462_2p0_modes_high_ob_db_tx_gain);
 577         else if (AR_SREV_9565_11(ah))
 578                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 579                                ar9565_1p1_modes_high_ob_db_tx_gain_table);
 580         else if (AR_SREV_9565(ah))
 581                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 582                                ar9565_1p0_modes_high_ob_db_tx_gain_table);
 583         else
 584                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 585                         ar9300Modes_high_ob_db_tx_gain_table_2p2);
 586 }
 587
 588 static void ar9003_tx_gain_table_mode2(struct ath_hw *ah)
 589 {
 590         if (AR_SREV_9330_12(ah))
 591                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 592                         ar9331_modes_low_ob_db_tx_gain_1p2);
 593         else if (AR_SREV_9330_11(ah))
 594                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 595                         ar9331_modes_low_ob_db_tx_gain_1p1);
 596         else if (AR_SREV_9340(ah))
 597                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 598                         ar9340Modes_low_ob_db_tx_gain_table_1p0);
 599         else if (AR_SREV_9485_11_OR_LATER(ah))
 600                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 601                         ar9485Modes_low_ob_db_tx_gain_1_1);
 602         else if (AR_SREV_9580(ah))
 603                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 604                         ar9580_1p0_low_ob_db_tx_gain_table);
 605         else if (AR_SREV_9565_11(ah))
 606                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 607                                ar9565_1p1_modes_low_ob_db_tx_gain_table);
 608         else if (AR_SREV_9565(ah))
 609                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 610                                ar9565_1p0_modes_low_ob_db_tx_gain_table);
 611         else
 612                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 613                         ar9300Modes_low_ob_db_tx_gain_table_2p2);
 614 }
 615
 616 static void ar9003_tx_gain_table_mode3(struct ath_hw *ah)
 617 {
 618         if (AR_SREV_9330_12(ah))
 619                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 620                         ar9331_modes_high_power_tx_gain_1p2);
 621         else if (AR_SREV_9330_11(ah))
 622                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 623                         ar9331_modes_high_power_tx_gain_1p1);
 624         else if (AR_SREV_9340(ah))
 625                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 626                         ar9340Modes_high_power_tx_gain_table_1p0);
 627         else if (AR_SREV_9485_11_OR_LATER(ah))
 628                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 629                         ar9485Modes_high_power_tx_gain_1_1);
 630         else if (AR_SREV_9580(ah))
 631                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 632                         ar9580_1p0_high_power_tx_gain_table);
 633         else if (AR_SREV_9565_11(ah))
 634                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 635                                ar9565_1p1_modes_high_power_tx_gain_table);
 636         else if (AR_SREV_9565(ah))
 637                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 638                                ar9565_1p0_modes_high_power_tx_gain_table);
 639         else {
 640                 if (ah->config.tx_gain_buffalo)
 641                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 642                                        ar9300Modes_high_power_tx_gain_table_buffalo);
 643                 else
 644                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 645                                        ar9300Modes_high_power_tx_gain_table_2p2);
 646         }
 647 }
 648
 649 static void ar9003_tx_gain_table_mode4(struct ath_hw *ah)
 650 {
 651         if (AR_SREV_9340(ah))
 652                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 653                         ar9340Modes_mixed_ob_db_tx_gain_table_1p0);
 654         else if (AR_SREV_9580(ah))
 655                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 656                         ar9580_1p0_mixed_ob_db_tx_gain_table);
 657         else if (AR_SREV_9462_21(ah))
 658                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 659                        ar9462_2p1_modes_mix_ob_db_tx_gain);
 660         else if (AR_SREV_9462_20(ah))
 661                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 662                        ar9462_2p0_modes_mix_ob_db_tx_gain);
 663         else
 664                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 665                         ar9300Modes_mixed_ob_db_tx_gain_table_2p2);
 666 }
 667
 668 static void ar9003_tx_gain_table_mode5(struct ath_hw *ah)
 669 {
 670         if (AR_SREV_9485_11_OR_LATER(ah))
 671                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 672                         ar9485Modes_green_ob_db_tx_gain_1_1);
 673         else if (AR_SREV_9340(ah))
 674                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 675                         ar9340Modes_ub124_tx_gain_table_1p0);
 676         else if (AR_SREV_9580(ah))
 677                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 678                         ar9580_1p0_type5_tx_gain_table);
 679         else if (AR_SREV_9300_22(ah))
 680                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 681                         ar9300Modes_type5_tx_gain_table_2p2);
 682 }
 683
 684 static void ar9003_tx_gain_table_mode6(struct ath_hw *ah)
 685 {
 686         if (AR_SREV_9340(ah))
 687                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 688                         ar9340Modes_low_ob_db_and_spur_tx_gain_table_1p0);
 689         else if (AR_SREV_9485_11_OR_LATER(ah))
 690                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 691                         ar9485Modes_green_spur_ob_db_tx_gain_1_1);
 692         else if (AR_SREV_9580(ah))
 693                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 694                         ar9580_1p0_type6_tx_gain_table);
 695 }
 696
 697 static void ar9003_tx_gain_table_mode7(struct ath_hw *ah)
 698 {
 699         if (AR_SREV_9340(ah))
 700                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 701                                ar9340_cus227_tx_gain_table_1p0);
 702 }
 703
 704 typedef void (*ath_txgain_tab)(struct ath_hw *ah);
 705
 706 static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
 707 {
 708         static const ath_txgain_tab modes[] = {
 709                 ar9003_tx_gain_table_mode0,
 710                 ar9003_tx_gain_table_mode1,
 711                 ar9003_tx_gain_table_mode2,
 712                 ar9003_tx_gain_table_mode3,
 713                 ar9003_tx_gain_table_mode4,
 714                 ar9003_tx_gain_table_mode5,
 715                 ar9003_tx_gain_table_mode6,
 716                 ar9003_tx_gain_table_mode7,
 717         };
 718         int idx = ar9003_hw_get_tx_gain_idx(ah);
 719
 720         if (idx >= ARRAY_SIZE(modes))
 721                 idx = 0;
 722
 723         modes[idx](ah);
 724 }
 725
 726 static void ar9003_rx_gain_table_mode0(struct ath_hw *ah)
 727 {
 728         if (AR_SREV_9330_12(ah))
 729                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 730                                 ar9331_common_rx_gain_1p2);
 731         else if (AR_SREV_9330_11(ah))
 732                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 733                                 ar9331_common_rx_gain_1p1);
 734         else if (AR_SREV_9340(ah))
 735                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 736                                 ar9340Common_rx_gain_table_1p0);
 737         else if (AR_SREV_9485_11_OR_LATER(ah))
 738                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 739                                ar9485_common_rx_gain_1_1);
 740         else if (AR_SREV_9550(ah)) {
 741                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 742                                 ar955x_1p0_common_rx_gain_table);
 743                 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 744                                 ar955x_1p0_common_rx_gain_bounds);
 745         } else if (AR_SREV_9531(ah)) {
 746                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 747                                qca953x_1p0_common_rx_gain_table);
 748                 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 749                                qca953x_1p0_common_rx_gain_bounds);
 750         } else if (AR_SREV_9580(ah))
 751                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 752                                 ar9580_1p0_rx_gain_table);
 753         else if (AR_SREV_9462_21(ah))
 754                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 755                                 ar9462_2p1_common_rx_gain);
 756         else if (AR_SREV_9462_20(ah))
 757                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 758                                 ar9462_2p0_common_rx_gain);
 759         else if (AR_SREV_9565_11(ah))
 760                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 761                                ar9565_1p1_Common_rx_gain_table);
 762         else if (AR_SREV_9565(ah))
 763                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 764                                ar9565_1p0_Common_rx_gain_table);
 765         else
 766                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 767                                 ar9300Common_rx_gain_table_2p2);
 768 }
 769
 770 static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
 771 {
 772         if (AR_SREV_9330_12(ah))
 773                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 774                         ar9331_common_wo_xlna_rx_gain_1p2);
 775         else if (AR_SREV_9330_11(ah))
 776                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 777                         ar9331_common_wo_xlna_rx_gain_1p1);
 778         else if (AR_SREV_9340(ah))
 779                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 780                         ar9340Common_wo_xlna_rx_gain_table_1p0);
 781         else if (AR_SREV_9485_11_OR_LATER(ah))
 782                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 783                         ar9485Common_wo_xlna_rx_gain_1_1);
 784         else if (AR_SREV_9462_21(ah))
 785                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 786                         ar9462_2p1_common_wo_xlna_rx_gain);
 787         else if (AR_SREV_9462_20(ah))
 788                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 789                         ar9462_2p0_common_wo_xlna_rx_gain);
 790         else if (AR_SREV_9550(ah)) {
 791                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 792                         ar955x_1p0_common_wo_xlna_rx_gain_table);
 793                 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 794                         ar955x_1p0_common_wo_xlna_rx_gain_bounds);
 795         } else if (AR_SREV_9531(ah)) {
 796                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 797                                qca953x_1p0_common_wo_xlna_rx_gain_table);
 798                 INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
 799                                qca953x_1p0_common_wo_xlna_rx_gain_bounds);
 800         } else if (AR_SREV_9580(ah))
 801                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 802                         ar9580_1p0_wo_xlna_rx_gain_table);
 803         else if (AR_SREV_9565_11(ah))
 804                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 805                                ar9565_1p1_common_wo_xlna_rx_gain_table);
 806         else if (AR_SREV_9565(ah))
 807                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 808                                ar9565_1p0_common_wo_xlna_rx_gain_table);
 809         else
 810                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 811                         ar9300Common_wo_xlna_rx_gain_table_2p2);
 812 }
 813
 814 static void ar9003_rx_gain_table_mode2(struct ath_hw *ah)
 815 {
 816         if (AR_SREV_9462_21(ah)) {
 817                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 818                                ar9462_2p1_common_mixed_rx_gain);
 819                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core,
 820                                ar9462_2p1_baseband_core_mix_rxgain);
 821                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
 822                                ar9462_2p1_baseband_postamble_mix_rxgain);
 823                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
 824                                ar9462_2p1_baseband_postamble_5g_xlna);
 825         } else if (AR_SREV_9462_20(ah)) {
 826                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 827                                ar9462_2p0_common_mixed_rx_gain);
 828                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_core,
 829                                ar9462_2p0_baseband_core_mix_rxgain);
 830                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
 831                                ar9462_2p0_baseband_postamble_mix_rxgain);
 832                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
 833                                ar9462_2p0_baseband_postamble_5g_xlna);
 834         }
 835 }
 836
 837 static void ar9003_rx_gain_table_mode3(struct ath_hw *ah)
 838 {
 839         if (AR_SREV_9462_21(ah)) {
 840                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 841                                ar9462_2p1_common_5g_xlna_only_rxgain);
 842                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
 843                                ar9462_2p1_baseband_postamble_5g_xlna);
 844         } else if (AR_SREV_9462_20(ah)) {
 845                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 846                                ar9462_2p0_common_5g_xlna_only_rxgain);
 847                 INIT_INI_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
 848                                ar9462_2p0_baseband_postamble_5g_xlna);
 849         }
 850 }
 851
 852 static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
 853 {
 854         switch (ar9003_hw_get_rx_gain_idx(ah)) {
 855         case 0:
 856         default:
 857                 ar9003_rx_gain_table_mode0(ah);
 858                 break;
 859         case 1:
 860                 ar9003_rx_gain_table_mode1(ah);
 861                 break;
 862         case 2:
 863                 ar9003_rx_gain_table_mode2(ah);
 864                 break;
 865         case 3:
 866                 ar9003_rx_gain_table_mode3(ah);
 867                 break;
 868         }
 869 }
 870
 871 /* set gain table pointers according to values read from the eeprom */
 872 static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah)
 873 {
 874         ar9003_tx_gain_table_apply(ah);
 875         ar9003_rx_gain_table_apply(ah);
 876 }
 877
 878 /*
 879  * Helper for ASPM support.
 880  *
 881  * Disable PLL when in L0s as well as receiver clock when in L1.
 882  * This power saving option must be enabled through the SerDes.
 883  *
 884  * Programming the SerDes must go through the same 288 bit serial shift
 885  * register as the other analog registers.  Hence the 9 writes.
 886  */
 887 static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
 888                                          bool power_off)
 889 {
 890         unsigned int i;
 891         struct ar5416IniArray *array;
 892
 893         /*
 894          * Increase L1 Entry Latency. Some WB222 boards don't have
 895          * this change in eeprom/OTP.
 896          *
 897          */
 898         if (AR_SREV_9462(ah)) {
 899                 u32 val = ah->config.aspm_l1_fix;
 900                 if ((val & 0xff000000) == 0x17000000) {
 901                         val &= 0x00ffffff;
 902                         val |= 0x27000000;
 903                         REG_WRITE(ah, 0x570c, val);
 904                 }
 905         }
 906
 907         /* Nothing to do on restore for 11N */
 908         if (!power_off /* !restore */) {
 909                 /* set bit 19 to allow forcing of pcie core into L1 state */
 910                 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
 911                 REG_WRITE(ah, AR_WA, ah->WARegVal);
 912         }
 913
 914         /*
 915          * Configire PCIE after Ini init. SERDES values now come from ini file
 916          * This enables PCIe low power mode.
 917          */
 918         array = power_off ? &ah->iniPcieSerdes :
 919                 &ah->iniPcieSerdesLowPower;
 920
 921         for (i = 0; i < array->ia_rows; i++) {
 922                 REG_WRITE(ah,
 923                           INI_RA(array, i, 0),
 924                           INI_RA(array, i, 1));
 925         }
 926 }
 927
 928 static void ar9003_hw_init_hang_checks(struct ath_hw *ah)
 929 {
 930         /*
 931          * All chips support detection of BB/MAC hangs.
 932          */
 933         ah->config.hw_hang_checks |= HW_BB_WATCHDOG;
 934         ah->config.hw_hang_checks |= HW_MAC_HANG;
 935
 936         /*
 937          * This is not required for AR9580 1.0
 938          */
 939         if (AR_SREV_9300_22(ah))
 940                 ah->config.hw_hang_checks |= HW_PHYRESTART_CLC_WAR;
 941
 942         if (AR_SREV_9330(ah))
 943                 ah->bb_watchdog_timeout_ms = 85;
 944         else
 945                 ah->bb_watchdog_timeout_ms = 25;
 946 }
 947
 948 /*
 949  * MAC HW hang check
 950  * =================
 951  *
 952  * Signature: dcu_chain_state is 0x6 and dcu_complete_state is 0x1.
 953  *
 954  * The state of each DCU chain (mapped to TX queues) is available from these
 955  * DMA debug registers:
 956  *
 957  * Chain 0 state : Bits 4:0   of AR_DMADBG_4
 958  * Chain 1 state : Bits 9:5   of AR_DMADBG_4
 959  * Chain 2 state : Bits 14:10 of AR_DMADBG_4
 960  * Chain 3 state : Bits 19:15 of AR_DMADBG_4
 961  * Chain 4 state : Bits 24:20 of AR_DMADBG_4
 962  * Chain 5 state : Bits 29:25 of AR_DMADBG_4
 963  * Chain 6 state : Bits 4:0   of AR_DMADBG_5
 964  * Chain 7 state : Bits 9:5   of AR_DMADBG_5
 965  * Chain 8 state : Bits 14:10 of AR_DMADBG_5
 966  * Chain 9 state : Bits 19:15 of AR_DMADBG_5
 967  *
 968  * The DCU chain state "0x6" means "WAIT_FRDONE" - wait for TX frame to be done.
 969  */
 970
 971 #define NUM_STATUS_READS 50
 972
 973 static bool ath9k_hw_verify_hang(struct ath_hw *ah, unsigned int queue)
 974 {
 975         u32 dma_dbg_chain, dma_dbg_complete;
 976         u8 dcu_chain_state, dcu_complete_state;
 977         int i;
 978
 979         for (i = 0; i < NUM_STATUS_READS; i++) {
 980                 if (queue < 6)
 981                         dma_dbg_chain = REG_READ(ah, AR_DMADBG_4);
 982                 else
 983                         dma_dbg_chain = REG_READ(ah, AR_DMADBG_5);
 984
 985                 dma_dbg_complete = REG_READ(ah, AR_DMADBG_6);
 986
 987                 dcu_chain_state = (dma_dbg_chain >> (5 * queue)) & 0x1f;
 988                 dcu_complete_state = dma_dbg_complete & 0x3;
 989
 990                 if ((dcu_chain_state != 0x6) || (dcu_complete_state != 0x1))
 991                         return false;
 992         }
 993
 994         ath_dbg(ath9k_hw_common(ah), RESET,
 995                 "MAC Hang signature found for queue: %d\n", queue);
 996
 997         return true;
 998 }
 999
1000 static bool ar9003_hw_detect_mac_hang(struct ath_hw *ah)
1001 {
1002         u32 dma_dbg_4, dma_dbg_5, dma_dbg_6, chk_dbg;
1003         u8 dcu_chain_state, dcu_complete_state;
1004         bool dcu_wait_frdone = false;
1005         unsigned long chk_dcu = 0;
1006         unsigned int i = 0;
1007
1008         dma_dbg_4 = REG_READ(ah, AR_DMADBG_4);
1009         dma_dbg_5 = REG_READ(ah, AR_DMADBG_5);
1010         dma_dbg_6 = REG_READ(ah, AR_DMADBG_6);
1011
1012         dcu_complete_state = dma_dbg_6 & 0x3;
1013         if (dcu_complete_state != 0x1)
1014                 goto exit;
1015
1016         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1017                 if (i < 6)
1018                         chk_dbg = dma_dbg_4;
1019                 else
1020                         chk_dbg = dma_dbg_5;
1021
1022                 dcu_chain_state = (chk_dbg >> (5 * i)) & 0x1f;
1023                 if (dcu_chain_state == 0x6) {
1024                         dcu_wait_frdone = true;
1025                         chk_dcu |= BIT(i);
1026                 }
1027         }
1028
1029         if ((dcu_complete_state == 0x1) && dcu_wait_frdone) {
1030                 for_each_set_bit(i, &chk_dcu, ATH9K_NUM_TX_QUEUES) {
1031                         if (ath9k_hw_verify_hang(ah, i))
1032                                 return true;
1033                 }
1034         }
1035 exit:
1036         return false;
1037 }
1038
1039 /* Sets up the AR9003 hardware familiy callbacks */
1040 void ar9003_hw_attach_ops(struct ath_hw *ah)
1041 {
1042         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1043         struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1044
1045         ar9003_hw_init_mode_regs(ah);
1046         priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
1047         priv_ops->init_hang_checks = ar9003_hw_init_hang_checks;
1048         priv_ops->detect_mac_hang = ar9003_hw_detect_mac_hang;
1049
1050         ops->config_pci_powersave = ar9003_hw_configpcipowersave;
1051
1052         ar9003_hw_attach_phy_ops(ah);
1053         ar9003_hw_attach_calib_ops(ah);
1054         ar9003_hw_attach_mac_ops(ah);
1055 }