drivers/net/phy/vitesse.c

   1 /*
   2  * Driver for Vitesse PHYs
   3  *
   4  * Author: Kriston Carson
   5  *
   6  * Copyright (c) 2005, 2009, 2011 Freescale Semiconductor, Inc.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/mii.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/phy.h>
  20
  21 /* Vitesse Extended Page Magic Register(s) */
  22 #define MII_VSC82X4_EXT_PAGE_16E        0x10
  23 #define MII_VSC82X4_EXT_PAGE_17E        0x11
  24 #define MII_VSC82X4_EXT_PAGE_18E        0x12
  25
  26 /* Vitesse Extended Control Register 1 */
  27 #define MII_VSC8244_EXT_CON1           0x17
  28 #define MII_VSC8244_EXTCON1_INIT       0x0000
  29 #define MII_VSC8244_EXTCON1_TX_SKEW_MASK        0x0c00
  30 #define MII_VSC8244_EXTCON1_RX_SKEW_MASK        0x0300
  31 #define MII_VSC8244_EXTCON1_TX_SKEW     0x0800
  32 #define MII_VSC8244_EXTCON1_RX_SKEW     0x0200
  33
  34 /* Vitesse Interrupt Mask Register */
  35 #define MII_VSC8244_IMASK               0x19
  36 #define MII_VSC8244_IMASK_IEN           0x8000
  37 #define MII_VSC8244_IMASK_SPEED         0x4000
  38 #define MII_VSC8244_IMASK_LINK          0x2000
  39 #define MII_VSC8244_IMASK_DUPLEX        0x1000
  40 #define MII_VSC8244_IMASK_MASK          0xf000
  41
  42 #define MII_VSC8221_IMASK_MASK          0xa000
  43
  44 /* Vitesse Interrupt Status Register */
  45 #define MII_VSC8244_ISTAT               0x1a
  46 #define MII_VSC8244_ISTAT_STATUS        0x8000
  47 #define MII_VSC8244_ISTAT_SPEED         0x4000
  48 #define MII_VSC8244_ISTAT_LINK          0x2000
  49 #define MII_VSC8244_ISTAT_DUPLEX        0x1000
  50
  51 /* Vitesse Auxiliary Control/Status Register */
  52 #define MII_VSC8244_AUX_CONSTAT         0x1c
  53 #define MII_VSC8244_AUXCONSTAT_INIT     0x0000
  54 #define MII_VSC8244_AUXCONSTAT_DUPLEX   0x0020
  55 #define MII_VSC8244_AUXCONSTAT_SPEED    0x0018
  56 #define MII_VSC8244_AUXCONSTAT_GBIT     0x0010
  57 #define MII_VSC8244_AUXCONSTAT_100      0x0008
  58
  59 #define MII_VSC8221_AUXCONSTAT_INIT     0x0004 /* need to set this bit? */
  60 #define MII_VSC8221_AUXCONSTAT_RESERVED 0x0004
  61
  62 /* Vitesse Extended Page Access Register */
  63 #define MII_VSC82X4_EXT_PAGE_ACCESS     0x1f
  64
  65 /* Vitesse VSC8601 Extended PHY Control Register 1 */
  66 #define MII_VSC8601_EPHY_CTL            0x17
  67 #define MII_VSC8601_EPHY_CTL_RGMII_SKEW (1 << 8)
  68
  69 #define PHY_ID_VSC8234                  0x000fc620
  70 #define PHY_ID_VSC8244                  0x000fc6c0
  71 #define PHY_ID_VSC8514                  0x00070670
  72 #define PHY_ID_VSC8572                  0x000704d0
  73 #define PHY_ID_VSC8574                  0x000704a0
  74 #define PHY_ID_VSC8601                  0x00070420
  75 #define PHY_ID_VSC8662                  0x00070660
  76 #define PHY_ID_VSC8221                  0x000fc550
  77 #define PHY_ID_VSC8211                  0x000fc4b0
  78
  79 MODULE_DESCRIPTION("Vitesse PHY driver");
  80 MODULE_AUTHOR("Kriston Carson");
  81 MODULE_LICENSE("GPL");
  82
  83 static int vsc824x_add_skew(struct phy_device *phydev)
  84 {
  85         int err;
  86         int extcon;
  87
  88         extcon = phy_read(phydev, MII_VSC8244_EXT_CON1);
  89
  90         if (extcon < 0)
  91                 return extcon;
  92
  93         extcon &= ~(MII_VSC8244_EXTCON1_TX_SKEW_MASK |
  94                         MII_VSC8244_EXTCON1_RX_SKEW_MASK);
  95
  96         extcon |= (MII_VSC8244_EXTCON1_TX_SKEW |
  97                         MII_VSC8244_EXTCON1_RX_SKEW);
  98
  99         err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon);
 100
 101         return err;
 102 }
 103
 104 static int vsc824x_config_init(struct phy_device *phydev)
 105 {
 106         int err;
 107
 108         err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
 109                         MII_VSC8244_AUXCONSTAT_INIT);
 110         if (err < 0)
 111                 return err;
 112
 113         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 114                 err = vsc824x_add_skew(phydev);
 115
 116         return err;
 117 }
 118
 119 /* This adds a skew for both TX and RX clocks, so the skew should only be
 120  * applied to "rgmii-id" interfaces. It may not work as expected
 121  * on "rgmii-txid", "rgmii-rxid" or "rgmii" interfaces. */
 122 static int vsc8601_add_skew(struct phy_device *phydev)
 123 {
 124         int ret;
 125
 126         ret = phy_read(phydev, MII_VSC8601_EPHY_CTL);
 127         if (ret < 0)
 128                 return ret;
 129
 130         ret |= MII_VSC8601_EPHY_CTL_RGMII_SKEW;
 131         return phy_write(phydev, MII_VSC8601_EPHY_CTL, ret);
 132 }
 133
 134 static int vsc8601_config_init(struct phy_device *phydev)
 135 {
 136         int ret = 0;
 137
 138         if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 139                 ret = vsc8601_add_skew(phydev);
 140
 141         if (ret < 0)
 142                 return ret;
 143
 144         return genphy_config_init(phydev);
 145 }
 146
 147 static int vsc824x_ack_interrupt(struct phy_device *phydev)
 148 {
 149         int err = 0;
 150
 151         /* Don't bother to ACK the interrupts if interrupts
 152          * are disabled.  The 824x cannot clear the interrupts
 153          * if they are disabled.
 154          */
 155         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 156                 err = phy_read(phydev, MII_VSC8244_ISTAT);
 157
 158         return (err < 0) ? err : 0;
 159 }
 160
 161 static int vsc82xx_config_intr(struct phy_device *phydev)
 162 {
 163         int err;
 164
 165         if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
 166                 err = phy_write(phydev, MII_VSC8244_IMASK,
 167                         (phydev->drv->phy_id == PHY_ID_VSC8234 ||
 168                          phydev->drv->phy_id == PHY_ID_VSC8244 ||
 169                          phydev->drv->phy_id == PHY_ID_VSC8514 ||
 170                          phydev->drv->phy_id == PHY_ID_VSC8572 ||
 171                          phydev->drv->phy_id == PHY_ID_VSC8574 ||
 172                          phydev->drv->phy_id == PHY_ID_VSC8601) ?
 173                                 MII_VSC8244_IMASK_MASK :
 174                                 MII_VSC8221_IMASK_MASK);
 175         else {
 176                 /* The Vitesse PHY cannot clear the interrupt
 177                  * once it has disabled them, so we clear them first
 178                  */
 179                 err = phy_read(phydev, MII_VSC8244_ISTAT);
 180
 181                 if (err < 0)
 182                         return err;
 183
 184                 err = phy_write(phydev, MII_VSC8244_IMASK, 0);
 185         }
 186
 187         return err;
 188 }
 189
 190 static int vsc8221_config_init(struct phy_device *phydev)
 191 {
 192         int err;
 193
 194         err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,
 195                         MII_VSC8221_AUXCONSTAT_INIT);
 196         return err;
 197
 198         /* Perhaps we should set EXT_CON1 based on the interface?
 199          * Options are 802.3Z SerDes or SGMII
 200          */
 201 }
 202
 203 /* vsc82x4_config_autocross_enable - Enable auto MDI/MDI-X for forced links
 204  * @phydev: target phy_device struct
 205  *
 206  * Enable auto MDI/MDI-X when in 10/100 forced link speeds by writing
 207  * special values in the VSC8234/VSC8244 extended reserved registers
 208  */
 209 static int vsc82x4_config_autocross_enable(struct phy_device *phydev)
 210 {
 211         int ret;
 212
 213         if (phydev->autoneg == AUTONEG_ENABLE || phydev->speed > SPEED_100)
 214                 return 0;
 215
 216         /* map extended registers set 0x10 - 0x1e */
 217         ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x52b5);
 218         if (ret >= 0)
 219                 ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_18E, 0x0012);
 220         if (ret >= 0)
 221                 ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_17E, 0x2803);
 222         if (ret >= 0)
 223                 ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_16E, 0x87fa);
 224         /* map standard registers set 0x10 - 0x1e */
 225         if (ret >= 0)
 226                 ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x0000);
 227         else
 228                 phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x0000);
 229
 230         return ret;
 231 }
 232
 233 /* vsc82x4_config_aneg - restart auto-negotiation or write BMCR
 234  * @phydev: target phy_device struct
 235  *
 236  * Description: If auto-negotiation is enabled, we configure the
 237  *   advertising, and then restart auto-negotiation.  If it is not
 238  *   enabled, then we write the BMCR and also start the auto
 239  *   MDI/MDI-X feature
 240  */
 241 static int vsc82x4_config_aneg(struct phy_device *phydev)
 242 {
 243         int ret;
 244
 245         /* Enable auto MDI/MDI-X when in 10/100 forced link speeds by
 246          * writing special values in the VSC8234 extended reserved registers
 247          */
 248         if (phydev->autoneg != AUTONEG_ENABLE && phydev->speed <= SPEED_100) {
 249                 ret = genphy_setup_forced(phydev);
 250
 251                 if (ret < 0) /* error */
 252                         return ret;
 253
 254                 return vsc82x4_config_autocross_enable(phydev);
 255         }
 256
 257         return genphy_config_aneg(phydev);
 258 }
 259
 260 /* Vitesse 82xx */
 261 static struct phy_driver vsc82xx_driver[] = {
 262 {
 263         .phy_id         = PHY_ID_VSC8234,
 264         .name           = "Vitesse VSC8234",
 265         .phy_id_mask    = 0x000ffff0,
 266         .features       = PHY_GBIT_FEATURES,
 267         .flags          = PHY_HAS_INTERRUPT,
 268         .config_init    = &vsc824x_config_init,
 269         .config_aneg    = &vsc82x4_config_aneg,
 270         .read_status    = &genphy_read_status,
 271         .ack_interrupt  = &vsc824x_ack_interrupt,
 272         .config_intr    = &vsc82xx_config_intr,
 273 }, {
 274         .phy_id         = PHY_ID_VSC8244,
 275         .name           = "Vitesse VSC8244",
 276         .phy_id_mask    = 0x000fffc0,
 277         .features       = PHY_GBIT_FEATURES,
 278         .flags          = PHY_HAS_INTERRUPT,
 279         .config_init    = &vsc824x_config_init,
 280         .config_aneg    = &vsc82x4_config_aneg,
 281         .read_status    = &genphy_read_status,
 282         .ack_interrupt  = &vsc824x_ack_interrupt,
 283         .config_intr    = &vsc82xx_config_intr,
 284 }, {
 285         .phy_id         = PHY_ID_VSC8514,
 286         .name           = "Vitesse VSC8514",
 287         .phy_id_mask    = 0x000ffff0,
 288         .features       = PHY_GBIT_FEATURES,
 289         .flags          = PHY_HAS_INTERRUPT,
 290         .config_init    = &vsc824x_config_init,
 291         .config_aneg    = &vsc82x4_config_aneg,
 292         .read_status    = &genphy_read_status,
 293         .ack_interrupt  = &vsc824x_ack_interrupt,
 294         .config_intr    = &vsc82xx_config_intr,
 295 }, {
 296         .phy_id         = PHY_ID_VSC8572,
 297         .name           = "Vitesse VSC8572",
 298         .phy_id_mask    = 0x000ffff0,
 299         .features       = PHY_GBIT_FEATURES,
 300         .flags          = PHY_HAS_INTERRUPT,
 301         .config_init    = &vsc824x_config_init,
 302         .config_aneg    = &vsc82x4_config_aneg,
 303         .read_status    = &genphy_read_status,
 304         .ack_interrupt  = &vsc824x_ack_interrupt,
 305         .config_intr    = &vsc82xx_config_intr,
 306 }, {
 307         .phy_id         = PHY_ID_VSC8574,
 308         .name           = "Vitesse VSC8574",
 309         .phy_id_mask    = 0x000ffff0,
 310         .features       = PHY_GBIT_FEATURES,
 311         .flags          = PHY_HAS_INTERRUPT,
 312         .config_init    = &vsc824x_config_init,
 313         .config_aneg    = &vsc82x4_config_aneg,
 314         .read_status    = &genphy_read_status,
 315         .ack_interrupt  = &vsc824x_ack_interrupt,
 316         .config_intr    = &vsc82xx_config_intr,
 317 }, {
 318         .phy_id         = PHY_ID_VSC8601,
 319         .name           = "Vitesse VSC8601",
 320         .phy_id_mask    = 0x000ffff0,
 321         .features       = PHY_GBIT_FEATURES,
 322         .flags          = PHY_HAS_INTERRUPT,
 323         .config_init    = &vsc8601_config_init,
 324         .config_aneg    = &genphy_config_aneg,
 325         .read_status    = &genphy_read_status,
 326         .ack_interrupt  = &vsc824x_ack_interrupt,
 327         .config_intr    = &vsc82xx_config_intr,
 328 }, {
 329         .phy_id         = PHY_ID_VSC8662,
 330         .name           = "Vitesse VSC8662",
 331         .phy_id_mask    = 0x000ffff0,
 332         .features       = PHY_GBIT_FEATURES,
 333         .flags          = PHY_HAS_INTERRUPT,
 334         .config_init    = &vsc824x_config_init,
 335         .config_aneg    = &vsc82x4_config_aneg,
 336         .read_status    = &genphy_read_status,
 337         .ack_interrupt  = &vsc824x_ack_interrupt,
 338         .config_intr    = &vsc82xx_config_intr,
 339 }, {
 340         /* Vitesse 8221 */
 341         .phy_id         = PHY_ID_VSC8221,
 342         .phy_id_mask    = 0x000ffff0,
 343         .name           = "Vitesse VSC8221",
 344         .features       = PHY_GBIT_FEATURES,
 345         .flags          = PHY_HAS_INTERRUPT,
 346         .config_init    = &vsc8221_config_init,
 347         .config_aneg    = &genphy_config_aneg,
 348         .read_status    = &genphy_read_status,
 349         .ack_interrupt  = &vsc824x_ack_interrupt,
 350         .config_intr    = &vsc82xx_config_intr,
 351 }, {
 352         /* Vitesse 8211 */
 353         .phy_id         = PHY_ID_VSC8211,
 354         .phy_id_mask    = 0x000ffff0,
 355         .name           = "Vitesse VSC8211",
 356         .features       = PHY_GBIT_FEATURES,
 357         .flags          = PHY_HAS_INTERRUPT,
 358         .config_init    = &vsc8221_config_init,
 359         .config_aneg    = &genphy_config_aneg,
 360         .read_status    = &genphy_read_status,
 361         .ack_interrupt  = &vsc824x_ack_interrupt,
 362         .config_intr    = &vsc82xx_config_intr,
 363 } };
 364
 365 module_phy_driver(vsc82xx_driver);
 366
 367 static struct mdio_device_id __maybe_unused vitesse_tbl[] = {
 368         { PHY_ID_VSC8234, 0x000ffff0 },
 369         { PHY_ID_VSC8244, 0x000fffc0 },
 370         { PHY_ID_VSC8514, 0x000ffff0 },
 371         { PHY_ID_VSC8572, 0x000ffff0 },
 372         { PHY_ID_VSC8574, 0x000ffff0 },
 373         { PHY_ID_VSC8662, 0x000ffff0 },
 374         { PHY_ID_VSC8221, 0x000ffff0 },
 375         { PHY_ID_VSC8211, 0x000ffff0 },
 376         { }
 377 };
 378
 379 MODULE_DEVICE_TABLE(mdio, vitesse_tbl);