drivers/net/irda/w83977af_ir.c

   1 /*********************************************************************
   2  *
   3  * Filename:      w83977af_ir.c
   4  * Version:       1.0
   5  * Description:   FIR driver for the Winbond W83977AF Super I/O chip
   6  * Status:        Experimental.
   7  * Author:        Paul VanderSpek
   8  * Created at:    Wed Nov  4 11:46:16 1998
   9  * Modified at:   Fri Jan 28 12:10:59 2000
  10  * Modified by:   Dag Brattli <dagb@cs.uit.no>
  11  *
  12  *     Copyright (c) 1998-2000 Dag Brattli <dagb@cs.uit.no>
  13  *     Copyright (c) 1998-1999 Rebel.com
  14  *
  15  *     This program is free software; you can redistribute it and/or
  16  *     modify it under the terms of the GNU General Public License as
  17  *     published by the Free Software Foundation; either version 2 of
  18  *     the License, or (at your option) any later version.
  19  *
  20  *     Neither Paul VanderSpek nor Rebel.com admit liability nor provide
  21  *     warranty for any of this software. This material is provided "AS-IS"
  22  *     and at no charge.
  23  *
  24  *     If you find bugs in this file, its very likely that the same bug
  25  *     will also be in pc87108.c since the implementations are quite
  26  *     similar.
  27  *
  28  *     Notice that all functions that needs to access the chip in _any_
  29  *     way, must save BSR register on entry, and restore it on exit.
  30  *     It is _very_ important to follow this policy!
  31  *
  32  *         __u8 bank;
  33  *
  34  *         bank = inb( iobase+BSR);
  35  *
  36  *         do_your_stuff_here();
  37  *
  38  *         outb( bank, iobase+BSR);
  39  *
  40  ********************************************************************/
  41
  42 #include <linux/module.h>
  43 #include <linux/kernel.h>
  44 #include <linux/types.h>
  45 #include <linux/skbuff.h>
  46 #include <linux/netdevice.h>
  47 #include <linux/ioport.h>
  48 #include <linux/delay.h>
  49 #include <linux/init.h>
  50 #include <linux/interrupt.h>
  51 #include <linux/rtnetlink.h>
  52 #include <linux/dma-mapping.h>
  53 #include <linux/gfp.h>
  54
  55 #include <asm/io.h>
  56 #include <asm/dma.h>
  57 #include <asm/byteorder.h>
  58
  59 #include <net/irda/irda.h>
  60 #include <net/irda/wrapper.h>
  61 #include <net/irda/irda_device.h>
  62 #include "w83977af.h"
  63 #include "w83977af_ir.h"
  64
  65 #define CONFIG_USE_W977_PNP        /* Currently needed */
  66 #define PIO_MAX_SPEED       115200
  67
  68 static char *driver_name = "w83977af_ir";
  69 static int  qos_mtt_bits = 0x07;   /* 1 ms or more */
  70
  71 #define CHIP_IO_EXTENT 8
  72
  73 static unsigned int io[] = { 0x180, ~0, ~0, ~0 };
  74 #ifdef CONFIG_ARCH_NETWINDER             /* Adjust to NetWinder differences */
  75 static unsigned int irq[] = { 6, 0, 0, 0 };
  76 #else
  77 static unsigned int irq[] = { 11, 0, 0, 0 };
  78 #endif
  79 static unsigned int dma[] = { 1, 0, 0, 0 };
  80 static unsigned int efbase[] = { W977_EFIO_BASE, W977_EFIO2_BASE };
  81 static unsigned int efio = W977_EFIO_BASE;
  82
  83 static struct w83977af_ir *dev_self[] = { NULL, NULL, NULL, NULL};
  84
  85 /* Some prototypes */
  86 static int  w83977af_open(int i, unsigned int iobase, unsigned int irq,
  87                           unsigned int dma);
  88 static int  w83977af_close(struct w83977af_ir *self);
  89 static int  w83977af_probe(int iobase, int irq, int dma);
  90 static int  w83977af_dma_receive(struct w83977af_ir *self);
  91 static int  w83977af_dma_receive_complete(struct w83977af_ir *self);
  92 static netdev_tx_t  w83977af_hard_xmit(struct sk_buff *skb,
  93                                              struct net_device *dev);
  94 static int  w83977af_pio_write(int iobase, __u8 *buf, int len, int fifo_size);
  95 static void w83977af_dma_write(struct w83977af_ir *self, int iobase);
  96 static void w83977af_change_speed(struct w83977af_ir *self, __u32 speed);
  97 static int  w83977af_is_receiving(struct w83977af_ir *self);
  98
  99 static int  w83977af_net_open(struct net_device *dev);
 100 static int  w83977af_net_close(struct net_device *dev);
 101 static int  w83977af_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 102
 103 /*
 104  * Function w83977af_init ()
 105  *
 106  *    Initialize chip. Just try to find out how many chips we are dealing with
 107  *    and where they are
 108  */
 109 static int __init w83977af_init(void)
 110 {
 111         int i;
 112
 113         for (i=0; i < ARRAY_SIZE(dev_self) && io[i] < 2000; i++) {
 114                 if (w83977af_open(i, io[i], irq[i], dma[i]) == 0)
 115                         return 0;
 116         }
 117         return -ENODEV;
 118 }
 119
 120 /*
 121  * Function w83977af_cleanup ()
 122  *
 123  *    Close all configured chips
 124  *
 125  */
 126 static void __exit w83977af_cleanup(void)
 127 {
 128         int i;
 129
 130         for (i=0; i < ARRAY_SIZE(dev_self); i++) {
 131                 if (dev_self[i])
 132                         w83977af_close(dev_self[i]);
 133         }
 134 }
 135
 136 static const struct net_device_ops w83977_netdev_ops = {
 137         .ndo_open       = w83977af_net_open,
 138         .ndo_stop       = w83977af_net_close,
 139         .ndo_start_xmit = w83977af_hard_xmit,
 140         .ndo_do_ioctl   = w83977af_net_ioctl,
 141 };
 142
 143 /*
 144  * Function w83977af_open (iobase, irq)
 145  *
 146  *    Open driver instance
 147  *
 148  */
 149 static int w83977af_open(int i, unsigned int iobase, unsigned int irq,
 150                          unsigned int dma)
 151 {
 152         struct net_device *dev;
 153         struct w83977af_ir *self;
 154         int err;
 155
 156         /* Lock the port that we need */
 157         if (!request_region(iobase, CHIP_IO_EXTENT, driver_name)) {
 158                 pr_debug("%s(), can't get iobase of 0x%03x\n",
 159                          __func__ , iobase);
 160                 return -ENODEV;
 161         }
 162
 163         if (w83977af_probe(iobase, irq, dma) == -1) {
 164                 err = -1;
 165                 goto err_out;
 166         }
 167         /*
 168          *  Allocate new instance of the driver
 169          */
 170         dev = alloc_irdadev(sizeof(struct w83977af_ir));
 171         if (dev == NULL) {
 172                 printk( KERN_ERR "IrDA: Can't allocate memory for "
 173                         "IrDA control block!\n");
 174                 err = -ENOMEM;
 175                 goto err_out;
 176         }
 177
 178         self = netdev_priv(dev);
 179         spin_lock_init(&self->lock);
 180
 181
 182         /* Initialize IO */
 183         self->io.fir_base   = iobase;
 184         self->io.irq       = irq;
 185         self->io.fir_ext   = CHIP_IO_EXTENT;
 186         self->io.dma       = dma;
 187         self->io.fifo_size = 32;
 188
 189         /* Initialize QoS for this device */
 190         irda_init_max_qos_capabilies(&self->qos);
 191
 192         /* The only value we must override it the baudrate */
 193
 194         /* FIXME: The HP HDLS-1100 does not support 1152000! */
 195         self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
 196                 IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8);
 197
 198         /* The HP HDLS-1100 needs 1 ms according to the specs */
 199         self->qos.min_turn_time.bits = qos_mtt_bits;
 200         irda_qos_bits_to_value(&self->qos);
 201
 202         /* Max DMA buffer size needed = (data_size + 6) * (window_size) + 6; */
 203         self->rx_buff.truesize = 14384;
 204         self->tx_buff.truesize = 4000;
 205
 206         /* Allocate memory if needed */
 207         self->rx_buff.head =
 208                 dma_zalloc_coherent(NULL, self->rx_buff.truesize,
 209                                     &self->rx_buff_dma, GFP_KERNEL);
 210         if (self->rx_buff.head == NULL) {
 211                 err = -ENOMEM;
 212                 goto err_out1;
 213         }
 214
 215         self->tx_buff.head =
 216                 dma_zalloc_coherent(NULL, self->tx_buff.truesize,
 217                                     &self->tx_buff_dma, GFP_KERNEL);
 218         if (self->tx_buff.head == NULL) {
 219                 err = -ENOMEM;
 220                 goto err_out2;
 221         }
 222
 223         self->rx_buff.in_frame = FALSE;
 224         self->rx_buff.state = OUTSIDE_FRAME;
 225         self->tx_buff.data = self->tx_buff.head;
 226         self->rx_buff.data = self->rx_buff.head;
 227         self->netdev = dev;
 228
 229         dev->netdev_ops = &w83977_netdev_ops;
 230
 231         err = register_netdev(dev);
 232         if (err) {
 233                 net_err_ratelimited("%s(), register_netdevice() failed!\n",
 234                                     __func__);
 235                 goto err_out3;
 236         }
 237         net_info_ratelimited("IrDA: Registered device %s\n", dev->name);
 238
 239         /* Need to store self somewhere */
 240         dev_self[i] = self;
 241
 242         return 0;
 243 err_out3:
 244         dma_free_coherent(NULL, self->tx_buff.truesize,
 245                           self->tx_buff.head, self->tx_buff_dma);
 246 err_out2:
 247         dma_free_coherent(NULL, self->rx_buff.truesize,
 248                           self->rx_buff.head, self->rx_buff_dma);
 249 err_out1:
 250         free_netdev(dev);
 251 err_out:
 252         release_region(iobase, CHIP_IO_EXTENT);
 253         return err;
 254 }
 255
 256 /*
 257  * Function w83977af_close (self)
 258  *
 259  *    Close driver instance
 260  *
 261  */
 262 static int w83977af_close(struct w83977af_ir *self)
 263 {
 264         int iobase;
 265
 266         iobase = self->io.fir_base;
 267
 268 #ifdef CONFIG_USE_W977_PNP
 269         /* enter PnP configuration mode */
 270         w977_efm_enter(efio);
 271
 272         w977_select_device(W977_DEVICE_IR, efio);
 273
 274         /* Deactivate device */
 275         w977_write_reg(0x30, 0x00, efio);
 276
 277         w977_efm_exit(efio);
 278 #endif /* CONFIG_USE_W977_PNP */
 279
 280         /* Remove netdevice */
 281         unregister_netdev(self->netdev);
 282
 283         /* Release the PORT that this driver is using */
 284         pr_debug("%s(), Releasing Region %03x\n",
 285                  __func__ , self->io.fir_base);
 286         release_region(self->io.fir_base, self->io.fir_ext);
 287
 288         if (self->tx_buff.head)
 289                 dma_free_coherent(NULL, self->tx_buff.truesize,
 290                                   self->tx_buff.head, self->tx_buff_dma);
 291
 292         if (self->rx_buff.head)
 293                 dma_free_coherent(NULL, self->rx_buff.truesize,
 294                                   self->rx_buff.head, self->rx_buff_dma);
 295
 296         free_netdev(self->netdev);
 297
 298         return 0;
 299 }
 300
 301 static int w83977af_probe(int iobase, int irq, int dma)
 302 {
 303         int version;
 304         int i;
 305
 306         for (i=0; i < 2; i++) {
 307 #ifdef CONFIG_USE_W977_PNP
 308                 /* Enter PnP configuration mode */
 309                 w977_efm_enter(efbase[i]);
 310
 311                 w977_select_device(W977_DEVICE_IR, efbase[i]);
 312
 313                 /* Configure PnP port, IRQ, and DMA channel */
 314                 w977_write_reg(0x60, (iobase >> 8) & 0xff, efbase[i]);
 315                 w977_write_reg(0x61, (iobase) & 0xff, efbase[i]);
 316
 317                 w977_write_reg(0x70, irq, efbase[i]);
 318 #ifdef CONFIG_ARCH_NETWINDER
 319                 /* Netwinder uses 1 higher than Linux */
 320                 w977_write_reg(0x74, dma+1, efbase[i]);
 321 #else
 322                 w977_write_reg(0x74, dma, efbase[i]);
 323 #endif /* CONFIG_ARCH_NETWINDER */
 324                 w977_write_reg(0x75, 0x04, efbase[i]);  /* Disable Tx DMA */
 325
 326                 /* Set append hardware CRC, enable IR bank selection */
 327                 w977_write_reg(0xf0, APEDCRC|ENBNKSEL, efbase[i]);
 328
 329                 /* Activate device */
 330                 w977_write_reg(0x30, 0x01, efbase[i]);
 331
 332                 w977_efm_exit(efbase[i]);
 333 #endif /* CONFIG_USE_W977_PNP */
 334                 /* Disable Advanced mode */
 335                 switch_bank(iobase, SET2);
 336                 outb(iobase+2, 0x00);
 337
 338                 /* Turn on UART (global) interrupts */
 339                 switch_bank(iobase, SET0);
 340                 outb(HCR_EN_IRQ, iobase+HCR);
 341
 342                 /* Switch to advanced mode */
 343                 switch_bank(iobase, SET2);
 344                 outb(inb(iobase+ADCR1) | ADCR1_ADV_SL, iobase+ADCR1);
 345
 346                 /* Set default IR-mode */
 347                 switch_bank(iobase, SET0);
 348                 outb(HCR_SIR, iobase+HCR);
 349
 350                 /* Read the Advanced IR ID */
 351                 switch_bank(iobase, SET3);
 352                 version = inb(iobase+AUID);
 353
 354                 /* Should be 0x1? */
 355                 if (0x10 == (version & 0xf0)) {
 356                         efio = efbase[i];
 357
 358                         /* Set FIFO size to 32 */
 359                         switch_bank(iobase, SET2);
 360                         outb(ADCR2_RXFS32|ADCR2_TXFS32, iobase+ADCR2);
 361
 362                         /* Set FIFO threshold to TX17, RX16 */
 363                         switch_bank(iobase, SET0);
 364                         outb(UFR_RXTL|UFR_TXTL|UFR_TXF_RST|UFR_RXF_RST|
 365                              UFR_EN_FIFO,iobase+UFR);
 366
 367                         /* Receiver frame length */
 368                         switch_bank(iobase, SET4);
 369                         outb(2048 & 0xff, iobase+6);
 370                         outb((2048 >> 8) & 0x1f, iobase+7);
 371
 372                         /*
 373                          * Init HP HSDL-1100 transceiver.
 374                          *
 375                          * Set IRX_MSL since we have 2 * receive paths IRRX,
 376                          * and IRRXH. Clear IRSL0D since we want IRSL0 * to
 377                          * be a input pin used for IRRXH
 378                          *
 379                          *   IRRX  pin 37 connected to receiver
 380                          *   IRTX  pin 38 connected to transmitter
 381                          *   FIRRX pin 39 connected to receiver      (IRSL0)
 382                          *   CIRRX pin 40 connected to pin 37
 383                          */
 384                         switch_bank(iobase, SET7);
 385                         outb(0x40, iobase+7);
 386
 387                         net_info_ratelimited("W83977AF (IR) driver loaded. Version: 0x%02x\n",
 388                                              version);
 389
 390                         return 0;
 391                 } else {
 392                         /* Try next extented function register address */
 393                         pr_debug("%s(), Wrong chip version", __func__);
 394                 }
 395         }
 396         return -1;
 397 }
 398
 399 static void w83977af_change_speed(struct w83977af_ir *self, __u32 speed)
 400 {
 401         int ir_mode = HCR_SIR;
 402         int iobase;
 403         __u8 set;
 404
 405         iobase = self->io.fir_base;
 406
 407         /* Update accounting for new speed */
 408         self->io.speed = speed;
 409
 410         /* Save current bank */
 411         set = inb(iobase+SSR);
 412
 413         /* Disable interrupts */
 414         switch_bank(iobase, SET0);
 415         outb(0, iobase+ICR);
 416
 417         /* Select Set 2 */
 418         switch_bank(iobase, SET2);
 419         outb(0x00, iobase+ABHL);
 420
 421         switch (speed) {
 422         case 9600:   outb(0x0c, iobase+ABLL); break;
 423         case 19200:  outb(0x06, iobase+ABLL); break;
 424         case 38400:  outb(0x03, iobase+ABLL); break;
 425         case 57600:  outb(0x02, iobase+ABLL); break;
 426         case 115200: outb(0x01, iobase+ABLL); break;
 427         case 576000:
 428                 ir_mode = HCR_MIR_576;
 429                 pr_debug("%s(), handling baud of 576000\n", __func__);
 430                 break;
 431         case 1152000:
 432                 ir_mode = HCR_MIR_1152;
 433                 pr_debug("%s(), handling baud of 1152000\n", __func__);
 434                 break;
 435         case 4000000:
 436                 ir_mode = HCR_FIR;
 437                 pr_debug("%s(), handling baud of 4000000\n", __func__);
 438                 break;
 439         default:
 440                 ir_mode = HCR_FIR;
 441                 pr_debug("%s(), unknown baud rate of %d\n", __func__ , speed);
 442                 break;
 443         }
 444
 445         /* Set speed mode */
 446         switch_bank(iobase, SET0);
 447         outb(ir_mode, iobase+HCR);
 448
 449         /* set FIFO size to 32 */
 450         switch_bank(iobase, SET2);
 451         outb(ADCR2_RXFS32|ADCR2_TXFS32, iobase+ADCR2);
 452
 453         /* set FIFO threshold to TX17, RX16 */
 454         switch_bank(iobase, SET0);
 455         outb(0x00, iobase+UFR);        /* Reset */
 456         outb(UFR_EN_FIFO, iobase+UFR); /* First we must enable FIFO */
 457         outb(0xa7, iobase+UFR);
 458
 459         netif_wake_queue(self->netdev);
 460
 461         /* Enable some interrupts so we can receive frames */
 462         switch_bank(iobase, SET0);
 463         if (speed > PIO_MAX_SPEED) {
 464                 outb(ICR_EFSFI, iobase+ICR);
 465                 w83977af_dma_receive(self);
 466         } else
 467                 outb(ICR_ERBRI, iobase+ICR);
 468
 469         /* Restore SSR */
 470         outb(set, iobase+SSR);
 471 }
 472
 473 /*
 474  * Function w83977af_hard_xmit (skb, dev)
 475  *
 476  *    Sets up a DMA transfer to send the current frame.
 477  *
 478  */
 479 static netdev_tx_t w83977af_hard_xmit(struct sk_buff *skb,
 480                                             struct net_device *dev)
 481 {
 482         struct w83977af_ir *self;
 483         __s32 speed;
 484         int iobase;
 485         __u8 set;
 486         int mtt;
 487
 488         self = netdev_priv(dev);
 489
 490         iobase = self->io.fir_base;
 491
 492         pr_debug("%s(%ld), skb->len=%d\n", __func__ , jiffies,
 493                  (int)skb->len);
 494
 495         /* Lock transmit buffer */
 496         netif_stop_queue(dev);
 497
 498         /* Check if we need to change the speed */
 499         speed = irda_get_next_speed(skb);
 500         if ((speed != self->io.speed) && (speed != -1)) {
 501                 /* Check for empty frame */
 502                 if (!skb->len) {
 503                         w83977af_change_speed(self, speed);
 504                         dev_kfree_skb(skb);
 505                         return NETDEV_TX_OK;
 506                 } else
 507                         self->new_speed = speed;
 508         }
 509
 510         /* Save current set */
 511         set = inb(iobase+SSR);
 512
 513         /* Decide if we should use PIO or DMA transfer */
 514         if (self->io.speed > PIO_MAX_SPEED) {
 515                 self->tx_buff.data = self->tx_buff.head;
 516                 skb_copy_from_linear_data(skb, self->tx_buff.data, skb->len);
 517                 self->tx_buff.len = skb->len;
 518
 519                 mtt = irda_get_mtt(skb);
 520                 pr_debug("%s(%ld), mtt=%d\n", __func__ , jiffies, mtt);
 521                         if (mtt > 1000)
 522                                 mdelay(mtt/1000);
 523                         else if (mtt)
 524                                 udelay(mtt);
 525
 526                         /* Enable DMA interrupt */
 527                         switch_bank(iobase, SET0);
 528                         outb(ICR_EDMAI, iobase+ICR);
 529                         w83977af_dma_write(self, iobase);
 530         } else {
 531                 self->tx_buff.data = self->tx_buff.head;
 532                 self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
 533                                                    self->tx_buff.truesize);
 534
 535                 /* Add interrupt on tx low level (will fire immediately) */
 536                 switch_bank(iobase, SET0);
 537                 outb(ICR_ETXTHI, iobase+ICR);
 538         }
 539         dev_kfree_skb(skb);
 540
 541         /* Restore set register */
 542         outb(set, iobase+SSR);
 543
 544         return NETDEV_TX_OK;
 545 }
 546
 547 /*
 548  * Function w83977af_dma_write (self, iobase)
 549  *
 550  *    Send frame using DMA
 551  *
 552  */
 553 static void w83977af_dma_write(struct w83977af_ir *self, int iobase)
 554 {
 555         __u8 set;
 556         pr_debug("%s(), len=%d\n", __func__ , self->tx_buff.len);
 557
 558         /* Save current set */
 559         set = inb(iobase+SSR);
 560
 561         /* Disable DMA */
 562         switch_bank(iobase, SET0);
 563         outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR);
 564
 565         /* Choose transmit DMA channel  */
 566         switch_bank(iobase, SET2);
 567         outb(ADCR1_D_CHSW|/*ADCR1_DMA_F|*/ADCR1_ADV_SL, iobase+ADCR1);
 568         irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
 569                        DMA_MODE_WRITE);
 570         self->io.direction = IO_XMIT;
 571
 572         /* Enable DMA */
 573         switch_bank(iobase, SET0);
 574         outb(inb(iobase+HCR) | HCR_EN_DMA | HCR_TX_WT, iobase+HCR);
 575
 576         /* Restore set register */
 577         outb(set, iobase+SSR);
 578 }
 579
 580 /*
 581  * Function w83977af_pio_write (iobase, buf, len, fifo_size)
 582  *
 583  *
 584  *
 585  */
 586 static int w83977af_pio_write(int iobase, __u8 *buf, int len, int fifo_size)
 587 {
 588         int actual = 0;
 589         __u8 set;
 590
 591         /* Save current bank */
 592         set = inb(iobase+SSR);
 593
 594         switch_bank(iobase, SET0);
 595         if (!(inb_p(iobase+USR) & USR_TSRE)) {
 596                 pr_debug("%s(), warning, FIFO not empty yet!\n", __func__);
 597
 598                 fifo_size -= 17;
 599                 pr_debug("%s(), %d bytes left in tx fifo\n",
 600                          __func__ , fifo_size);
 601         }
 602
 603         /* Fill FIFO with current frame */
 604         while ((fifo_size-- > 0) && (actual < len)) {
 605                 /* Transmit next byte */
 606                 outb(buf[actual++], iobase+TBR);
 607         }
 608
 609         pr_debug("%s(), fifo_size %d ; %d sent of %d\n",
 610                  __func__ , fifo_size, actual, len);
 611
 612         /* Restore bank */
 613         outb(set, iobase+SSR);
 614
 615         return actual;
 616 }
 617
 618 /*
 619  * Function w83977af_dma_xmit_complete (self)
 620  *
 621  *    The transfer of a frame in finished. So do the necessary things
 622  *
 623  *
 624  */
 625 static void w83977af_dma_xmit_complete(struct w83977af_ir *self)
 626 {
 627         int iobase;
 628         __u8 set;
 629
 630         pr_debug("%s(%ld)\n", __func__ , jiffies);
 631
 632         IRDA_ASSERT(self != NULL, return;);
 633
 634         iobase = self->io.fir_base;
 635
 636         /* Save current set */
 637         set = inb(iobase+SSR);
 638
 639         /* Disable DMA */
 640         switch_bank(iobase, SET0);
 641         outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR);
 642
 643         /* Check for underrun! */
 644         if (inb(iobase+AUDR) & AUDR_UNDR) {
 645                 pr_debug("%s(), Transmit underrun!\n", __func__);
 646
 647                 self->netdev->stats.tx_errors++;
 648                 self->netdev->stats.tx_fifo_errors++;
 649
 650                 /* Clear bit, by writing 1 to it */
 651                 outb(AUDR_UNDR, iobase+AUDR);
 652         } else
 653                 self->netdev->stats.tx_packets++;
 654
 655
 656         if (self->new_speed) {
 657                 w83977af_change_speed(self, self->new_speed);
 658                 self->new_speed = 0;
 659         }
 660
 661         /* Unlock tx_buff and request another frame */
 662         /* Tell the network layer, that we want more frames */
 663         netif_wake_queue(self->netdev);
 664
 665         /* Restore set */
 666         outb(set, iobase+SSR);
 667 }
 668
 669 /*
 670  * Function w83977af_dma_receive (self)
 671  *
 672  *    Get ready for receiving a frame. The device will initiate a DMA
 673  *    if it starts to receive a frame.
 674  *
 675  */
 676 static int w83977af_dma_receive(struct w83977af_ir *self)
 677 {
 678         int iobase;
 679         __u8 set;
 680 #ifdef CONFIG_ARCH_NETWINDER
 681         unsigned long flags;
 682         __u8 hcr;
 683 #endif
 684         IRDA_ASSERT(self != NULL, return -1;);
 685
 686         pr_debug("%s\n", __func__);
 687
 688         iobase= self->io.fir_base;
 689
 690         /* Save current set */
 691         set = inb(iobase+SSR);
 692
 693         /* Disable DMA */
 694         switch_bank(iobase, SET0);
 695         outb(inb(iobase+HCR) & ~HCR_EN_DMA, iobase+HCR);
 696
 697         /* Choose DMA Rx, DMA Fairness, and Advanced mode */
 698         switch_bank(iobase, SET2);
 699         outb((inb(iobase+ADCR1) & ~ADCR1_D_CHSW)/*|ADCR1_DMA_F*/|ADCR1_ADV_SL,
 700              iobase+ADCR1);
 701
 702         self->io.direction = IO_RECV;
 703         self->rx_buff.data = self->rx_buff.head;
 704
 705 #ifdef CONFIG_ARCH_NETWINDER
 706         spin_lock_irqsave(&self->lock, flags);
 707
 708         disable_dma(self->io.dma);
 709         clear_dma_ff(self->io.dma);
 710         set_dma_mode(self->io.dma, DMA_MODE_READ);
 711         set_dma_addr(self->io.dma, self->rx_buff_dma);
 712         set_dma_count(self->io.dma, self->rx_buff.truesize);
 713 #else
 714         irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
 715                        DMA_MODE_READ);
 716 #endif
 717         /*
 718          * Reset Rx FIFO. This will also flush the ST_FIFO, it's very
 719          * important that we don't reset the Tx FIFO since it might not
 720          * be finished transmitting yet
 721          */
 722         switch_bank(iobase, SET0);
 723         outb(UFR_RXTL|UFR_TXTL|UFR_RXF_RST|UFR_EN_FIFO, iobase+UFR);
 724         self->st_fifo.len = self->st_fifo.tail = self->st_fifo.head = 0;
 725
 726         /* Enable DMA */
 727         switch_bank(iobase, SET0);
 728 #ifdef CONFIG_ARCH_NETWINDER
 729         hcr = inb(iobase+HCR);
 730         outb(hcr | HCR_EN_DMA, iobase+HCR);
 731         enable_dma(self->io.dma);
 732         spin_unlock_irqrestore(&self->lock, flags);
 733 #else
 734         outb(inb(iobase+HCR) | HCR_EN_DMA, iobase+HCR);
 735 #endif
 736         /* Restore set */
 737         outb(set, iobase+SSR);
 738
 739         return 0;
 740 }
 741
 742 /*
 743  * Function w83977af_receive_complete (self)
 744  *
 745  *    Finished with receiving a frame
 746  *
 747  */
 748 static int w83977af_dma_receive_complete(struct w83977af_ir *self)
 749 {
 750         struct sk_buff *skb;
 751         struct st_fifo *st_fifo;
 752         int len;
 753         int iobase;
 754         __u8 set;
 755         __u8 status;
 756
 757         pr_debug("%s\n", __func__);
 758
 759         st_fifo = &self->st_fifo;
 760
 761         iobase = self->io.fir_base;
 762
 763         /* Save current set */
 764         set = inb(iobase+SSR);
 765
 766         iobase = self->io.fir_base;
 767
 768         /* Read status FIFO */
 769         switch_bank(iobase, SET5);
 770         while ((status = inb(iobase+FS_FO)) & FS_FO_FSFDR) {
 771                 st_fifo->entries[st_fifo->tail].status = status;
 772
 773                 st_fifo->entries[st_fifo->tail].len  = inb(iobase+RFLFL);
 774                 st_fifo->entries[st_fifo->tail].len |= inb(iobase+RFLFH) << 8;
 775
 776                 st_fifo->tail++;
 777                 st_fifo->len++;
 778         }
 779
 780         while (st_fifo->len) {
 781                 /* Get first entry */
 782                 status = st_fifo->entries[st_fifo->head].status;
 783                 len    = st_fifo->entries[st_fifo->head].len;
 784                 st_fifo->head++;
 785                 st_fifo->len--;
 786
 787                 /* Check for errors */
 788                 if (status & FS_FO_ERR_MSK) {
 789                         if (status & FS_FO_LST_FR) {
 790                                 /* Add number of lost frames to stats */
 791                                 self->netdev->stats.rx_errors += len;
 792                         } else {
 793                                 /* Skip frame */
 794                                 self->netdev->stats.rx_errors++;
 795
 796                                 self->rx_buff.data += len;
 797
 798                                 if (status & FS_FO_MX_LEX)
 799                                         self->netdev->stats.rx_length_errors++;
 800
 801                                 if (status & FS_FO_PHY_ERR)
 802                                         self->netdev->stats.rx_frame_errors++;
 803
 804                                 if (status & FS_FO_CRC_ERR)
 805                                         self->netdev->stats.rx_crc_errors++;
 806                         }
 807                         /* The errors below can be reported in both cases */
 808                         if (status & FS_FO_RX_OV)
 809                                 self->netdev->stats.rx_fifo_errors++;
 810
 811                         if (status & FS_FO_FSF_OV)
 812                                 self->netdev->stats.rx_fifo_errors++;
 813
 814                 } else {
 815                         /* Check if we have transferred all data to memory */
 816                         switch_bank(iobase, SET0);
 817                         if (inb(iobase+USR) & USR_RDR) {
 818                                 udelay(80); /* Should be enough!? */
 819                         }
 820
 821                         skb = dev_alloc_skb(len+1);
 822                         if (skb == NULL)  {
 823                                 printk(KERN_INFO
 824                                        "%s(), memory squeeze, dropping frame.\n", __func__);
 825                                 /* Restore set register */
 826                                 outb(set, iobase+SSR);
 827
 828                                 return FALSE;
 829                         }
 830
 831                         /*  Align to 20 bytes */
 832                         skb_reserve(skb, 1);
 833
 834                         /* Copy frame without CRC */
 835                         if (self->io.speed < 4000000) {
 836                                 skb_put(skb, len-2);
 837                                 skb_copy_to_linear_data(skb,
 838                                                         self->rx_buff.data,
 839                                                         len - 2);
 840                         } else {
 841                                 skb_put(skb, len-4);
 842                                 skb_copy_to_linear_data(skb,
 843                                                         self->rx_buff.data,
 844                                                         len - 4);
 845                         }
 846
 847                         /* Move to next frame */
 848                         self->rx_buff.data += len;
 849                         self->netdev->stats.rx_packets++;
 850
 851                         skb->dev = self->netdev;
 852                         skb_reset_mac_header(skb);
 853                         skb->protocol = htons(ETH_P_IRDA);
 854                         netif_rx(skb);
 855                 }
 856         }
 857         /* Restore set register */
 858         outb(set, iobase+SSR);
 859
 860         return TRUE;
 861 }
 862
 863 /*
 864  * Function pc87108_pio_receive (self)
 865  *
 866  *    Receive all data in receiver FIFO
 867  *
 868  */
 869 static void w83977af_pio_receive(struct w83977af_ir *self)
 870 {
 871         __u8 byte = 0x00;
 872         int iobase;
 873
 874         IRDA_ASSERT(self != NULL, return;);
 875
 876         iobase = self->io.fir_base;
 877
 878         /*  Receive all characters in Rx FIFO */
 879         do {
 880                 byte = inb(iobase+RBR);
 881                 async_unwrap_char(self->netdev, &self->netdev->stats, &self->rx_buff,
 882                                   byte);
 883         } while (inb(iobase+USR) & USR_RDR); /* Data available */
 884 }
 885
 886 /*
 887  * Function w83977af_sir_interrupt (self, eir)
 888  *
 889  *    Handle SIR interrupt
 890  *
 891  */
 892 static __u8 w83977af_sir_interrupt(struct w83977af_ir *self, int isr)
 893 {
 894         int actual;
 895         __u8 new_icr = 0;
 896         __u8 set;
 897         int iobase;
 898
 899         pr_debug("%s(), isr=%#x\n", __func__ , isr);
 900
 901         iobase = self->io.fir_base;
 902         /* Transmit FIFO low on data */
 903         if (isr & ISR_TXTH_I) {
 904                 /* Write data left in transmit buffer */
 905                 actual = w83977af_pio_write(self->io.fir_base,
 906                                             self->tx_buff.data,
 907                                             self->tx_buff.len,
 908                                             self->io.fifo_size);
 909
 910                 self->tx_buff.data += actual;
 911                 self->tx_buff.len  -= actual;
 912
 913                 self->io.direction = IO_XMIT;
 914
 915                 /* Check if finished */
 916                 if (self->tx_buff.len > 0) {
 917                         new_icr |= ICR_ETXTHI;
 918                 } else {
 919                         set = inb(iobase+SSR);
 920                         switch_bank(iobase, SET0);
 921                         outb(AUDR_SFEND, iobase+AUDR);
 922                         outb(set, iobase+SSR);
 923
 924                         self->netdev->stats.tx_packets++;
 925
 926                         /* Feed me more packets */
 927                         netif_wake_queue(self->netdev);
 928                         new_icr |= ICR_ETBREI;
 929                 }
 930         }
 931         /* Check if transmission has completed */
 932         if (isr & ISR_TXEMP_I) {
 933                 /* Check if we need to change the speed? */
 934                 if (self->new_speed) {
 935                         pr_debug("%s(), Changing speed!\n", __func__);
 936                         w83977af_change_speed(self, self->new_speed);
 937                         self->new_speed = 0;
 938                 }
 939
 940                 /* Turn around and get ready to receive some data */
 941                 self->io.direction = IO_RECV;
 942                 new_icr |= ICR_ERBRI;
 943         }
 944
 945         /* Rx FIFO threshold or timeout */
 946         if (isr & ISR_RXTH_I) {
 947                 w83977af_pio_receive(self);
 948
 949                 /* Keep receiving */
 950                 new_icr |= ICR_ERBRI;
 951         }
 952         return new_icr;
 953 }
 954
 955 /*
 956  * Function pc87108_fir_interrupt (self, eir)
 957  *
 958  *    Handle MIR/FIR interrupt
 959  *
 960  */
 961 static __u8 w83977af_fir_interrupt(struct w83977af_ir *self, int isr)
 962 {
 963         __u8 new_icr = 0;
 964         __u8 set;
 965         int iobase;
 966
 967         iobase = self->io.fir_base;
 968         set = inb(iobase+SSR);
 969
 970         /* End of frame detected in FIFO */
 971         if (isr & (ISR_FEND_I|ISR_FSF_I)) {
 972                 if (w83977af_dma_receive_complete(self)) {
 973
 974                         /* Wait for next status FIFO interrupt */
 975                         new_icr |= ICR_EFSFI;
 976                 } else {
 977                         /* DMA not finished yet */
 978
 979                         /* Set timer value, resolution 1 ms */
 980                         switch_bank(iobase, SET4);
 981                         outb(0x01, iobase+TMRL); /* 1 ms */
 982                         outb(0x00, iobase+TMRH);
 983
 984                         /* Start timer */
 985                         outb(IR_MSL_EN_TMR, iobase+IR_MSL);
 986
 987                         new_icr |= ICR_ETMRI;
 988                 }
 989         }
 990         /* Timer finished */
 991         if (isr & ISR_TMR_I) {
 992                 /* Disable timer */
 993                 switch_bank(iobase, SET4);
 994                 outb(0, iobase+IR_MSL);
 995
 996                 /* Clear timer event */
 997                 /* switch_bank(iobase, SET0); */
 998 /*              outb(ASCR_CTE, iobase+ASCR); */
 999
1000                 /* Check if this is a TX timer interrupt */
1001                 if (self->io.direction == IO_XMIT) {
1002                         w83977af_dma_write(self, iobase);
1003
1004                         new_icr |= ICR_EDMAI;
1005                 } else {
1006                         /* Check if DMA has now finished */
1007                         w83977af_dma_receive_complete(self);
1008
1009                         new_icr |= ICR_EFSFI;
1010                 }
1011         }
1012         /* Finished with DMA */
1013         if (isr & ISR_DMA_I) {
1014                 w83977af_dma_xmit_complete(self);
1015
1016                 /* Check if there are more frames to be transmitted */
1017                 /* if (irda_device_txqueue_empty(self)) { */
1018
1019                 /* Prepare for receive
1020                  *
1021                  * ** Netwinder Tx DMA likes that we do this anyway **
1022                  */
1023                 w83977af_dma_receive(self);
1024                 new_icr = ICR_EFSFI;
1025                /* } */
1026         }
1027
1028         /* Restore set */
1029         outb(set, iobase+SSR);
1030
1031         return new_icr;
1032 }
1033
1034 /*
1035  * Function w83977af_interrupt (irq, dev_id, regs)
1036  *
1037  *    An interrupt from the chip has arrived. Time to do some work
1038  *
1039  */
1040 static irqreturn_t w83977af_interrupt(int irq, void *dev_id)
1041 {
1042         struct net_device *dev = dev_id;
1043         struct w83977af_ir *self;
1044         __u8 set, icr, isr;
1045         int iobase;
1046
1047         self = netdev_priv(dev);
1048
1049         iobase = self->io.fir_base;
1050
1051         /* Save current bank */
1052         set = inb(iobase+SSR);
1053         switch_bank(iobase, SET0);
1054
1055         icr = inb(iobase+ICR);
1056         isr = inb(iobase+ISR) & icr; /* Mask out the interesting ones */
1057
1058         outb(0, iobase+ICR); /* Disable interrupts */
1059
1060         if (isr) {
1061                 /* Dispatch interrupt handler for the current speed */
1062                 if (self->io.speed > PIO_MAX_SPEED )
1063                         icr = w83977af_fir_interrupt(self, isr);
1064                 else
1065                         icr = w83977af_sir_interrupt(self, isr);
1066         }
1067
1068         outb(icr, iobase+ICR);    /* Restore (new) interrupts */
1069         outb(set, iobase+SSR);    /* Restore bank register */
1070         return IRQ_RETVAL(isr);
1071 }
1072
1073 /*
1074  * Function w83977af_is_receiving (self)
1075  *
1076  *    Return TRUE is we are currently receiving a frame
1077  *
1078  */
1079 static int w83977af_is_receiving(struct w83977af_ir *self)
1080 {
1081         int status = FALSE;
1082         int iobase;
1083         __u8 set;
1084
1085         IRDA_ASSERT(self != NULL, return FALSE;);
1086
1087         if (self->io.speed > 115200) {
1088                 iobase = self->io.fir_base;
1089
1090                 /* Check if rx FIFO is not empty */
1091                 set = inb(iobase+SSR);
1092                 switch_bank(iobase, SET2);
1093                 if ((inb(iobase+RXFDTH) & 0x3f) != 0) {
1094                         /* We are receiving something */
1095                         status =  TRUE;
1096                 }
1097                 outb(set, iobase+SSR);
1098         } else
1099                 status = (self->rx_buff.state != OUTSIDE_FRAME);
1100
1101         return status;
1102 }
1103
1104 /*
1105  * Function w83977af_net_open (dev)
1106  *
1107  *    Start the device
1108  *
1109  */
1110 static int w83977af_net_open(struct net_device *dev)
1111 {
1112         struct w83977af_ir *self;
1113         int iobase;
1114         char hwname[32];
1115         __u8 set;
1116
1117
1118         IRDA_ASSERT(dev != NULL, return -1;);
1119         self = netdev_priv(dev);
1120
1121         IRDA_ASSERT(self != NULL, return 0;);
1122
1123         iobase = self->io.fir_base;
1124
1125         if (request_irq(self->io.irq, w83977af_interrupt, 0, dev->name,
1126                         (void *) dev)) {
1127                 return -EAGAIN;
1128         }
1129         /*
1130          * Always allocate the DMA channel after the IRQ,
1131          * and clean up on failure.
1132          */
1133         if (request_dma(self->io.dma, dev->name)) {
1134                 free_irq(self->io.irq, dev);
1135                 return -EAGAIN;
1136         }
1137
1138         /* Save current set */
1139         set = inb(iobase+SSR);
1140
1141         /* Enable some interrupts so we can receive frames again */
1142         switch_bank(iobase, SET0);
1143         if (self->io.speed > 115200) {
1144                 outb(ICR_EFSFI, iobase+ICR);
1145                 w83977af_dma_receive(self);
1146         } else
1147                 outb(ICR_ERBRI, iobase+ICR);
1148
1149         /* Restore bank register */
1150         outb(set, iobase+SSR);
1151
1152         /* Ready to play! */
1153         netif_start_queue(dev);
1154
1155         /* Give self a hardware name */
1156         sprintf(hwname, "w83977af @ 0x%03x", self->io.fir_base);
1157
1158         /*
1159          * Open new IrLAP layer instance, now that everything should be
1160          * initialized properly
1161          */
1162         self->irlap = irlap_open(dev, &self->qos, hwname);
1163
1164         return 0;
1165 }
1166
1167 /*
1168  * Function w83977af_net_close (dev)
1169  *
1170  *    Stop the device
1171  *
1172  */
1173 static int w83977af_net_close(struct net_device *dev)
1174 {
1175         struct w83977af_ir *self;
1176         int iobase;
1177         __u8 set;
1178
1179         IRDA_ASSERT(dev != NULL, return -1;);
1180
1181         self = netdev_priv(dev);
1182
1183         IRDA_ASSERT(self != NULL, return 0;);
1184
1185         iobase = self->io.fir_base;
1186
1187         /* Stop device */
1188         netif_stop_queue(dev);
1189
1190         /* Stop and remove instance of IrLAP */
1191         if (self->irlap)
1192                 irlap_close(self->irlap);
1193         self->irlap = NULL;
1194
1195         disable_dma(self->io.dma);
1196
1197         /* Save current set */
1198         set = inb(iobase+SSR);
1199
1200         /* Disable interrupts */
1201         switch_bank(iobase, SET0);
1202         outb(0, iobase+ICR);
1203
1204         free_irq(self->io.irq, dev);
1205         free_dma(self->io.dma);
1206
1207         /* Restore bank register */
1208         outb(set, iobase+SSR);
1209
1210         return 0;
1211 }
1212
1213 /*
1214  * Function w83977af_net_ioctl (dev, rq, cmd)
1215  *
1216  *    Process IOCTL commands for this device
1217  *
1218  */
1219 static int w83977af_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1220 {
1221         struct if_irda_req *irq = (struct if_irda_req *) rq;
1222         struct w83977af_ir *self;
1223         unsigned long flags;
1224         int ret = 0;
1225
1226         IRDA_ASSERT(dev != NULL, return -1;);
1227
1228         self = netdev_priv(dev);
1229
1230         IRDA_ASSERT(self != NULL, return -1;);
1231
1232         pr_debug("%s(), %s, (cmd=0x%X)\n", __func__ , dev->name, cmd);
1233
1234         spin_lock_irqsave(&self->lock, flags);
1235
1236         switch (cmd) {
1237         case SIOCSBANDWIDTH: /* Set bandwidth */
1238                 if (!capable(CAP_NET_ADMIN)) {
1239                         ret = -EPERM;
1240                         goto out;
1241                 }
1242                 w83977af_change_speed(self, irq->ifr_baudrate);
1243                 break;
1244         case SIOCSMEDIABUSY: /* Set media busy */
1245                 if (!capable(CAP_NET_ADMIN)) {
1246                         ret = -EPERM;
1247                         goto out;
1248                 }
1249                 irda_device_set_media_busy(self->netdev, TRUE);
1250                 break;
1251         case SIOCGRECEIVING: /* Check if we are receiving right now */
1252                 irq->ifr_receiving = w83977af_is_receiving(self);
1253                 break;
1254         default:
1255                 ret = -EOPNOTSUPP;
1256         }
1257 out:
1258         spin_unlock_irqrestore(&self->lock, flags);
1259         return ret;
1260 }
1261
1262 MODULE_AUTHOR("Dag Brattli <dagb@cs.uit.no>");
1263 MODULE_DESCRIPTION("Winbond W83977AF IrDA Device Driver");
1264 MODULE_LICENSE("GPL");
1265
1266
1267 module_param(qos_mtt_bits, int, 0);
1268 MODULE_PARM_DESC(qos_mtt_bits, "Mimimum Turn Time");
1269 module_param_array(io, int, NULL, 0);
1270 MODULE_PARM_DESC(io, "Base I/O addresses");
1271 module_param_array(irq, int, NULL, 0);
1272 MODULE_PARM_DESC(irq, "IRQ lines");
1273
1274 /*
1275  * Function init_module (void)
1276  *
1277  *
1278  *
1279  */
1280 module_init(w83977af_init);
1281
1282 /*
1283  * Function cleanup_module (void)
1284  *
1285  *
1286  *
1287  */
1288 module_exit(w83977af_cleanup);