drivers/net/ethernet/ti/cpsw_priv.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Texas Instruments Ethernet Switch Driver
   4  *
   5  * Copyright (C) 2019 Texas Instruments
   6  */
   7
   8 #include <linux/if_ether.h>
   9 #include <linux/if_vlan.h>
  10 #include <linux/module.h>
  11 #include <linux/netdevice.h>
  12 #include <linux/phy.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/skbuff.h>
  15
  16 #include "cpts.h"
  17 #include "cpsw_ale.h"
  18 #include "cpsw_priv.h"
  19 #include "cpsw_sl.h"
  20 #include "davinci_cpdma.h"
  21
  22 int cpsw_init_common(struct cpsw_common *cpsw, void __iomem *ss_regs,
  23                      int ale_ageout, phys_addr_t desc_mem_phys,
  24                      int descs_pool_size)
  25 {
  26         u32 slave_offset, sliver_offset, slave_size;
  27         struct cpsw_ale_params ale_params;
  28         struct cpsw_platform_data *data;
  29         struct cpdma_params dma_params;
  30         struct device *dev = cpsw->dev;
  31         void __iomem *cpts_regs;
  32         int ret = 0, i;
  33
  34         data = &cpsw->data;
  35         cpsw->rx_ch_num = 1;
  36         cpsw->tx_ch_num = 1;
  37
  38         cpsw->version = readl(&cpsw->regs->id_ver);
  39
  40         memset(&dma_params, 0, sizeof(dma_params));
  41         memset(&ale_params, 0, sizeof(ale_params));
  42
  43         switch (cpsw->version) {
  44         case CPSW_VERSION_1:
  45                 cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
  46                 cpts_regs            = ss_regs + CPSW1_CPTS_OFFSET;
  47                 cpsw->hw_stats       = ss_regs + CPSW1_HW_STATS;
  48                 dma_params.dmaregs   = ss_regs + CPSW1_CPDMA_OFFSET;
  49                 dma_params.txhdp     = ss_regs + CPSW1_STATERAM_OFFSET;
  50                 ale_params.ale_regs  = ss_regs + CPSW1_ALE_OFFSET;
  51                 slave_offset         = CPSW1_SLAVE_OFFSET;
  52                 slave_size           = CPSW1_SLAVE_SIZE;
  53                 sliver_offset        = CPSW1_SLIVER_OFFSET;
  54                 dma_params.desc_mem_phys = 0;
  55                 break;
  56         case CPSW_VERSION_2:
  57         case CPSW_VERSION_3:
  58         case CPSW_VERSION_4:
  59                 cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
  60                 cpts_regs            = ss_regs + CPSW2_CPTS_OFFSET;
  61                 cpsw->hw_stats       = ss_regs + CPSW2_HW_STATS;
  62                 dma_params.dmaregs   = ss_regs + CPSW2_CPDMA_OFFSET;
  63                 dma_params.txhdp     = ss_regs + CPSW2_STATERAM_OFFSET;
  64                 ale_params.ale_regs  = ss_regs + CPSW2_ALE_OFFSET;
  65                 slave_offset         = CPSW2_SLAVE_OFFSET;
  66                 slave_size           = CPSW2_SLAVE_SIZE;
  67                 sliver_offset        = CPSW2_SLIVER_OFFSET;
  68                 dma_params.desc_mem_phys = desc_mem_phys;
  69                 break;
  70         default:
  71                 dev_err(dev, "unknown version 0x%08x\n", cpsw->version);
  72                 return -ENODEV;
  73         }
  74
  75         for (i = 0; i < cpsw->data.slaves; i++) {
  76                 struct cpsw_slave *slave = &cpsw->slaves[i];
  77                 void __iomem            *regs = cpsw->regs;
  78
  79                 slave->slave_num = i;
  80                 slave->data     = &cpsw->data.slave_data[i];
  81                 slave->regs     = regs + slave_offset;
  82                 slave->port_vlan = slave->data->dual_emac_res_vlan;
  83                 slave->mac_sl = cpsw_sl_get("cpsw", dev, regs + sliver_offset);
  84                 if (IS_ERR(slave->mac_sl))
  85                         return PTR_ERR(slave->mac_sl);
  86
  87                 slave_offset  += slave_size;
  88                 sliver_offset += SLIVER_SIZE;
  89         }
  90
  91         ale_params.dev                  = dev;
  92         ale_params.ale_ageout           = ale_ageout;
  93         ale_params.ale_entries          = data->ale_entries;
  94         ale_params.ale_ports            = CPSW_ALE_PORTS_NUM;
  95
  96         cpsw->ale = cpsw_ale_create(&ale_params);
  97         if (!cpsw->ale) {
  98                 dev_err(dev, "error initializing ale engine\n");
  99                 return -ENODEV;
 100         }
 101
 102         dma_params.dev          = dev;
 103         dma_params.rxthresh     = dma_params.dmaregs + CPDMA_RXTHRESH;
 104         dma_params.rxfree       = dma_params.dmaregs + CPDMA_RXFREE;
 105         dma_params.rxhdp        = dma_params.txhdp + CPDMA_RXHDP;
 106         dma_params.txcp         = dma_params.txhdp + CPDMA_TXCP;
 107         dma_params.rxcp         = dma_params.txhdp + CPDMA_RXCP;
 108
 109         dma_params.num_chan             = data->channels;
 110         dma_params.has_soft_reset       = true;
 111         dma_params.min_packet_size      = CPSW_MIN_PACKET_SIZE;
 112         dma_params.desc_mem_size        = data->bd_ram_size;
 113         dma_params.desc_align           = 16;
 114         dma_params.has_ext_regs         = true;
 115         dma_params.desc_hw_addr         = dma_params.desc_mem_phys;
 116         dma_params.bus_freq_mhz         = cpsw->bus_freq_mhz;
 117         dma_params.descs_pool_size      = descs_pool_size;
 118
 119         cpsw->dma = cpdma_ctlr_create(&dma_params);
 120         if (!cpsw->dma) {
 121                 dev_err(dev, "error initializing dma\n");
 122                 return -ENOMEM;
 123         }
 124
 125         cpsw->cpts = cpts_create(cpsw->dev, cpts_regs, cpsw->dev->of_node);
 126         if (IS_ERR(cpsw->cpts)) {
 127                 ret = PTR_ERR(cpsw->cpts);
 128                 cpdma_ctlr_destroy(cpsw->dma);
 129         }
 130
 131         return ret;
 132 }