drivers/net/ethernet/ti/cpsw.c

   1 /*
   2  * Texas Instruments Ethernet Switch Driver
   3  *
   4  * Copyright (C) 2012 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/io.h>
  18 #include <linux/clk.h>
  19 #include <linux/timer.h>
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/irqreturn.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/net_tstamp.h>
  28 #include <linux/phy.h>
  29 #include <linux/workqueue.h>
  30 #include <linux/delay.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/gpio.h>
  33 #include <linux/of.h>
  34 #include <linux/of_mdio.h>
  35 #include <linux/of_net.h>
  36 #include <linux/of_device.h>
  37 #include <linux/if_vlan.h>
  38
  39 #include <linux/pinctrl/consumer.h>
  40
  41 #include "cpsw.h"
  42 #include "cpsw_ale.h"
  43 #include "cpts.h"
  44 #include "davinci_cpdma.h"
  45
  46 #define CPSW_DEBUG      (NETIF_MSG_HW           | NETIF_MSG_WOL         | \
  47                          NETIF_MSG_DRV          | NETIF_MSG_LINK        | \
  48                          NETIF_MSG_IFUP         | NETIF_MSG_INTR        | \
  49                          NETIF_MSG_PROBE        | NETIF_MSG_TIMER       | \
  50                          NETIF_MSG_IFDOWN       | NETIF_MSG_RX_ERR      | \
  51                          NETIF_MSG_TX_ERR       | NETIF_MSG_TX_DONE     | \
  52                          NETIF_MSG_PKTDATA      | NETIF_MSG_TX_QUEUED   | \
  53                          NETIF_MSG_RX_STATUS)
  54
  55 #define cpsw_info(priv, type, format, ...)              \
  56 do {                                                            \
  57         if (netif_msg_##type(priv) && net_ratelimit())          \
  58                 dev_info(priv->dev, format, ## __VA_ARGS__);    \
  59 } while (0)
  60
  61 #define cpsw_err(priv, type, format, ...)               \
  62 do {                                                            \
  63         if (netif_msg_##type(priv) && net_ratelimit())          \
  64                 dev_err(priv->dev, format, ## __VA_ARGS__);     \
  65 } while (0)
  66
  67 #define cpsw_dbg(priv, type, format, ...)               \
  68 do {                                                            \
  69         if (netif_msg_##type(priv) && net_ratelimit())          \
  70                 dev_dbg(priv->dev, format, ## __VA_ARGS__);     \
  71 } while (0)
  72
  73 #define cpsw_notice(priv, type, format, ...)            \
  74 do {                                                            \
  75         if (netif_msg_##type(priv) && net_ratelimit())          \
  76                 dev_notice(priv->dev, format, ## __VA_ARGS__);  \
  77 } while (0)
  78
  79 #define ALE_ALL_PORTS           0x7
  80
  81 #define CPSW_MAJOR_VERSION(reg)         (reg >> 8 & 0x7)
  82 #define CPSW_MINOR_VERSION(reg)         (reg & 0xff)
  83 #define CPSW_RTL_VERSION(reg)           ((reg >> 11) & 0x1f)
  84
  85 #define CPSW_VERSION_1          0x19010a
  86 #define CPSW_VERSION_2          0x19010c
  87 #define CPSW_VERSION_3          0x19010f
  88 #define CPSW_VERSION_4          0x190112
  89
  90 #define HOST_PORT_NUM           0
  91 #define SLIVER_SIZE             0x40
  92
  93 #define CPSW1_HOST_PORT_OFFSET  0x028
  94 #define CPSW1_SLAVE_OFFSET      0x050
  95 #define CPSW1_SLAVE_SIZE        0x040
  96 #define CPSW1_CPDMA_OFFSET      0x100
  97 #define CPSW1_STATERAM_OFFSET   0x200
  98 #define CPSW1_HW_STATS          0x400
  99 #define CPSW1_CPTS_OFFSET       0x500
 100 #define CPSW1_ALE_OFFSET        0x600
 101 #define CPSW1_SLIVER_OFFSET     0x700
 102
 103 #define CPSW2_HOST_PORT_OFFSET  0x108
 104 #define CPSW2_SLAVE_OFFSET      0x200
 105 #define CPSW2_SLAVE_SIZE        0x100
 106 #define CPSW2_CPDMA_OFFSET      0x800
 107 #define CPSW2_HW_STATS          0x900
 108 #define CPSW2_STATERAM_OFFSET   0xa00
 109 #define CPSW2_CPTS_OFFSET       0xc00
 110 #define CPSW2_ALE_OFFSET        0xd00
 111 #define CPSW2_SLIVER_OFFSET     0xd80
 112 #define CPSW2_BD_OFFSET         0x2000
 113
 114 #define CPDMA_RXTHRESH          0x0c0
 115 #define CPDMA_RXFREE            0x0e0
 116 #define CPDMA_TXHDP             0x00
 117 #define CPDMA_RXHDP             0x20
 118 #define CPDMA_TXCP              0x40
 119 #define CPDMA_RXCP              0x60
 120
 121 #define CPSW_POLL_WEIGHT        64
 122 #define CPSW_MIN_PACKET_SIZE    60
 123 #define CPSW_MAX_PACKET_SIZE    (1500 + 14 + 4 + 4)
 124
 125 #define RX_PRIORITY_MAPPING     0x76543210
 126 #define TX_PRIORITY_MAPPING     0x33221100
 127 #define CPDMA_TX_PRIORITY_MAP   0x76543210
 128
 129 #define CPSW_VLAN_AWARE         BIT(1)
 130 #define CPSW_ALE_VLAN_AWARE     1
 131
 132 #define CPSW_FIFO_NORMAL_MODE           (0 << 16)
 133 #define CPSW_FIFO_DUAL_MAC_MODE         (1 << 16)
 134 #define CPSW_FIFO_RATE_LIMIT_MODE       (2 << 16)
 135
 136 #define CPSW_INTPACEEN          (0x3f << 16)
 137 #define CPSW_INTPRESCALE_MASK   (0x7FF << 0)
 138 #define CPSW_CMINTMAX_CNT       63
 139 #define CPSW_CMINTMIN_CNT       2
 140 #define CPSW_CMINTMAX_INTVL     (1000 / CPSW_CMINTMIN_CNT)
 141 #define CPSW_CMINTMIN_INTVL     ((1000 / CPSW_CMINTMAX_CNT) + 1)
 142
 143 #define cpsw_slave_index(cpsw, priv)                            \
 144                 ((cpsw->data.dual_emac) ? priv->emac_port :     \
 145                 cpsw->data.active_slave)
 146 #define IRQ_NUM                 2
 147 #define CPSW_MAX_QUEUES         8
 148
 149 static int debug_level;
 150 module_param(debug_level, int, 0);
 151 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
 152
 153 static int ale_ageout = 10;
 154 module_param(ale_ageout, int, 0);
 155 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
 156
 157 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
 158 module_param(rx_packet_max, int, 0);
 159 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
 160
 161 struct cpsw_wr_regs {
 162         u32     id_ver;
 163         u32     soft_reset;
 164         u32     control;
 165         u32     int_control;
 166         u32     rx_thresh_en;
 167         u32     rx_en;
 168         u32     tx_en;
 169         u32     misc_en;
 170         u32     mem_allign1[8];
 171         u32     rx_thresh_stat;
 172         u32     rx_stat;
 173         u32     tx_stat;
 174         u32     misc_stat;
 175         u32     mem_allign2[8];
 176         u32     rx_imax;
 177         u32     tx_imax;
 178
 179 };
 180
 181 struct cpsw_ss_regs {
 182         u32     id_ver;
 183         u32     control;
 184         u32     soft_reset;
 185         u32     stat_port_en;
 186         u32     ptype;
 187         u32     soft_idle;
 188         u32     thru_rate;
 189         u32     gap_thresh;
 190         u32     tx_start_wds;
 191         u32     flow_control;
 192         u32     vlan_ltype;
 193         u32     ts_ltype;
 194         u32     dlr_ltype;
 195 };
 196
 197 /* CPSW_PORT_V1 */
 198 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
 199 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
 200 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
 201 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
 202 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
 203 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
 204 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
 205 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
 206
 207 /* CPSW_PORT_V2 */
 208 #define CPSW2_CONTROL       0x00 /* Control Register */
 209 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
 210 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
 211 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
 212 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
 213 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
 214 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
 215
 216 /* CPSW_PORT_V1 and V2 */
 217 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
 218 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
 219 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
 220
 221 /* CPSW_PORT_V2 only */
 222 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
 223 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
 224 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
 225 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
 226 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
 227 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
 228 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
 229 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
 230
 231 /* Bit definitions for the CPSW2_CONTROL register */
 232 #define PASS_PRI_TAGGED     (1<<24) /* Pass Priority Tagged */
 233 #define VLAN_LTYPE2_EN      (1<<21) /* VLAN LTYPE 2 enable */
 234 #define VLAN_LTYPE1_EN      (1<<20) /* VLAN LTYPE 1 enable */
 235 #define DSCP_PRI_EN         (1<<16) /* DSCP Priority Enable */
 236 #define TS_320              (1<<14) /* Time Sync Dest Port 320 enable */
 237 #define TS_319              (1<<13) /* Time Sync Dest Port 319 enable */
 238 #define TS_132              (1<<12) /* Time Sync Dest IP Addr 132 enable */
 239 #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
 240 #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
 241 #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
 242 #define TS_TTL_NONZERO      (1<<8)  /* Time Sync Time To Live Non-zero enable */
 243 #define TS_ANNEX_F_EN       (1<<6)  /* Time Sync Annex F enable */
 244 #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
 245 #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
 246 #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
 247 #define TS_TX_EN            (1<<1)  /* Time Sync Transmit Enable */
 248 #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
 249
 250 #define CTRL_V2_TS_BITS \
 251         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 252          TS_TTL_NONZERO  | TS_ANNEX_D_EN | TS_LTYPE1_EN)
 253
 254 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
 255 #define CTRL_V2_TX_TS_BITS  (CTRL_V2_TS_BITS | TS_TX_EN)
 256 #define CTRL_V2_RX_TS_BITS  (CTRL_V2_TS_BITS | TS_RX_EN)
 257
 258
 259 #define CTRL_V3_TS_BITS \
 260         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 261          TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
 262          TS_LTYPE1_EN)
 263
 264 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
 265 #define CTRL_V3_TX_TS_BITS  (CTRL_V3_TS_BITS | TS_TX_EN)
 266 #define CTRL_V3_RX_TS_BITS  (CTRL_V3_TS_BITS | TS_RX_EN)
 267
 268 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
 269 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
 270 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
 271 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
 272 #define TS_MSG_TYPE_EN_MASK      (0xffff)
 273
 274 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
 275 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
 276
 277 /* Bit definitions for the CPSW1_TS_CTL register */
 278 #define CPSW_V1_TS_RX_EN                BIT(0)
 279 #define CPSW_V1_TS_TX_EN                BIT(4)
 280 #define CPSW_V1_MSG_TYPE_OFS            16
 281
 282 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
 283 #define CPSW_V1_SEQ_ID_OFS_SHIFT        16
 284
 285 #define CPSW_MAX_BLKS_TX                15
 286 #define CPSW_MAX_BLKS_TX_SHIFT          4
 287 #define CPSW_MAX_BLKS_RX                5
 288
 289 struct cpsw_host_regs {
 290         u32     max_blks;
 291         u32     blk_cnt;
 292         u32     tx_in_ctl;
 293         u32     port_vlan;
 294         u32     tx_pri_map;
 295         u32     cpdma_tx_pri_map;
 296         u32     cpdma_rx_chan_map;
 297 };
 298
 299 struct cpsw_sliver_regs {
 300         u32     id_ver;
 301         u32     mac_control;
 302         u32     mac_status;
 303         u32     soft_reset;
 304         u32     rx_maxlen;
 305         u32     __reserved_0;
 306         u32     rx_pause;
 307         u32     tx_pause;
 308         u32     __reserved_1;
 309         u32     rx_pri_map;
 310 };
 311
 312 struct cpsw_hw_stats {
 313         u32     rxgoodframes;
 314         u32     rxbroadcastframes;
 315         u32     rxmulticastframes;
 316         u32     rxpauseframes;
 317         u32     rxcrcerrors;
 318         u32     rxaligncodeerrors;
 319         u32     rxoversizedframes;
 320         u32     rxjabberframes;
 321         u32     rxundersizedframes;
 322         u32     rxfragments;
 323         u32     __pad_0[2];
 324         u32     rxoctets;
 325         u32     txgoodframes;
 326         u32     txbroadcastframes;
 327         u32     txmulticastframes;
 328         u32     txpauseframes;
 329         u32     txdeferredframes;
 330         u32     txcollisionframes;
 331         u32     txsinglecollframes;
 332         u32     txmultcollframes;
 333         u32     txexcessivecollisions;
 334         u32     txlatecollisions;
 335         u32     txunderrun;
 336         u32     txcarriersenseerrors;
 337         u32     txoctets;
 338         u32     octetframes64;
 339         u32     octetframes65t127;
 340         u32     octetframes128t255;
 341         u32     octetframes256t511;
 342         u32     octetframes512t1023;
 343         u32     octetframes1024tup;
 344         u32     netoctets;
 345         u32     rxsofoverruns;
 346         u32     rxmofoverruns;
 347         u32     rxdmaoverruns;
 348 };
 349
 350 struct cpsw_slave {
 351         void __iomem                    *regs;
 352         struct cpsw_sliver_regs __iomem *sliver;
 353         int                             slave_num;
 354         u32                             mac_control;
 355         struct cpsw_slave_data          *data;
 356         struct phy_device               *phy;
 357         struct net_device               *ndev;
 358         u32                             port_vlan;
 359         u32                             open_stat;
 360 };
 361
 362 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
 363 {
 364         return __raw_readl(slave->regs + offset);
 365 }
 366
 367 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
 368 {
 369         __raw_writel(val, slave->regs + offset);
 370 }
 371
 372 struct cpsw_common {
 373         struct device                   *dev;
 374         struct cpsw_platform_data       data;
 375         struct napi_struct              napi_rx;
 376         struct napi_struct              napi_tx;
 377         struct cpsw_ss_regs __iomem     *regs;
 378         struct cpsw_wr_regs __iomem     *wr_regs;
 379         u8 __iomem                      *hw_stats;
 380         struct cpsw_host_regs __iomem   *host_port_regs;
 381         u32                             version;
 382         u32                             coal_intvl;
 383         u32                             bus_freq_mhz;
 384         int                             rx_packet_max;
 385         struct cpsw_slave               *slaves;
 386         struct cpdma_ctlr               *dma;
 387         struct cpdma_chan               *txch[CPSW_MAX_QUEUES];
 388         struct cpdma_chan               *rxch[CPSW_MAX_QUEUES];
 389         struct cpsw_ale                 *ale;
 390         bool                            quirk_irq;
 391         bool                            rx_irq_disabled;
 392         bool                            tx_irq_disabled;
 393         u32 irqs_table[IRQ_NUM];
 394         struct cpts                     *cpts;
 395         int                             rx_ch_num, tx_ch_num;
 396 };
 397
 398 struct cpsw_priv {
 399         struct net_device               *ndev;
 400         struct device                   *dev;
 401         u32                             msg_enable;
 402         u8                              mac_addr[ETH_ALEN];
 403         bool                            rx_pause;
 404         bool                            tx_pause;
 405         u32 emac_port;
 406         struct cpsw_common *cpsw;
 407 };
 408
 409 struct cpsw_stats {
 410         char stat_string[ETH_GSTRING_LEN];
 411         int type;
 412         int sizeof_stat;
 413         int stat_offset;
 414 };
 415
 416 enum {
 417         CPSW_STATS,
 418         CPDMA_RX_STATS,
 419         CPDMA_TX_STATS,
 420 };
 421
 422 #define CPSW_STAT(m)            CPSW_STATS,                             \
 423                                 sizeof(((struct cpsw_hw_stats *)0)->m), \
 424                                 offsetof(struct cpsw_hw_stats, m)
 425 #define CPDMA_RX_STAT(m)        CPDMA_RX_STATS,                            \
 426                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 427                                 offsetof(struct cpdma_chan_stats, m)
 428 #define CPDMA_TX_STAT(m)        CPDMA_TX_STATS,                            \
 429                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 430                                 offsetof(struct cpdma_chan_stats, m)
 431
 432 static const struct cpsw_stats cpsw_gstrings_stats[] = {
 433         { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
 434         { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
 435         { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
 436         { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
 437         { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
 438         { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
 439         { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
 440         { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
 441         { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
 442         { "Rx Fragments", CPSW_STAT(rxfragments) },
 443         { "Rx Octets", CPSW_STAT(rxoctets) },
 444         { "Good Tx Frames", CPSW_STAT(txgoodframes) },
 445         { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
 446         { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
 447         { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
 448         { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
 449         { "Collisions", CPSW_STAT(txcollisionframes) },
 450         { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
 451         { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
 452         { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
 453         { "Late Collisions", CPSW_STAT(txlatecollisions) },
 454         { "Tx Underrun", CPSW_STAT(txunderrun) },
 455         { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
 456         { "Tx Octets", CPSW_STAT(txoctets) },
 457         { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
 458         { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
 459         { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
 460         { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
 461         { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
 462         { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
 463         { "Net Octets", CPSW_STAT(netoctets) },
 464         { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
 465         { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
 466         { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
 467 };
 468
 469 static const struct cpsw_stats cpsw_gstrings_ch_stats[] = {
 470         { "head_enqueue", CPDMA_RX_STAT(head_enqueue) },
 471         { "tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
 472         { "pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
 473         { "misqueued", CPDMA_RX_STAT(misqueued) },
 474         { "desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
 475         { "pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
 476         { "runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
 477         { "runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
 478         { "empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
 479         { "busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
 480         { "good_dequeue", CPDMA_RX_STAT(good_dequeue) },
 481         { "requeue", CPDMA_RX_STAT(requeue) },
 482         { "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
 483 };
 484
 485 #define CPSW_STATS_COMMON_LEN   ARRAY_SIZE(cpsw_gstrings_stats)
 486 #define CPSW_STATS_CH_LEN       ARRAY_SIZE(cpsw_gstrings_ch_stats)
 487
 488 #define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw)
 489 #define napi_to_cpsw(napi)      container_of(napi, struct cpsw_common, napi)
 490 #define for_each_slave(priv, func, arg...)                              \
 491         do {                                                            \
 492                 struct cpsw_slave *slave;                               \
 493                 struct cpsw_common *cpsw = (priv)->cpsw;                \
 494                 int n;                                                  \
 495                 if (cpsw->data.dual_emac)                               \
 496                         (func)((cpsw)->slaves + priv->emac_port, ##arg);\
 497                 else                                                    \
 498                         for (n = cpsw->data.slaves,                     \
 499                                         slave = cpsw->slaves;           \
 500                                         n; n--)                         \
 501                                 (func)(slave++, ##arg);                 \
 502         } while (0)
 503
 504 #define cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb)         \
 505         do {                                                            \
 506                 if (!cpsw->data.dual_emac)                              \
 507                         break;                                          \
 508                 if (CPDMA_RX_SOURCE_PORT(status) == 1) {                \
 509                         ndev = cpsw->slaves[0].ndev;                    \
 510                         skb->dev = ndev;                                \
 511                 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) {         \
 512                         ndev = cpsw->slaves[1].ndev;                    \
 513                         skb->dev = ndev;                                \
 514                 }                                                       \
 515         } while (0)
 516 #define cpsw_add_mcast(cpsw, priv, addr)                                \
 517         do {                                                            \
 518                 if (cpsw->data.dual_emac) {                             \
 519                         struct cpsw_slave *slave = cpsw->slaves +       \
 520                                                 priv->emac_port;        \
 521                         int slave_port = cpsw_get_slave_port(           \
 522                                                 slave->slave_num);      \
 523                         cpsw_ale_add_mcast(cpsw->ale, addr,             \
 524                                 1 << slave_port | ALE_PORT_HOST,        \
 525                                 ALE_VLAN, slave->port_vlan, 0);         \
 526                 } else {                                                \
 527                         cpsw_ale_add_mcast(cpsw->ale, addr,             \
 528                                 ALE_ALL_PORTS,                          \
 529                                 0, 0, 0);                               \
 530                 }                                                       \
 531         } while (0)
 532
 533 static inline int cpsw_get_slave_port(u32 slave_num)
 534 {
 535         return slave_num + 1;
 536 }
 537
 538 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
 539 {
 540         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
 541         struct cpsw_ale *ale = cpsw->ale;
 542         int i;
 543
 544         if (cpsw->data.dual_emac) {
 545                 bool flag = false;
 546
 547                 /* Enabling promiscuous mode for one interface will be
 548                  * common for both the interface as the interface shares
 549                  * the same hardware resource.
 550                  */
 551                 for (i = 0; i < cpsw->data.slaves; i++)
 552                         if (cpsw->slaves[i].ndev->flags & IFF_PROMISC)
 553                                 flag = true;
 554
 555                 if (!enable && flag) {
 556                         enable = true;
 557                         dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
 558                 }
 559
 560                 if (enable) {
 561                         /* Enable Bypass */
 562                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
 563
 564                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 565                 } else {
 566                         /* Disable Bypass */
 567                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
 568                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 569                 }
 570         } else {
 571                 if (enable) {
 572                         unsigned long timeout = jiffies + HZ;
 573
 574                         /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
 575                         for (i = 0; i <= cpsw->data.slaves; i++) {
 576                                 cpsw_ale_control_set(ale, i,
 577                                                      ALE_PORT_NOLEARN, 1);
 578                                 cpsw_ale_control_set(ale, i,
 579                                                      ALE_PORT_NO_SA_UPDATE, 1);
 580                         }
 581
 582                         /* Clear All Untouched entries */
 583                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 584                         do {
 585                                 cpu_relax();
 586                                 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
 587                                         break;
 588                         } while (time_after(timeout, jiffies));
 589                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 590
 591                         /* Clear all mcast from ALE */
 592                         cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1);
 593
 594                         /* Flood All Unicast Packets to Host port */
 595                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
 596                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 597                 } else {
 598                         /* Don't Flood All Unicast Packets to Host port */
 599                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
 600
 601                         /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
 602                         for (i = 0; i <= cpsw->data.slaves; i++) {
 603                                 cpsw_ale_control_set(ale, i,
 604                                                      ALE_PORT_NOLEARN, 0);
 605                                 cpsw_ale_control_set(ale, i,
 606                                                      ALE_PORT_NO_SA_UPDATE, 0);
 607                         }
 608                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 609                 }
 610         }
 611 }
 612
 613 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
 614 {
 615         struct cpsw_priv *priv = netdev_priv(ndev);
 616         struct cpsw_common *cpsw = priv->cpsw;
 617         int vid;
 618
 619         if (cpsw->data.dual_emac)
 620                 vid = cpsw->slaves[priv->emac_port].port_vlan;
 621         else
 622                 vid = cpsw->data.default_vlan;
 623
 624         if (ndev->flags & IFF_PROMISC) {
 625                 /* Enable promiscuous mode */
 626                 cpsw_set_promiscious(ndev, true);
 627                 cpsw_ale_set_allmulti(cpsw->ale, IFF_ALLMULTI);
 628                 return;
 629         } else {
 630                 /* Disable promiscuous mode */
 631                 cpsw_set_promiscious(ndev, false);
 632         }
 633
 634         /* Restore allmulti on vlans if necessary */
 635         cpsw_ale_set_allmulti(cpsw->ale, priv->ndev->flags & IFF_ALLMULTI);
 636
 637         /* Clear all mcast from ALE */
 638         cpsw_ale_flush_multicast(cpsw->ale, ALE_ALL_PORTS, vid);
 639
 640         if (!netdev_mc_empty(ndev)) {
 641                 struct netdev_hw_addr *ha;
 642
 643                 /* program multicast address list into ALE register */
 644                 netdev_for_each_mc_addr(ha, ndev) {
 645                         cpsw_add_mcast(cpsw, priv, (u8 *)ha->addr);
 646                 }
 647         }
 648 }
 649
 650 static void cpsw_intr_enable(struct cpsw_common *cpsw)
 651 {
 652         __raw_writel(0xFF, &cpsw->wr_regs->tx_en);
 653         __raw_writel(0xFF, &cpsw->wr_regs->rx_en);
 654
 655         cpdma_ctlr_int_ctrl(cpsw->dma, true);
 656         return;
 657 }
 658
 659 static void cpsw_intr_disable(struct cpsw_common *cpsw)
 660 {
 661         __raw_writel(0, &cpsw->wr_regs->tx_en);
 662         __raw_writel(0, &cpsw->wr_regs->rx_en);
 663
 664         cpdma_ctlr_int_ctrl(cpsw->dma, false);
 665         return;
 666 }
 667
 668 static void cpsw_tx_handler(void *token, int len, int status)
 669 {
 670         struct netdev_queue     *txq;
 671         struct sk_buff          *skb = token;
 672         struct net_device       *ndev = skb->dev;
 673         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
 674
 675         /* Check whether the queue is stopped due to stalled tx dma, if the
 676          * queue is stopped then start the queue as we have free desc for tx
 677          */
 678         txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb));
 679         if (unlikely(netif_tx_queue_stopped(txq)))
 680                 netif_tx_wake_queue(txq);
 681
 682         cpts_tx_timestamp(cpsw->cpts, skb);
 683         ndev->stats.tx_packets++;
 684         ndev->stats.tx_bytes += len;
 685         dev_kfree_skb_any(skb);
 686 }
 687
 688 static void cpsw_rx_handler(void *token, int len, int status)
 689 {
 690         struct cpdma_chan       *ch;
 691         struct sk_buff          *skb = token;
 692         struct sk_buff          *new_skb;
 693         struct net_device       *ndev = skb->dev;
 694         int                     ret = 0;
 695         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
 696
 697         cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb);
 698
 699         if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
 700                 bool ndev_status = false;
 701                 struct cpsw_slave *slave = cpsw->slaves;
 702                 int n;
 703
 704                 if (cpsw->data.dual_emac) {
 705                         /* In dual emac mode check for all interfaces */
 706                         for (n = cpsw->data.slaves; n; n--, slave++)
 707                                 if (netif_running(slave->ndev))
 708                                         ndev_status = true;
 709                 }
 710
 711                 if (ndev_status && (status >= 0)) {
 712                         /* The packet received is for the interface which
 713                          * is already down and the other interface is up
 714                          * and running, instead of freeing which results
 715                          * in reducing of the number of rx descriptor in
 716                          * DMA engine, requeue skb back to cpdma.
 717                          */
 718                         new_skb = skb;
 719                         goto requeue;
 720                 }
 721
 722                 /* the interface is going down, skbs are purged */
 723                 dev_kfree_skb_any(skb);
 724                 return;
 725         }
 726
 727         new_skb = netdev_alloc_skb_ip_align(ndev, cpsw->rx_packet_max);
 728         if (new_skb) {
 729                 skb_copy_queue_mapping(new_skb, skb);
 730                 skb_put(skb, len);
 731                 cpts_rx_timestamp(cpsw->cpts, skb);
 732                 skb->protocol = eth_type_trans(skb, ndev);
 733                 netif_receive_skb(skb);
 734                 ndev->stats.rx_bytes += len;
 735                 ndev->stats.rx_packets++;
 736                 kmemleak_not_leak(new_skb);
 737         } else {
 738                 ndev->stats.rx_dropped++;
 739                 new_skb = skb;
 740         }
 741
 742 requeue:
 743         if (netif_dormant(ndev)) {
 744                 dev_kfree_skb_any(new_skb);
 745                 return;
 746         }
 747
 748         ch = cpsw->rxch[skb_get_queue_mapping(new_skb)];
 749         ret = cpdma_chan_submit(ch, new_skb, new_skb->data,
 750                                 skb_tailroom(new_skb), 0);
 751         if (WARN_ON(ret < 0))
 752                 dev_kfree_skb_any(new_skb);
 753 }
 754
 755 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
 756 {
 757         struct cpsw_common *cpsw = dev_id;
 758
 759         writel(0, &cpsw->wr_regs->tx_en);
 760         cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_TX);
 761
 762         if (cpsw->quirk_irq) {
 763                 disable_irq_nosync(cpsw->irqs_table[1]);
 764                 cpsw->tx_irq_disabled = true;
 765         }
 766
 767         napi_schedule(&cpsw->napi_tx);
 768         return IRQ_HANDLED;
 769 }
 770
 771 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
 772 {
 773         struct cpsw_common *cpsw = dev_id;
 774
 775         cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_RX);
 776         writel(0, &cpsw->wr_regs->rx_en);
 777
 778         if (cpsw->quirk_irq) {
 779                 disable_irq_nosync(cpsw->irqs_table[0]);
 780                 cpsw->rx_irq_disabled = true;
 781         }
 782
 783         napi_schedule(&cpsw->napi_rx);
 784         return IRQ_HANDLED;
 785 }
 786
 787 static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
 788 {
 789         u32                     ch_map;
 790         int                     num_tx, ch;
 791         struct cpsw_common      *cpsw = napi_to_cpsw(napi_tx);
 792
 793         /* process every unprocessed channel */
 794         ch_map = cpdma_ctrl_txchs_state(cpsw->dma);
 795         for (ch = 0, num_tx = 0; num_tx < budget; ch_map >>= 1, ch++) {
 796                 if (!ch_map) {
 797                         ch_map = cpdma_ctrl_txchs_state(cpsw->dma);
 798                         if (!ch_map)
 799                                 break;
 800
 801                         ch = 0;
 802                 }
 803
 804                 if (!(ch_map & 0x01))
 805                         continue;
 806
 807                 num_tx += cpdma_chan_process(cpsw->txch[ch], budget - num_tx);
 808         }
 809
 810         if (num_tx < budget) {
 811                 napi_complete(napi_tx);
 812                 writel(0xff, &cpsw->wr_regs->tx_en);
 813                 if (cpsw->quirk_irq && cpsw->tx_irq_disabled) {
 814                         cpsw->tx_irq_disabled = false;
 815                         enable_irq(cpsw->irqs_table[1]);
 816                 }
 817         }
 818
 819         return num_tx;
 820 }
 821
 822 static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
 823 {
 824         u32                     ch_map;
 825         int                     num_rx, ch;
 826         struct cpsw_common      *cpsw = napi_to_cpsw(napi_rx);
 827
 828         /* process every unprocessed channel */
 829         ch_map = cpdma_ctrl_rxchs_state(cpsw->dma);
 830         for (ch = 0, num_rx = 0; num_rx < budget; ch_map >>= 1, ch++) {
 831                 if (!ch_map) {
 832                         ch_map = cpdma_ctrl_rxchs_state(cpsw->dma);
 833                         if (!ch_map)
 834                                 break;
 835
 836                         ch = 0;
 837                 }
 838
 839                 if (!(ch_map & 0x01))
 840                         continue;
 841
 842                 num_rx += cpdma_chan_process(cpsw->rxch[ch], budget - num_rx);
 843         }
 844
 845         if (num_rx < budget) {
 846                 napi_complete(napi_rx);
 847                 writel(0xff, &cpsw->wr_regs->rx_en);
 848                 if (cpsw->quirk_irq && cpsw->rx_irq_disabled) {
 849                         cpsw->rx_irq_disabled = false;
 850                         enable_irq(cpsw->irqs_table[0]);
 851                 }
 852         }
 853
 854         return num_rx;
 855 }
 856
 857 static inline void soft_reset(const char *module, void __iomem *reg)
 858 {
 859         unsigned long timeout = jiffies + HZ;
 860
 861         __raw_writel(1, reg);
 862         do {
 863                 cpu_relax();
 864         } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
 865
 866         WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
 867 }
 868
 869 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
 870                          ((mac)[2] << 16) | ((mac)[3] << 24))
 871 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
 872
 873 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 874                                struct cpsw_priv *priv)
 875 {
 876         slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
 877         slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
 878 }
 879
 880 static void _cpsw_adjust_link(struct cpsw_slave *slave,
 881                               struct cpsw_priv *priv, bool *link)
 882 {
 883         struct phy_device       *phy = slave->phy;
 884         u32                     mac_control = 0;
 885         u32                     slave_port;
 886         struct cpsw_common *cpsw = priv->cpsw;
 887
 888         if (!phy)
 889                 return;
 890
 891         slave_port = cpsw_get_slave_port(slave->slave_num);
 892
 893         if (phy->link) {
 894                 mac_control = cpsw->data.mac_control;
 895
 896                 /* enable forwarding */
 897                 cpsw_ale_control_set(cpsw->ale, slave_port,
 898                                      ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
 899
 900                 if (phy->speed == 1000)
 901                         mac_control |= BIT(7);  /* GIGABITEN    */
 902                 if (phy->duplex)
 903                         mac_control |= BIT(0);  /* FULLDUPLEXEN */
 904
 905                 /* set speed_in input in case RMII mode is used in 100Mbps */
 906                 if (phy->speed == 100)
 907                         mac_control |= BIT(15);
 908                 /* in band mode only works in 10Mbps RGMII mode */
 909                 else if ((phy->speed == 10) && phy_interface_is_rgmii(phy))
 910                         mac_control |= BIT(18); /* In Band mode */
 911
 912                 if (priv->rx_pause)
 913                         mac_control |= BIT(3);
 914
 915                 if (priv->tx_pause)
 916                         mac_control |= BIT(4);
 917
 918                 *link = true;
 919         } else {
 920                 mac_control = 0;
 921                 /* disable forwarding */
 922                 cpsw_ale_control_set(cpsw->ale, slave_port,
 923                                      ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
 924         }
 925
 926         if (mac_control != slave->mac_control) {
 927                 phy_print_status(phy);
 928                 __raw_writel(mac_control, &slave->sliver->mac_control);
 929         }
 930
 931         slave->mac_control = mac_control;
 932 }
 933
 934 static void cpsw_adjust_link(struct net_device *ndev)
 935 {
 936         struct cpsw_priv        *priv = netdev_priv(ndev);
 937         bool                    link = false;
 938
 939         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
 940
 941         if (link) {
 942                 netif_carrier_on(ndev);
 943                 if (netif_running(ndev))
 944                         netif_tx_wake_all_queues(ndev);
 945         } else {
 946                 netif_carrier_off(ndev);
 947                 netif_tx_stop_all_queues(ndev);
 948         }
 949 }
 950
 951 static int cpsw_get_coalesce(struct net_device *ndev,
 952                                 struct ethtool_coalesce *coal)
 953 {
 954         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
 955
 956         coal->rx_coalesce_usecs = cpsw->coal_intvl;
 957         return 0;
 958 }
 959
 960 static int cpsw_set_coalesce(struct net_device *ndev,
 961                                 struct ethtool_coalesce *coal)
 962 {
 963         struct cpsw_priv *priv = netdev_priv(ndev);
 964         u32 int_ctrl;
 965         u32 num_interrupts = 0;
 966         u32 prescale = 0;
 967         u32 addnl_dvdr = 1;
 968         u32 coal_intvl = 0;
 969         struct cpsw_common *cpsw = priv->cpsw;
 970
 971         coal_intvl = coal->rx_coalesce_usecs;
 972
 973         int_ctrl =  readl(&cpsw->wr_regs->int_control);
 974         prescale = cpsw->bus_freq_mhz * 4;
 975
 976         if (!coal->rx_coalesce_usecs) {
 977                 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
 978                 goto update_return;
 979         }
 980
 981         if (coal_intvl < CPSW_CMINTMIN_INTVL)
 982                 coal_intvl = CPSW_CMINTMIN_INTVL;
 983
 984         if (coal_intvl > CPSW_CMINTMAX_INTVL) {
 985                 /* Interrupt pacer works with 4us Pulse, we can
 986                  * throttle further by dilating the 4us pulse.
 987                  */
 988                 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
 989
 990                 if (addnl_dvdr > 1) {
 991                         prescale *= addnl_dvdr;
 992                         if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
 993                                 coal_intvl = (CPSW_CMINTMAX_INTVL
 994                                                 * addnl_dvdr);
 995                 } else {
 996                         addnl_dvdr = 1;
 997                         coal_intvl = CPSW_CMINTMAX_INTVL;
 998                 }
 999         }
1000
1001         num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
1002         writel(num_interrupts, &cpsw->wr_regs->rx_imax);
1003         writel(num_interrupts, &cpsw->wr_regs->tx_imax);
1004
1005         int_ctrl |= CPSW_INTPACEEN;
1006         int_ctrl &= (~CPSW_INTPRESCALE_MASK);
1007         int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
1008
1009 update_return:
1010         writel(int_ctrl, &cpsw->wr_regs->int_control);
1011
1012         cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
1013         cpsw->coal_intvl = coal_intvl;
1014
1015         return 0;
1016 }
1017
1018 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
1019 {
1020         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1021
1022         switch (sset) {
1023         case ETH_SS_STATS:
1024                 return (CPSW_STATS_COMMON_LEN +
1025                        (cpsw->rx_ch_num + cpsw->tx_ch_num) *
1026                        CPSW_STATS_CH_LEN);
1027         default:
1028                 return -EOPNOTSUPP;
1029         }
1030 }
1031
1032 static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir)
1033 {
1034         int ch_stats_len;
1035         int line;
1036         int i;
1037
1038         ch_stats_len = CPSW_STATS_CH_LEN * ch_num;
1039         for (i = 0; i < ch_stats_len; i++) {
1040                 line = i % CPSW_STATS_CH_LEN;
1041                 snprintf(*p, ETH_GSTRING_LEN,
1042                          "%s DMA chan %d: %s", rx_dir ? "Rx" : "Tx",
1043                          i / CPSW_STATS_CH_LEN,
1044                          cpsw_gstrings_ch_stats[line].stat_string);
1045                 *p += ETH_GSTRING_LEN;
1046         }
1047 }
1048
1049 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1050 {
1051         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1052         u8 *p = data;
1053         int i;
1054
1055         switch (stringset) {
1056         case ETH_SS_STATS:
1057                 for (i = 0; i < CPSW_STATS_COMMON_LEN; i++) {
1058                         memcpy(p, cpsw_gstrings_stats[i].stat_string,
1059                                ETH_GSTRING_LEN);
1060                         p += ETH_GSTRING_LEN;
1061                 }
1062
1063                 cpsw_add_ch_strings(&p, cpsw->rx_ch_num, 1);
1064                 cpsw_add_ch_strings(&p, cpsw->tx_ch_num, 0);
1065                 break;
1066         }
1067 }
1068
1069 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1070                                     struct ethtool_stats *stats, u64 *data)
1071 {
1072         u8 *p;
1073         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1074         struct cpdma_chan_stats ch_stats;
1075         int i, l, ch;
1076
1077         /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1078         for (l = 0; l < CPSW_STATS_COMMON_LEN; l++)
1079                 data[l] = readl(cpsw->hw_stats +
1080                                 cpsw_gstrings_stats[l].stat_offset);
1081
1082         for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1083                 cpdma_chan_get_stats(cpsw->rxch[ch], &ch_stats);
1084                 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1085                         p = (u8 *)&ch_stats +
1086                                 cpsw_gstrings_ch_stats[i].stat_offset;
1087                         data[l] = *(u32 *)p;
1088                 }
1089         }
1090
1091         for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1092                 cpdma_chan_get_stats(cpsw->txch[ch], &ch_stats);
1093                 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1094                         p = (u8 *)&ch_stats +
1095                                 cpsw_gstrings_ch_stats[i].stat_offset;
1096                         data[l] = *(u32 *)p;
1097                 }
1098         }
1099 }
1100
1101 static int cpsw_common_res_usage_state(struct cpsw_common *cpsw)
1102 {
1103         u32 i;
1104         u32 usage_count = 0;
1105
1106         if (!cpsw->data.dual_emac)
1107                 return 0;
1108
1109         for (i = 0; i < cpsw->data.slaves; i++)
1110                 if (cpsw->slaves[i].open_stat)
1111                         usage_count++;
1112
1113         return usage_count;
1114 }
1115
1116 static inline int cpsw_tx_packet_submit(struct cpsw_priv *priv,
1117                                         struct sk_buff *skb,
1118                                         struct cpdma_chan *txch)
1119 {
1120         struct cpsw_common *cpsw = priv->cpsw;
1121
1122         return cpdma_chan_submit(txch, skb, skb->data, skb->len,
1123                                  priv->emac_port + cpsw->data.dual_emac);
1124 }
1125
1126 static inline void cpsw_add_dual_emac_def_ale_entries(
1127                 struct cpsw_priv *priv, struct cpsw_slave *slave,
1128                 u32 slave_port)
1129 {
1130         struct cpsw_common *cpsw = priv->cpsw;
1131         u32 port_mask = 1 << slave_port | ALE_PORT_HOST;
1132
1133         if (cpsw->version == CPSW_VERSION_1)
1134                 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1135         else
1136                 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1137         cpsw_ale_add_vlan(cpsw->ale, slave->port_vlan, port_mask,
1138                           port_mask, port_mask, 0);
1139         cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1140                            port_mask, ALE_VLAN, slave->port_vlan, 0);
1141         cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1142                            HOST_PORT_NUM, ALE_VLAN |
1143                            ALE_SECURE, slave->port_vlan);
1144         cpsw_ale_control_set(cpsw->ale, slave_port,
1145                              ALE_PORT_DROP_UNKNOWN_VLAN, 1);
1146 }
1147
1148 static void soft_reset_slave(struct cpsw_slave *slave)
1149 {
1150         char name[32];
1151
1152         snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1153         soft_reset(name, &slave->sliver->soft_reset);
1154 }
1155
1156 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1157 {
1158         u32 slave_port;
1159         struct cpsw_common *cpsw = priv->cpsw;
1160
1161         soft_reset_slave(slave);
1162
1163         /* setup priority mapping */
1164         __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1165
1166         switch (cpsw->version) {
1167         case CPSW_VERSION_1:
1168                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1169                 /* Increase RX FIFO size to 5 for supporting fullduplex
1170                  * flow control mode
1171                  */
1172                 slave_write(slave,
1173                             (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |
1174                             CPSW_MAX_BLKS_RX, CPSW1_MAX_BLKS);
1175                 break;
1176         case CPSW_VERSION_2:
1177         case CPSW_VERSION_3:
1178         case CPSW_VERSION_4:
1179                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1180                 /* Increase RX FIFO size to 5 for supporting fullduplex
1181                  * flow control mode
1182                  */
1183                 slave_write(slave,
1184                             (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |
1185                             CPSW_MAX_BLKS_RX, CPSW2_MAX_BLKS);
1186                 break;
1187         }
1188
1189         /* setup max packet size, and mac address */
1190         __raw_writel(cpsw->rx_packet_max, &slave->sliver->rx_maxlen);
1191         cpsw_set_slave_mac(slave, priv);
1192
1193         slave->mac_control = 0; /* no link yet */
1194
1195         slave_port = cpsw_get_slave_port(slave->slave_num);
1196
1197         if (cpsw->data.dual_emac)
1198                 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1199         else
1200                 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1201                                    1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1202
1203         if (slave->data->phy_node) {
1204                 slave->phy = of_phy_connect(priv->ndev, slave->data->phy_node,
1205                                  &cpsw_adjust_link, 0, slave->data->phy_if);
1206                 if (!slave->phy) {
1207                         dev_err(priv->dev, "phy \"%s\" not found on slave %d\n",
1208                                 slave->data->phy_node->full_name,
1209                                 slave->slave_num);
1210                         return;
1211                 }
1212         } else {
1213                 slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
1214                                  &cpsw_adjust_link, slave->data->phy_if);
1215                 if (IS_ERR(slave->phy)) {
1216                         dev_err(priv->dev,
1217                                 "phy \"%s\" not found on slave %d, err %ld\n",
1218                                 slave->data->phy_id, slave->slave_num,
1219                                 PTR_ERR(slave->phy));
1220                         slave->phy = NULL;
1221                         return;
1222                 }
1223         }
1224
1225         phy_attached_info(slave->phy);
1226
1227         phy_start(slave->phy);
1228
1229         /* Configure GMII_SEL register */
1230         cpsw_phy_sel(cpsw->dev, slave->phy->interface, slave->slave_num);
1231 }
1232
1233 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1234 {
1235         struct cpsw_common *cpsw = priv->cpsw;
1236         const int vlan = cpsw->data.default_vlan;
1237         u32 reg;
1238         int i;
1239         int unreg_mcast_mask;
1240
1241         reg = (cpsw->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1242                CPSW2_PORT_VLAN;
1243
1244         writel(vlan, &cpsw->host_port_regs->port_vlan);
1245
1246         for (i = 0; i < cpsw->data.slaves; i++)
1247                 slave_write(cpsw->slaves + i, vlan, reg);
1248
1249         if (priv->ndev->flags & IFF_ALLMULTI)
1250                 unreg_mcast_mask = ALE_ALL_PORTS;
1251         else
1252                 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1253
1254         cpsw_ale_add_vlan(cpsw->ale, vlan, ALE_ALL_PORTS,
1255                           ALE_ALL_PORTS, ALE_ALL_PORTS,
1256                           unreg_mcast_mask);
1257 }
1258
1259 static void cpsw_init_host_port(struct cpsw_priv *priv)
1260 {
1261         u32 fifo_mode;
1262         u32 control_reg;
1263         struct cpsw_common *cpsw = priv->cpsw;
1264
1265         /* soft reset the controller and initialize ale */
1266         soft_reset("cpsw", &cpsw->regs->soft_reset);
1267         cpsw_ale_start(cpsw->ale);
1268
1269         /* switch to vlan unaware mode */
1270         cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_VLAN_AWARE,
1271                              CPSW_ALE_VLAN_AWARE);
1272         control_reg = readl(&cpsw->regs->control);
1273         control_reg |= CPSW_VLAN_AWARE;
1274         writel(control_reg, &cpsw->regs->control);
1275         fifo_mode = (cpsw->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1276                      CPSW_FIFO_NORMAL_MODE;
1277         writel(fifo_mode, &cpsw->host_port_regs->tx_in_ctl);
1278
1279         /* setup host port priority mapping */
1280         __raw_writel(CPDMA_TX_PRIORITY_MAP,
1281                      &cpsw->host_port_regs->cpdma_tx_pri_map);
1282         __raw_writel(0, &cpsw->host_port_regs->cpdma_rx_chan_map);
1283
1284         cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM,
1285                              ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1286
1287         if (!cpsw->data.dual_emac) {
1288                 cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1289                                    0, 0);
1290                 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1291                                    ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2);
1292         }
1293 }
1294
1295 static int cpsw_fill_rx_channels(struct cpsw_priv *priv)
1296 {
1297         struct cpsw_common *cpsw = priv->cpsw;
1298         struct sk_buff *skb;
1299         int ch_buf_num;
1300         int ch, i, ret;
1301
1302         for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1303                 ch_buf_num = cpdma_chan_get_rx_buf_num(cpsw->rxch[ch]);
1304                 for (i = 0; i < ch_buf_num; i++) {
1305                         skb = __netdev_alloc_skb_ip_align(priv->ndev,
1306                                                           cpsw->rx_packet_max,
1307                                                           GFP_KERNEL);
1308                         if (!skb) {
1309                                 cpsw_err(priv, ifup, "cannot allocate skb\n");
1310                                 return -ENOMEM;
1311                         }
1312
1313                         skb_set_queue_mapping(skb, ch);
1314                         ret = cpdma_chan_submit(cpsw->rxch[ch], skb, skb->data,
1315                                                 skb_tailroom(skb), 0);
1316                         if (ret < 0) {
1317                                 cpsw_err(priv, ifup,
1318                                          "cannot submit skb to channel %d rx, error %d\n",
1319                                          ch, ret);
1320                                 kfree_skb(skb);
1321                                 return ret;
1322                         }
1323                         kmemleak_not_leak(skb);
1324                 }
1325
1326                 cpsw_info(priv, ifup, "ch %d rx, submitted %d descriptors\n",
1327                           ch, ch_buf_num);
1328         }
1329
1330         return 0;
1331 }
1332
1333 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_common *cpsw)
1334 {
1335         u32 slave_port;
1336
1337         slave_port = cpsw_get_slave_port(slave->slave_num);
1338
1339         if (!slave->phy)
1340                 return;
1341         phy_stop(slave->phy);
1342         phy_disconnect(slave->phy);
1343         slave->phy = NULL;
1344         cpsw_ale_control_set(cpsw->ale, slave_port,
1345                              ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1346         soft_reset_slave(slave);
1347 }
1348
1349 static int cpsw_ndo_open(struct net_device *ndev)
1350 {
1351         struct cpsw_priv *priv = netdev_priv(ndev);
1352         struct cpsw_common *cpsw = priv->cpsw;
1353         int ret;
1354         u32 reg;
1355
1356         ret = pm_runtime_get_sync(cpsw->dev);
1357         if (ret < 0) {
1358                 pm_runtime_put_noidle(cpsw->dev);
1359                 return ret;
1360         }
1361
1362         if (!cpsw_common_res_usage_state(cpsw))
1363                 cpsw_intr_disable(cpsw);
1364         netif_carrier_off(ndev);
1365
1366         /* Notify the stack of the actual queue counts. */
1367         ret = netif_set_real_num_tx_queues(ndev, cpsw->tx_ch_num);
1368         if (ret) {
1369                 dev_err(priv->dev, "cannot set real number of tx queues\n");
1370                 goto err_cleanup;
1371         }
1372
1373         ret = netif_set_real_num_rx_queues(ndev, cpsw->rx_ch_num);
1374         if (ret) {
1375                 dev_err(priv->dev, "cannot set real number of rx queues\n");
1376                 goto err_cleanup;
1377         }
1378
1379         reg = cpsw->version;
1380
1381         dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1382                  CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1383                  CPSW_RTL_VERSION(reg));
1384
1385         /* initialize host and slave ports */
1386         if (!cpsw_common_res_usage_state(cpsw))
1387                 cpsw_init_host_port(priv);
1388         for_each_slave(priv, cpsw_slave_open, priv);
1389
1390         /* Add default VLAN */
1391         if (!cpsw->data.dual_emac)
1392                 cpsw_add_default_vlan(priv);
1393         else
1394                 cpsw_ale_add_vlan(cpsw->ale, cpsw->data.default_vlan,
1395                                   ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0);
1396
1397         if (!cpsw_common_res_usage_state(cpsw)) {
1398                 /* setup tx dma to fixed prio and zero offset */
1399                 cpdma_control_set(cpsw->dma, CPDMA_TX_PRIO_FIXED, 1);
1400                 cpdma_control_set(cpsw->dma, CPDMA_RX_BUFFER_OFFSET, 0);
1401
1402                 /* disable priority elevation */
1403                 __raw_writel(0, &cpsw->regs->ptype);
1404
1405                 /* enable statistics collection only on all ports */
1406                 __raw_writel(0x7, &cpsw->regs->stat_port_en);
1407
1408                 /* Enable internal fifo flow control */
1409                 writel(0x7, &cpsw->regs->flow_control);
1410
1411                 napi_enable(&cpsw->napi_rx);
1412                 napi_enable(&cpsw->napi_tx);
1413
1414                 if (cpsw->tx_irq_disabled) {
1415                         cpsw->tx_irq_disabled = false;
1416                         enable_irq(cpsw->irqs_table[1]);
1417                 }
1418
1419                 if (cpsw->rx_irq_disabled) {
1420                         cpsw->rx_irq_disabled = false;
1421                         enable_irq(cpsw->irqs_table[0]);
1422                 }
1423
1424                 ret = cpsw_fill_rx_channels(priv);
1425                 if (ret < 0)
1426                         goto err_cleanup;
1427
1428                 if (cpts_register(cpsw->dev, cpsw->cpts,
1429                                   cpsw->data.cpts_clock_mult,
1430                                   cpsw->data.cpts_clock_shift))
1431                         dev_err(priv->dev, "error registering cpts device\n");
1432
1433         }
1434
1435         /* Enable Interrupt pacing if configured */
1436         if (cpsw->coal_intvl != 0) {
1437                 struct ethtool_coalesce coal;
1438
1439                 coal.rx_coalesce_usecs = cpsw->coal_intvl;
1440                 cpsw_set_coalesce(ndev, &coal);
1441         }
1442
1443         cpdma_ctlr_start(cpsw->dma);
1444         cpsw_intr_enable(cpsw);
1445
1446         if (cpsw->data.dual_emac)
1447                 cpsw->slaves[priv->emac_port].open_stat = true;
1448
1449         netif_tx_start_all_queues(ndev);
1450
1451         return 0;
1452
1453 err_cleanup:
1454         cpdma_ctlr_stop(cpsw->dma);
1455         for_each_slave(priv, cpsw_slave_stop, cpsw);
1456         pm_runtime_put_sync(cpsw->dev);
1457         netif_carrier_off(priv->ndev);
1458         return ret;
1459 }
1460
1461 static int cpsw_ndo_stop(struct net_device *ndev)
1462 {
1463         struct cpsw_priv *priv = netdev_priv(ndev);
1464         struct cpsw_common *cpsw = priv->cpsw;
1465
1466         cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1467         netif_tx_stop_all_queues(priv->ndev);
1468         netif_carrier_off(priv->ndev);
1469
1470         if (cpsw_common_res_usage_state(cpsw) <= 1) {
1471                 napi_disable(&cpsw->napi_rx);
1472                 napi_disable(&cpsw->napi_tx);
1473                 cpts_unregister(cpsw->cpts);
1474                 cpsw_intr_disable(cpsw);
1475                 cpdma_ctlr_stop(cpsw->dma);
1476                 cpsw_ale_stop(cpsw->ale);
1477         }
1478         for_each_slave(priv, cpsw_slave_stop, cpsw);
1479         pm_runtime_put_sync(cpsw->dev);
1480         if (cpsw->data.dual_emac)
1481                 cpsw->slaves[priv->emac_port].open_stat = false;
1482         return 0;
1483 }
1484
1485 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1486                                        struct net_device *ndev)
1487 {
1488         struct cpsw_priv *priv = netdev_priv(ndev);
1489         struct cpsw_common *cpsw = priv->cpsw;
1490         struct netdev_queue *txq;
1491         struct cpdma_chan *txch;
1492         int ret, q_idx;
1493
1494         netif_trans_update(ndev);
1495
1496         if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1497                 cpsw_err(priv, tx_err, "packet pad failed\n");
1498                 ndev->stats.tx_dropped++;
1499                 return NETDEV_TX_OK;
1500         }
1501
1502         if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1503                                 cpsw->cpts->tx_enable)
1504                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1505
1506         skb_tx_timestamp(skb);
1507
1508         q_idx = skb_get_queue_mapping(skb);
1509         if (q_idx >= cpsw->tx_ch_num)
1510                 q_idx = q_idx % cpsw->tx_ch_num;
1511
1512         txch = cpsw->txch[q_idx];
1513         ret = cpsw_tx_packet_submit(priv, skb, txch);
1514         if (unlikely(ret != 0)) {
1515                 cpsw_err(priv, tx_err, "desc submit failed\n");
1516                 goto fail;
1517         }
1518
1519         /* If there is no more tx desc left free then we need to
1520          * tell the kernel to stop sending us tx frames.
1521          */
1522         if (unlikely(!cpdma_check_free_tx_desc(txch))) {
1523                 txq = netdev_get_tx_queue(ndev, q_idx);
1524                 netif_tx_stop_queue(txq);
1525         }
1526
1527         return NETDEV_TX_OK;
1528 fail:
1529         ndev->stats.tx_dropped++;
1530         txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb));
1531         netif_tx_stop_queue(txq);
1532         return NETDEV_TX_BUSY;
1533 }
1534
1535 #ifdef CONFIG_TI_CPTS
1536
1537 static void cpsw_hwtstamp_v1(struct cpsw_common *cpsw)
1538 {
1539         struct cpsw_slave *slave = &cpsw->slaves[cpsw->data.active_slave];
1540         u32 ts_en, seq_id;
1541
1542         if (!cpsw->cpts->tx_enable && !cpsw->cpts->rx_enable) {
1543                 slave_write(slave, 0, CPSW1_TS_CTL);
1544                 return;
1545         }
1546
1547         seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1548         ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1549
1550         if (cpsw->cpts->tx_enable)
1551                 ts_en |= CPSW_V1_TS_TX_EN;
1552
1553         if (cpsw->cpts->rx_enable)
1554                 ts_en |= CPSW_V1_TS_RX_EN;
1555
1556         slave_write(slave, ts_en, CPSW1_TS_CTL);
1557         slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1558 }
1559
1560 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1561 {
1562         struct cpsw_slave *slave;
1563         struct cpsw_common *cpsw = priv->cpsw;
1564         u32 ctrl, mtype;
1565
1566         if (cpsw->data.dual_emac)
1567                 slave = &cpsw->slaves[priv->emac_port];
1568         else
1569                 slave = &cpsw->slaves[cpsw->data.active_slave];
1570
1571         ctrl = slave_read(slave, CPSW2_CONTROL);
1572         switch (cpsw->version) {
1573         case CPSW_VERSION_2:
1574                 ctrl &= ~CTRL_V2_ALL_TS_MASK;
1575
1576                 if (cpsw->cpts->tx_enable)
1577                         ctrl |= CTRL_V2_TX_TS_BITS;
1578
1579                 if (cpsw->cpts->rx_enable)
1580                         ctrl |= CTRL_V2_RX_TS_BITS;
1581                 break;
1582         case CPSW_VERSION_3:
1583         default:
1584                 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1585
1586                 if (cpsw->cpts->tx_enable)
1587                         ctrl |= CTRL_V3_TX_TS_BITS;
1588
1589                 if (cpsw->cpts->rx_enable)
1590                         ctrl |= CTRL_V3_RX_TS_BITS;
1591                 break;
1592         }
1593
1594         mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1595
1596         slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1597         slave_write(slave, ctrl, CPSW2_CONTROL);
1598         __raw_writel(ETH_P_1588, &cpsw->regs->ts_ltype);
1599 }
1600
1601 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1602 {
1603         struct cpsw_priv *priv = netdev_priv(dev);
1604         struct hwtstamp_config cfg;
1605         struct cpsw_common *cpsw = priv->cpsw;
1606         struct cpts *cpts = cpsw->cpts;
1607
1608         if (cpsw->version != CPSW_VERSION_1 &&
1609             cpsw->version != CPSW_VERSION_2 &&
1610             cpsw->version != CPSW_VERSION_3)
1611                 return -EOPNOTSUPP;
1612
1613         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1614                 return -EFAULT;
1615
1616         /* reserved for future extensions */
1617         if (cfg.flags)
1618                 return -EINVAL;
1619
1620         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1621                 return -ERANGE;
1622
1623         switch (cfg.rx_filter) {
1624         case HWTSTAMP_FILTER_NONE:
1625                 cpts->rx_enable = 0;
1626                 break;
1627         case HWTSTAMP_FILTER_ALL:
1628         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1629         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1630         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1631                 return -ERANGE;
1632         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1633         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1634         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1635         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1636         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1637         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1638         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1639         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1640         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1641                 cpts->rx_enable = 1;
1642                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1643                 break;
1644         default:
1645                 return -ERANGE;
1646         }
1647
1648         cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1649
1650         switch (cpsw->version) {
1651         case CPSW_VERSION_1:
1652                 cpsw_hwtstamp_v1(cpsw);
1653                 break;
1654         case CPSW_VERSION_2:
1655         case CPSW_VERSION_3:
1656                 cpsw_hwtstamp_v2(priv);
1657                 break;
1658         default:
1659                 WARN_ON(1);
1660         }
1661
1662         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1663 }
1664
1665 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1666 {
1667         struct cpsw_common *cpsw = ndev_to_cpsw(dev);
1668         struct cpts *cpts = cpsw->cpts;
1669         struct hwtstamp_config cfg;
1670
1671         if (cpsw->version != CPSW_VERSION_1 &&
1672             cpsw->version != CPSW_VERSION_2 &&
1673             cpsw->version != CPSW_VERSION_3)
1674                 return -EOPNOTSUPP;
1675
1676         cfg.flags = 0;
1677         cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1678         cfg.rx_filter = (cpts->rx_enable ?
1679                          HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1680
1681         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1682 }
1683
1684 #endif /*CONFIG_TI_CPTS*/
1685
1686 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1687 {
1688         struct cpsw_priv *priv = netdev_priv(dev);
1689         struct cpsw_common *cpsw = priv->cpsw;
1690         int slave_no = cpsw_slave_index(cpsw, priv);
1691
1692         if (!netif_running(dev))
1693                 return -EINVAL;
1694
1695         switch (cmd) {
1696 #ifdef CONFIG_TI_CPTS
1697         case SIOCSHWTSTAMP:
1698                 return cpsw_hwtstamp_set(dev, req);
1699         case SIOCGHWTSTAMP:
1700                 return cpsw_hwtstamp_get(dev, req);
1701 #endif
1702         }
1703
1704         if (!cpsw->slaves[slave_no].phy)
1705                 return -EOPNOTSUPP;
1706         return phy_mii_ioctl(cpsw->slaves[slave_no].phy, req, cmd);
1707 }
1708
1709 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1710 {
1711         struct cpsw_priv *priv = netdev_priv(ndev);
1712         struct cpsw_common *cpsw = priv->cpsw;
1713         int ch;
1714
1715         cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1716         ndev->stats.tx_errors++;
1717         cpsw_intr_disable(cpsw);
1718         for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1719                 cpdma_chan_stop(cpsw->txch[ch]);
1720                 cpdma_chan_start(cpsw->txch[ch]);
1721         }
1722
1723         cpsw_intr_enable(cpsw);
1724 }
1725
1726 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1727 {
1728         struct cpsw_priv *priv = netdev_priv(ndev);
1729         struct sockaddr *addr = (struct sockaddr *)p;
1730         struct cpsw_common *cpsw = priv->cpsw;
1731         int flags = 0;
1732         u16 vid = 0;
1733         int ret;
1734
1735         if (!is_valid_ether_addr(addr->sa_data))
1736                 return -EADDRNOTAVAIL;
1737
1738         ret = pm_runtime_get_sync(cpsw->dev);
1739         if (ret < 0) {
1740                 pm_runtime_put_noidle(cpsw->dev);
1741                 return ret;
1742         }
1743
1744         if (cpsw->data.dual_emac) {
1745                 vid = cpsw->slaves[priv->emac_port].port_vlan;
1746                 flags = ALE_VLAN;
1747         }
1748
1749         cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1750                            flags, vid);
1751         cpsw_ale_add_ucast(cpsw->ale, addr->sa_data, HOST_PORT_NUM,
1752                            flags, vid);
1753
1754         memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1755         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1756         for_each_slave(priv, cpsw_set_slave_mac, priv);
1757
1758         pm_runtime_put(cpsw->dev);
1759
1760         return 0;
1761 }
1762
1763 #ifdef CONFIG_NET_POLL_CONTROLLER
1764 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1765 {
1766         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1767
1768         cpsw_intr_disable(cpsw);
1769         cpsw_rx_interrupt(cpsw->irqs_table[0], cpsw);
1770         cpsw_tx_interrupt(cpsw->irqs_table[1], cpsw);
1771         cpsw_intr_enable(cpsw);
1772 }
1773 #endif
1774
1775 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1776                                 unsigned short vid)
1777 {
1778         int ret;
1779         int unreg_mcast_mask = 0;
1780         u32 port_mask;
1781         struct cpsw_common *cpsw = priv->cpsw;
1782
1783         if (cpsw->data.dual_emac) {
1784                 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
1785
1786                 if (priv->ndev->flags & IFF_ALLMULTI)
1787                         unreg_mcast_mask = port_mask;
1788         } else {
1789                 port_mask = ALE_ALL_PORTS;
1790
1791                 if (priv->ndev->flags & IFF_ALLMULTI)
1792                         unreg_mcast_mask = ALE_ALL_PORTS;
1793                 else
1794                         unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1795         }
1796
1797         ret = cpsw_ale_add_vlan(cpsw->ale, vid, port_mask, 0, port_mask,
1798                                 unreg_mcast_mask);
1799         if (ret != 0)
1800                 return ret;
1801
1802         ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1803                                  HOST_PORT_NUM, ALE_VLAN, vid);
1804         if (ret != 0)
1805                 goto clean_vid;
1806
1807         ret = cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1808                                  port_mask, ALE_VLAN, vid, 0);
1809         if (ret != 0)
1810                 goto clean_vlan_ucast;
1811         return 0;
1812
1813 clean_vlan_ucast:
1814         cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
1815                            HOST_PORT_NUM, ALE_VLAN, vid);
1816 clean_vid:
1817         cpsw_ale_del_vlan(cpsw->ale, vid, 0);
1818         return ret;
1819 }
1820
1821 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1822                                     __be16 proto, u16 vid)
1823 {
1824         struct cpsw_priv *priv = netdev_priv(ndev);
1825         struct cpsw_common *cpsw = priv->cpsw;
1826         int ret;
1827
1828         if (vid == cpsw->data.default_vlan)
1829                 return 0;
1830
1831         ret = pm_runtime_get_sync(cpsw->dev);
1832         if (ret < 0) {
1833                 pm_runtime_put_noidle(cpsw->dev);
1834                 return ret;
1835         }
1836
1837         if (cpsw->data.dual_emac) {
1838                 /* In dual EMAC, reserved VLAN id should not be used for
1839                  * creating VLAN interfaces as this can break the dual
1840                  * EMAC port separation
1841                  */
1842                 int i;
1843
1844                 for (i = 0; i < cpsw->data.slaves; i++) {
1845                         if (vid == cpsw->slaves[i].port_vlan)
1846                                 return -EINVAL;
1847                 }
1848         }
1849
1850         dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1851         ret = cpsw_add_vlan_ale_entry(priv, vid);
1852
1853         pm_runtime_put(cpsw->dev);
1854         return ret;
1855 }
1856
1857 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1858                                      __be16 proto, u16 vid)
1859 {
1860         struct cpsw_priv *priv = netdev_priv(ndev);
1861         struct cpsw_common *cpsw = priv->cpsw;
1862         int ret;
1863
1864         if (vid == cpsw->data.default_vlan)
1865                 return 0;
1866
1867         ret = pm_runtime_get_sync(cpsw->dev);
1868         if (ret < 0) {
1869                 pm_runtime_put_noidle(cpsw->dev);
1870                 return ret;
1871         }
1872
1873         if (cpsw->data.dual_emac) {
1874                 int i;
1875
1876                 for (i = 0; i < cpsw->data.slaves; i++) {
1877                         if (vid == cpsw->slaves[i].port_vlan)
1878                                 return -EINVAL;
1879                 }
1880         }
1881
1882         dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1883         ret = cpsw_ale_del_vlan(cpsw->ale, vid, 0);
1884         if (ret != 0)
1885                 return ret;
1886
1887         ret = cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
1888                                  HOST_PORT_NUM, ALE_VLAN, vid);
1889         if (ret != 0)
1890                 return ret;
1891
1892         ret = cpsw_ale_del_mcast(cpsw->ale, priv->ndev->broadcast,
1893                                  0, ALE_VLAN, vid);
1894         pm_runtime_put(cpsw->dev);
1895         return ret;
1896 }
1897
1898 static const struct net_device_ops cpsw_netdev_ops = {
1899         .ndo_open               = cpsw_ndo_open,
1900         .ndo_stop               = cpsw_ndo_stop,
1901         .ndo_start_xmit         = cpsw_ndo_start_xmit,
1902         .ndo_set_mac_address    = cpsw_ndo_set_mac_address,
1903         .ndo_do_ioctl           = cpsw_ndo_ioctl,
1904         .ndo_validate_addr      = eth_validate_addr,
1905         .ndo_change_mtu         = eth_change_mtu,
1906         .ndo_tx_timeout         = cpsw_ndo_tx_timeout,
1907         .ndo_set_rx_mode        = cpsw_ndo_set_rx_mode,
1908 #ifdef CONFIG_NET_POLL_CONTROLLER
1909         .ndo_poll_controller    = cpsw_ndo_poll_controller,
1910 #endif
1911         .ndo_vlan_rx_add_vid    = cpsw_ndo_vlan_rx_add_vid,
1912         .ndo_vlan_rx_kill_vid   = cpsw_ndo_vlan_rx_kill_vid,
1913 };
1914
1915 static int cpsw_get_regs_len(struct net_device *ndev)
1916 {
1917         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1918
1919         return cpsw->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
1920 }
1921
1922 static void cpsw_get_regs(struct net_device *ndev,
1923                           struct ethtool_regs *regs, void *p)
1924 {
1925         u32 *reg = p;
1926         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1927
1928         /* update CPSW IP version */
1929         regs->version = cpsw->version;
1930
1931         cpsw_ale_dump(cpsw->ale, reg);
1932 }
1933
1934 static void cpsw_get_drvinfo(struct net_device *ndev,
1935                              struct ethtool_drvinfo *info)
1936 {
1937         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1938         struct platform_device  *pdev = to_platform_device(cpsw->dev);
1939
1940         strlcpy(info->driver, "cpsw", sizeof(info->driver));
1941         strlcpy(info->version, "1.0", sizeof(info->version));
1942         strlcpy(info->bus_info, pdev->name, sizeof(info->bus_info));
1943 }
1944
1945 static u32 cpsw_get_msglevel(struct net_device *ndev)
1946 {
1947         struct cpsw_priv *priv = netdev_priv(ndev);
1948         return priv->msg_enable;
1949 }
1950
1951 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1952 {
1953         struct cpsw_priv *priv = netdev_priv(ndev);
1954         priv->msg_enable = value;
1955 }
1956
1957 static int cpsw_get_ts_info(struct net_device *ndev,
1958                             struct ethtool_ts_info *info)
1959 {
1960 #ifdef CONFIG_TI_CPTS
1961         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1962
1963         info->so_timestamping =
1964                 SOF_TIMESTAMPING_TX_HARDWARE |
1965                 SOF_TIMESTAMPING_TX_SOFTWARE |
1966                 SOF_TIMESTAMPING_RX_HARDWARE |
1967                 SOF_TIMESTAMPING_RX_SOFTWARE |
1968                 SOF_TIMESTAMPING_SOFTWARE |
1969                 SOF_TIMESTAMPING_RAW_HARDWARE;
1970         info->phc_index = cpsw->cpts->phc_index;
1971         info->tx_types =
1972                 (1 << HWTSTAMP_TX_OFF) |
1973                 (1 << HWTSTAMP_TX_ON);
1974         info->rx_filters =
1975                 (1 << HWTSTAMP_FILTER_NONE) |
1976                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1977 #else
1978         info->so_timestamping =
1979                 SOF_TIMESTAMPING_TX_SOFTWARE |
1980                 SOF_TIMESTAMPING_RX_SOFTWARE |
1981                 SOF_TIMESTAMPING_SOFTWARE;
1982         info->phc_index = -1;
1983         info->tx_types = 0;
1984         info->rx_filters = 0;
1985 #endif
1986         return 0;
1987 }
1988
1989 static int cpsw_get_settings(struct net_device *ndev,
1990                              struct ethtool_cmd *ecmd)
1991 {
1992         struct cpsw_priv *priv = netdev_priv(ndev);
1993         struct cpsw_common *cpsw = priv->cpsw;
1994         int slave_no = cpsw_slave_index(cpsw, priv);
1995
1996         if (cpsw->slaves[slave_no].phy)
1997                 return phy_ethtool_gset(cpsw->slaves[slave_no].phy, ecmd);
1998         else
1999                 return -EOPNOTSUPP;
2000 }
2001
2002 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
2003 {
2004         struct cpsw_priv *priv = netdev_priv(ndev);
2005         struct cpsw_common *cpsw = priv->cpsw;
2006         int slave_no = cpsw_slave_index(cpsw, priv);
2007
2008         if (cpsw->slaves[slave_no].phy)
2009                 return phy_ethtool_sset(cpsw->slaves[slave_no].phy, ecmd);
2010         else
2011                 return -EOPNOTSUPP;
2012 }
2013
2014 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2015 {
2016         struct cpsw_priv *priv = netdev_priv(ndev);
2017         struct cpsw_common *cpsw = priv->cpsw;
2018         int slave_no = cpsw_slave_index(cpsw, priv);
2019
2020         wol->supported = 0;
2021         wol->wolopts = 0;
2022
2023         if (cpsw->slaves[slave_no].phy)
2024                 phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol);
2025 }
2026
2027 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2028 {
2029         struct cpsw_priv *priv = netdev_priv(ndev);
2030         struct cpsw_common *cpsw = priv->cpsw;
2031         int slave_no = cpsw_slave_index(cpsw, priv);
2032
2033         if (cpsw->slaves[slave_no].phy)
2034                 return phy_ethtool_set_wol(cpsw->slaves[slave_no].phy, wol);
2035         else
2036                 return -EOPNOTSUPP;
2037 }
2038
2039 static void cpsw_get_pauseparam(struct net_device *ndev,
2040                                 struct ethtool_pauseparam *pause)
2041 {
2042         struct cpsw_priv *priv = netdev_priv(ndev);
2043
2044         pause->autoneg = AUTONEG_DISABLE;
2045         pause->rx_pause = priv->rx_pause ? true : false;
2046         pause->tx_pause = priv->tx_pause ? true : false;
2047 }
2048
2049 static int cpsw_set_pauseparam(struct net_device *ndev,
2050                                struct ethtool_pauseparam *pause)
2051 {
2052         struct cpsw_priv *priv = netdev_priv(ndev);
2053         bool link;
2054
2055         priv->rx_pause = pause->rx_pause ? true : false;
2056         priv->tx_pause = pause->tx_pause ? true : false;
2057
2058         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
2059         return 0;
2060 }
2061
2062 static int cpsw_ethtool_op_begin(struct net_device *ndev)
2063 {
2064         struct cpsw_priv *priv = netdev_priv(ndev);
2065         struct cpsw_common *cpsw = priv->cpsw;
2066         int ret;
2067
2068         ret = pm_runtime_get_sync(cpsw->dev);
2069         if (ret < 0) {
2070                 cpsw_err(priv, drv, "ethtool begin failed %d\n", ret);
2071                 pm_runtime_put_noidle(cpsw->dev);
2072         }
2073
2074         return ret;
2075 }
2076
2077 static void cpsw_ethtool_op_complete(struct net_device *ndev)
2078 {
2079         struct cpsw_priv *priv = netdev_priv(ndev);
2080         int ret;
2081
2082         ret = pm_runtime_put(priv->cpsw->dev);
2083         if (ret < 0)
2084                 cpsw_err(priv, drv, "ethtool complete failed %d\n", ret);
2085 }
2086
2087 static void cpsw_get_channels(struct net_device *ndev,
2088                               struct ethtool_channels *ch)
2089 {
2090         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2091
2092         ch->max_combined = 0;
2093         ch->max_rx = CPSW_MAX_QUEUES;
2094         ch->max_tx = CPSW_MAX_QUEUES;
2095         ch->max_other = 0;
2096         ch->other_count = 0;
2097         ch->rx_count = cpsw->rx_ch_num;
2098         ch->tx_count = cpsw->tx_ch_num;
2099         ch->combined_count = 0;
2100 }
2101
2102 static int cpsw_check_ch_settings(struct cpsw_common *cpsw,
2103                                   struct ethtool_channels *ch)
2104 {
2105         if (ch->combined_count)
2106                 return -EINVAL;
2107
2108         /* verify we have at least one channel in each direction */
2109         if (!ch->rx_count || !ch->tx_count)
2110                 return -EINVAL;
2111
2112         if (ch->rx_count > cpsw->data.channels ||
2113             ch->tx_count > cpsw->data.channels)
2114                 return -EINVAL;
2115
2116         return 0;
2117 }
2118
2119 static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx)
2120 {
2121         int (*poll)(struct napi_struct *, int);
2122         struct cpsw_common *cpsw = priv->cpsw;
2123         void (*handler)(void *, int, int);
2124         struct cpdma_chan **chan;
2125         int ret, *ch;
2126
2127         if (rx) {
2128                 ch = &cpsw->rx_ch_num;
2129                 chan = cpsw->rxch;
2130                 handler = cpsw_rx_handler;
2131                 poll = cpsw_rx_poll;
2132         } else {
2133                 ch = &cpsw->tx_ch_num;
2134                 chan = cpsw->txch;
2135                 handler = cpsw_tx_handler;
2136                 poll = cpsw_tx_poll;
2137         }
2138
2139         while (*ch < ch_num) {
2140                 chan[*ch] = cpdma_chan_create(cpsw->dma, *ch, handler, rx);
2141
2142                 if (IS_ERR(chan[*ch]))
2143                         return PTR_ERR(chan[*ch]);
2144
2145                 if (!chan[*ch])
2146                         return -EINVAL;
2147
2148                 cpsw_info(priv, ifup, "created new %d %s channel\n", *ch,
2149                           (rx ? "rx" : "tx"));
2150                 (*ch)++;
2151         }
2152
2153         while (*ch > ch_num) {
2154                 (*ch)--;
2155
2156                 ret = cpdma_chan_destroy(chan[*ch]);
2157                 if (ret)
2158                         return ret;
2159
2160                 cpsw_info(priv, ifup, "destroyed %d %s channel\n", *ch,
2161                           (rx ? "rx" : "tx"));
2162         }
2163
2164         return 0;
2165 }
2166
2167 static int cpsw_update_channels(struct cpsw_priv *priv,
2168                                 struct ethtool_channels *ch)
2169 {
2170         int ret;
2171
2172         ret = cpsw_update_channels_res(priv, ch->rx_count, 1);
2173         if (ret)
2174                 return ret;
2175
2176         ret = cpsw_update_channels_res(priv, ch->tx_count, 0);
2177         if (ret)
2178                 return ret;
2179
2180         return 0;
2181 }
2182
2183 static int cpsw_set_channels(struct net_device *ndev,
2184                              struct ethtool_channels *chs)
2185 {
2186         struct cpsw_priv *priv = netdev_priv(ndev);
2187         struct cpsw_common *cpsw = priv->cpsw;
2188         struct cpsw_slave *slave;
2189         int i, ret;
2190
2191         ret = cpsw_check_ch_settings(cpsw, chs);
2192         if (ret < 0)
2193                 return ret;
2194
2195         /* Disable NAPI scheduling */
2196         cpsw_intr_disable(cpsw);
2197
2198         /* Stop all transmit queues for every network device.
2199          * Disable re-using rx descriptors with dormant_on.
2200          */
2201         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2202                 if (!(slave->ndev && netif_running(slave->ndev)))
2203                         continue;
2204
2205                 netif_tx_stop_all_queues(slave->ndev);
2206                 netif_dormant_on(slave->ndev);
2207         }
2208
2209         /* Handle rest of tx packets and stop cpdma channels */
2210         cpdma_ctlr_stop(cpsw->dma);
2211         ret = cpsw_update_channels(priv, chs);
2212         if (ret)
2213                 goto err;
2214
2215         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2216                 if (!(slave->ndev && netif_running(slave->ndev)))
2217                         continue;
2218
2219                 /* Inform stack about new count of queues */
2220                 ret = netif_set_real_num_tx_queues(slave->ndev,
2221                                                    cpsw->tx_ch_num);
2222                 if (ret) {
2223                         dev_err(priv->dev, "cannot set real number of tx queues\n");
2224                         goto err;
2225                 }
2226
2227                 ret = netif_set_real_num_rx_queues(slave->ndev,
2228                                                    cpsw->rx_ch_num);
2229                 if (ret) {
2230                         dev_err(priv->dev, "cannot set real number of rx queues\n");
2231                         goto err;
2232                 }
2233
2234                 /* Enable rx packets handling */
2235                 netif_dormant_off(slave->ndev);
2236         }
2237
2238         if (cpsw_common_res_usage_state(cpsw)) {
2239                 ret = cpsw_fill_rx_channels(priv);
2240                 if (ret)
2241                         goto err;
2242
2243                 /* After this receive is started */
2244                 cpdma_ctlr_start(cpsw->dma);
2245                 cpsw_intr_enable(cpsw);
2246         }
2247
2248         /* Resume transmit for every affected interface */
2249         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2250                 if (!(slave->ndev && netif_running(slave->ndev)))
2251                         continue;
2252                 netif_tx_start_all_queues(slave->ndev);
2253         }
2254         return 0;
2255 err:
2256         dev_err(priv->dev, "cannot update channels number, closing device\n");
2257         dev_close(ndev);
2258         return ret;
2259 }
2260
2261 static const struct ethtool_ops cpsw_ethtool_ops = {
2262         .get_drvinfo    = cpsw_get_drvinfo,
2263         .get_msglevel   = cpsw_get_msglevel,
2264         .set_msglevel   = cpsw_set_msglevel,
2265         .get_link       = ethtool_op_get_link,
2266         .get_ts_info    = cpsw_get_ts_info,
2267         .get_settings   = cpsw_get_settings,
2268         .set_settings   = cpsw_set_settings,
2269         .get_coalesce   = cpsw_get_coalesce,
2270         .set_coalesce   = cpsw_set_coalesce,
2271         .get_sset_count         = cpsw_get_sset_count,
2272         .get_strings            = cpsw_get_strings,
2273         .get_ethtool_stats      = cpsw_get_ethtool_stats,
2274         .get_pauseparam         = cpsw_get_pauseparam,
2275         .set_pauseparam         = cpsw_set_pauseparam,
2276         .get_wol        = cpsw_get_wol,
2277         .set_wol        = cpsw_set_wol,
2278         .get_regs_len   = cpsw_get_regs_len,
2279         .get_regs       = cpsw_get_regs,
2280         .begin          = cpsw_ethtool_op_begin,
2281         .complete       = cpsw_ethtool_op_complete,
2282         .get_channels   = cpsw_get_channels,
2283         .set_channels   = cpsw_set_channels,
2284 };
2285
2286 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_common *cpsw,
2287                             u32 slave_reg_ofs, u32 sliver_reg_ofs)
2288 {
2289         void __iomem            *regs = cpsw->regs;
2290         int                     slave_num = slave->slave_num;
2291         struct cpsw_slave_data  *data = cpsw->data.slave_data + slave_num;
2292
2293         slave->data     = data;
2294         slave->regs     = regs + slave_reg_ofs;
2295         slave->sliver   = regs + sliver_reg_ofs;
2296         slave->port_vlan = data->dual_emac_res_vlan;
2297 }
2298
2299 static int cpsw_probe_dt(struct cpsw_platform_data *data,
2300                          struct platform_device *pdev)
2301 {
2302         struct device_node *node = pdev->dev.of_node;
2303         struct device_node *slave_node;
2304         int i = 0, ret;
2305         u32 prop;
2306
2307         if (!node)
2308                 return -EINVAL;
2309
2310         if (of_property_read_u32(node, "slaves", &prop)) {
2311                 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
2312                 return -EINVAL;
2313         }
2314         data->slaves = prop;
2315
2316         if (of_property_read_u32(node, "active_slave", &prop)) {
2317                 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
2318                 return -EINVAL;
2319         }
2320         data->active_slave = prop;
2321
2322         if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
2323                 dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
2324                 return -EINVAL;
2325         }
2326         data->cpts_clock_mult = prop;
2327
2328         if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
2329                 dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
2330                 return -EINVAL;
2331         }
2332         data->cpts_clock_shift = prop;
2333
2334         data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
2335                                         * sizeof(struct cpsw_slave_data),
2336                                         GFP_KERNEL);
2337         if (!data->slave_data)
2338                 return -ENOMEM;
2339
2340         if (of_property_read_u32(node, "cpdma_channels", &prop)) {
2341                 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
2342                 return -EINVAL;
2343         }
2344         data->channels = prop;
2345
2346         if (of_property_read_u32(node, "ale_entries", &prop)) {
2347                 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
2348                 return -EINVAL;
2349         }
2350         data->ale_entries = prop;
2351
2352         if (of_property_read_u32(node, "bd_ram_size", &prop)) {
2353                 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
2354                 return -EINVAL;
2355         }
2356         data->bd_ram_size = prop;
2357
2358         if (of_property_read_u32(node, "mac_control", &prop)) {
2359                 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
2360                 return -EINVAL;
2361         }
2362         data->mac_control = prop;
2363
2364         if (of_property_read_bool(node, "dual_emac"))
2365                 data->dual_emac = 1;
2366
2367         /*
2368          * Populate all the child nodes here...
2369          */
2370         ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2371         /* We do not want to force this, as in some cases may not have child */
2372         if (ret)
2373                 dev_warn(&pdev->dev, "Doesn't have any child node\n");
2374
2375         for_each_available_child_of_node(node, slave_node) {
2376                 struct cpsw_slave_data *slave_data = data->slave_data + i;
2377                 const void *mac_addr = NULL;
2378                 int lenp;
2379                 const __be32 *parp;
2380
2381                 /* This is no slave child node, continue */
2382                 if (strcmp(slave_node->name, "slave"))
2383                         continue;
2384
2385                 slave_data->phy_node = of_parse_phandle(slave_node,
2386                                                         "phy-handle", 0);
2387                 parp = of_get_property(slave_node, "phy_id", &lenp);
2388                 if (slave_data->phy_node) {
2389                         dev_dbg(&pdev->dev,
2390                                 "slave[%d] using phy-handle=\"%s\"\n",
2391                                 i, slave_data->phy_node->full_name);
2392                 } else if (of_phy_is_fixed_link(slave_node)) {
2393                         /* In the case of a fixed PHY, the DT node associated
2394                          * to the PHY is the Ethernet MAC DT node.
2395                          */
2396                         ret = of_phy_register_fixed_link(slave_node);
2397                         if (ret) {
2398                                 if (ret != -EPROBE_DEFER)
2399                                         dev_err(&pdev->dev, "failed to register fixed-link phy: %d\n", ret);
2400                                 return ret;
2401                         }
2402                         slave_data->phy_node = of_node_get(slave_node);
2403                 } else if (parp) {
2404                         u32 phyid;
2405                         struct device_node *mdio_node;
2406                         struct platform_device *mdio;
2407
2408                         if (lenp != (sizeof(__be32) * 2)) {
2409                                 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
2410                                 goto no_phy_slave;
2411                         }
2412                         mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2413                         phyid = be32_to_cpup(parp+1);
2414                         mdio = of_find_device_by_node(mdio_node);
2415                         of_node_put(mdio_node);
2416                         if (!mdio) {
2417                                 dev_err(&pdev->dev, "Missing mdio platform device\n");
2418                                 return -EINVAL;
2419                         }
2420                         snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2421                                  PHY_ID_FMT, mdio->name, phyid);
2422                         put_device(&mdio->dev);
2423                 } else {
2424                         dev_err(&pdev->dev,
2425                                 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
2426                                 i);
2427                         goto no_phy_slave;
2428                 }
2429                 slave_data->phy_if = of_get_phy_mode(slave_node);
2430                 if (slave_data->phy_if < 0) {
2431                         dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2432                                 i);
2433                         return slave_data->phy_if;
2434                 }
2435
2436 no_phy_slave:
2437                 mac_addr = of_get_mac_address(slave_node);
2438                 if (mac_addr) {
2439                         memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
2440                 } else {
2441                         ret = ti_cm_get_macid(&pdev->dev, i,
2442                                               slave_data->mac_addr);
2443                         if (ret)
2444                                 return ret;
2445                 }
2446                 if (data->dual_emac) {
2447                         if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
2448                                                  &prop)) {
2449                                 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
2450                                 slave_data->dual_emac_res_vlan = i+1;
2451                                 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2452                                         slave_data->dual_emac_res_vlan, i);
2453                         } else {
2454                                 slave_data->dual_emac_res_vlan = prop;
2455                         }
2456                 }
2457
2458                 i++;
2459                 if (i == data->slaves)
2460                         break;
2461         }
2462
2463         return 0;
2464 }
2465
2466 static void cpsw_remove_dt(struct platform_device *pdev)
2467 {
2468         struct net_device *ndev = platform_get_drvdata(pdev);
2469         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2470         struct cpsw_platform_data *data = &cpsw->data;
2471         struct device_node *node = pdev->dev.of_node;
2472         struct device_node *slave_node;
2473         int i = 0;
2474
2475         for_each_available_child_of_node(node, slave_node) {
2476                 struct cpsw_slave_data *slave_data = &data->slave_data[i];
2477
2478                 if (strcmp(slave_node->name, "slave"))
2479                         continue;
2480
2481                 if (of_phy_is_fixed_link(slave_node))
2482                         of_phy_deregister_fixed_link(slave_node);
2483
2484                 of_node_put(slave_data->phy_node);
2485
2486                 i++;
2487                 if (i == data->slaves)
2488                         break;
2489         }
2490
2491         of_platform_depopulate(&pdev->dev);
2492 }
2493
2494 static int cpsw_probe_dual_emac(struct cpsw_priv *priv)
2495 {
2496         struct cpsw_common              *cpsw = priv->cpsw;
2497         struct cpsw_platform_data       *data = &cpsw->data;
2498         struct net_device               *ndev;
2499         struct cpsw_priv                *priv_sl2;
2500         int ret = 0;
2501
2502         ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
2503         if (!ndev) {
2504                 dev_err(cpsw->dev, "cpsw: error allocating net_device\n");
2505                 return -ENOMEM;
2506         }
2507
2508         priv_sl2 = netdev_priv(ndev);
2509         priv_sl2->cpsw = cpsw;
2510         priv_sl2->ndev = ndev;
2511         priv_sl2->dev  = &ndev->dev;
2512         priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2513
2514         if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2515                 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2516                         ETH_ALEN);
2517                 dev_info(cpsw->dev, "cpsw: Detected MACID = %pM\n",
2518                          priv_sl2->mac_addr);
2519         } else {
2520                 random_ether_addr(priv_sl2->mac_addr);
2521                 dev_info(cpsw->dev, "cpsw: Random MACID = %pM\n",
2522                          priv_sl2->mac_addr);
2523         }
2524         memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2525
2526         priv_sl2->emac_port = 1;
2527         cpsw->slaves[1].ndev = ndev;
2528         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2529
2530         ndev->netdev_ops = &cpsw_netdev_ops;
2531         ndev->ethtool_ops = &cpsw_ethtool_ops;
2532
2533         /* register the network device */
2534         SET_NETDEV_DEV(ndev, cpsw->dev);
2535         ret = register_netdev(ndev);
2536         if (ret) {
2537                 dev_err(cpsw->dev, "cpsw: error registering net device\n");
2538                 free_netdev(ndev);
2539                 ret = -ENODEV;
2540         }
2541
2542         return ret;
2543 }
2544
2545 #define CPSW_QUIRK_IRQ          BIT(0)
2546
2547 static struct platform_device_id cpsw_devtype[] = {
2548         {
2549                 /* keep it for existing comaptibles */
2550                 .name = "cpsw",
2551                 .driver_data = CPSW_QUIRK_IRQ,
2552         }, {
2553                 .name = "am335x-cpsw",
2554                 .driver_data = CPSW_QUIRK_IRQ,
2555         }, {
2556                 .name = "am4372-cpsw",
2557                 .driver_data = 0,
2558         }, {
2559                 .name = "dra7-cpsw",
2560                 .driver_data = 0,
2561         }, {
2562                 /* sentinel */
2563         }
2564 };
2565 MODULE_DEVICE_TABLE(platform, cpsw_devtype);
2566
2567 enum ti_cpsw_type {
2568         CPSW = 0,
2569         AM335X_CPSW,
2570         AM4372_CPSW,
2571         DRA7_CPSW,
2572 };
2573
2574 static const struct of_device_id cpsw_of_mtable[] = {
2575         { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], },
2576         { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], },
2577         { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], },
2578         { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], },
2579         { /* sentinel */ },
2580 };
2581 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2582
2583 static int cpsw_probe(struct platform_device *pdev)
2584 {
2585         struct clk                      *clk;
2586         struct cpsw_platform_data       *data;
2587         struct net_device               *ndev;
2588         struct cpsw_priv                *priv;
2589         struct cpdma_params             dma_params;
2590         struct cpsw_ale_params          ale_params;
2591         void __iomem                    *ss_regs;
2592         struct resource                 *res, *ss_res;
2593         const struct of_device_id       *of_id;
2594         struct gpio_descs               *mode;
2595         u32 slave_offset, sliver_offset, slave_size;
2596         struct cpsw_common              *cpsw;
2597         int ret = 0, i;
2598         int irq;
2599
2600         cpsw = devm_kzalloc(&pdev->dev, sizeof(struct cpsw_common), GFP_KERNEL);
2601         if (!cpsw)
2602                 return -ENOMEM;
2603
2604         cpsw->dev = &pdev->dev;
2605
2606         ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
2607         if (!ndev) {
2608                 dev_err(&pdev->dev, "error allocating net_device\n");
2609                 return -ENOMEM;
2610         }
2611
2612         platform_set_drvdata(pdev, ndev);
2613         priv = netdev_priv(ndev);
2614         priv->cpsw = cpsw;
2615         priv->ndev = ndev;
2616         priv->dev  = &ndev->dev;
2617         priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2618         cpsw->rx_packet_max = max(rx_packet_max, 128);
2619         cpsw->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
2620         if (!cpsw->cpts) {
2621                 dev_err(&pdev->dev, "error allocating cpts\n");
2622                 ret = -ENOMEM;
2623                 goto clean_ndev_ret;
2624         }
2625
2626         mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
2627         if (IS_ERR(mode)) {
2628                 ret = PTR_ERR(mode);
2629                 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
2630                 goto clean_ndev_ret;
2631         }
2632
2633         /*
2634          * This may be required here for child devices.
2635          */
2636         pm_runtime_enable(&pdev->dev);
2637
2638         /* Select default pin state */
2639         pinctrl_pm_select_default_state(&pdev->dev);
2640
2641         /* Need to enable clocks with runtime PM api to access module
2642          * registers
2643          */
2644         ret = pm_runtime_get_sync(&pdev->dev);
2645         if (ret < 0) {
2646                 pm_runtime_put_noidle(&pdev->dev);
2647                 goto clean_runtime_disable_ret;
2648         }
2649
2650         ret = cpsw_probe_dt(&cpsw->data, pdev);
2651         if (ret)
2652                 goto clean_dt_ret;
2653
2654         data = &cpsw->data;
2655         cpsw->rx_ch_num = 1;
2656         cpsw->tx_ch_num = 1;
2657
2658         if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2659                 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2660                 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
2661         } else {
2662                 eth_random_addr(priv->mac_addr);
2663                 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
2664         }
2665
2666         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2667
2668         cpsw->slaves = devm_kzalloc(&pdev->dev,
2669                                     sizeof(struct cpsw_slave) * data->slaves,
2670                                     GFP_KERNEL);
2671         if (!cpsw->slaves) {
2672                 ret = -ENOMEM;
2673                 goto clean_dt_ret;
2674         }
2675         for (i = 0; i < data->slaves; i++)
2676                 cpsw->slaves[i].slave_num = i;
2677
2678         cpsw->slaves[0].ndev = ndev;
2679         priv->emac_port = 0;
2680
2681         clk = devm_clk_get(&pdev->dev, "fck");
2682         if (IS_ERR(clk)) {
2683                 dev_err(priv->dev, "fck is not found\n");
2684                 ret = -ENODEV;
2685                 goto clean_dt_ret;
2686         }
2687         cpsw->bus_freq_mhz = clk_get_rate(clk) / 1000000;
2688
2689         ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2690         ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2691         if (IS_ERR(ss_regs)) {
2692                 ret = PTR_ERR(ss_regs);
2693                 goto clean_dt_ret;
2694         }
2695         cpsw->regs = ss_regs;
2696
2697         cpsw->version = readl(&cpsw->regs->id_ver);
2698
2699         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2700         cpsw->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2701         if (IS_ERR(cpsw->wr_regs)) {
2702                 ret = PTR_ERR(cpsw->wr_regs);
2703                 goto clean_dt_ret;
2704         }
2705
2706         memset(&dma_params, 0, sizeof(dma_params));
2707         memset(&ale_params, 0, sizeof(ale_params));
2708
2709         switch (cpsw->version) {
2710         case CPSW_VERSION_1:
2711                 cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
2712                 cpsw->cpts->reg      = ss_regs + CPSW1_CPTS_OFFSET;
2713                 cpsw->hw_stats       = ss_regs + CPSW1_HW_STATS;
2714                 dma_params.dmaregs   = ss_regs + CPSW1_CPDMA_OFFSET;
2715                 dma_params.txhdp     = ss_regs + CPSW1_STATERAM_OFFSET;
2716                 ale_params.ale_regs  = ss_regs + CPSW1_ALE_OFFSET;
2717                 slave_offset         = CPSW1_SLAVE_OFFSET;
2718                 slave_size           = CPSW1_SLAVE_SIZE;
2719                 sliver_offset        = CPSW1_SLIVER_OFFSET;
2720                 dma_params.desc_mem_phys = 0;
2721                 break;
2722         case CPSW_VERSION_2:
2723         case CPSW_VERSION_3:
2724         case CPSW_VERSION_4:
2725                 cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
2726                 cpsw->cpts->reg      = ss_regs + CPSW2_CPTS_OFFSET;
2727                 cpsw->hw_stats       = ss_regs + CPSW2_HW_STATS;
2728                 dma_params.dmaregs   = ss_regs + CPSW2_CPDMA_OFFSET;
2729                 dma_params.txhdp     = ss_regs + CPSW2_STATERAM_OFFSET;
2730                 ale_params.ale_regs  = ss_regs + CPSW2_ALE_OFFSET;
2731                 slave_offset         = CPSW2_SLAVE_OFFSET;
2732                 slave_size           = CPSW2_SLAVE_SIZE;
2733                 sliver_offset        = CPSW2_SLIVER_OFFSET;
2734                 dma_params.desc_mem_phys =
2735                         (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
2736                 break;
2737         default:
2738                 dev_err(priv->dev, "unknown version 0x%08x\n", cpsw->version);
2739                 ret = -ENODEV;
2740                 goto clean_dt_ret;
2741         }
2742         for (i = 0; i < cpsw->data.slaves; i++) {
2743                 struct cpsw_slave *slave = &cpsw->slaves[i];
2744
2745                 cpsw_slave_init(slave, cpsw, slave_offset, sliver_offset);
2746                 slave_offset  += slave_size;
2747                 sliver_offset += SLIVER_SIZE;
2748         }
2749
2750         dma_params.dev          = &pdev->dev;
2751         dma_params.rxthresh     = dma_params.dmaregs + CPDMA_RXTHRESH;
2752         dma_params.rxfree       = dma_params.dmaregs + CPDMA_RXFREE;
2753         dma_params.rxhdp        = dma_params.txhdp + CPDMA_RXHDP;
2754         dma_params.txcp         = dma_params.txhdp + CPDMA_TXCP;
2755         dma_params.rxcp         = dma_params.txhdp + CPDMA_RXCP;
2756
2757         dma_params.num_chan             = data->channels;
2758         dma_params.has_soft_reset       = true;
2759         dma_params.min_packet_size      = CPSW_MIN_PACKET_SIZE;
2760         dma_params.desc_mem_size        = data->bd_ram_size;
2761         dma_params.desc_align           = 16;
2762         dma_params.has_ext_regs         = true;
2763         dma_params.desc_hw_addr         = dma_params.desc_mem_phys;
2764
2765         cpsw->dma = cpdma_ctlr_create(&dma_params);
2766         if (!cpsw->dma) {
2767                 dev_err(priv->dev, "error initializing dma\n");
2768                 ret = -ENOMEM;
2769                 goto clean_dt_ret;
2770         }
2771
2772         cpsw->txch[0] = cpdma_chan_create(cpsw->dma, 0, cpsw_tx_handler, 0);
2773         cpsw->rxch[0] = cpdma_chan_create(cpsw->dma, 0, cpsw_rx_handler, 1);
2774         if (WARN_ON(!cpsw->rxch[0] || !cpsw->txch[0])) {
2775                 dev_err(priv->dev, "error initializing dma channels\n");
2776                 ret = -ENOMEM;
2777                 goto clean_dma_ret;
2778         }
2779
2780         ale_params.dev                  = &ndev->dev;
2781         ale_params.ale_ageout           = ale_ageout;
2782         ale_params.ale_entries          = data->ale_entries;
2783         ale_params.ale_ports            = data->slaves;
2784
2785         cpsw->ale = cpsw_ale_create(&ale_params);
2786         if (!cpsw->ale) {
2787                 dev_err(priv->dev, "error initializing ale engine\n");
2788                 ret = -ENODEV;
2789                 goto clean_dma_ret;
2790         }
2791
2792         ndev->irq = platform_get_irq(pdev, 1);
2793         if (ndev->irq < 0) {
2794                 dev_err(priv->dev, "error getting irq resource\n");
2795                 ret = ndev->irq;
2796                 goto clean_ale_ret;
2797         }
2798
2799         of_id = of_match_device(cpsw_of_mtable, &pdev->dev);
2800         if (of_id) {
2801                 pdev->id_entry = of_id->data;
2802                 if (pdev->id_entry->driver_data)
2803                         cpsw->quirk_irq = true;
2804         }
2805
2806         /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
2807          * MISC IRQs which are always kept disabled with this driver so
2808          * we will not request them.
2809          *
2810          * If anyone wants to implement support for those, make sure to
2811          * first request and append them to irqs_table array.
2812          */
2813
2814         /* RX IRQ */
2815         irq = platform_get_irq(pdev, 1);
2816         if (irq < 0) {
2817                 ret = irq;
2818                 goto clean_ale_ret;
2819         }
2820
2821         cpsw->irqs_table[0] = irq;
2822         ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
2823                                0, dev_name(&pdev->dev), cpsw);
2824         if (ret < 0) {
2825                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2826                 goto clean_ale_ret;
2827         }
2828
2829         /* TX IRQ */
2830         irq = platform_get_irq(pdev, 2);
2831         if (irq < 0) {
2832                 ret = irq;
2833                 goto clean_ale_ret;
2834         }
2835
2836         cpsw->irqs_table[1] = irq;
2837         ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
2838                                0, dev_name(&pdev->dev), cpsw);
2839         if (ret < 0) {
2840                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2841                 goto clean_ale_ret;
2842         }
2843
2844         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2845
2846         ndev->netdev_ops = &cpsw_netdev_ops;
2847         ndev->ethtool_ops = &cpsw_ethtool_ops;
2848         netif_napi_add(ndev, &cpsw->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT);
2849         netif_tx_napi_add(ndev, &cpsw->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT);
2850
2851         /* register the network device */
2852         SET_NETDEV_DEV(ndev, &pdev->dev);
2853         ret = register_netdev(ndev);
2854         if (ret) {
2855                 dev_err(priv->dev, "error registering net device\n");
2856                 ret = -ENODEV;
2857                 goto clean_ale_ret;
2858         }
2859
2860         cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2861                     &ss_res->start, ndev->irq);
2862
2863         if (cpsw->data.dual_emac) {
2864                 ret = cpsw_probe_dual_emac(priv);
2865                 if (ret) {
2866                         cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
2867                         goto clean_unregister_netdev_ret;
2868                 }
2869         }
2870
2871         pm_runtime_put(&pdev->dev);
2872
2873         return 0;
2874
2875 clean_unregister_netdev_ret:
2876         unregister_netdev(ndev);
2877 clean_ale_ret:
2878         cpsw_ale_destroy(cpsw->ale);
2879 clean_dma_ret:
2880         cpdma_ctlr_destroy(cpsw->dma);
2881 clean_dt_ret:
2882         cpsw_remove_dt(pdev);
2883         pm_runtime_put_sync(&pdev->dev);
2884 clean_runtime_disable_ret:
2885         pm_runtime_disable(&pdev->dev);
2886 clean_ndev_ret:
2887         free_netdev(priv->ndev);
2888         return ret;
2889 }
2890
2891 static int cpsw_remove(struct platform_device *pdev)
2892 {
2893         struct net_device *ndev = platform_get_drvdata(pdev);
2894         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2895         int ret;
2896
2897         ret = pm_runtime_get_sync(&pdev->dev);
2898         if (ret < 0) {
2899                 pm_runtime_put_noidle(&pdev->dev);
2900                 return ret;
2901         }
2902
2903         if (cpsw->data.dual_emac)
2904                 unregister_netdev(cpsw->slaves[1].ndev);
2905         unregister_netdev(ndev);
2906
2907         cpsw_ale_destroy(cpsw->ale);
2908         cpdma_ctlr_destroy(cpsw->dma);
2909         cpsw_remove_dt(pdev);
2910         pm_runtime_put_sync(&pdev->dev);
2911         pm_runtime_disable(&pdev->dev);
2912         if (cpsw->data.dual_emac)
2913                 free_netdev(cpsw->slaves[1].ndev);
2914         free_netdev(ndev);
2915         return 0;
2916 }
2917
2918 #ifdef CONFIG_PM_SLEEP
2919 static int cpsw_suspend(struct device *dev)
2920 {
2921         struct platform_device  *pdev = to_platform_device(dev);
2922         struct net_device       *ndev = platform_get_drvdata(pdev);
2923         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
2924
2925         if (cpsw->data.dual_emac) {
2926                 int i;
2927
2928                 for (i = 0; i < cpsw->data.slaves; i++) {
2929                         if (netif_running(cpsw->slaves[i].ndev))
2930                                 cpsw_ndo_stop(cpsw->slaves[i].ndev);
2931                 }
2932         } else {
2933                 if (netif_running(ndev))
2934                         cpsw_ndo_stop(ndev);
2935         }
2936
2937         /* Select sleep pin state */
2938         pinctrl_pm_select_sleep_state(dev);
2939
2940         return 0;
2941 }
2942
2943 static int cpsw_resume(struct device *dev)
2944 {
2945         struct platform_device  *pdev = to_platform_device(dev);
2946         struct net_device       *ndev = platform_get_drvdata(pdev);
2947         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
2948
2949         /* Select default pin state */
2950         pinctrl_pm_select_default_state(dev);
2951
2952         /* shut up ASSERT_RTNL() warning in netif_set_real_num_tx/rx_queues */
2953         rtnl_lock();
2954         if (cpsw->data.dual_emac) {
2955                 int i;
2956
2957                 for (i = 0; i < cpsw->data.slaves; i++) {
2958                         if (netif_running(cpsw->slaves[i].ndev))
2959                                 cpsw_ndo_open(cpsw->slaves[i].ndev);
2960                 }
2961         } else {
2962                 if (netif_running(ndev))
2963                         cpsw_ndo_open(ndev);
2964         }
2965         rtnl_unlock();
2966
2967         return 0;
2968 }
2969 #endif
2970
2971 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
2972
2973 static struct platform_driver cpsw_driver = {
2974         .driver = {
2975                 .name    = "cpsw",
2976                 .pm      = &cpsw_pm_ops,
2977                 .of_match_table = cpsw_of_mtable,
2978         },
2979         .probe = cpsw_probe,
2980         .remove = cpsw_remove,
2981 };
2982
2983 module_platform_driver(cpsw_driver);
2984
2985 MODULE_LICENSE("GPL");
2986 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2987 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2988 MODULE_DESCRIPTION("TI CPSW Ethernet driver");