drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
   4  * DWC Ether MAC version 4.00  has been used for developing this code.
   5  *
   6  * This only implements the mac core functions for this chip.
   7  *
   8  * Copyright (C) 2015  STMicroelectronics Ltd
   9  *
  10  * Author: Alexandre Torgue <alexandre.torgue@st.com>
  11  */
  12
  13 #include <linux/crc32.h>
  14 #include <linux/slab.h>
  15 #include <linux/ethtool.h>
  16 #include <linux/io.h>
  17 #include <net/dsa.h>
  18 #include "stmmac.h"
  19 #include "stmmac_pcs.h"
  20 #include "dwmac4.h"
  21 #include "dwmac5.h"
  22
  23 static void dwmac4_core_init(struct mac_device_info *hw,
  24                              struct net_device *dev)
  25 {
  26         void __iomem *ioaddr = hw->pcsr;
  27         u32 value = readl(ioaddr + GMAC_CONFIG);
  28
  29         value |= GMAC_CORE_INIT;
  30
  31         if (hw->ps) {
  32                 value |= GMAC_CONFIG_TE;
  33
  34                 value &= hw->link.speed_mask;
  35                 switch (hw->ps) {
  36                 case SPEED_1000:
  37                         value |= hw->link.speed1000;
  38                         break;
  39                 case SPEED_100:
  40                         value |= hw->link.speed100;
  41                         break;
  42                 case SPEED_10:
  43                         value |= hw->link.speed10;
  44                         break;
  45                 }
  46         }
  47
  48         writel(value, ioaddr + GMAC_CONFIG);
  49
  50         /* Enable GMAC interrupts */
  51         value = GMAC_INT_DEFAULT_ENABLE;
  52
  53         if (hw->pcs)
  54                 value |= GMAC_PCS_IRQ_DEFAULT;
  55
  56         writel(value, ioaddr + GMAC_INT_EN);
  57 }
  58
  59 static void dwmac4_rx_queue_enable(struct mac_device_info *hw,
  60                                    u8 mode, u32 queue)
  61 {
  62         void __iomem *ioaddr = hw->pcsr;
  63         u32 value = readl(ioaddr + GMAC_RXQ_CTRL0);
  64
  65         value &= GMAC_RX_QUEUE_CLEAR(queue);
  66         if (mode == MTL_QUEUE_AVB)
  67                 value |= GMAC_RX_AV_QUEUE_ENABLE(queue);
  68         else if (mode == MTL_QUEUE_DCB)
  69                 value |= GMAC_RX_DCB_QUEUE_ENABLE(queue);
  70
  71         writel(value, ioaddr + GMAC_RXQ_CTRL0);
  72 }
  73
  74 static void dwmac4_rx_queue_priority(struct mac_device_info *hw,
  75                                      u32 prio, u32 queue)
  76 {
  77         void __iomem *ioaddr = hw->pcsr;
  78         u32 base_register;
  79         u32 value;
  80
  81         base_register = (queue < 4) ? GMAC_RXQ_CTRL2 : GMAC_RXQ_CTRL3;
  82         if (queue >= 4)
  83                 queue -= 4;
  84
  85         value = readl(ioaddr + base_register);
  86
  87         value &= ~GMAC_RXQCTRL_PSRQX_MASK(queue);
  88         value |= (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) &
  89                                                 GMAC_RXQCTRL_PSRQX_MASK(queue);
  90         writel(value, ioaddr + base_register);
  91 }
  92
  93 static void dwmac4_tx_queue_priority(struct mac_device_info *hw,
  94                                      u32 prio, u32 queue)
  95 {
  96         void __iomem *ioaddr = hw->pcsr;
  97         u32 base_register;
  98         u32 value;
  99
 100         base_register = (queue < 4) ? GMAC_TXQ_PRTY_MAP0 : GMAC_TXQ_PRTY_MAP1;
 101         if (queue >= 4)
 102                 queue -= 4;
 103
 104         value = readl(ioaddr + base_register);
 105
 106         value &= ~GMAC_TXQCTRL_PSTQX_MASK(queue);
 107         value |= (prio << GMAC_TXQCTRL_PSTQX_SHIFT(queue)) &
 108                                                 GMAC_TXQCTRL_PSTQX_MASK(queue);
 109
 110         writel(value, ioaddr + base_register);
 111 }
 112
 113 static void dwmac4_rx_queue_routing(struct mac_device_info *hw,
 114                                     u8 packet, u32 queue)
 115 {
 116         void __iomem *ioaddr = hw->pcsr;
 117         u32 value;
 118
 119         static const struct stmmac_rx_routing route_possibilities[] = {
 120                 { GMAC_RXQCTRL_AVCPQ_MASK, GMAC_RXQCTRL_AVCPQ_SHIFT },
 121                 { GMAC_RXQCTRL_PTPQ_MASK, GMAC_RXQCTRL_PTPQ_SHIFT },
 122                 { GMAC_RXQCTRL_DCBCPQ_MASK, GMAC_RXQCTRL_DCBCPQ_SHIFT },
 123                 { GMAC_RXQCTRL_UPQ_MASK, GMAC_RXQCTRL_UPQ_SHIFT },
 124                 { GMAC_RXQCTRL_MCBCQ_MASK, GMAC_RXQCTRL_MCBCQ_SHIFT },
 125         };
 126
 127         value = readl(ioaddr + GMAC_RXQ_CTRL1);
 128
 129         /* routing configuration */
 130         value &= ~route_possibilities[packet - 1].reg_mask;
 131         value |= (queue << route_possibilities[packet-1].reg_shift) &
 132                  route_possibilities[packet - 1].reg_mask;
 133
 134         /* some packets require extra ops */
 135         if (packet == PACKET_AVCPQ) {
 136                 value &= ~GMAC_RXQCTRL_TACPQE;
 137                 value |= 0x1 << GMAC_RXQCTRL_TACPQE_SHIFT;
 138         } else if (packet == PACKET_MCBCQ) {
 139                 value &= ~GMAC_RXQCTRL_MCBCQEN;
 140                 value |= 0x1 << GMAC_RXQCTRL_MCBCQEN_SHIFT;
 141         }
 142
 143         writel(value, ioaddr + GMAC_RXQ_CTRL1);
 144 }
 145
 146 static void dwmac4_prog_mtl_rx_algorithms(struct mac_device_info *hw,
 147                                           u32 rx_alg)
 148 {
 149         void __iomem *ioaddr = hw->pcsr;
 150         u32 value = readl(ioaddr + MTL_OPERATION_MODE);
 151
 152         value &= ~MTL_OPERATION_RAA;
 153         switch (rx_alg) {
 154         case MTL_RX_ALGORITHM_SP:
 155                 value |= MTL_OPERATION_RAA_SP;
 156                 break;
 157         case MTL_RX_ALGORITHM_WSP:
 158                 value |= MTL_OPERATION_RAA_WSP;
 159                 break;
 160         default:
 161                 break;
 162         }
 163
 164         writel(value, ioaddr + MTL_OPERATION_MODE);
 165 }
 166
 167 static void dwmac4_prog_mtl_tx_algorithms(struct mac_device_info *hw,
 168                                           u32 tx_alg)
 169 {
 170         void __iomem *ioaddr = hw->pcsr;
 171         u32 value = readl(ioaddr + MTL_OPERATION_MODE);
 172
 173         value &= ~MTL_OPERATION_SCHALG_MASK;
 174         switch (tx_alg) {
 175         case MTL_TX_ALGORITHM_WRR:
 176                 value |= MTL_OPERATION_SCHALG_WRR;
 177                 break;
 178         case MTL_TX_ALGORITHM_WFQ:
 179                 value |= MTL_OPERATION_SCHALG_WFQ;
 180                 break;
 181         case MTL_TX_ALGORITHM_DWRR:
 182                 value |= MTL_OPERATION_SCHALG_DWRR;
 183                 break;
 184         case MTL_TX_ALGORITHM_SP:
 185                 value |= MTL_OPERATION_SCHALG_SP;
 186                 break;
 187         default:
 188                 break;
 189         }
 190
 191         writel(value, ioaddr + MTL_OPERATION_MODE);
 192 }
 193
 194 static void dwmac4_set_mtl_tx_queue_weight(struct mac_device_info *hw,
 195                                            u32 weight, u32 queue)
 196 {
 197         void __iomem *ioaddr = hw->pcsr;
 198         u32 value = readl(ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
 199
 200         value &= ~MTL_TXQ_WEIGHT_ISCQW_MASK;
 201         value |= weight & MTL_TXQ_WEIGHT_ISCQW_MASK;
 202         writel(value, ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
 203 }
 204
 205 static void dwmac4_map_mtl_dma(struct mac_device_info *hw, u32 queue, u32 chan)
 206 {
 207         void __iomem *ioaddr = hw->pcsr;
 208         u32 value;
 209
 210         if (queue < 4)
 211                 value = readl(ioaddr + MTL_RXQ_DMA_MAP0);
 212         else
 213                 value = readl(ioaddr + MTL_RXQ_DMA_MAP1);
 214
 215         if (queue == 0 || queue == 4) {
 216                 value &= ~MTL_RXQ_DMA_Q04MDMACH_MASK;
 217                 value |= MTL_RXQ_DMA_Q04MDMACH(chan);
 218         } else {
 219                 value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue);
 220                 value |= MTL_RXQ_DMA_QXMDMACH(chan, queue);
 221         }
 222
 223         if (queue < 4)
 224                 writel(value, ioaddr + MTL_RXQ_DMA_MAP0);
 225         else
 226                 writel(value, ioaddr + MTL_RXQ_DMA_MAP1);
 227 }
 228
 229 static void dwmac4_config_cbs(struct mac_device_info *hw,
 230                               u32 send_slope, u32 idle_slope,
 231                               u32 high_credit, u32 low_credit, u32 queue)
 232 {
 233         void __iomem *ioaddr = hw->pcsr;
 234         u32 value;
 235
 236         pr_debug("Queue %d configured as AVB. Parameters:\n", queue);
 237         pr_debug("\tsend_slope: 0x%08x\n", send_slope);
 238         pr_debug("\tidle_slope: 0x%08x\n", idle_slope);
 239         pr_debug("\thigh_credit: 0x%08x\n", high_credit);
 240         pr_debug("\tlow_credit: 0x%08x\n", low_credit);
 241
 242         /* enable AV algorithm */
 243         value = readl(ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue));
 244         value |= MTL_ETS_CTRL_AVALG;
 245         value |= MTL_ETS_CTRL_CC;
 246         writel(value, ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue));
 247
 248         /* configure send slope */
 249         value = readl(ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue));
 250         value &= ~MTL_SEND_SLP_CRED_SSC_MASK;
 251         value |= send_slope & MTL_SEND_SLP_CRED_SSC_MASK;
 252         writel(value, ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue));
 253
 254         /* configure idle slope (same register as tx weight) */
 255         dwmac4_set_mtl_tx_queue_weight(hw, idle_slope, queue);
 256
 257         /* configure high credit */
 258         value = readl(ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue));
 259         value &= ~MTL_HIGH_CRED_HC_MASK;
 260         value |= high_credit & MTL_HIGH_CRED_HC_MASK;
 261         writel(value, ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue));
 262
 263         /* configure high credit */
 264         value = readl(ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue));
 265         value &= ~MTL_HIGH_CRED_LC_MASK;
 266         value |= low_credit & MTL_HIGH_CRED_LC_MASK;
 267         writel(value, ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue));
 268 }
 269
 270 static void dwmac4_dump_regs(struct mac_device_info *hw, u32 *reg_space)
 271 {
 272         void __iomem *ioaddr = hw->pcsr;
 273         int i;
 274
 275         for (i = 0; i < GMAC_REG_NUM; i++)
 276                 reg_space[i] = readl(ioaddr + i * 4);
 277 }
 278
 279 static int dwmac4_rx_ipc_enable(struct mac_device_info *hw)
 280 {
 281         void __iomem *ioaddr = hw->pcsr;
 282         u32 value = readl(ioaddr + GMAC_CONFIG);
 283
 284         if (hw->rx_csum)
 285                 value |= GMAC_CONFIG_IPC;
 286         else
 287                 value &= ~GMAC_CONFIG_IPC;
 288
 289         writel(value, ioaddr + GMAC_CONFIG);
 290
 291         value = readl(ioaddr + GMAC_CONFIG);
 292
 293         return !!(value & GMAC_CONFIG_IPC);
 294 }
 295
 296 static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode)
 297 {
 298         void __iomem *ioaddr = hw->pcsr;
 299         unsigned int pmt = 0;
 300         u32 config;
 301
 302         if (mode & WAKE_MAGIC) {
 303                 pr_debug("GMAC: WOL Magic frame\n");
 304                 pmt |= power_down | magic_pkt_en;
 305         }
 306         if (mode & WAKE_UCAST) {
 307                 pr_debug("GMAC: WOL on global unicast\n");
 308                 pmt |= power_down | global_unicast | wake_up_frame_en;
 309         }
 310
 311         if (pmt) {
 312                 /* The receiver must be enabled for WOL before powering down */
 313                 config = readl(ioaddr + GMAC_CONFIG);
 314                 config |= GMAC_CONFIG_RE;
 315                 writel(config, ioaddr + GMAC_CONFIG);
 316         }
 317         writel(pmt, ioaddr + GMAC_PMT);
 318 }
 319
 320 static void dwmac4_set_umac_addr(struct mac_device_info *hw,
 321                                  unsigned char *addr, unsigned int reg_n)
 322 {
 323         void __iomem *ioaddr = hw->pcsr;
 324
 325         stmmac_dwmac4_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 326                                    GMAC_ADDR_LOW(reg_n));
 327 }
 328
 329 static void dwmac4_get_umac_addr(struct mac_device_info *hw,
 330                                  unsigned char *addr, unsigned int reg_n)
 331 {
 332         void __iomem *ioaddr = hw->pcsr;
 333
 334         stmmac_dwmac4_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 335                                    GMAC_ADDR_LOW(reg_n));
 336 }
 337
 338 static void dwmac4_set_eee_mode(struct mac_device_info *hw,
 339                                 bool en_tx_lpi_clockgating)
 340 {
 341         void __iomem *ioaddr = hw->pcsr;
 342         u32 value;
 343
 344         /* Enable the link status receive on RGMII, SGMII ore SMII
 345          * receive path and instruct the transmit to enter in LPI
 346          * state.
 347          */
 348         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 349         value |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;
 350
 351         if (en_tx_lpi_clockgating)
 352                 value |= GMAC4_LPI_CTRL_STATUS_LPITCSE;
 353
 354         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 355 }
 356
 357 static void dwmac4_reset_eee_mode(struct mac_device_info *hw)
 358 {
 359         void __iomem *ioaddr = hw->pcsr;
 360         u32 value;
 361
 362         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 363         value &= ~(GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA);
 364         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 365 }
 366
 367 static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link)
 368 {
 369         void __iomem *ioaddr = hw->pcsr;
 370         u32 value;
 371
 372         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 373
 374         if (link)
 375                 value |= GMAC4_LPI_CTRL_STATUS_PLS;
 376         else
 377                 value &= ~GMAC4_LPI_CTRL_STATUS_PLS;
 378
 379         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 380 }
 381
 382 static void dwmac4_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
 383 {
 384         void __iomem *ioaddr = hw->pcsr;
 385         int value = ((tw & 0xffff)) | ((ls & 0x3ff) << 16);
 386
 387         /* Program the timers in the LPI timer control register:
 388          * LS: minimum time (ms) for which the link
 389          *  status from PHY should be ok before transmitting
 390          *  the LPI pattern.
 391          * TW: minimum time (us) for which the core waits
 392          *  after it has stopped transmitting the LPI pattern.
 393          */
 394         writel(value, ioaddr + GMAC4_LPI_TIMER_CTRL);
 395 }
 396
 397 static void dwmac4_write_single_vlan(struct net_device *dev, u16 vid)
 398 {
 399         void __iomem *ioaddr = (void __iomem *)dev->base_addr;
 400         u32 val;
 401
 402         val = readl(ioaddr + GMAC_VLAN_TAG);
 403         val &= ~GMAC_VLAN_TAG_VID;
 404         val |= GMAC_VLAN_TAG_ETV | vid;
 405
 406         writel(val, ioaddr + GMAC_VLAN_TAG);
 407 }
 408
 409 static int dwmac4_write_vlan_filter(struct net_device *dev,
 410                                     struct mac_device_info *hw,
 411                                     u8 index, u32 data)
 412 {
 413         void __iomem *ioaddr = (void __iomem *)dev->base_addr;
 414         int i, timeout = 10;
 415         u32 val;
 416
 417         if (index >= hw->num_vlan)
 418                 return -EINVAL;
 419
 420         writel(data, ioaddr + GMAC_VLAN_TAG_DATA);
 421
 422         val = readl(ioaddr + GMAC_VLAN_TAG);
 423         val &= ~(GMAC_VLAN_TAG_CTRL_OFS_MASK |
 424                 GMAC_VLAN_TAG_CTRL_CT |
 425                 GMAC_VLAN_TAG_CTRL_OB);
 426         val |= (index << GMAC_VLAN_TAG_CTRL_OFS_SHIFT) | GMAC_VLAN_TAG_CTRL_OB;
 427
 428         writel(val, ioaddr + GMAC_VLAN_TAG);
 429
 430         for (i = 0; i < timeout; i++) {
 431                 val = readl(ioaddr + GMAC_VLAN_TAG);
 432                 if (!(val & GMAC_VLAN_TAG_CTRL_OB))
 433                         return 0;
 434                 udelay(1);
 435         }
 436
 437         netdev_err(dev, "Timeout accessing MAC_VLAN_Tag_Filter\n");
 438
 439         return -EBUSY;
 440 }
 441
 442 static int dwmac4_add_hw_vlan_rx_fltr(struct net_device *dev,
 443                                       struct mac_device_info *hw,
 444                                       __be16 proto, u16 vid)
 445 {
 446         int index = -1;
 447         u32 val = 0;
 448         int i, ret;
 449
 450         if (vid > 4095)
 451                 return -EINVAL;
 452
 453         /* Single Rx VLAN Filter */
 454         if (hw->num_vlan == 1) {
 455                 /* For single VLAN filter, VID 0 means VLAN promiscuous */
 456                 if (vid == 0) {
 457                         netdev_warn(dev, "Adding VLAN ID 0 is not supported\n");
 458                         return -EPERM;
 459                 }
 460
 461                 if (hw->vlan_filter[0] & GMAC_VLAN_TAG_VID) {
 462                         netdev_err(dev, "Only single VLAN ID supported\n");
 463                         return -EPERM;
 464                 }
 465
 466                 hw->vlan_filter[0] = vid;
 467                 dwmac4_write_single_vlan(dev, vid);
 468
 469                 return 0;
 470         }
 471
 472         /* Extended Rx VLAN Filter Enable */
 473         val |= GMAC_VLAN_TAG_DATA_ETV | GMAC_VLAN_TAG_DATA_VEN | vid;
 474
 475         for (i = 0; i < hw->num_vlan; i++) {
 476                 if (hw->vlan_filter[i] == val)
 477                         return 0;
 478                 else if (!(hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VEN))
 479                         index = i;
 480         }
 481
 482         if (index == -1) {
 483                 netdev_err(dev, "MAC_VLAN_Tag_Filter full (size: %0u)\n",
 484                            hw->num_vlan);
 485                 return -EPERM;
 486         }
 487
 488         ret = dwmac4_write_vlan_filter(dev, hw, index, val);
 489
 490         if (!ret)
 491                 hw->vlan_filter[index] = val;
 492
 493         return ret;
 494 }
 495
 496 static int dwmac4_del_hw_vlan_rx_fltr(struct net_device *dev,
 497                                       struct mac_device_info *hw,
 498                                       __be16 proto, u16 vid)
 499 {
 500         int i, ret = 0;
 501
 502         /* Single Rx VLAN Filter */
 503         if (hw->num_vlan == 1) {
 504                 if ((hw->vlan_filter[0] & GMAC_VLAN_TAG_VID) == vid) {
 505                         hw->vlan_filter[0] = 0;
 506                         dwmac4_write_single_vlan(dev, 0);
 507                 }
 508                 return 0;
 509         }
 510
 511         /* Extended Rx VLAN Filter Enable */
 512         for (i = 0; i < hw->num_vlan; i++) {
 513                 if ((hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VID) == vid) {
 514                         ret = dwmac4_write_vlan_filter(dev, hw, i, 0);
 515
 516                         if (!ret)
 517                                 hw->vlan_filter[i] = 0;
 518                         else
 519                                 return ret;
 520                 }
 521         }
 522
 523         return ret;
 524 }
 525
 526 static void dwmac4_restore_hw_vlan_rx_fltr(struct net_device *dev,
 527                                            struct mac_device_info *hw)
 528 {
 529         u32 val;
 530         int i;
 531
 532         /* Single Rx VLAN Filter */
 533         if (hw->num_vlan == 1) {
 534                 dwmac4_write_single_vlan(dev, hw->vlan_filter[0]);
 535                 return;
 536         }
 537
 538         /* Extended Rx VLAN Filter Enable */
 539         for (i = 0; i < hw->num_vlan; i++) {
 540                 if (hw->vlan_filter[i] & GMAC_VLAN_TAG_DATA_VEN) {
 541                         val = hw->vlan_filter[i];
 542                         dwmac4_write_vlan_filter(dev, hw, i, val);
 543                 }
 544         }
 545 }
 546
 547 static void dwmac4_set_filter(struct mac_device_info *hw,
 548                               struct net_device *dev)
 549 {
 550         void __iomem *ioaddr = (void __iomem *)dev->base_addr;
 551         int numhashregs = (hw->multicast_filter_bins >> 5);
 552         int mcbitslog2 = hw->mcast_bits_log2;
 553         unsigned int value;
 554         u32 mc_filter[8];
 555         int i;
 556
 557         memset(mc_filter, 0, sizeof(mc_filter));
 558
 559         value = readl(ioaddr + GMAC_PACKET_FILTER);
 560         value &= ~GMAC_PACKET_FILTER_HMC;
 561         value &= ~GMAC_PACKET_FILTER_HPF;
 562         value &= ~GMAC_PACKET_FILTER_PCF;
 563         value &= ~GMAC_PACKET_FILTER_PM;
 564         value &= ~GMAC_PACKET_FILTER_PR;
 565         if (dev->flags & IFF_PROMISC) {
 566                 value = GMAC_PACKET_FILTER_PR | GMAC_PACKET_FILTER_PCF;
 567         } else if ((dev->flags & IFF_ALLMULTI) ||
 568                    (netdev_mc_count(dev) > hw->multicast_filter_bins)) {
 569                 /* Pass all multi */
 570                 value |= GMAC_PACKET_FILTER_PM;
 571                 /* Set all the bits of the HASH tab */
 572                 memset(mc_filter, 0xff, sizeof(mc_filter));
 573         } else if (!netdev_mc_empty(dev) && (dev->flags & IFF_MULTICAST)) {
 574                 struct netdev_hw_addr *ha;
 575
 576                 /* Hash filter for multicast */
 577                 value |= GMAC_PACKET_FILTER_HMC;
 578
 579                 netdev_for_each_mc_addr(ha, dev) {
 580                         /* The upper n bits of the calculated CRC are used to
 581                          * index the contents of the hash table. The number of
 582                          * bits used depends on the hardware configuration
 583                          * selected at core configuration time.
 584                          */
 585                         u32 bit_nr = bitrev32(~crc32_le(~0, ha->addr,
 586                                         ETH_ALEN)) >> (32 - mcbitslog2);
 587                         /* The most significant bit determines the register to
 588                          * use (H/L) while the other 5 bits determine the bit
 589                          * within the register.
 590                          */
 591                         mc_filter[bit_nr >> 5] |= (1 << (bit_nr & 0x1f));
 592                 }
 593         }
 594
 595         for (i = 0; i < numhashregs; i++)
 596                 writel(mc_filter[i], ioaddr + GMAC_HASH_TAB(i));
 597
 598         value |= GMAC_PACKET_FILTER_HPF;
 599
 600         /* Handle multiple unicast addresses */
 601         if (netdev_uc_count(dev) > hw->unicast_filter_entries) {
 602                 /* Switch to promiscuous mode if more than 128 addrs
 603                  * are required
 604                  */
 605                 value |= GMAC_PACKET_FILTER_PR;
 606         } else {
 607                 struct netdev_hw_addr *ha;
 608                 int reg = 1;
 609
 610                 netdev_for_each_uc_addr(ha, dev) {
 611                         dwmac4_set_umac_addr(hw, ha->addr, reg);
 612                         reg++;
 613                 }
 614
 615                 while (reg < GMAC_MAX_PERFECT_ADDRESSES) {
 616                         writel(0, ioaddr + GMAC_ADDR_HIGH(reg));
 617                         writel(0, ioaddr + GMAC_ADDR_LOW(reg));
 618                         reg++;
 619                 }
 620         }
 621
 622         /* VLAN filtering */
 623         if (dev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
 624                 value |= GMAC_PACKET_FILTER_VTFE;
 625
 626         writel(value, ioaddr + GMAC_PACKET_FILTER);
 627 }
 628
 629 static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
 630                              unsigned int fc, unsigned int pause_time,
 631                              u32 tx_cnt)
 632 {
 633         void __iomem *ioaddr = hw->pcsr;
 634         unsigned int flow = 0;
 635         u32 queue = 0;
 636
 637         pr_debug("GMAC Flow-Control:\n");
 638         if (fc & FLOW_RX) {
 639                 pr_debug("\tReceive Flow-Control ON\n");
 640                 flow |= GMAC_RX_FLOW_CTRL_RFE;
 641         }
 642         writel(flow, ioaddr + GMAC_RX_FLOW_CTRL);
 643
 644         if (fc & FLOW_TX) {
 645                 pr_debug("\tTransmit Flow-Control ON\n");
 646
 647                 if (duplex)
 648                         pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
 649
 650                 for (queue = 0; queue < tx_cnt; queue++) {
 651                         flow = GMAC_TX_FLOW_CTRL_TFE;
 652
 653                         if (duplex)
 654                                 flow |=
 655                                 (pause_time << GMAC_TX_FLOW_CTRL_PT_SHIFT);
 656
 657                         writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
 658                 }
 659         } else {
 660                 for (queue = 0; queue < tx_cnt; queue++)
 661                         writel(0, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
 662         }
 663 }
 664
 665 static void dwmac4_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
 666                             bool loopback)
 667 {
 668         dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
 669 }
 670
 671 static void dwmac4_rane(void __iomem *ioaddr, bool restart)
 672 {
 673         dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
 674 }
 675
 676 static void dwmac4_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
 677 {
 678         dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
 679 }
 680
 681 /* RGMII or SMII interface */
 682 static void dwmac4_phystatus(void __iomem *ioaddr, struct stmmac_extra_stats *x)
 683 {
 684         u32 status;
 685
 686         status = readl(ioaddr + GMAC_PHYIF_CONTROL_STATUS);
 687         x->irq_rgmii_n++;
 688
 689         /* Check the link status */
 690         if (status & GMAC_PHYIF_CTRLSTATUS_LNKSTS) {
 691                 int speed_value;
 692
 693                 x->pcs_link = 1;
 694
 695                 speed_value = ((status & GMAC_PHYIF_CTRLSTATUS_SPEED) >>
 696                                GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT);
 697                 if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_125)
 698                         x->pcs_speed = SPEED_1000;
 699                 else if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_25)
 700                         x->pcs_speed = SPEED_100;
 701                 else
 702                         x->pcs_speed = SPEED_10;
 703
 704                 x->pcs_duplex = (status & GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK);
 705
 706                 pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
 707                         x->pcs_duplex ? "Full" : "Half");
 708         } else {
 709                 x->pcs_link = 0;
 710                 pr_info("Link is Down\n");
 711         }
 712 }
 713
 714 static int dwmac4_irq_mtl_status(struct mac_device_info *hw, u32 chan)
 715 {
 716         void __iomem *ioaddr = hw->pcsr;
 717         u32 mtl_int_qx_status;
 718         int ret = 0;
 719
 720         mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS);
 721
 722         /* Check MTL Interrupt */
 723         if (mtl_int_qx_status & MTL_INT_QX(chan)) {
 724                 /* read Queue x Interrupt status */
 725                 u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(chan));
 726
 727                 if (status & MTL_RX_OVERFLOW_INT) {
 728                         /*  clear Interrupt */
 729                         writel(status | MTL_RX_OVERFLOW_INT,
 730                                ioaddr + MTL_CHAN_INT_CTRL(chan));
 731                         ret = CORE_IRQ_MTL_RX_OVERFLOW;
 732                 }
 733         }
 734
 735         return ret;
 736 }
 737
 738 static int dwmac4_irq_status(struct mac_device_info *hw,
 739                              struct stmmac_extra_stats *x)
 740 {
 741         void __iomem *ioaddr = hw->pcsr;
 742         u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
 743         u32 intr_enable = readl(ioaddr + GMAC_INT_EN);
 744         int ret = 0;
 745
 746         /* Discard disabled bits */
 747         intr_status &= intr_enable;
 748
 749         /* Not used events (e.g. MMC interrupts) are not handled. */
 750         if ((intr_status & mmc_tx_irq))
 751                 x->mmc_tx_irq_n++;
 752         if (unlikely(intr_status & mmc_rx_irq))
 753                 x->mmc_rx_irq_n++;
 754         if (unlikely(intr_status & mmc_rx_csum_offload_irq))
 755                 x->mmc_rx_csum_offload_irq_n++;
 756         /* Clear the PMT bits 5 and 6 by reading the PMT status reg */
 757         if (unlikely(intr_status & pmt_irq)) {
 758                 readl(ioaddr + GMAC_PMT);
 759                 x->irq_receive_pmt_irq_n++;
 760         }
 761
 762         /* MAC tx/rx EEE LPI entry/exit interrupts */
 763         if (intr_status & lpi_irq) {
 764                 /* Clear LPI interrupt by reading MAC_LPI_Control_Status */
 765                 u32 status = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 766
 767                 if (status & GMAC4_LPI_CTRL_STATUS_TLPIEN) {
 768                         ret |= CORE_IRQ_TX_PATH_IN_LPI_MODE;
 769                         x->irq_tx_path_in_lpi_mode_n++;
 770                 }
 771                 if (status & GMAC4_LPI_CTRL_STATUS_TLPIEX) {
 772                         ret |= CORE_IRQ_TX_PATH_EXIT_LPI_MODE;
 773                         x->irq_tx_path_exit_lpi_mode_n++;
 774                 }
 775                 if (status & GMAC4_LPI_CTRL_STATUS_RLPIEN)
 776                         x->irq_rx_path_in_lpi_mode_n++;
 777                 if (status & GMAC4_LPI_CTRL_STATUS_RLPIEX)
 778                         x->irq_rx_path_exit_lpi_mode_n++;
 779         }
 780
 781         dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
 782         if (intr_status & PCS_RGSMIIIS_IRQ)
 783                 dwmac4_phystatus(ioaddr, x);
 784
 785         return ret;
 786 }
 787
 788 static void dwmac4_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x,
 789                          u32 rx_queues, u32 tx_queues)
 790 {
 791         u32 value;
 792         u32 queue;
 793
 794         for (queue = 0; queue < tx_queues; queue++) {
 795                 value = readl(ioaddr + MTL_CHAN_TX_DEBUG(queue));
 796
 797                 if (value & MTL_DEBUG_TXSTSFSTS)
 798                         x->mtl_tx_status_fifo_full++;
 799                 if (value & MTL_DEBUG_TXFSTS)
 800                         x->mtl_tx_fifo_not_empty++;
 801                 if (value & MTL_DEBUG_TWCSTS)
 802                         x->mmtl_fifo_ctrl++;
 803                 if (value & MTL_DEBUG_TRCSTS_MASK) {
 804                         u32 trcsts = (value & MTL_DEBUG_TRCSTS_MASK)
 805                                      >> MTL_DEBUG_TRCSTS_SHIFT;
 806                         if (trcsts == MTL_DEBUG_TRCSTS_WRITE)
 807                                 x->mtl_tx_fifo_read_ctrl_write++;
 808                         else if (trcsts == MTL_DEBUG_TRCSTS_TXW)
 809                                 x->mtl_tx_fifo_read_ctrl_wait++;
 810                         else if (trcsts == MTL_DEBUG_TRCSTS_READ)
 811                                 x->mtl_tx_fifo_read_ctrl_read++;
 812                         else
 813                                 x->mtl_tx_fifo_read_ctrl_idle++;
 814                 }
 815                 if (value & MTL_DEBUG_TXPAUSED)
 816                         x->mac_tx_in_pause++;
 817         }
 818
 819         for (queue = 0; queue < rx_queues; queue++) {
 820                 value = readl(ioaddr + MTL_CHAN_RX_DEBUG(queue));
 821
 822                 if (value & MTL_DEBUG_RXFSTS_MASK) {
 823                         u32 rxfsts = (value & MTL_DEBUG_RXFSTS_MASK)
 824                                      >> MTL_DEBUG_RRCSTS_SHIFT;
 825
 826                         if (rxfsts == MTL_DEBUG_RXFSTS_FULL)
 827                                 x->mtl_rx_fifo_fill_level_full++;
 828                         else if (rxfsts == MTL_DEBUG_RXFSTS_AT)
 829                                 x->mtl_rx_fifo_fill_above_thresh++;
 830                         else if (rxfsts == MTL_DEBUG_RXFSTS_BT)
 831                                 x->mtl_rx_fifo_fill_below_thresh++;
 832                         else
 833                                 x->mtl_rx_fifo_fill_level_empty++;
 834                 }
 835                 if (value & MTL_DEBUG_RRCSTS_MASK) {
 836                         u32 rrcsts = (value & MTL_DEBUG_RRCSTS_MASK) >>
 837                                      MTL_DEBUG_RRCSTS_SHIFT;
 838
 839                         if (rrcsts == MTL_DEBUG_RRCSTS_FLUSH)
 840                                 x->mtl_rx_fifo_read_ctrl_flush++;
 841                         else if (rrcsts == MTL_DEBUG_RRCSTS_RSTAT)
 842                                 x->mtl_rx_fifo_read_ctrl_read_data++;
 843                         else if (rrcsts == MTL_DEBUG_RRCSTS_RDATA)
 844                                 x->mtl_rx_fifo_read_ctrl_status++;
 845                         else
 846                                 x->mtl_rx_fifo_read_ctrl_idle++;
 847                 }
 848                 if (value & MTL_DEBUG_RWCSTS)
 849                         x->mtl_rx_fifo_ctrl_active++;
 850         }
 851
 852         /* GMAC debug */
 853         value = readl(ioaddr + GMAC_DEBUG);
 854
 855         if (value & GMAC_DEBUG_TFCSTS_MASK) {
 856                 u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
 857                               >> GMAC_DEBUG_TFCSTS_SHIFT;
 858
 859                 if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
 860                         x->mac_tx_frame_ctrl_xfer++;
 861                 else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
 862                         x->mac_tx_frame_ctrl_pause++;
 863                 else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
 864                         x->mac_tx_frame_ctrl_wait++;
 865                 else
 866                         x->mac_tx_frame_ctrl_idle++;
 867         }
 868         if (value & GMAC_DEBUG_TPESTS)
 869                 x->mac_gmii_tx_proto_engine++;
 870         if (value & GMAC_DEBUG_RFCFCSTS_MASK)
 871                 x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
 872                                             >> GMAC_DEBUG_RFCFCSTS_SHIFT;
 873         if (value & GMAC_DEBUG_RPESTS)
 874                 x->mac_gmii_rx_proto_engine++;
 875 }
 876
 877 static void dwmac4_set_mac_loopback(void __iomem *ioaddr, bool enable)
 878 {
 879         u32 value = readl(ioaddr + GMAC_CONFIG);
 880
 881         if (enable)
 882                 value |= GMAC_CONFIG_LM;
 883         else
 884                 value &= ~GMAC_CONFIG_LM;
 885
 886         writel(value, ioaddr + GMAC_CONFIG);
 887 }
 888
 889 static void dwmac4_update_vlan_hash(struct mac_device_info *hw, u32 hash,
 890                                     __le16 perfect_match, bool is_double)
 891 {
 892         void __iomem *ioaddr = hw->pcsr;
 893         u32 value;
 894
 895         writel(hash, ioaddr + GMAC_VLAN_HASH_TABLE);
 896
 897         value = readl(ioaddr + GMAC_VLAN_TAG);
 898
 899         if (hash) {
 900                 value |= GMAC_VLAN_VTHM | GMAC_VLAN_ETV;
 901                 if (is_double) {
 902                         value |= GMAC_VLAN_EDVLP;
 903                         value |= GMAC_VLAN_ESVL;
 904                         value |= GMAC_VLAN_DOVLTC;
 905                 }
 906
 907                 writel(value, ioaddr + GMAC_VLAN_TAG);
 908         } else if (perfect_match) {
 909                 u32 value = GMAC_VLAN_ETV;
 910
 911                 if (is_double) {
 912                         value |= GMAC_VLAN_EDVLP;
 913                         value |= GMAC_VLAN_ESVL;
 914                         value |= GMAC_VLAN_DOVLTC;
 915                 }
 916
 917                 writel(value | perfect_match, ioaddr + GMAC_VLAN_TAG);
 918         } else {
 919                 value &= ~(GMAC_VLAN_VTHM | GMAC_VLAN_ETV);
 920                 value &= ~(GMAC_VLAN_EDVLP | GMAC_VLAN_ESVL);
 921                 value &= ~GMAC_VLAN_DOVLTC;
 922                 value &= ~GMAC_VLAN_VID;
 923
 924                 writel(value, ioaddr + GMAC_VLAN_TAG);
 925         }
 926 }
 927
 928 static void dwmac4_sarc_configure(void __iomem *ioaddr, int val)
 929 {
 930         u32 value = readl(ioaddr + GMAC_CONFIG);
 931
 932         value &= ~GMAC_CONFIG_SARC;
 933         value |= val << GMAC_CONFIG_SARC_SHIFT;
 934
 935         writel(value, ioaddr + GMAC_CONFIG);
 936 }
 937
 938 static void dwmac4_enable_vlan(struct mac_device_info *hw, u32 type)
 939 {
 940         void __iomem *ioaddr = hw->pcsr;
 941         u32 value;
 942
 943         value = readl(ioaddr + GMAC_VLAN_INCL);
 944         value |= GMAC_VLAN_VLTI;
 945         value |= GMAC_VLAN_CSVL; /* Only use SVLAN */
 946         value &= ~GMAC_VLAN_VLC;
 947         value |= (type << GMAC_VLAN_VLC_SHIFT) & GMAC_VLAN_VLC;
 948         writel(value, ioaddr + GMAC_VLAN_INCL);
 949 }
 950
 951 static void dwmac4_set_arp_offload(struct mac_device_info *hw, bool en,
 952                                    u32 addr)
 953 {
 954         void __iomem *ioaddr = hw->pcsr;
 955         u32 value;
 956
 957         writel(addr, ioaddr + GMAC_ARP_ADDR);
 958
 959         value = readl(ioaddr + GMAC_CONFIG);
 960         if (en)
 961                 value |= GMAC_CONFIG_ARPEN;
 962         else
 963                 value &= ~GMAC_CONFIG_ARPEN;
 964         writel(value, ioaddr + GMAC_CONFIG);
 965 }
 966
 967 static int dwmac4_config_l3_filter(struct mac_device_info *hw, u32 filter_no,
 968                                    bool en, bool ipv6, bool sa, bool inv,
 969                                    u32 match)
 970 {
 971         void __iomem *ioaddr = hw->pcsr;
 972         u32 value;
 973
 974         value = readl(ioaddr + GMAC_PACKET_FILTER);
 975         value |= GMAC_PACKET_FILTER_IPFE;
 976         writel(value, ioaddr + GMAC_PACKET_FILTER);
 977
 978         value = readl(ioaddr + GMAC_L3L4_CTRL(filter_no));
 979
 980         /* For IPv6 not both SA/DA filters can be active */
 981         if (ipv6) {
 982                 value |= GMAC_L3PEN0;
 983                 value &= ~(GMAC_L3SAM0 | GMAC_L3SAIM0);
 984                 value &= ~(GMAC_L3DAM0 | GMAC_L3DAIM0);
 985                 if (sa) {
 986                         value |= GMAC_L3SAM0;
 987                         if (inv)
 988                                 value |= GMAC_L3SAIM0;
 989                 } else {
 990                         value |= GMAC_L3DAM0;
 991                         if (inv)
 992                                 value |= GMAC_L3DAIM0;
 993                 }
 994         } else {
 995                 value &= ~GMAC_L3PEN0;
 996                 if (sa) {
 997                         value |= GMAC_L3SAM0;
 998                         if (inv)
 999                                 value |= GMAC_L3SAIM0;
1000                 } else {
1001                         value |= GMAC_L3DAM0;
1002                         if (inv)
1003                                 value |= GMAC_L3DAIM0;
1004                 }
1005         }
1006
1007         writel(value, ioaddr + GMAC_L3L4_CTRL(filter_no));
1008
1009         if (sa) {
1010                 writel(match, ioaddr + GMAC_L3_ADDR0(filter_no));
1011         } else {
1012                 writel(match, ioaddr + GMAC_L3_ADDR1(filter_no));
1013         }
1014
1015         if (!en)
1016                 writel(0, ioaddr + GMAC_L3L4_CTRL(filter_no));
1017
1018         return 0;
1019 }
1020
1021 static int dwmac4_config_l4_filter(struct mac_device_info *hw, u32 filter_no,
1022                                    bool en, bool udp, bool sa, bool inv,
1023                                    u32 match)
1024 {
1025         void __iomem *ioaddr = hw->pcsr;
1026         u32 value;
1027
1028         value = readl(ioaddr + GMAC_PACKET_FILTER);
1029         value |= GMAC_PACKET_FILTER_IPFE;
1030         writel(value, ioaddr + GMAC_PACKET_FILTER);
1031
1032         value = readl(ioaddr + GMAC_L3L4_CTRL(filter_no));
1033         if (udp) {
1034                 value |= GMAC_L4PEN0;
1035         } else {
1036                 value &= ~GMAC_L4PEN0;
1037         }
1038
1039         value &= ~(GMAC_L4SPM0 | GMAC_L4SPIM0);
1040         value &= ~(GMAC_L4DPM0 | GMAC_L4DPIM0);
1041         if (sa) {
1042                 value |= GMAC_L4SPM0;
1043                 if (inv)
1044                         value |= GMAC_L4SPIM0;
1045         } else {
1046                 value |= GMAC_L4DPM0;
1047                 if (inv)
1048                         value |= GMAC_L4DPIM0;
1049         }
1050
1051         writel(value, ioaddr + GMAC_L3L4_CTRL(filter_no));
1052
1053         if (sa) {
1054                 value = match & GMAC_L4SP0;
1055         } else {
1056                 value = (match << GMAC_L4DP0_SHIFT) & GMAC_L4DP0;
1057         }
1058
1059         writel(value, ioaddr + GMAC_L4_ADDR(filter_no));
1060
1061         if (!en)
1062                 writel(0, ioaddr + GMAC_L3L4_CTRL(filter_no));
1063
1064         return 0;
1065 }
1066
1067 const struct stmmac_ops dwmac4_ops = {
1068         .core_init = dwmac4_core_init,
1069         .set_mac = stmmac_set_mac,
1070         .rx_ipc = dwmac4_rx_ipc_enable,
1071         .rx_queue_enable = dwmac4_rx_queue_enable,
1072         .rx_queue_prio = dwmac4_rx_queue_priority,
1073         .tx_queue_prio = dwmac4_tx_queue_priority,
1074         .rx_queue_routing = dwmac4_rx_queue_routing,
1075         .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
1076         .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
1077         .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
1078         .map_mtl_to_dma = dwmac4_map_mtl_dma,
1079         .config_cbs = dwmac4_config_cbs,
1080         .dump_regs = dwmac4_dump_regs,
1081         .host_irq_status = dwmac4_irq_status,
1082         .host_mtl_irq_status = dwmac4_irq_mtl_status,
1083         .flow_ctrl = dwmac4_flow_ctrl,
1084         .pmt = dwmac4_pmt,
1085         .set_umac_addr = dwmac4_set_umac_addr,
1086         .get_umac_addr = dwmac4_get_umac_addr,
1087         .set_eee_mode = dwmac4_set_eee_mode,
1088         .reset_eee_mode = dwmac4_reset_eee_mode,
1089         .set_eee_timer = dwmac4_set_eee_timer,
1090         .set_eee_pls = dwmac4_set_eee_pls,
1091         .pcs_ctrl_ane = dwmac4_ctrl_ane,
1092         .pcs_rane = dwmac4_rane,
1093         .pcs_get_adv_lp = dwmac4_get_adv_lp,
1094         .debug = dwmac4_debug,
1095         .set_filter = dwmac4_set_filter,
1096         .flex_pps_config = dwmac5_flex_pps_config,
1097         .set_mac_loopback = dwmac4_set_mac_loopback,
1098         .update_vlan_hash = dwmac4_update_vlan_hash,
1099         .sarc_configure = dwmac4_sarc_configure,
1100         .enable_vlan = dwmac4_enable_vlan,
1101         .set_arp_offload = dwmac4_set_arp_offload,
1102         .config_l3_filter = dwmac4_config_l3_filter,
1103         .config_l4_filter = dwmac4_config_l4_filter,
1104         .add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,
1105         .del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,
1106         .restore_hw_vlan_rx_fltr = dwmac4_restore_hw_vlan_rx_fltr,
1107 };
1108
1109 const struct stmmac_ops dwmac410_ops = {
1110         .core_init = dwmac4_core_init,
1111         .set_mac = stmmac_dwmac4_set_mac,
1112         .rx_ipc = dwmac4_rx_ipc_enable,
1113         .rx_queue_enable = dwmac4_rx_queue_enable,
1114         .rx_queue_prio = dwmac4_rx_queue_priority,
1115         .tx_queue_prio = dwmac4_tx_queue_priority,
1116         .rx_queue_routing = dwmac4_rx_queue_routing,
1117         .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
1118         .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
1119         .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
1120         .map_mtl_to_dma = dwmac4_map_mtl_dma,
1121         .config_cbs = dwmac4_config_cbs,
1122         .dump_regs = dwmac4_dump_regs,
1123         .host_irq_status = dwmac4_irq_status,
1124         .host_mtl_irq_status = dwmac4_irq_mtl_status,
1125         .flow_ctrl = dwmac4_flow_ctrl,
1126         .pmt = dwmac4_pmt,
1127         .set_umac_addr = dwmac4_set_umac_addr,
1128         .get_umac_addr = dwmac4_get_umac_addr,
1129         .set_eee_mode = dwmac4_set_eee_mode,
1130         .reset_eee_mode = dwmac4_reset_eee_mode,
1131         .set_eee_timer = dwmac4_set_eee_timer,
1132         .set_eee_pls = dwmac4_set_eee_pls,
1133         .pcs_ctrl_ane = dwmac4_ctrl_ane,
1134         .pcs_rane = dwmac4_rane,
1135         .pcs_get_adv_lp = dwmac4_get_adv_lp,
1136         .debug = dwmac4_debug,
1137         .set_filter = dwmac4_set_filter,
1138         .set_mac_loopback = dwmac4_set_mac_loopback,
1139         .update_vlan_hash = dwmac4_update_vlan_hash,
1140         .sarc_configure = dwmac4_sarc_configure,
1141         .enable_vlan = dwmac4_enable_vlan,
1142         .set_arp_offload = dwmac4_set_arp_offload,
1143         .config_l3_filter = dwmac4_config_l3_filter,
1144         .config_l4_filter = dwmac4_config_l4_filter,
1145         .est_configure = dwmac5_est_configure,
1146         .fpe_configure = dwmac5_fpe_configure,
1147         .add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,
1148         .del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,
1149         .restore_hw_vlan_rx_fltr = dwmac4_restore_hw_vlan_rx_fltr,
1150 };
1151
1152 const struct stmmac_ops dwmac510_ops = {
1153         .core_init = dwmac4_core_init,
1154         .set_mac = stmmac_dwmac4_set_mac,
1155         .rx_ipc = dwmac4_rx_ipc_enable,
1156         .rx_queue_enable = dwmac4_rx_queue_enable,
1157         .rx_queue_prio = dwmac4_rx_queue_priority,
1158         .tx_queue_prio = dwmac4_tx_queue_priority,
1159         .rx_queue_routing = dwmac4_rx_queue_routing,
1160         .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
1161         .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
1162         .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
1163         .map_mtl_to_dma = dwmac4_map_mtl_dma,
1164         .config_cbs = dwmac4_config_cbs,
1165         .dump_regs = dwmac4_dump_regs,
1166         .host_irq_status = dwmac4_irq_status,
1167         .host_mtl_irq_status = dwmac4_irq_mtl_status,
1168         .flow_ctrl = dwmac4_flow_ctrl,
1169         .pmt = dwmac4_pmt,
1170         .set_umac_addr = dwmac4_set_umac_addr,
1171         .get_umac_addr = dwmac4_get_umac_addr,
1172         .set_eee_mode = dwmac4_set_eee_mode,
1173         .reset_eee_mode = dwmac4_reset_eee_mode,
1174         .set_eee_timer = dwmac4_set_eee_timer,
1175         .set_eee_pls = dwmac4_set_eee_pls,
1176         .pcs_ctrl_ane = dwmac4_ctrl_ane,
1177         .pcs_rane = dwmac4_rane,
1178         .pcs_get_adv_lp = dwmac4_get_adv_lp,
1179         .debug = dwmac4_debug,
1180         .set_filter = dwmac4_set_filter,
1181         .safety_feat_config = dwmac5_safety_feat_config,
1182         .safety_feat_irq_status = dwmac5_safety_feat_irq_status,
1183         .safety_feat_dump = dwmac5_safety_feat_dump,
1184         .rxp_config = dwmac5_rxp_config,
1185         .flex_pps_config = dwmac5_flex_pps_config,
1186         .set_mac_loopback = dwmac4_set_mac_loopback,
1187         .update_vlan_hash = dwmac4_update_vlan_hash,
1188         .sarc_configure = dwmac4_sarc_configure,
1189         .enable_vlan = dwmac4_enable_vlan,
1190         .set_arp_offload = dwmac4_set_arp_offload,
1191         .config_l3_filter = dwmac4_config_l3_filter,
1192         .config_l4_filter = dwmac4_config_l4_filter,
1193         .est_configure = dwmac5_est_configure,
1194         .fpe_configure = dwmac5_fpe_configure,
1195         .add_hw_vlan_rx_fltr = dwmac4_add_hw_vlan_rx_fltr,
1196         .del_hw_vlan_rx_fltr = dwmac4_del_hw_vlan_rx_fltr,
1197         .restore_hw_vlan_rx_fltr = dwmac4_restore_hw_vlan_rx_fltr,
1198 };
1199
1200 static u32 dwmac4_get_num_vlan(void __iomem *ioaddr)
1201 {
1202         u32 val, num_vlan;
1203
1204         val = readl(ioaddr + GMAC_HW_FEATURE3);
1205         switch (val & GMAC_HW_FEAT_NRVF) {
1206         case 0:
1207                 num_vlan = 1;
1208                 break;
1209         case 1:
1210                 num_vlan = 4;
1211                 break;
1212         case 2:
1213                 num_vlan = 8;
1214                 break;
1215         case 3:
1216                 num_vlan = 16;
1217                 break;
1218         case 4:
1219                 num_vlan = 24;
1220                 break;
1221         case 5:
1222                 num_vlan = 32;
1223                 break;
1224         default:
1225                 num_vlan = 1;
1226         }
1227
1228         return num_vlan;
1229 }
1230
1231 int dwmac4_setup(struct stmmac_priv *priv)
1232 {
1233         struct mac_device_info *mac = priv->hw;
1234
1235         dev_info(priv->device, "\tDWMAC4/5\n");
1236
1237         priv->dev->priv_flags |= IFF_UNICAST_FLT;
1238         mac->pcsr = priv->ioaddr;
1239         mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
1240         mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
1241         mac->mcast_bits_log2 = 0;
1242
1243         if (mac->multicast_filter_bins)
1244                 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
1245
1246         mac->link.duplex = GMAC_CONFIG_DM;
1247         mac->link.speed10 = GMAC_CONFIG_PS;
1248         mac->link.speed100 = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
1249         mac->link.speed1000 = 0;
1250         mac->link.speed_mask = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
1251         mac->mii.addr = GMAC_MDIO_ADDR;
1252         mac->mii.data = GMAC_MDIO_DATA;
1253         mac->mii.addr_shift = 21;
1254         mac->mii.addr_mask = GENMASK(25, 21);
1255         mac->mii.reg_shift = 16;
1256         mac->mii.reg_mask = GENMASK(20, 16);
1257         mac->mii.clk_csr_shift = 8;
1258         mac->mii.clk_csr_mask = GENMASK(11, 8);
1259         mac->num_vlan = dwmac4_get_num_vlan(priv->ioaddr);
1260
1261         return 0;
1262 }