drivers/net/ethernet/sfc/farch.c

   1 /****************************************************************************
   2  * Driver for Solarflare network controllers and boards
   3  * Copyright 2005-2006 Fen Systems Ltd.
   4  * Copyright 2006-2013 Solarflare Communications Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation, incorporated herein by reference.
   9  */
  10
  11 #include <linux/bitops.h>
  12 #include <linux/delay.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/pci.h>
  15 #include <linux/module.h>
  16 #include <linux/seq_file.h>
  17 #include <linux/crc32.h>
  18 #include "net_driver.h"
  19 #include "bitfield.h"
  20 #include "efx.h"
  21 #include "nic.h"
  22 #include "farch_regs.h"
  23 #include "sriov.h"
  24 #include "siena_sriov.h"
  25 #include "io.h"
  26 #include "workarounds.h"
  27
  28 /* Falcon-architecture (SFC9000-family) support */
  29
  30 /**************************************************************************
  31  *
  32  * Configurable values
  33  *
  34  **************************************************************************
  35  */
  36
  37 /* This is set to 16 for a good reason.  In summary, if larger than
  38  * 16, the descriptor cache holds more than a default socket
  39  * buffer's worth of packets (for UDP we can only have at most one
  40  * socket buffer's worth outstanding).  This combined with the fact
  41  * that we only get 1 TX event per descriptor cache means the NIC
  42  * goes idle.
  43  */
  44 #define TX_DC_ENTRIES 16
  45 #define TX_DC_ENTRIES_ORDER 1
  46
  47 #define RX_DC_ENTRIES 64
  48 #define RX_DC_ENTRIES_ORDER 3
  49
  50 /* If EFX_MAX_INT_ERRORS internal errors occur within
  51  * EFX_INT_ERROR_EXPIRE seconds, we consider the NIC broken and
  52  * disable it.
  53  */
  54 #define EFX_INT_ERROR_EXPIRE 3600
  55 #define EFX_MAX_INT_ERRORS 5
  56
  57 /* Depth of RX flush request fifo */
  58 #define EFX_RX_FLUSH_COUNT 4
  59
  60 /* Driver generated events */
  61 #define _EFX_CHANNEL_MAGIC_TEST         0x000101
  62 #define _EFX_CHANNEL_MAGIC_FILL         0x000102
  63 #define _EFX_CHANNEL_MAGIC_RX_DRAIN     0x000103
  64 #define _EFX_CHANNEL_MAGIC_TX_DRAIN     0x000104
  65
  66 #define _EFX_CHANNEL_MAGIC(_code, _data)        ((_code) << 8 | (_data))
  67 #define _EFX_CHANNEL_MAGIC_CODE(_magic)         ((_magic) >> 8)
  68
  69 #define EFX_CHANNEL_MAGIC_TEST(_channel)                                \
  70         _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_TEST, (_channel)->channel)
  71 #define EFX_CHANNEL_MAGIC_FILL(_rx_queue)                               \
  72         _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_FILL,                     \
  73                            efx_rx_queue_index(_rx_queue))
  74 #define EFX_CHANNEL_MAGIC_RX_DRAIN(_rx_queue)                           \
  75         _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_RX_DRAIN,                 \
  76                            efx_rx_queue_index(_rx_queue))
  77 #define EFX_CHANNEL_MAGIC_TX_DRAIN(_tx_queue)                           \
  78         _EFX_CHANNEL_MAGIC(_EFX_CHANNEL_MAGIC_TX_DRAIN,                 \
  79                            (_tx_queue)->queue)
  80
  81 static void efx_farch_magic_event(struct efx_channel *channel, u32 magic);
  82
  83 /**************************************************************************
  84  *
  85  * Hardware access
  86  *
  87  **************************************************************************/
  88
  89 static inline void efx_write_buf_tbl(struct efx_nic *efx, efx_qword_t *value,
  90                                      unsigned int index)
  91 {
  92         efx_sram_writeq(efx, efx->membase + efx->type->buf_tbl_base,
  93                         value, index);
  94 }
  95
  96 static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
  97                                      const efx_oword_t *mask)
  98 {
  99         return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
 100                 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
 101 }
 102
 103 int efx_farch_test_registers(struct efx_nic *efx,
 104                              const struct efx_farch_register_test *regs,
 105                              size_t n_regs)
 106 {
 107         unsigned address = 0;
 108         int i, j;
 109         efx_oword_t mask, imask, original, reg, buf;
 110
 111         for (i = 0; i < n_regs; ++i) {
 112                 address = regs[i].address;
 113                 mask = imask = regs[i].mask;
 114                 EFX_INVERT_OWORD(imask);
 115
 116                 efx_reado(efx, &original, address);
 117
 118                 /* bit sweep on and off */
 119                 for (j = 0; j < 128; j++) {
 120                         if (!EFX_EXTRACT_OWORD32(mask, j, j))
 121                                 continue;
 122
 123                         /* Test this testable bit can be set in isolation */
 124                         EFX_AND_OWORD(reg, original, mask);
 125                         EFX_SET_OWORD32(reg, j, j, 1);
 126
 127                         efx_writeo(efx, &reg, address);
 128                         efx_reado(efx, &buf, address);
 129
 130                         if (efx_masked_compare_oword(&reg, &buf, &mask))
 131                                 goto fail;
 132
 133                         /* Test this testable bit can be cleared in isolation */
 134                         EFX_OR_OWORD(reg, original, mask);
 135                         EFX_SET_OWORD32(reg, j, j, 0);
 136
 137                         efx_writeo(efx, &reg, address);
 138                         efx_reado(efx, &buf, address);
 139
 140                         if (efx_masked_compare_oword(&reg, &buf, &mask))
 141                                 goto fail;
 142                 }
 143
 144                 efx_writeo(efx, &original, address);
 145         }
 146
 147         return 0;
 148
 149 fail:
 150         netif_err(efx, hw, efx->net_dev,
 151                   "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
 152                   " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
 153                   EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
 154         return -EIO;
 155 }
 156
 157 /**************************************************************************
 158  *
 159  * Special buffer handling
 160  * Special buffers are used for event queues and the TX and RX
 161  * descriptor rings.
 162  *
 163  *************************************************************************/
 164
 165 /*
 166  * Initialise a special buffer
 167  *
 168  * This will define a buffer (previously allocated via
 169  * efx_alloc_special_buffer()) in the buffer table, allowing
 170  * it to be used for event queues, descriptor rings etc.
 171  */
 172 static void
 173 efx_init_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
 174 {
 175         efx_qword_t buf_desc;
 176         unsigned int index;
 177         dma_addr_t dma_addr;
 178         int i;
 179
 180         EFX_WARN_ON_PARANOID(!buffer->buf.addr);
 181
 182         /* Write buffer descriptors to NIC */
 183         for (i = 0; i < buffer->entries; i++) {
 184                 index = buffer->index + i;
 185                 dma_addr = buffer->buf.dma_addr + (i * EFX_BUF_SIZE);
 186                 netif_dbg(efx, probe, efx->net_dev,
 187                           "mapping special buffer %d at %llx\n",
 188                           index, (unsigned long long)dma_addr);
 189                 EFX_POPULATE_QWORD_3(buf_desc,
 190                                      FRF_AZ_BUF_ADR_REGION, 0,
 191                                      FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12,
 192                                      FRF_AZ_BUF_OWNER_ID_FBUF, 0);
 193                 efx_write_buf_tbl(efx, &buf_desc, index);
 194         }
 195 }
 196
 197 /* Unmaps a buffer and clears the buffer table entries */
 198 static void
 199 efx_fini_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
 200 {
 201         efx_oword_t buf_tbl_upd;
 202         unsigned int start = buffer->index;
 203         unsigned int end = (buffer->index + buffer->entries - 1);
 204
 205         if (!buffer->entries)
 206                 return;
 207
 208         netif_dbg(efx, hw, efx->net_dev, "unmapping special buffers %d-%d\n",
 209                   buffer->index, buffer->index + buffer->entries - 1);
 210
 211         EFX_POPULATE_OWORD_4(buf_tbl_upd,
 212                              FRF_AZ_BUF_UPD_CMD, 0,
 213                              FRF_AZ_BUF_CLR_CMD, 1,
 214                              FRF_AZ_BUF_CLR_END_ID, end,
 215                              FRF_AZ_BUF_CLR_START_ID, start);
 216         efx_writeo(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD);
 217 }
 218
 219 /*
 220  * Allocate a new special buffer
 221  *
 222  * This allocates memory for a new buffer, clears it and allocates a
 223  * new buffer ID range.  It does not write into the buffer table.
 224  *
 225  * This call will allocate 4KB buffers, since 8KB buffers can't be
 226  * used for event queues and descriptor rings.
 227  */
 228 static int efx_alloc_special_buffer(struct efx_nic *efx,
 229                                     struct efx_special_buffer *buffer,
 230                                     unsigned int len)
 231 {
 232 #ifdef CONFIG_SFC_SRIOV
 233         struct siena_nic_data *nic_data = efx->nic_data;
 234 #endif
 235         len = ALIGN(len, EFX_BUF_SIZE);
 236
 237         if (efx_nic_alloc_buffer(efx, &buffer->buf, len, GFP_KERNEL))
 238                 return -ENOMEM;
 239         buffer->entries = len / EFX_BUF_SIZE;
 240         BUG_ON(buffer->buf.dma_addr & (EFX_BUF_SIZE - 1));
 241
 242         /* Select new buffer ID */
 243         buffer->index = efx->next_buffer_table;
 244         efx->next_buffer_table += buffer->entries;
 245 #ifdef CONFIG_SFC_SRIOV
 246         BUG_ON(efx_siena_sriov_enabled(efx) &&
 247                nic_data->vf_buftbl_base < efx->next_buffer_table);
 248 #endif
 249
 250         netif_dbg(efx, probe, efx->net_dev,
 251                   "allocating special buffers %d-%d at %llx+%x "
 252                   "(virt %p phys %llx)\n", buffer->index,
 253                   buffer->index + buffer->entries - 1,
 254                   (u64)buffer->buf.dma_addr, len,
 255                   buffer->buf.addr, (u64)virt_to_phys(buffer->buf.addr));
 256
 257         return 0;
 258 }
 259
 260 static void
 261 efx_free_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer)
 262 {
 263         if (!buffer->buf.addr)
 264                 return;
 265
 266         netif_dbg(efx, hw, efx->net_dev,
 267                   "deallocating special buffers %d-%d at %llx+%x "
 268                   "(virt %p phys %llx)\n", buffer->index,
 269                   buffer->index + buffer->entries - 1,
 270                   (u64)buffer->buf.dma_addr, buffer->buf.len,
 271                   buffer->buf.addr, (u64)virt_to_phys(buffer->buf.addr));
 272
 273         efx_nic_free_buffer(efx, &buffer->buf);
 274         buffer->entries = 0;
 275 }
 276
 277 /**************************************************************************
 278  *
 279  * TX path
 280  *
 281  **************************************************************************/
 282
 283 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
 284 static inline void efx_farch_notify_tx_desc(struct efx_tx_queue *tx_queue)
 285 {
 286         unsigned write_ptr;
 287         efx_dword_t reg;
 288
 289         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
 290         EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr);
 291         efx_writed_page(tx_queue->efx, &reg,
 292                         FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue);
 293 }
 294
 295 /* Write pointer and first descriptor for TX descriptor ring */
 296 static inline void efx_farch_push_tx_desc(struct efx_tx_queue *tx_queue,
 297                                           const efx_qword_t *txd)
 298 {
 299         unsigned write_ptr;
 300         efx_oword_t reg;
 301
 302         BUILD_BUG_ON(FRF_AZ_TX_DESC_LBN != 0);
 303         BUILD_BUG_ON(FR_AA_TX_DESC_UPD_KER != FR_BZ_TX_DESC_UPD_P0);
 304
 305         write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
 306         EFX_POPULATE_OWORD_2(reg, FRF_AZ_TX_DESC_PUSH_CMD, true,
 307                              FRF_AZ_TX_DESC_WPTR, write_ptr);
 308         reg.qword[0] = *txd;
 309         efx_writeo_page(tx_queue->efx, &reg,
 310                         FR_BZ_TX_DESC_UPD_P0, tx_queue->queue);
 311 }
 312
 313
 314 /* For each entry inserted into the software descriptor ring, create a
 315  * descriptor in the hardware TX descriptor ring (in host memory), and
 316  * write a doorbell.
 317  */
 318 void efx_farch_tx_write(struct efx_tx_queue *tx_queue)
 319 {
 320         struct efx_tx_buffer *buffer;
 321         efx_qword_t *txd;
 322         unsigned write_ptr;
 323         unsigned old_write_count = tx_queue->write_count;
 324
 325         tx_queue->xmit_more_available = false;
 326         if (unlikely(tx_queue->write_count == tx_queue->insert_count))
 327                 return;
 328
 329         do {
 330                 write_ptr = tx_queue->write_count & tx_queue->ptr_mask;
 331                 buffer = &tx_queue->buffer[write_ptr];
 332                 txd = efx_tx_desc(tx_queue, write_ptr);
 333                 ++tx_queue->write_count;
 334
 335                 EFX_WARN_ON_ONCE_PARANOID(buffer->flags & EFX_TX_BUF_OPTION);
 336
 337                 /* Create TX descriptor ring entry */
 338                 BUILD_BUG_ON(EFX_TX_BUF_CONT != 1);
 339                 EFX_POPULATE_QWORD_4(*txd,
 340                                      FSF_AZ_TX_KER_CONT,
 341                                      buffer->flags & EFX_TX_BUF_CONT,
 342                                      FSF_AZ_TX_KER_BYTE_COUNT, buffer->len,
 343                                      FSF_AZ_TX_KER_BUF_REGION, 0,
 344                                      FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr);
 345         } while (tx_queue->write_count != tx_queue->insert_count);
 346
 347         wmb(); /* Ensure descriptors are written before they are fetched */
 348
 349         if (efx_nic_may_push_tx_desc(tx_queue, old_write_count)) {
 350                 txd = efx_tx_desc(tx_queue,
 351                                   old_write_count & tx_queue->ptr_mask);
 352                 efx_farch_push_tx_desc(tx_queue, txd);
 353                 ++tx_queue->pushes;
 354         } else {
 355                 efx_farch_notify_tx_desc(tx_queue);
 356         }
 357 }
 358
 359 unsigned int efx_farch_tx_limit_len(struct efx_tx_queue *tx_queue,
 360                                     dma_addr_t dma_addr, unsigned int len)
 361 {
 362         /* Don't cross 4K boundaries with descriptors. */
 363         unsigned int limit = (~dma_addr & (EFX_PAGE_SIZE - 1)) + 1;
 364
 365         len = min(limit, len);
 366
 367         return len;
 368 }
 369
 370
 371 /* Allocate hardware resources for a TX queue */
 372 int efx_farch_tx_probe(struct efx_tx_queue *tx_queue)
 373 {
 374         struct efx_nic *efx = tx_queue->efx;
 375         unsigned entries;
 376
 377         entries = tx_queue->ptr_mask + 1;
 378         return efx_alloc_special_buffer(efx, &tx_queue->txd,
 379                                         entries * sizeof(efx_qword_t));
 380 }
 381
 382 void efx_farch_tx_init(struct efx_tx_queue *tx_queue)
 383 {
 384         int csum = tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD;
 385         struct efx_nic *efx = tx_queue->efx;
 386         efx_oword_t reg;
 387
 388         /* Pin TX descriptor ring */
 389         efx_init_special_buffer(efx, &tx_queue->txd);
 390
 391         /* Push TX descriptor ring to card */
 392         EFX_POPULATE_OWORD_10(reg,
 393                               FRF_AZ_TX_DESCQ_EN, 1,
 394                               FRF_AZ_TX_ISCSI_DDIG_EN, 0,
 395                               FRF_AZ_TX_ISCSI_HDIG_EN, 0,
 396                               FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
 397                               FRF_AZ_TX_DESCQ_EVQ_ID,
 398                               tx_queue->channel->channel,
 399                               FRF_AZ_TX_DESCQ_OWNER_ID, 0,
 400                               FRF_AZ_TX_DESCQ_LABEL, tx_queue->queue,
 401                               FRF_AZ_TX_DESCQ_SIZE,
 402                               __ffs(tx_queue->txd.entries),
 403                               FRF_AZ_TX_DESCQ_TYPE, 0,
 404                               FRF_BZ_TX_NON_IP_DROP_DIS, 1);
 405
 406         EFX_SET_OWORD_FIELD(reg, FRF_BZ_TX_IP_CHKSM_DIS, !csum);
 407         EFX_SET_OWORD_FIELD(reg, FRF_BZ_TX_TCP_CHKSM_DIS, !csum);
 408
 409         efx_writeo_table(efx, &reg, efx->type->txd_ptr_tbl_base,
 410                          tx_queue->queue);
 411
 412         EFX_POPULATE_OWORD_1(reg,
 413                              FRF_BZ_TX_PACE,
 414                              (tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI) ?
 415                              FFE_BZ_TX_PACE_OFF :
 416                              FFE_BZ_TX_PACE_RESERVED);
 417         efx_writeo_table(efx, &reg, FR_BZ_TX_PACE_TBL, tx_queue->queue);
 418 }
 419
 420 static void efx_farch_flush_tx_queue(struct efx_tx_queue *tx_queue)
 421 {
 422         struct efx_nic *efx = tx_queue->efx;
 423         efx_oword_t tx_flush_descq;
 424
 425         WARN_ON(atomic_read(&tx_queue->flush_outstanding));
 426         atomic_set(&tx_queue->flush_outstanding, 1);
 427
 428         EFX_POPULATE_OWORD_2(tx_flush_descq,
 429                              FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
 430                              FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue);
 431         efx_writeo(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ);
 432 }
 433
 434 void efx_farch_tx_fini(struct efx_tx_queue *tx_queue)
 435 {
 436         struct efx_nic *efx = tx_queue->efx;
 437         efx_oword_t tx_desc_ptr;
 438
 439         /* Remove TX descriptor ring from card */
 440         EFX_ZERO_OWORD(tx_desc_ptr);
 441         efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
 442                          tx_queue->queue);
 443
 444         /* Unpin TX descriptor ring */
 445         efx_fini_special_buffer(efx, &tx_queue->txd);
 446 }
 447
 448 /* Free buffers backing TX queue */
 449 void efx_farch_tx_remove(struct efx_tx_queue *tx_queue)
 450 {
 451         efx_free_special_buffer(tx_queue->efx, &tx_queue->txd);
 452 }
 453
 454 /**************************************************************************
 455  *
 456  * RX path
 457  *
 458  **************************************************************************/
 459
 460 /* This creates an entry in the RX descriptor queue */
 461 static inline void
 462 efx_farch_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned index)
 463 {
 464         struct efx_rx_buffer *rx_buf;
 465         efx_qword_t *rxd;
 466
 467         rxd = efx_rx_desc(rx_queue, index);
 468         rx_buf = efx_rx_buffer(rx_queue, index);
 469         EFX_POPULATE_QWORD_3(*rxd,
 470                              FSF_AZ_RX_KER_BUF_SIZE,
 471                              rx_buf->len -
 472                              rx_queue->efx->type->rx_buffer_padding,
 473                              FSF_AZ_RX_KER_BUF_REGION, 0,
 474                              FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr);
 475 }
 476
 477 /* This writes to the RX_DESC_WPTR register for the specified receive
 478  * descriptor ring.
 479  */
 480 void efx_farch_rx_write(struct efx_rx_queue *rx_queue)
 481 {
 482         struct efx_nic *efx = rx_queue->efx;
 483         efx_dword_t reg;
 484         unsigned write_ptr;
 485
 486         while (rx_queue->notified_count != rx_queue->added_count) {
 487                 efx_farch_build_rx_desc(
 488                         rx_queue,
 489                         rx_queue->notified_count & rx_queue->ptr_mask);
 490                 ++rx_queue->notified_count;
 491         }
 492
 493         wmb();
 494         write_ptr = rx_queue->added_count & rx_queue->ptr_mask;
 495         EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr);
 496         efx_writed_page(efx, &reg, FR_AZ_RX_DESC_UPD_DWORD_P0,
 497                         efx_rx_queue_index(rx_queue));
 498 }
 499
 500 int efx_farch_rx_probe(struct efx_rx_queue *rx_queue)
 501 {
 502         struct efx_nic *efx = rx_queue->efx;
 503         unsigned entries;
 504
 505         entries = rx_queue->ptr_mask + 1;
 506         return efx_alloc_special_buffer(efx, &rx_queue->rxd,
 507                                         entries * sizeof(efx_qword_t));
 508 }
 509
 510 void efx_farch_rx_init(struct efx_rx_queue *rx_queue)
 511 {
 512         efx_oword_t rx_desc_ptr;
 513         struct efx_nic *efx = rx_queue->efx;
 514         bool jumbo_en;
 515
 516         /* For kernel-mode queues in Siena, the JUMBO flag enables scatter. */
 517         jumbo_en = efx->rx_scatter;
 518
 519         netif_dbg(efx, hw, efx->net_dev,
 520                   "RX queue %d ring in special buffers %d-%d\n",
 521                   efx_rx_queue_index(rx_queue), rx_queue->rxd.index,
 522                   rx_queue->rxd.index + rx_queue->rxd.entries - 1);
 523
 524         rx_queue->scatter_n = 0;
 525
 526         /* Pin RX descriptor ring */
 527         efx_init_special_buffer(efx, &rx_queue->rxd);
 528
 529         /* Push RX descriptor ring to card */
 530         EFX_POPULATE_OWORD_10(rx_desc_ptr,
 531                               FRF_AZ_RX_ISCSI_DDIG_EN, true,
 532                               FRF_AZ_RX_ISCSI_HDIG_EN, true,
 533                               FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
 534                               FRF_AZ_RX_DESCQ_EVQ_ID,
 535                               efx_rx_queue_channel(rx_queue)->channel,
 536                               FRF_AZ_RX_DESCQ_OWNER_ID, 0,
 537                               FRF_AZ_RX_DESCQ_LABEL,
 538                               efx_rx_queue_index(rx_queue),
 539                               FRF_AZ_RX_DESCQ_SIZE,
 540                               __ffs(rx_queue->rxd.entries),
 541                               FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ ,
 542                               FRF_AZ_RX_DESCQ_JUMBO, jumbo_en,
 543                               FRF_AZ_RX_DESCQ_EN, 1);
 544         efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
 545                          efx_rx_queue_index(rx_queue));
 546 }
 547
 548 static void efx_farch_flush_rx_queue(struct efx_rx_queue *rx_queue)
 549 {
 550         struct efx_nic *efx = rx_queue->efx;
 551         efx_oword_t rx_flush_descq;
 552
 553         EFX_POPULATE_OWORD_2(rx_flush_descq,
 554                              FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
 555                              FRF_AZ_RX_FLUSH_DESCQ,
 556                              efx_rx_queue_index(rx_queue));
 557         efx_writeo(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ);
 558 }
 559
 560 void efx_farch_rx_fini(struct efx_rx_queue *rx_queue)
 561 {
 562         efx_oword_t rx_desc_ptr;
 563         struct efx_nic *efx = rx_queue->efx;
 564
 565         /* Remove RX descriptor ring from card */
 566         EFX_ZERO_OWORD(rx_desc_ptr);
 567         efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
 568                          efx_rx_queue_index(rx_queue));
 569
 570         /* Unpin RX descriptor ring */
 571         efx_fini_special_buffer(efx, &rx_queue->rxd);
 572 }
 573
 574 /* Free buffers backing RX queue */
 575 void efx_farch_rx_remove(struct efx_rx_queue *rx_queue)
 576 {
 577         efx_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
 578 }
 579
 580 /**************************************************************************
 581  *
 582  * Flush handling
 583  *
 584  **************************************************************************/
 585
 586 /* efx_farch_flush_queues() must be woken up when all flushes are completed,
 587  * or more RX flushes can be kicked off.
 588  */
 589 static bool efx_farch_flush_wake(struct efx_nic *efx)
 590 {
 591         /* Ensure that all updates are visible to efx_farch_flush_queues() */
 592         smp_mb();
 593
 594         return (atomic_read(&efx->active_queues) == 0 ||
 595                 (atomic_read(&efx->rxq_flush_outstanding) < EFX_RX_FLUSH_COUNT
 596                  && atomic_read(&efx->rxq_flush_pending) > 0));
 597 }
 598
 599 static bool efx_check_tx_flush_complete(struct efx_nic *efx)
 600 {
 601         bool i = true;
 602         efx_oword_t txd_ptr_tbl;
 603         struct efx_channel *channel;
 604         struct efx_tx_queue *tx_queue;
 605
 606         efx_for_each_channel(channel, efx) {
 607                 efx_for_each_channel_tx_queue(tx_queue, channel) {
 608                         efx_reado_table(efx, &txd_ptr_tbl,
 609                                         FR_BZ_TX_DESC_PTR_TBL, tx_queue->queue);
 610                         if (EFX_OWORD_FIELD(txd_ptr_tbl,
 611                                             FRF_AZ_TX_DESCQ_FLUSH) ||
 612                             EFX_OWORD_FIELD(txd_ptr_tbl,
 613                                             FRF_AZ_TX_DESCQ_EN)) {
 614                                 netif_dbg(efx, hw, efx->net_dev,
 615                                           "flush did not complete on TXQ %d\n",
 616                                           tx_queue->queue);
 617                                 i = false;
 618                         } else if (atomic_cmpxchg(&tx_queue->flush_outstanding,
 619                                                   1, 0)) {
 620                                 /* The flush is complete, but we didn't
 621                                  * receive a flush completion event
 622                                  */
 623                                 netif_dbg(efx, hw, efx->net_dev,
 624                                           "flush complete on TXQ %d, so drain "
 625                                           "the queue\n", tx_queue->queue);
 626                                 /* Don't need to increment active_queues as it
 627                                  * has already been incremented for the queues
 628                                  * which did not drain
 629                                  */
 630                                 efx_farch_magic_event(channel,
 631                                                       EFX_CHANNEL_MAGIC_TX_DRAIN(
 632                                                               tx_queue));
 633                         }
 634                 }
 635         }
 636
 637         return i;
 638 }
 639
 640 /* Flush all the transmit queues, and continue flushing receive queues until
 641  * they're all flushed. Wait for the DRAIN events to be received so that there
 642  * are no more RX and TX events left on any channel. */
 643 static int efx_farch_do_flush(struct efx_nic *efx)
 644 {
 645         unsigned timeout = msecs_to_jiffies(5000); /* 5s for all flushes and drains */
 646         struct efx_channel *channel;
 647         struct efx_rx_queue *rx_queue;
 648         struct efx_tx_queue *tx_queue;
 649         int rc = 0;
 650
 651         efx_for_each_channel(channel, efx) {
 652                 efx_for_each_channel_tx_queue(tx_queue, channel) {
 653                         efx_farch_flush_tx_queue(tx_queue);
 654                 }
 655                 efx_for_each_channel_rx_queue(rx_queue, channel) {
 656                         rx_queue->flush_pending = true;
 657                         atomic_inc(&efx->rxq_flush_pending);
 658                 }
 659         }
 660
 661         while (timeout && atomic_read(&efx->active_queues) > 0) {
 662                 /* If SRIOV is enabled, then offload receive queue flushing to
 663                  * the firmware (though we will still have to poll for
 664                  * completion). If that fails, fall back to the old scheme.
 665                  */
 666                 if (efx_siena_sriov_enabled(efx)) {
 667                         rc = efx_mcdi_flush_rxqs(efx);
 668                         if (!rc)
 669                                 goto wait;
 670                 }
 671
 672                 /* The hardware supports four concurrent rx flushes, each of
 673                  * which may need to be retried if there is an outstanding
 674                  * descriptor fetch
 675                  */
 676                 efx_for_each_channel(channel, efx) {
 677                         efx_for_each_channel_rx_queue(rx_queue, channel) {
 678                                 if (atomic_read(&efx->rxq_flush_outstanding) >=
 679                                     EFX_RX_FLUSH_COUNT)
 680                                         break;
 681
 682                                 if (rx_queue->flush_pending) {
 683                                         rx_queue->flush_pending = false;
 684                                         atomic_dec(&efx->rxq_flush_pending);
 685                                         atomic_inc(&efx->rxq_flush_outstanding);
 686                                         efx_farch_flush_rx_queue(rx_queue);
 687                                 }
 688                         }
 689                 }
 690
 691         wait:
 692                 timeout = wait_event_timeout(efx->flush_wq,
 693                                              efx_farch_flush_wake(efx),
 694                                              timeout);
 695         }
 696
 697         if (atomic_read(&efx->active_queues) &&
 698             !efx_check_tx_flush_complete(efx)) {
 699                 netif_err(efx, hw, efx->net_dev, "failed to flush %d queues "
 700                           "(rx %d+%d)\n", atomic_read(&efx->active_queues),
 701                           atomic_read(&efx->rxq_flush_outstanding),
 702                           atomic_read(&efx->rxq_flush_pending));
 703                 rc = -ETIMEDOUT;
 704
 705                 atomic_set(&efx->active_queues, 0);
 706                 atomic_set(&efx->rxq_flush_pending, 0);
 707                 atomic_set(&efx->rxq_flush_outstanding, 0);
 708         }
 709
 710         return rc;
 711 }
 712
 713 int efx_farch_fini_dmaq(struct efx_nic *efx)
 714 {
 715         struct efx_channel *channel;
 716         struct efx_tx_queue *tx_queue;
 717         struct efx_rx_queue *rx_queue;
 718         int rc = 0;
 719
 720         /* Do not attempt to write to the NIC during EEH recovery */
 721         if (efx->state != STATE_RECOVERY) {
 722                 /* Only perform flush if DMA is enabled */
 723                 if (efx->pci_dev->is_busmaster) {
 724                         efx->type->prepare_flush(efx);
 725                         rc = efx_farch_do_flush(efx);
 726                         efx->type->finish_flush(efx);
 727                 }
 728
 729                 efx_for_each_channel(channel, efx) {
 730                         efx_for_each_channel_rx_queue(rx_queue, channel)
 731                                 efx_farch_rx_fini(rx_queue);
 732                         efx_for_each_channel_tx_queue(tx_queue, channel)
 733                                 efx_farch_tx_fini(tx_queue);
 734                 }
 735         }
 736
 737         return rc;
 738 }
 739
 740 /* Reset queue and flush accounting after FLR
 741  *
 742  * One possible cause of FLR recovery is that DMA may be failing (eg. if bus
 743  * mastering was disabled), in which case we don't receive (RXQ) flush
 744  * completion events.  This means that efx->rxq_flush_outstanding remained at 4
 745  * after the FLR; also, efx->active_queues was non-zero (as no flush completion
 746  * events were received, and we didn't go through efx_check_tx_flush_complete())
 747  * If we don't fix this up, on the next call to efx_realloc_channels() we won't
 748  * flush any RX queues because efx->rxq_flush_outstanding is at the limit of 4
 749  * for batched flush requests; and the efx->active_queues gets messed up because
 750  * we keep incrementing for the newly initialised queues, but it never went to
 751  * zero previously.  Then we get a timeout every time we try to restart the
 752  * queues, as it doesn't go back to zero when we should be flushing the queues.
 753  */
 754 void efx_farch_finish_flr(struct efx_nic *efx)
 755 {
 756         atomic_set(&efx->rxq_flush_pending, 0);
 757         atomic_set(&efx->rxq_flush_outstanding, 0);
 758         atomic_set(&efx->active_queues, 0);
 759 }
 760
 761
 762 /**************************************************************************
 763  *
 764  * Event queue processing
 765  * Event queues are processed by per-channel tasklets.
 766  *
 767  **************************************************************************/
 768
 769 /* Update a channel's event queue's read pointer (RPTR) register
 770  *
 771  * This writes the EVQ_RPTR_REG register for the specified channel's
 772  * event queue.
 773  */
 774 void efx_farch_ev_read_ack(struct efx_channel *channel)
 775 {
 776         efx_dword_t reg;
 777         struct efx_nic *efx = channel->efx;
 778
 779         EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR,
 780                              channel->eventq_read_ptr & channel->eventq_mask);
 781
 782         /* For Falcon A1, EVQ_RPTR_KER is documented as having a step size
 783          * of 4 bytes, but it is really 16 bytes just like later revisions.
 784          */
 785         efx_writed(efx, &reg,
 786                    efx->type->evq_rptr_tbl_base +
 787                    FR_BZ_EVQ_RPTR_STEP * channel->channel);
 788 }
 789
 790 /* Use HW to insert a SW defined event */
 791 void efx_farch_generate_event(struct efx_nic *efx, unsigned int evq,
 792                               efx_qword_t *event)
 793 {
 794         efx_oword_t drv_ev_reg;
 795
 796         BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 ||
 797                      FRF_AZ_DRV_EV_DATA_WIDTH != 64);
 798         drv_ev_reg.u32[0] = event->u32[0];
 799         drv_ev_reg.u32[1] = event->u32[1];
 800         drv_ev_reg.u32[2] = 0;
 801         drv_ev_reg.u32[3] = 0;
 802         EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, evq);
 803         efx_writeo(efx, &drv_ev_reg, FR_AZ_DRV_EV);
 804 }
 805
 806 static void efx_farch_magic_event(struct efx_channel *channel, u32 magic)
 807 {
 808         efx_qword_t event;
 809
 810         EFX_POPULATE_QWORD_2(event, FSF_AZ_EV_CODE,
 811                              FSE_AZ_EV_CODE_DRV_GEN_EV,
 812                              FSF_AZ_DRV_GEN_EV_MAGIC, magic);
 813         efx_farch_generate_event(channel->efx, channel->channel, &event);
 814 }
 815
 816 /* Handle a transmit completion event
 817  *
 818  * The NIC batches TX completion events; the message we receive is of
 819  * the form "complete all TX events up to this index".
 820  */
 821 static int
 822 efx_farch_handle_tx_event(struct efx_channel *channel, efx_qword_t *event)
 823 {
 824         unsigned int tx_ev_desc_ptr;
 825         unsigned int tx_ev_q_label;
 826         struct efx_tx_queue *tx_queue;
 827         struct efx_nic *efx = channel->efx;
 828         int tx_packets = 0;
 829
 830         if (unlikely(ACCESS_ONCE(efx->reset_pending)))
 831                 return 0;
 832
 833         if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) {
 834                 /* Transmit completion */
 835                 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR);
 836                 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
 837                 tx_queue = efx_channel_get_tx_queue(
 838                         channel, tx_ev_q_label % EFX_TXQ_TYPES);
 839                 tx_packets = ((tx_ev_desc_ptr - tx_queue->read_count) &
 840                               tx_queue->ptr_mask);
 841                 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
 842         } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) {
 843                 /* Rewrite the FIFO write pointer */
 844                 tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL);
 845                 tx_queue = efx_channel_get_tx_queue(
 846                         channel, tx_ev_q_label % EFX_TXQ_TYPES);
 847
 848                 netif_tx_lock(efx->net_dev);
 849                 efx_farch_notify_tx_desc(tx_queue);
 850                 netif_tx_unlock(efx->net_dev);
 851         } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR)) {
 852                 efx_schedule_reset(efx, RESET_TYPE_DMA_ERROR);
 853         } else {
 854                 netif_err(efx, tx_err, efx->net_dev,
 855                           "channel %d unexpected TX event "
 856                           EFX_QWORD_FMT"\n", channel->channel,
 857                           EFX_QWORD_VAL(*event));
 858         }
 859
 860         return tx_packets;
 861 }
 862
 863 /* Detect errors included in the rx_evt_pkt_ok bit. */
 864 static u16 efx_farch_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
 865                                       const efx_qword_t *event)
 866 {
 867         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
 868         struct efx_nic *efx = rx_queue->efx;
 869         bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
 870         bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
 871         bool rx_ev_frm_trunc, rx_ev_tobe_disc;
 872         bool rx_ev_other_err, rx_ev_pause_frm;
 873         bool rx_ev_hdr_type, rx_ev_mcast_pkt;
 874         unsigned rx_ev_pkt_type;
 875
 876         rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
 877         rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
 878         rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC);
 879         rx_ev_pkt_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_TYPE);
 880         rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
 881                                                  FSF_AZ_RX_EV_BUF_OWNER_ID_ERR);
 882         rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
 883                                                   FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR);
 884         rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
 885                                                    FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR);
 886         rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR);
 887         rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC);
 888         rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR);
 889
 890         /* Every error apart from tobe_disc and pause_frm */
 891         rx_ev_other_err = (rx_ev_tcp_udp_chksum_err |
 892                            rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
 893                            rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
 894
 895         /* Count errors that are not in MAC stats.  Ignore expected
 896          * checksum errors during self-test. */
 897         if (rx_ev_frm_trunc)
 898                 ++channel->n_rx_frm_trunc;
 899         else if (rx_ev_tobe_disc)
 900                 ++channel->n_rx_tobe_disc;
 901         else if (!efx->loopback_selftest) {
 902                 if (rx_ev_ip_hdr_chksum_err)
 903                         ++channel->n_rx_ip_hdr_chksum_err;
 904                 else if (rx_ev_tcp_udp_chksum_err)
 905                         ++channel->n_rx_tcp_udp_chksum_err;
 906         }
 907
 908         /* TOBE_DISC is expected on unicast mismatches; don't print out an
 909          * error message.  FRM_TRUNC indicates RXDP dropped the packet due
 910          * to a FIFO overflow.
 911          */
 912 #ifdef DEBUG
 913         if (rx_ev_other_err && net_ratelimit()) {
 914                 netif_dbg(efx, rx_err, efx->net_dev,
 915                           " RX queue %d unexpected RX event "
 916                           EFX_QWORD_FMT "%s%s%s%s%s%s%s\n",
 917                           efx_rx_queue_index(rx_queue), EFX_QWORD_VAL(*event),
 918                           rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
 919                           rx_ev_ip_hdr_chksum_err ?
 920                           " [IP_HDR_CHKSUM_ERR]" : "",
 921                           rx_ev_tcp_udp_chksum_err ?
 922                           " [TCP_UDP_CHKSUM_ERR]" : "",
 923                           rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
 924                           rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
 925                           rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
 926                           rx_ev_pause_frm ? " [PAUSE]" : "");
 927         }
 928 #endif
 929
 930         /* The frame must be discarded if any of these are true. */
 931         return (rx_ev_eth_crc_err | rx_ev_frm_trunc |
 932                 rx_ev_tobe_disc | rx_ev_pause_frm) ?
 933                 EFX_RX_PKT_DISCARD : 0;
 934 }
 935
 936 /* Handle receive events that are not in-order. Return true if this
 937  * can be handled as a partial packet discard, false if it's more
 938  * serious.
 939  */
 940 static bool
 941 efx_farch_handle_rx_bad_index(struct efx_rx_queue *rx_queue, unsigned index)
 942 {
 943         struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
 944         struct efx_nic *efx = rx_queue->efx;
 945         unsigned expected, dropped;
 946
 947         if (rx_queue->scatter_n &&
 948             index == ((rx_queue->removed_count + rx_queue->scatter_n - 1) &
 949                       rx_queue->ptr_mask)) {
 950                 ++channel->n_rx_nodesc_trunc;
 951                 return true;
 952         }
 953
 954         expected = rx_queue->removed_count & rx_queue->ptr_mask;
 955         dropped = (index - expected) & rx_queue->ptr_mask;
 956         netif_info(efx, rx_err, efx->net_dev,
 957                    "dropped %d events (index=%d expected=%d)\n",
 958                    dropped, index, expected);
 959
 960         efx_schedule_reset(efx, RESET_TYPE_DISABLE);
 961         return false;
 962 }
 963
 964 /* Handle a packet received event
 965  *
 966  * The NIC gives a "discard" flag if it's a unicast packet with the
 967  * wrong destination address
 968  * Also "is multicast" and "matches multicast filter" flags can be used to
 969  * discard non-matching multicast packets.
 970  */
 971 static void
 972 efx_farch_handle_rx_event(struct efx_channel *channel, const efx_qword_t *event)
 973 {
 974         unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
 975         unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
 976         unsigned expected_ptr;
 977         bool rx_ev_pkt_ok, rx_ev_sop, rx_ev_cont;
 978         u16 flags;
 979         struct efx_rx_queue *rx_queue;
 980         struct efx_nic *efx = channel->efx;
 981
 982         if (unlikely(ACCESS_ONCE(efx->reset_pending)))
 983                 return;
 984
 985         rx_ev_cont = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT);
 986         rx_ev_sop = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP);
 987         WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) !=
 988                 channel->channel);
 989
 990         rx_queue = efx_channel_get_rx_queue(channel);
 991
 992         rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR);
 993         expected_ptr = ((rx_queue->removed_count + rx_queue->scatter_n) &
 994                         rx_queue->ptr_mask);
 995
 996         /* Check for partial drops and other errors */
 997         if (unlikely(rx_ev_desc_ptr != expected_ptr) ||
 998             unlikely(rx_ev_sop != (rx_queue->scatter_n == 0))) {
 999                 if (rx_ev_desc_ptr != expected_ptr &&
1000                     !efx_farch_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr))
1001                         return;
1002
1003                 /* Discard all pending fragments */
1004                 if (rx_queue->scatter_n) {
1005                         efx_rx_packet(
1006                                 rx_queue,
1007                                 rx_queue->removed_count & rx_queue->ptr_mask,
1008                                 rx_queue->scatter_n, 0, EFX_RX_PKT_DISCARD);
1009                         rx_queue->removed_count += rx_queue->scatter_n;
1010                         rx_queue->scatter_n = 0;
1011                 }
1012
1013                 /* Return if there is no new fragment */
1014                 if (rx_ev_desc_ptr != expected_ptr)
1015                         return;
1016
1017                 /* Discard new fragment if not SOP */
1018                 if (!rx_ev_sop) {
1019                         efx_rx_packet(
1020                                 rx_queue,
1021                                 rx_queue->removed_count & rx_queue->ptr_mask,
1022                                 1, 0, EFX_RX_PKT_DISCARD);
1023                         ++rx_queue->removed_count;
1024                         return;
1025                 }
1026         }
1027
1028         ++rx_queue->scatter_n;
1029         if (rx_ev_cont)
1030                 return;
1031
1032         rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT);
1033         rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK);
1034         rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE);
1035
1036         if (likely(rx_ev_pkt_ok)) {
1037                 /* If packet is marked as OK then we can rely on the
1038                  * hardware checksum and classification.
1039                  */
1040                 flags = 0;
1041                 switch (rx_ev_hdr_type) {
1042                 case FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_TCP:
1043                         flags |= EFX_RX_PKT_TCP;
1044                         /* fall through */
1045                 case FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_UDP:
1046                         flags |= EFX_RX_PKT_CSUMMED;
1047                         /* fall through */
1048                 case FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_OTHER:
1049                 case FSE_AZ_RX_EV_HDR_TYPE_OTHER:
1050                         break;
1051                 }
1052         } else {
1053                 flags = efx_farch_handle_rx_not_ok(rx_queue, event);
1054         }
1055
1056         /* Detect multicast packets that didn't match the filter */
1057         rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT);
1058         if (rx_ev_mcast_pkt) {
1059                 unsigned int rx_ev_mcast_hash_match =
1060                         EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH);
1061
1062                 if (unlikely(!rx_ev_mcast_hash_match)) {
1063                         ++channel->n_rx_mcast_mismatch;
1064                         flags |= EFX_RX_PKT_DISCARD;
1065                 }
1066         }
1067
1068         channel->irq_mod_score += 2;
1069
1070         /* Handle received packet */
1071         efx_rx_packet(rx_queue,
1072                       rx_queue->removed_count & rx_queue->ptr_mask,
1073                       rx_queue->scatter_n, rx_ev_byte_cnt, flags);
1074         rx_queue->removed_count += rx_queue->scatter_n;
1075         rx_queue->scatter_n = 0;
1076 }
1077
1078 /* If this flush done event corresponds to a &struct efx_tx_queue, then
1079  * send an %EFX_CHANNEL_MAGIC_TX_DRAIN event to drain the event queue
1080  * of all transmit completions.
1081  */
1082 static void
1083 efx_farch_handle_tx_flush_done(struct efx_nic *efx, efx_qword_t *event)
1084 {
1085         struct efx_tx_queue *tx_queue;
1086         int qid;
1087
1088         qid = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
1089         if (qid < EFX_TXQ_TYPES * efx->n_tx_channels) {
1090                 tx_queue = efx_get_tx_queue(efx, qid / EFX_TXQ_TYPES,
1091                                             qid % EFX_TXQ_TYPES);
1092                 if (atomic_cmpxchg(&tx_queue->flush_outstanding, 1, 0)) {
1093                         efx_farch_magic_event(tx_queue->channel,
1094                                               EFX_CHANNEL_MAGIC_TX_DRAIN(tx_queue));
1095                 }
1096         }
1097 }
1098
1099 /* If this flush done event corresponds to a &struct efx_rx_queue: If the flush
1100  * was successful then send an %EFX_CHANNEL_MAGIC_RX_DRAIN, otherwise add
1101  * the RX queue back to the mask of RX queues in need of flushing.
1102  */
1103 static void
1104 efx_farch_handle_rx_flush_done(struct efx_nic *efx, efx_qword_t *event)
1105 {
1106         struct efx_channel *channel;
1107         struct efx_rx_queue *rx_queue;
1108         int qid;
1109         bool failed;
1110
1111         qid = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
1112         failed = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
1113         if (qid >= efx->n_channels)
1114                 return;
1115         channel = efx_get_channel(efx, qid);
1116         if (!efx_channel_has_rx_queue(channel))
1117                 return;
1118         rx_queue = efx_channel_get_rx_queue(channel);
1119
1120         if (failed) {
1121                 netif_info(efx, hw, efx->net_dev,
1122                            "RXQ %d flush retry\n", qid);
1123                 rx_queue->flush_pending = true;
1124                 atomic_inc(&efx->rxq_flush_pending);
1125         } else {
1126                 efx_farch_magic_event(efx_rx_queue_channel(rx_queue),
1127                                       EFX_CHANNEL_MAGIC_RX_DRAIN(rx_queue));
1128         }
1129         atomic_dec(&efx->rxq_flush_outstanding);
1130         if (efx_farch_flush_wake(efx))
1131                 wake_up(&efx->flush_wq);
1132 }
1133
1134 static void
1135 efx_farch_handle_drain_event(struct efx_channel *channel)
1136 {
1137         struct efx_nic *efx = channel->efx;
1138
1139         WARN_ON(atomic_read(&efx->active_queues) == 0);
1140         atomic_dec(&efx->active_queues);
1141         if (efx_farch_flush_wake(efx))
1142                 wake_up(&efx->flush_wq);
1143 }
1144
1145 static void efx_farch_handle_generated_event(struct efx_channel *channel,
1146                                              efx_qword_t *event)
1147 {
1148         struct efx_nic *efx = channel->efx;
1149         struct efx_rx_queue *rx_queue =
1150                 efx_channel_has_rx_queue(channel) ?
1151                 efx_channel_get_rx_queue(channel) : NULL;
1152         unsigned magic, code;
1153
1154         magic = EFX_QWORD_FIELD(*event, FSF_AZ_DRV_GEN_EV_MAGIC);
1155         code = _EFX_CHANNEL_MAGIC_CODE(magic);
1156
1157         if (magic == EFX_CHANNEL_MAGIC_TEST(channel)) {
1158                 channel->event_test_cpu = raw_smp_processor_id();
1159         } else if (rx_queue && magic == EFX_CHANNEL_MAGIC_FILL(rx_queue)) {
1160                 /* The queue must be empty, so we won't receive any rx
1161                  * events, so efx_process_channel() won't refill the
1162                  * queue. Refill it here */
1163                 efx_fast_push_rx_descriptors(rx_queue, true);
1164         } else if (rx_queue && magic == EFX_CHANNEL_MAGIC_RX_DRAIN(rx_queue)) {
1165                 efx_farch_handle_drain_event(channel);
1166         } else if (code == _EFX_CHANNEL_MAGIC_TX_DRAIN) {
1167                 efx_farch_handle_drain_event(channel);
1168         } else {
1169                 netif_dbg(efx, hw, efx->net_dev, "channel %d received "
1170                           "generated event "EFX_QWORD_FMT"\n",
1171                           channel->channel, EFX_QWORD_VAL(*event));
1172         }
1173 }
1174
1175 static void
1176 efx_farch_handle_driver_event(struct efx_channel *channel, efx_qword_t *event)
1177 {
1178         struct efx_nic *efx = channel->efx;
1179         unsigned int ev_sub_code;
1180         unsigned int ev_sub_data;
1181
1182         ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE);
1183         ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA);
1184
1185         switch (ev_sub_code) {
1186         case FSE_AZ_TX_DESCQ_FLS_DONE_EV:
1187                 netif_vdbg(efx, hw, efx->net_dev, "channel %d TXQ %d flushed\n",
1188                            channel->channel, ev_sub_data);
1189                 efx_farch_handle_tx_flush_done(efx, event);
1190 #ifdef CONFIG_SFC_SRIOV
1191                 efx_siena_sriov_tx_flush_done(efx, event);
1192 #endif
1193                 break;
1194         case FSE_AZ_RX_DESCQ_FLS_DONE_EV:
1195                 netif_vdbg(efx, hw, efx->net_dev, "channel %d RXQ %d flushed\n",
1196                            channel->channel, ev_sub_data);
1197                 efx_farch_handle_rx_flush_done(efx, event);
1198 #ifdef CONFIG_SFC_SRIOV
1199                 efx_siena_sriov_rx_flush_done(efx, event);
1200 #endif
1201                 break;
1202         case FSE_AZ_EVQ_INIT_DONE_EV:
1203                 netif_dbg(efx, hw, efx->net_dev,
1204                           "channel %d EVQ %d initialised\n",
1205                           channel->channel, ev_sub_data);
1206                 break;
1207         case FSE_AZ_SRM_UPD_DONE_EV:
1208                 netif_vdbg(efx, hw, efx->net_dev,
1209                            "channel %d SRAM update done\n", channel->channel);
1210                 break;
1211         case FSE_AZ_WAKE_UP_EV:
1212                 netif_vdbg(efx, hw, efx->net_dev,
1213                            "channel %d RXQ %d wakeup event\n",
1214                            channel->channel, ev_sub_data);
1215                 break;
1216         case FSE_AZ_TIMER_EV:
1217                 netif_vdbg(efx, hw, efx->net_dev,
1218                            "channel %d RX queue %d timer expired\n",
1219                            channel->channel, ev_sub_data);
1220                 break;
1221         case FSE_AA_RX_RECOVER_EV:
1222                 netif_err(efx, rx_err, efx->net_dev,
1223                           "channel %d seen DRIVER RX_RESET event. "
1224                         "Resetting.\n", channel->channel);
1225                 atomic_inc(&efx->rx_reset);
1226                 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1227                 break;
1228         case FSE_BZ_RX_DSC_ERROR_EV:
1229                 if (ev_sub_data < EFX_VI_BASE) {
1230                         netif_err(efx, rx_err, efx->net_dev,
1231                                   "RX DMA Q %d reports descriptor fetch error."
1232                                   " RX Q %d is disabled.\n", ev_sub_data,
1233                                   ev_sub_data);
1234                         efx_schedule_reset(efx, RESET_TYPE_DMA_ERROR);
1235                 }
1236 #ifdef CONFIG_SFC_SRIOV
1237                 else
1238                         efx_siena_sriov_desc_fetch_err(efx, ev_sub_data);
1239 #endif
1240                 break;
1241         case FSE_BZ_TX_DSC_ERROR_EV:
1242                 if (ev_sub_data < EFX_VI_BASE) {
1243                         netif_err(efx, tx_err, efx->net_dev,
1244                                   "TX DMA Q %d reports descriptor fetch error."
1245                                   " TX Q %d is disabled.\n", ev_sub_data,
1246                                   ev_sub_data);
1247                         efx_schedule_reset(efx, RESET_TYPE_DMA_ERROR);
1248                 }
1249 #ifdef CONFIG_SFC_SRIOV
1250                 else
1251                         efx_siena_sriov_desc_fetch_err(efx, ev_sub_data);
1252 #endif
1253                 break;
1254         default:
1255                 netif_vdbg(efx, hw, efx->net_dev,
1256                            "channel %d unknown driver event code %d "
1257                            "data %04x\n", channel->channel, ev_sub_code,
1258                            ev_sub_data);
1259                 break;
1260         }
1261 }
1262
1263 int efx_farch_ev_process(struct efx_channel *channel, int budget)
1264 {
1265         struct efx_nic *efx = channel->efx;
1266         unsigned int read_ptr;
1267         efx_qword_t event, *p_event;
1268         int ev_code;
1269         int tx_packets = 0;
1270         int spent = 0;
1271
1272         if (budget <= 0)
1273                 return spent;
1274
1275         read_ptr = channel->eventq_read_ptr;
1276
1277         for (;;) {
1278                 p_event = efx_event(channel, read_ptr);
1279                 event = *p_event;
1280
1281                 if (!efx_event_present(&event))
1282                         /* End of events */
1283                         break;
1284
1285                 netif_vdbg(channel->efx, intr, channel->efx->net_dev,
1286                            "channel %d event is "EFX_QWORD_FMT"\n",
1287                            channel->channel, EFX_QWORD_VAL(event));
1288
1289                 /* Clear this event by marking it all ones */
1290                 EFX_SET_QWORD(*p_event);
1291
1292                 ++read_ptr;
1293
1294                 ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE);
1295
1296                 switch (ev_code) {
1297                 case FSE_AZ_EV_CODE_RX_EV:
1298                         efx_farch_handle_rx_event(channel, &event);
1299                         if (++spent == budget)
1300                                 goto out;
1301                         break;
1302                 case FSE_AZ_EV_CODE_TX_EV:
1303                         tx_packets += efx_farch_handle_tx_event(channel,
1304                                                                 &event);
1305                         if (tx_packets > efx->txq_entries) {
1306                                 spent = budget;
1307                                 goto out;
1308                         }
1309                         break;
1310                 case FSE_AZ_EV_CODE_DRV_GEN_EV:
1311                         efx_farch_handle_generated_event(channel, &event);
1312                         break;
1313                 case FSE_AZ_EV_CODE_DRIVER_EV:
1314                         efx_farch_handle_driver_event(channel, &event);
1315                         break;
1316 #ifdef CONFIG_SFC_SRIOV
1317                 case FSE_CZ_EV_CODE_USER_EV:
1318                         efx_siena_sriov_event(channel, &event);
1319                         break;
1320 #endif
1321                 case FSE_CZ_EV_CODE_MCDI_EV:
1322                         efx_mcdi_process_event(channel, &event);
1323                         break;
1324                 case FSE_AZ_EV_CODE_GLOBAL_EV:
1325                         if (efx->type->handle_global_event &&
1326                             efx->type->handle_global_event(channel, &event))
1327                                 break;
1328                         /* else fall through */
1329                 default:
1330                         netif_err(channel->efx, hw, channel->efx->net_dev,
1331                                   "channel %d unknown event type %d (data "
1332                                   EFX_QWORD_FMT ")\n", channel->channel,
1333                                   ev_code, EFX_QWORD_VAL(event));
1334                 }
1335         }
1336
1337 out:
1338         channel->eventq_read_ptr = read_ptr;
1339         return spent;
1340 }
1341
1342 /* Allocate buffer table entries for event queue */
1343 int efx_farch_ev_probe(struct efx_channel *channel)
1344 {
1345         struct efx_nic *efx = channel->efx;
1346         unsigned entries;
1347
1348         entries = channel->eventq_mask + 1;
1349         return efx_alloc_special_buffer(efx, &channel->eventq,
1350                                         entries * sizeof(efx_qword_t));
1351 }
1352
1353 int efx_farch_ev_init(struct efx_channel *channel)
1354 {
1355         efx_oword_t reg;
1356         struct efx_nic *efx = channel->efx;
1357
1358         netif_dbg(efx, hw, efx->net_dev,
1359                   "channel %d event queue in special buffers %d-%d\n",
1360                   channel->channel, channel->eventq.index,
1361                   channel->eventq.index + channel->eventq.entries - 1);
1362
1363         EFX_POPULATE_OWORD_3(reg,
1364                              FRF_CZ_TIMER_Q_EN, 1,
1365                              FRF_CZ_HOST_NOTIFY_MODE, 0,
1366                              FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
1367         efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL, channel->channel);
1368
1369         /* Pin event queue buffer */
1370         efx_init_special_buffer(efx, &channel->eventq);
1371
1372         /* Fill event queue with all ones (i.e. empty events) */
1373         memset(channel->eventq.buf.addr, 0xff, channel->eventq.buf.len);
1374
1375         /* Push event queue to card */
1376         EFX_POPULATE_OWORD_3(reg,
1377                              FRF_AZ_EVQ_EN, 1,
1378                              FRF_AZ_EVQ_SIZE, __ffs(channel->eventq.entries),
1379                              FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index);
1380         efx_writeo_table(efx, &reg, efx->type->evq_ptr_tbl_base,
1381                          channel->channel);
1382
1383         return 0;
1384 }
1385
1386 void efx_farch_ev_fini(struct efx_channel *channel)
1387 {
1388         efx_oword_t reg;
1389         struct efx_nic *efx = channel->efx;
1390
1391         /* Remove event queue from card */
1392         EFX_ZERO_OWORD(reg);
1393         efx_writeo_table(efx, &reg, efx->type->evq_ptr_tbl_base,
1394                          channel->channel);
1395         efx_writeo_table(efx, &reg, FR_BZ_TIMER_TBL, channel->channel);
1396
1397         /* Unpin event queue */
1398         efx_fini_special_buffer(efx, &channel->eventq);
1399 }
1400
1401 /* Free buffers backing event queue */
1402 void efx_farch_ev_remove(struct efx_channel *channel)
1403 {
1404         efx_free_special_buffer(channel->efx, &channel->eventq);
1405 }
1406
1407
1408 void efx_farch_ev_test_generate(struct efx_channel *channel)
1409 {
1410         efx_farch_magic_event(channel, EFX_CHANNEL_MAGIC_TEST(channel));
1411 }
1412
1413 void efx_farch_rx_defer_refill(struct efx_rx_queue *rx_queue)
1414 {
1415         efx_farch_magic_event(efx_rx_queue_channel(rx_queue),
1416                               EFX_CHANNEL_MAGIC_FILL(rx_queue));
1417 }
1418
1419 /**************************************************************************
1420  *
1421  * Hardware interrupts
1422  * The hardware interrupt handler does very little work; all the event
1423  * queue processing is carried out by per-channel tasklets.
1424  *
1425  **************************************************************************/
1426
1427 /* Enable/disable/generate interrupts */
1428 static inline void efx_farch_interrupts(struct efx_nic *efx,
1429                                       bool enabled, bool force)
1430 {
1431         efx_oword_t int_en_reg_ker;
1432
1433         EFX_POPULATE_OWORD_3(int_en_reg_ker,
1434                              FRF_AZ_KER_INT_LEVE_SEL, efx->irq_level,
1435                              FRF_AZ_KER_INT_KER, force,
1436                              FRF_AZ_DRV_INT_EN_KER, enabled);
1437         efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER);
1438 }
1439
1440 void efx_farch_irq_enable_master(struct efx_nic *efx)
1441 {
1442         EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1443         wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1444
1445         efx_farch_interrupts(efx, true, false);
1446 }
1447
1448 void efx_farch_irq_disable_master(struct efx_nic *efx)
1449 {
1450         /* Disable interrupts */
1451         efx_farch_interrupts(efx, false, false);
1452 }
1453
1454 /* Generate a test interrupt
1455  * Interrupt must already have been enabled, otherwise nasty things
1456  * may happen.
1457  */
1458 int efx_farch_irq_test_generate(struct efx_nic *efx)
1459 {
1460         efx_farch_interrupts(efx, true, true);
1461         return 0;
1462 }
1463
1464 /* Process a fatal interrupt
1465  * Disable bus mastering ASAP and schedule a reset
1466  */
1467 irqreturn_t efx_farch_fatal_interrupt(struct efx_nic *efx)
1468 {
1469         efx_oword_t *int_ker = efx->irq_status.addr;
1470         efx_oword_t fatal_intr;
1471         int error, mem_perr;
1472
1473         efx_reado(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER);
1474         error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR);
1475
1476         netif_err(efx, hw, efx->net_dev, "SYSTEM ERROR "EFX_OWORD_FMT" status "
1477                   EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1478                   EFX_OWORD_VAL(fatal_intr),
1479                   error ? "disabling bus mastering" : "no recognised error");
1480
1481         /* If this is a memory parity error dump which blocks are offending */
1482         mem_perr = (EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER) ||
1483                     EFX_OWORD_FIELD(fatal_intr, FRF_AZ_SRM_PERR_INT_KER));
1484         if (mem_perr) {
1485                 efx_oword_t reg;
1486                 efx_reado(efx, &reg, FR_AZ_MEM_STAT);
1487                 netif_err(efx, hw, efx->net_dev,
1488                           "SYSTEM ERROR: memory parity error "EFX_OWORD_FMT"\n",
1489                           EFX_OWORD_VAL(reg));
1490         }
1491
1492         /* Disable both devices */
1493         pci_clear_master(efx->pci_dev);
1494         efx_farch_irq_disable_master(efx);
1495
1496         /* Count errors and reset or disable the NIC accordingly */
1497         if (efx->int_error_count == 0 ||
1498             time_after(jiffies, efx->int_error_expire)) {
1499                 efx->int_error_count = 0;
1500                 efx->int_error_expire =
1501                         jiffies + EFX_INT_ERROR_EXPIRE * HZ;
1502         }
1503         if (++efx->int_error_count < EFX_MAX_INT_ERRORS) {
1504                 netif_err(efx, hw, efx->net_dev,
1505                           "SYSTEM ERROR - reset scheduled\n");
1506                 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1507         } else {
1508                 netif_err(efx, hw, efx->net_dev,
1509                           "SYSTEM ERROR - max number of errors seen."
1510                           "NIC will be disabled\n");
1511                 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1512         }
1513
1514         return IRQ_HANDLED;
1515 }
1516
1517 /* Handle a legacy interrupt
1518  * Acknowledges the interrupt and schedule event queue processing.
1519  */
1520 irqreturn_t efx_farch_legacy_interrupt(int irq, void *dev_id)
1521 {
1522         struct efx_nic *efx = dev_id;
1523         bool soft_enabled = ACCESS_ONCE(efx->irq_soft_enabled);
1524         efx_oword_t *int_ker = efx->irq_status.addr;
1525         irqreturn_t result = IRQ_NONE;
1526         struct efx_channel *channel;
1527         efx_dword_t reg;
1528         u32 queues;
1529         int syserr;
1530
1531         /* Read the ISR which also ACKs the interrupts */
1532         efx_readd(efx, &reg, FR_BZ_INT_ISR0);
1533         queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1534
1535         /* Legacy interrupts are disabled too late by the EEH kernel
1536          * code. Disable them earlier.
1537          * If an EEH error occurred, the read will have returned all ones.
1538          */
1539         if (EFX_DWORD_IS_ALL_ONES(reg) && efx_try_recovery(efx) &&
1540             !efx->eeh_disabled_legacy_irq) {
1541                 disable_irq_nosync(efx->legacy_irq);
1542                 efx->eeh_disabled_legacy_irq = true;
1543         }
1544
1545         /* Handle non-event-queue sources */
1546         if (queues & (1U << efx->irq_level) && soft_enabled) {
1547                 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1548                 if (unlikely(syserr))
1549                         return efx_farch_fatal_interrupt(efx);
1550                 efx->last_irq_cpu = raw_smp_processor_id();
1551         }
1552
1553         if (queues != 0) {
1554                 efx->irq_zero_count = 0;
1555
1556                 /* Schedule processing of any interrupting queues */
1557                 if (likely(soft_enabled)) {
1558                         efx_for_each_channel(channel, efx) {
1559                                 if (queues & 1)
1560                                         efx_schedule_channel_irq(channel);
1561                                 queues >>= 1;
1562                         }
1563                 }
1564                 result = IRQ_HANDLED;
1565
1566         } else {
1567                 efx_qword_t *event;
1568
1569                 /* Legacy ISR read can return zero once (SF bug 15783) */
1570
1571                 /* We can't return IRQ_HANDLED more than once on seeing ISR=0
1572                  * because this might be a shared interrupt. */
1573                 if (efx->irq_zero_count++ == 0)
1574                         result = IRQ_HANDLED;
1575
1576                 /* Ensure we schedule or rearm all event queues */
1577                 if (likely(soft_enabled)) {
1578                         efx_for_each_channel(channel, efx) {
1579                                 event = efx_event(channel,
1580                                                   channel->eventq_read_ptr);
1581                                 if (efx_event_present(event))
1582                                         efx_schedule_channel_irq(channel);
1583                                 else
1584                                         efx_farch_ev_read_ack(channel);
1585                         }
1586                 }
1587         }
1588
1589         if (result == IRQ_HANDLED)
1590                 netif_vdbg(efx, intr, efx->net_dev,
1591                            "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1592                            irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1593
1594         return result;
1595 }
1596
1597 /* Handle an MSI interrupt
1598  *
1599  * Handle an MSI hardware interrupt.  This routine schedules event
1600  * queue processing.  No interrupt acknowledgement cycle is necessary.
1601  * Also, we never need to check that the interrupt is for us, since
1602  * MSI interrupts cannot be shared.
1603  */
1604 irqreturn_t efx_farch_msi_interrupt(int irq, void *dev_id)
1605 {
1606         struct efx_msi_context *context = dev_id;
1607         struct efx_nic *efx = context->efx;
1608         efx_oword_t *int_ker = efx->irq_status.addr;
1609         int syserr;
1610
1611         netif_vdbg(efx, intr, efx->net_dev,
1612                    "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1613                    irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1614
1615         if (!likely(ACCESS_ONCE(efx->irq_soft_enabled)))
1616                 return IRQ_HANDLED;
1617
1618         /* Handle non-event-queue sources */
1619         if (context->index == efx->irq_level) {
1620                 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
1621                 if (unlikely(syserr))
1622                         return efx_farch_fatal_interrupt(efx);
1623                 efx->last_irq_cpu = raw_smp_processor_id();
1624         }
1625
1626         /* Schedule processing of the channel */
1627         efx_schedule_channel_irq(efx->channel[context->index]);
1628
1629         return IRQ_HANDLED;
1630 }
1631
1632 /* Setup RSS indirection table.
1633  * This maps from the hash value of the packet to RXQ
1634  */
1635 void efx_farch_rx_push_indir_table(struct efx_nic *efx)
1636 {
1637         size_t i = 0;
1638         efx_dword_t dword;
1639
1640         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
1641                      FR_BZ_RX_INDIRECTION_TBL_ROWS);
1642
1643         for (i = 0; i < FR_BZ_RX_INDIRECTION_TBL_ROWS; i++) {
1644                 EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE,
1645                                      efx->rx_indir_table[i]);
1646                 efx_writed(efx, &dword,
1647                            FR_BZ_RX_INDIRECTION_TBL +
1648                            FR_BZ_RX_INDIRECTION_TBL_STEP * i);
1649         }
1650 }
1651
1652 void efx_farch_rx_pull_indir_table(struct efx_nic *efx)
1653 {
1654         size_t i = 0;
1655         efx_dword_t dword;
1656
1657         BUILD_BUG_ON(ARRAY_SIZE(efx->rx_indir_table) !=
1658                      FR_BZ_RX_INDIRECTION_TBL_ROWS);
1659
1660         for (i = 0; i < FR_BZ_RX_INDIRECTION_TBL_ROWS; i++) {
1661                 efx_readd(efx, &dword,
1662                            FR_BZ_RX_INDIRECTION_TBL +
1663                            FR_BZ_RX_INDIRECTION_TBL_STEP * i);
1664                 efx->rx_indir_table[i] = EFX_DWORD_FIELD(dword, FRF_BZ_IT_QUEUE);
1665         }
1666 }
1667
1668 /* Looks at available SRAM resources and works out how many queues we
1669  * can support, and where things like descriptor caches should live.
1670  *
1671  * SRAM is split up as follows:
1672  * 0                          buftbl entries for channels
1673  * efx->vf_buftbl_base        buftbl entries for SR-IOV
1674  * efx->rx_dc_base            RX descriptor caches
1675  * efx->tx_dc_base            TX descriptor caches
1676  */
1677 void efx_farch_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw)
1678 {
1679         unsigned vi_count, buftbl_min;
1680
1681 #ifdef CONFIG_SFC_SRIOV
1682         struct siena_nic_data *nic_data = efx->nic_data;
1683 #endif
1684
1685         /* Account for the buffer table entries backing the datapath channels
1686          * and the descriptor caches for those channels.
1687          */
1688         buftbl_min = ((efx->n_rx_channels * EFX_MAX_DMAQ_SIZE +
1689                        efx->n_tx_channels * EFX_TXQ_TYPES * EFX_MAX_DMAQ_SIZE +
1690                        efx->n_channels * EFX_MAX_EVQ_SIZE)
1691                       * sizeof(efx_qword_t) / EFX_BUF_SIZE);
1692         vi_count = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
1693
1694 #ifdef CONFIG_SFC_SRIOV
1695         if (efx->type->sriov_wanted) {
1696                 if (efx->type->sriov_wanted(efx)) {
1697                         unsigned vi_dc_entries, buftbl_free;
1698                         unsigned entries_per_vf, vf_limit;
1699
1700                         nic_data->vf_buftbl_base = buftbl_min;
1701
1702                         vi_dc_entries = RX_DC_ENTRIES + TX_DC_ENTRIES;
1703                         vi_count = max(vi_count, EFX_VI_BASE);
1704                         buftbl_free = (sram_lim_qw - buftbl_min -
1705                                        vi_count * vi_dc_entries);
1706
1707                         entries_per_vf = ((vi_dc_entries +
1708                                            EFX_VF_BUFTBL_PER_VI) *
1709                                           efx_vf_size(efx));
1710                         vf_limit = min(buftbl_free / entries_per_vf,
1711                                        (1024U - EFX_VI_BASE) >> efx->vi_scale);
1712
1713                         if (efx->vf_count > vf_limit) {
1714                                 netif_err(efx, probe, efx->net_dev,
1715                                           "Reducing VF count from from %d to %d\n",
1716                                           efx->vf_count, vf_limit);
1717                                 efx->vf_count = vf_limit;
1718                         }
1719                         vi_count += efx->vf_count * efx_vf_size(efx);
1720                 }
1721         }
1722 #endif
1723
1724         efx->tx_dc_base = sram_lim_qw - vi_count * TX_DC_ENTRIES;
1725         efx->rx_dc_base = efx->tx_dc_base - vi_count * RX_DC_ENTRIES;
1726 }
1727
1728 u32 efx_farch_fpga_ver(struct efx_nic *efx)
1729 {
1730         efx_oword_t altera_build;
1731         efx_reado(efx, &altera_build, FR_AZ_ALTERA_BUILD);
1732         return EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER);
1733 }
1734
1735 void efx_farch_init_common(struct efx_nic *efx)
1736 {
1737         efx_oword_t temp;
1738
1739         /* Set positions of descriptor caches in SRAM. */
1740         EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, efx->tx_dc_base);
1741         efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG);
1742         EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, efx->rx_dc_base);
1743         efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG);
1744
1745         /* Set TX descriptor cache size. */
1746         BUILD_BUG_ON(TX_DC_ENTRIES != (8 << TX_DC_ENTRIES_ORDER));
1747         EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
1748         efx_writeo(efx, &temp, FR_AZ_TX_DC_CFG);
1749
1750         /* Set RX descriptor cache size.  Set low watermark to size-8, as
1751          * this allows most efficient prefetching.
1752          */
1753         BUILD_BUG_ON(RX_DC_ENTRIES != (8 << RX_DC_ENTRIES_ORDER));
1754         EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
1755         efx_writeo(efx, &temp, FR_AZ_RX_DC_CFG);
1756         EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
1757         efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM);
1758
1759         /* Program INT_KER address */
1760         EFX_POPULATE_OWORD_2(temp,
1761                              FRF_AZ_NORM_INT_VEC_DIS_KER,
1762                              EFX_INT_MODE_USE_MSI(efx),
1763                              FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr);
1764         efx_writeo(efx, &temp, FR_AZ_INT_ADR_KER);
1765
1766         if (EFX_WORKAROUND_17213(efx) && !EFX_INT_MODE_USE_MSI(efx))
1767                 /* Use an interrupt level unused by event queues */
1768                 efx->irq_level = 0x1f;
1769         else
1770                 /* Use a valid MSI-X vector */
1771                 efx->irq_level = 0;
1772
1773         /* Enable all the genuinely fatal interrupts.  (They are still
1774          * masked by the overall interrupt mask, controlled by
1775          * falcon_interrupts()).
1776          *
1777          * Note: All other fatal interrupts are enabled
1778          */
1779         EFX_POPULATE_OWORD_3(temp,
1780                              FRF_AZ_ILL_ADR_INT_KER_EN, 1,
1781                              FRF_AZ_RBUF_OWN_INT_KER_EN, 1,
1782                              FRF_AZ_TBUF_OWN_INT_KER_EN, 1);
1783         EFX_SET_OWORD_FIELD(temp, FRF_CZ_SRAM_PERR_INT_P_KER_EN, 1);
1784         EFX_INVERT_OWORD(temp);
1785         efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER);
1786
1787         /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
1788          * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
1789          */
1790         efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
1791         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe);
1792         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1);
1793         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1);
1794         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 1);
1795         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1);
1796         /* Enable SW_EV to inherit in char driver - assume harmless here */
1797         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1);
1798         /* Prefetch threshold 2 => fetch when descriptor cache half empty */
1799         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2);
1800         /* Disable hardware watchdog which can misfire */
1801         EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_WD_TMR, 0x3fffff);
1802         /* Squash TX of packets of 16 bytes or less */
1803         EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
1804         efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
1805
1806         EFX_POPULATE_OWORD_4(temp,
1807                              /* Default values */
1808                              FRF_BZ_TX_PACE_SB_NOT_AF, 0x15,
1809                              FRF_BZ_TX_PACE_SB_AF, 0xb,
1810                              FRF_BZ_TX_PACE_FB_BASE, 0,
1811                              /* Allow large pace values in the fast bin. */
1812                              FRF_BZ_TX_PACE_BIN_TH,
1813                              FFE_BZ_TX_PACE_RESERVED);
1814         efx_writeo(efx, &temp, FR_BZ_TX_PACE);
1815 }
1816
1817 /**************************************************************************
1818  *
1819  * Filter tables
1820  *
1821  **************************************************************************
1822  */
1823
1824 /* "Fudge factors" - difference between programmed value and actual depth.
1825  * Due to pipelined implementation we need to program H/W with a value that
1826  * is larger than the hop limit we want.
1827  */
1828 #define EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD 3
1829 #define EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL 1
1830
1831 /* Hard maximum search limit.  Hardware will time-out beyond 200-something.
1832  * We also need to avoid infinite loops in efx_farch_filter_search() when the
1833  * table is full.
1834  */
1835 #define EFX_FARCH_FILTER_CTL_SRCH_MAX 200
1836
1837 /* Don't try very hard to find space for performance hints, as this is
1838  * counter-productive. */
1839 #define EFX_FARCH_FILTER_CTL_SRCH_HINT_MAX 5
1840
1841 enum efx_farch_filter_type {
1842         EFX_FARCH_FILTER_TCP_FULL = 0,
1843         EFX_FARCH_FILTER_TCP_WILD,
1844         EFX_FARCH_FILTER_UDP_FULL,
1845         EFX_FARCH_FILTER_UDP_WILD,
1846         EFX_FARCH_FILTER_MAC_FULL = 4,
1847         EFX_FARCH_FILTER_MAC_WILD,
1848         EFX_FARCH_FILTER_UC_DEF = 8,
1849         EFX_FARCH_FILTER_MC_DEF,
1850         EFX_FARCH_FILTER_TYPE_COUNT,            /* number of specific types */
1851 };
1852
1853 enum efx_farch_filter_table_id {
1854         EFX_FARCH_FILTER_TABLE_RX_IP = 0,
1855         EFX_FARCH_FILTER_TABLE_RX_MAC,
1856         EFX_FARCH_FILTER_TABLE_RX_DEF,
1857         EFX_FARCH_FILTER_TABLE_TX_MAC,
1858         EFX_FARCH_FILTER_TABLE_COUNT,
1859 };
1860
1861 enum efx_farch_filter_index {
1862         EFX_FARCH_FILTER_INDEX_UC_DEF,
1863         EFX_FARCH_FILTER_INDEX_MC_DEF,
1864         EFX_FARCH_FILTER_SIZE_RX_DEF,
1865 };
1866
1867 struct efx_farch_filter_spec {
1868         u8      type:4;
1869         u8      priority:4;
1870         u8      flags;
1871         u16     dmaq_id;
1872         u32     data[3];
1873 };
1874
1875 struct efx_farch_filter_table {
1876         enum efx_farch_filter_table_id id;
1877         u32             offset;         /* address of table relative to BAR */
1878         unsigned        size;           /* number of entries */
1879         unsigned        step;           /* step between entries */
1880         unsigned        used;           /* number currently used */
1881         unsigned long   *used_bitmap;
1882         struct efx_farch_filter_spec *spec;
1883         unsigned        search_limit[EFX_FARCH_FILTER_TYPE_COUNT];
1884 };
1885
1886 struct efx_farch_filter_state {
1887         struct efx_farch_filter_table table[EFX_FARCH_FILTER_TABLE_COUNT];
1888 };
1889
1890 static void
1891 efx_farch_filter_table_clear_entry(struct efx_nic *efx,
1892                                    struct efx_farch_filter_table *table,
1893                                    unsigned int filter_idx);
1894
1895 /* The filter hash function is LFSR polynomial x^16 + x^3 + 1 of a 32-bit
1896  * key derived from the n-tuple.  The initial LFSR state is 0xffff. */
1897 static u16 efx_farch_filter_hash(u32 key)
1898 {
1899         u16 tmp;
1900
1901         /* First 16 rounds */
1902         tmp = 0x1fff ^ key >> 16;
1903         tmp = tmp ^ tmp >> 3 ^ tmp >> 6;
1904         tmp = tmp ^ tmp >> 9;
1905         /* Last 16 rounds */
1906         tmp = tmp ^ tmp << 13 ^ key;
1907         tmp = tmp ^ tmp >> 3 ^ tmp >> 6;
1908         return tmp ^ tmp >> 9;
1909 }
1910
1911 /* To allow for hash collisions, filter search continues at these
1912  * increments from the first possible entry selected by the hash. */
1913 static u16 efx_farch_filter_increment(u32 key)
1914 {
1915         return key * 2 - 1;
1916 }
1917
1918 static enum efx_farch_filter_table_id
1919 efx_farch_filter_spec_table_id(const struct efx_farch_filter_spec *spec)
1920 {
1921         BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_IP !=
1922                      (EFX_FARCH_FILTER_TCP_FULL >> 2));
1923         BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_IP !=
1924                      (EFX_FARCH_FILTER_TCP_WILD >> 2));
1925         BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_IP !=
1926                      (EFX_FARCH_FILTER_UDP_FULL >> 2));
1927         BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_IP !=
1928                      (EFX_FARCH_FILTER_UDP_WILD >> 2));
1929         BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_MAC !=
1930                      (EFX_FARCH_FILTER_MAC_FULL >> 2));
1931         BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_RX_MAC !=
1932                      (EFX_FARCH_FILTER_MAC_WILD >> 2));
1933         BUILD_BUG_ON(EFX_FARCH_FILTER_TABLE_TX_MAC !=
1934                      EFX_FARCH_FILTER_TABLE_RX_MAC + 2);
1935         return (spec->type >> 2) + ((spec->flags & EFX_FILTER_FLAG_TX) ? 2 : 0);
1936 }
1937
1938 static void efx_farch_filter_push_rx_config(struct efx_nic *efx)
1939 {
1940         struct efx_farch_filter_state *state = efx->filter_state;
1941         struct efx_farch_filter_table *table;
1942         efx_oword_t filter_ctl;
1943
1944         efx_reado(efx, &filter_ctl, FR_BZ_RX_FILTER_CTL);
1945
1946         table = &state->table[EFX_FARCH_FILTER_TABLE_RX_IP];
1947         EFX_SET_OWORD_FIELD(filter_ctl, FRF_BZ_TCP_FULL_SRCH_LIMIT,
1948                             table->search_limit[EFX_FARCH_FILTER_TCP_FULL] +
1949                             EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL);
1950         EFX_SET_OWORD_FIELD(filter_ctl, FRF_BZ_TCP_WILD_SRCH_LIMIT,
1951                             table->search_limit[EFX_FARCH_FILTER_TCP_WILD] +
1952                             EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD);
1953         EFX_SET_OWORD_FIELD(filter_ctl, FRF_BZ_UDP_FULL_SRCH_LIMIT,
1954                             table->search_limit[EFX_FARCH_FILTER_UDP_FULL] +
1955                             EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL);
1956         EFX_SET_OWORD_FIELD(filter_ctl, FRF_BZ_UDP_WILD_SRCH_LIMIT,
1957                             table->search_limit[EFX_FARCH_FILTER_UDP_WILD] +
1958                             EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD);
1959
1960         table = &state->table[EFX_FARCH_FILTER_TABLE_RX_MAC];
1961         if (table->size) {
1962                 EFX_SET_OWORD_FIELD(
1963                         filter_ctl, FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT,
1964                         table->search_limit[EFX_FARCH_FILTER_MAC_FULL] +
1965                         EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL);
1966                 EFX_SET_OWORD_FIELD(
1967                         filter_ctl, FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT,
1968                         table->search_limit[EFX_FARCH_FILTER_MAC_WILD] +
1969                         EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD);
1970         }
1971
1972         table = &state->table[EFX_FARCH_FILTER_TABLE_RX_DEF];
1973         if (table->size) {
1974                 EFX_SET_OWORD_FIELD(
1975                         filter_ctl, FRF_CZ_UNICAST_NOMATCH_Q_ID,
1976                         table->spec[EFX_FARCH_FILTER_INDEX_UC_DEF].dmaq_id);
1977                 EFX_SET_OWORD_FIELD(
1978                         filter_ctl, FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED,
1979                         !!(table->spec[EFX_FARCH_FILTER_INDEX_UC_DEF].flags &
1980                            EFX_FILTER_FLAG_RX_RSS));
1981                 EFX_SET_OWORD_FIELD(
1982                         filter_ctl, FRF_CZ_MULTICAST_NOMATCH_Q_ID,
1983                         table->spec[EFX_FARCH_FILTER_INDEX_MC_DEF].dmaq_id);
1984                 EFX_SET_OWORD_FIELD(
1985                         filter_ctl, FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED,
1986                         !!(table->spec[EFX_FARCH_FILTER_INDEX_MC_DEF].flags &
1987                            EFX_FILTER_FLAG_RX_RSS));
1988
1989                 /* There is a single bit to enable RX scatter for all
1990                  * unmatched packets.  Only set it if scatter is
1991                  * enabled in both filter specs.
1992                  */
1993                 EFX_SET_OWORD_FIELD(
1994                         filter_ctl, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q,
1995                         !!(table->spec[EFX_FARCH_FILTER_INDEX_UC_DEF].flags &
1996                            table->spec[EFX_FARCH_FILTER_INDEX_MC_DEF].flags &
1997                            EFX_FILTER_FLAG_RX_SCATTER));
1998         } else {
1999                 /* We don't expose 'default' filters because unmatched
2000                  * packets always go to the queue number found in the
2001                  * RSS table.  But we still need to set the RX scatter
2002                  * bit here.
2003                  */
2004                 EFX_SET_OWORD_FIELD(
2005                         filter_ctl, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q,
2006                         efx->rx_scatter);
2007         }
2008
2009         efx_writeo(efx, &filter_ctl, FR_BZ_RX_FILTER_CTL);
2010 }
2011
2012 static void efx_farch_filter_push_tx_limits(struct efx_nic *efx)
2013 {
2014         struct efx_farch_filter_state *state = efx->filter_state;
2015         struct efx_farch_filter_table *table;
2016         efx_oword_t tx_cfg;
2017
2018         efx_reado(efx, &tx_cfg, FR_AZ_TX_CFG);
2019
2020         table = &state->table[EFX_FARCH_FILTER_TABLE_TX_MAC];
2021         if (table->size) {
2022                 EFX_SET_OWORD_FIELD(
2023                         tx_cfg, FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE,
2024                         table->search_limit[EFX_FARCH_FILTER_MAC_FULL] +
2025                         EFX_FARCH_FILTER_CTL_SRCH_FUDGE_FULL);
2026                 EFX_SET_OWORD_FIELD(
2027                         tx_cfg, FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE,
2028                         table->search_limit[EFX_FARCH_FILTER_MAC_WILD] +
2029                         EFX_FARCH_FILTER_CTL_SRCH_FUDGE_WILD);
2030         }
2031
2032         efx_writeo(efx, &tx_cfg, FR_AZ_TX_CFG);
2033 }
2034
2035 static int
2036 efx_farch_filter_from_gen_spec(struct efx_farch_filter_spec *spec,
2037                                const struct efx_filter_spec *gen_spec)
2038 {
2039         bool is_full = false;
2040
2041         if ((gen_spec->flags & EFX_FILTER_FLAG_RX_RSS) &&
2042             gen_spec->rss_context != EFX_FILTER_RSS_CONTEXT_DEFAULT)
2043                 return -EINVAL;
2044
2045         spec->priority = gen_spec->priority;
2046         spec->flags = gen_spec->flags;
2047         spec->dmaq_id = gen_spec->dmaq_id;
2048
2049         switch (gen_spec->match_flags) {
2050         case (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
2051               EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT |
2052               EFX_FILTER_MATCH_REM_HOST | EFX_FILTER_MATCH_REM_PORT):
2053                 is_full = true;
2054                 /* fall through */
2055         case (EFX_FILTER_MATCH_ETHER_TYPE | EFX_FILTER_MATCH_IP_PROTO |
2056               EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT): {
2057                 __be32 rhost, host1, host2;
2058                 __be16 rport, port1, port2;
2059
2060                 EFX_WARN_ON_PARANOID(!(gen_spec->flags & EFX_FILTER_FLAG_RX));
2061
2062                 if (gen_spec->ether_type != htons(ETH_P_IP))
2063                         return -EPROTONOSUPPORT;
2064                 if (gen_spec->loc_port == 0 ||
2065                     (is_full && gen_spec->rem_port == 0))
2066                         return -EADDRNOTAVAIL;
2067                 switch (gen_spec->ip_proto) {
2068                 case IPPROTO_TCP:
2069                         spec->type = (is_full ? EFX_FARCH_FILTER_TCP_FULL :
2070                                       EFX_FARCH_FILTER_TCP_WILD);
2071                         break;
2072                 case IPPROTO_UDP:
2073                         spec->type = (is_full ? EFX_FARCH_FILTER_UDP_FULL :
2074                                       EFX_FARCH_FILTER_UDP_WILD);
2075                         break;
2076                 default:
2077                         return -EPROTONOSUPPORT;
2078                 }
2079
2080                 /* Filter is constructed in terms of source and destination,
2081                  * with the odd wrinkle that the ports are swapped in a UDP
2082                  * wildcard filter.  We need to convert from local and remote
2083                  * (= zero for wildcard) addresses.
2084                  */
2085                 rhost = is_full ? gen_spec->rem_host[0] : 0;
2086                 rport = is_full ? gen_spec->rem_port : 0;
2087                 host1 = rhost;
2088                 host2 = gen_spec->loc_host[0];
2089                 if (!is_full && gen_spec->ip_proto == IPPROTO_UDP) {
2090                         port1 = gen_spec->loc_port;
2091                         port2 = rport;
2092                 } else {
2093                         port1 = rport;
2094                         port2 = gen_spec->loc_port;
2095                 }
2096                 spec->data[0] = ntohl(host1) << 16 | ntohs(port1);
2097                 spec->data[1] = ntohs(port2) << 16 | ntohl(host1) >> 16;
2098                 spec->data[2] = ntohl(host2);
2099
2100                 break;
2101         }
2102
2103         case EFX_FILTER_MATCH_LOC_MAC | EFX_FILTER_MATCH_OUTER_VID:
2104                 is_full = true;
2105                 /* fall through */
2106         case EFX_FILTER_MATCH_LOC_MAC:
2107                 spec->type = (is_full ? EFX_FARCH_FILTER_MAC_FULL :
2108                               EFX_FARCH_FILTER_MAC_WILD);
2109                 spec->data[0] = is_full ? ntohs(gen_spec->outer_vid) : 0;
2110                 spec->data[1] = (gen_spec->loc_mac[2] << 24 |
2111                                  gen_spec->loc_mac[3] << 16 |
2112                                  gen_spec->loc_mac[4] << 8 |
2113                                  gen_spec->loc_mac[5]);
2114                 spec->data[2] = (gen_spec->loc_mac[0] << 8 |
2115                                  gen_spec->loc_mac[1]);
2116                 break;
2117
2118         case EFX_FILTER_MATCH_LOC_MAC_IG:
2119                 spec->type = (is_multicast_ether_addr(gen_spec->loc_mac) ?
2120                               EFX_FARCH_FILTER_MC_DEF :
2121                               EFX_FARCH_FILTER_UC_DEF);
2122                 memset(spec->data, 0, sizeof(spec->data)); /* ensure equality */
2123                 break;
2124
2125         default:
2126                 return -EPROTONOSUPPORT;
2127         }
2128
2129         return 0;
2130 }
2131
2132 static void
2133 efx_farch_filter_to_gen_spec(struct efx_filter_spec *gen_spec,
2134                              const struct efx_farch_filter_spec *spec)
2135 {
2136         bool is_full = false;
2137
2138         /* *gen_spec should be completely initialised, to be consistent
2139          * with efx_filter_init_{rx,tx}() and in case we want to copy
2140          * it back to userland.
2141          */
2142         memset(gen_spec, 0, sizeof(*gen_spec));
2143
2144         gen_spec->priority = spec->priority;
2145         gen_spec->flags = spec->flags;
2146         gen_spec->dmaq_id = spec->dmaq_id;
2147
2148         switch (spec->type) {
2149         case EFX_FARCH_FILTER_TCP_FULL:
2150         case EFX_FARCH_FILTER_UDP_FULL:
2151                 is_full = true;
2152                 /* fall through */
2153         case EFX_FARCH_FILTER_TCP_WILD:
2154         case EFX_FARCH_FILTER_UDP_WILD: {
2155                 __be32 host1, host2;
2156                 __be16 port1, port2;
2157
2158                 gen_spec->match_flags =
2159                         EFX_FILTER_MATCH_ETHER_TYPE |
2160                         EFX_FILTER_MATCH_IP_PROTO |
2161                         EFX_FILTER_MATCH_LOC_HOST | EFX_FILTER_MATCH_LOC_PORT;
2162                 if (is_full)
2163                         gen_spec->match_flags |= (EFX_FILTER_MATCH_REM_HOST |
2164                                                   EFX_FILTER_MATCH_REM_PORT);
2165                 gen_spec->ether_type = htons(ETH_P_IP);
2166                 gen_spec->ip_proto =
2167                         (spec->type == EFX_FARCH_FILTER_TCP_FULL ||
2168                          spec->type == EFX_FARCH_FILTER_TCP_WILD) ?
2169                         IPPROTO_TCP : IPPROTO_UDP;
2170
2171                 host1 = htonl(spec->data[0] >> 16 | spec->data[1] << 16);
2172                 port1 = htons(spec->data[0]);
2173                 host2 = htonl(spec->data[2]);
2174                 port2 = htons(spec->data[1] >> 16);
2175                 if (spec->flags & EFX_FILTER_FLAG_TX) {
2176                         gen_spec->loc_host[0] = host1;
2177                         gen_spec->rem_host[0] = host2;
2178                 } else {
2179                         gen_spec->loc_host[0] = host2;
2180                         gen_spec->rem_host[0] = host1;
2181                 }
2182                 if (!!(gen_spec->flags & EFX_FILTER_FLAG_TX) ^
2183                     (!is_full && gen_spec->ip_proto == IPPROTO_UDP)) {
2184                         gen_spec->loc_port = port1;
2185                         gen_spec->rem_port = port2;
2186                 } else {
2187                         gen_spec->loc_port = port2;
2188                         gen_spec->rem_port = port1;
2189                 }
2190
2191                 break;
2192         }
2193
2194         case EFX_FARCH_FILTER_MAC_FULL:
2195                 is_full = true;
2196                 /* fall through */
2197         case EFX_FARCH_FILTER_MAC_WILD:
2198                 gen_spec->match_flags = EFX_FILTER_MATCH_LOC_MAC;
2199                 if (is_full)
2200                         gen_spec->match_flags |= EFX_FILTER_MATCH_OUTER_VID;
2201                 gen_spec->loc_mac[0] = spec->data[2] >> 8;
2202                 gen_spec->loc_mac[1] = spec->data[2];
2203                 gen_spec->loc_mac[2] = spec->data[1] >> 24;
2204                 gen_spec->loc_mac[3] = spec->data[1] >> 16;
2205                 gen_spec->loc_mac[4] = spec->data[1] >> 8;
2206                 gen_spec->loc_mac[5] = spec->data[1];
2207                 gen_spec->outer_vid = htons(spec->data[0]);
2208                 break;
2209
2210         case EFX_FARCH_FILTER_UC_DEF:
2211         case EFX_FARCH_FILTER_MC_DEF:
2212                 gen_spec->match_flags = EFX_FILTER_MATCH_LOC_MAC_IG;
2213                 gen_spec->loc_mac[0] = spec->type == EFX_FARCH_FILTER_MC_DEF;
2214                 break;
2215
2216         default:
2217                 WARN_ON(1);
2218                 break;
2219         }
2220 }
2221
2222 static void
2223 efx_farch_filter_init_rx_auto(struct efx_nic *efx,
2224                               struct efx_farch_filter_spec *spec)
2225 {
2226         /* If there's only one channel then disable RSS for non VF
2227          * traffic, thereby allowing VFs to use RSS when the PF can't.
2228          */
2229         spec->priority = EFX_FILTER_PRI_AUTO;
2230         spec->flags = (EFX_FILTER_FLAG_RX |
2231                        (efx_rss_enabled(efx) ? EFX_FILTER_FLAG_RX_RSS : 0) |
2232                        (efx->rx_scatter ? EFX_FILTER_FLAG_RX_SCATTER : 0));
2233         spec->dmaq_id = 0;
2234 }
2235
2236 /* Build a filter entry and return its n-tuple key. */
2237 static u32 efx_farch_filter_build(efx_oword_t *filter,
2238                                   struct efx_farch_filter_spec *spec)
2239 {
2240         u32 data3;
2241
2242         switch (efx_farch_filter_spec_table_id(spec)) {
2243         case EFX_FARCH_FILTER_TABLE_RX_IP: {
2244                 bool is_udp = (spec->type == EFX_FARCH_FILTER_UDP_FULL ||
2245                                spec->type == EFX_FARCH_FILTER_UDP_WILD);
2246                 EFX_POPULATE_OWORD_7(
2247                         *filter,
2248                         FRF_BZ_RSS_EN,
2249                         !!(spec->flags & EFX_FILTER_FLAG_RX_RSS),
2250                         FRF_BZ_SCATTER_EN,
2251                         !!(spec->flags & EFX_FILTER_FLAG_RX_SCATTER),
2252                         FRF_BZ_TCP_UDP, is_udp,
2253                         FRF_BZ_RXQ_ID, spec->dmaq_id,
2254                         EFX_DWORD_2, spec->data[2],
2255                         EFX_DWORD_1, spec->data[1],
2256                         EFX_DWORD_0, spec->data[0]);
2257                 data3 = is_udp;
2258                 break;
2259         }
2260
2261         case EFX_FARCH_FILTER_TABLE_RX_MAC: {
2262                 bool is_wild = spec->type == EFX_FARCH_FILTER_MAC_WILD;
2263                 EFX_POPULATE_OWORD_7(
2264                         *filter,
2265                         FRF_CZ_RMFT_RSS_EN,
2266                         !!(spec->flags & EFX_FILTER_FLAG_RX_RSS),
2267                         FRF_CZ_RMFT_SCATTER_EN,
2268                         !!(spec->flags & EFX_FILTER_FLAG_RX_SCATTER),
2269                         FRF_CZ_RMFT_RXQ_ID, spec->dmaq_id,
2270                         FRF_CZ_RMFT_WILDCARD_MATCH, is_wild,
2271                         FRF_CZ_RMFT_DEST_MAC_HI, spec->data[2],
2272                         FRF_CZ_RMFT_DEST_MAC_LO, spec->data[1],
2273                         FRF_CZ_RMFT_VLAN_ID, spec->data[0]);
2274                 data3 = is_wild;
2275                 break;
2276         }
2277
2278         case EFX_FARCH_FILTER_TABLE_TX_MAC: {
2279                 bool is_wild = spec->type == EFX_FARCH_FILTER_MAC_WILD;
2280                 EFX_POPULATE_OWORD_5(*filter,
2281                                      FRF_CZ_TMFT_TXQ_ID, spec->dmaq_id,
2282                                      FRF_CZ_TMFT_WILDCARD_MATCH, is_wild,
2283                                      FRF_CZ_TMFT_SRC_MAC_HI, spec->data[2],
2284                                      FRF_CZ_TMFT_SRC_MAC_LO, spec->data[1],
2285                                      FRF_CZ_TMFT_VLAN_ID, spec->data[0]);
2286                 data3 = is_wild | spec->dmaq_id << 1;
2287                 break;
2288         }
2289
2290         default:
2291                 BUG();
2292         }
2293
2294         return spec->data[0] ^ spec->data[1] ^ spec->data[2] ^ data3;
2295 }
2296
2297 static bool efx_farch_filter_equal(const struct efx_farch_filter_spec *left,
2298                                    const struct efx_farch_filter_spec *right)
2299 {
2300         if (left->type != right->type ||
2301             memcmp(left->data, right->data, sizeof(left->data)))
2302                 return false;
2303
2304         if (left->flags & EFX_FILTER_FLAG_TX &&
2305             left->dmaq_id != right->dmaq_id)
2306                 return false;
2307
2308         return true;
2309 }
2310
2311 /*
2312  * Construct/deconstruct external filter IDs.  At least the RX filter
2313  * IDs must be ordered by matching priority, for RX NFC semantics.
2314  *
2315  * Deconstruction needs to be robust against invalid IDs so that
2316  * efx_filter_remove_id_safe() and efx_filter_get_filter_safe() can
2317  * accept user-provided IDs.
2318  */
2319
2320 #define EFX_FARCH_FILTER_MATCH_PRI_COUNT        5
2321
2322 static const u8 efx_farch_filter_type_match_pri[EFX_FARCH_FILTER_TYPE_COUNT] = {
2323         [EFX_FARCH_FILTER_TCP_FULL]     = 0,
2324         [EFX_FARCH_FILTER_UDP_FULL]     = 0,
2325         [EFX_FARCH_FILTER_TCP_WILD]     = 1,
2326         [EFX_FARCH_FILTER_UDP_WILD]     = 1,
2327         [EFX_FARCH_FILTER_MAC_FULL]     = 2,
2328         [EFX_FARCH_FILTER_MAC_WILD]     = 3,
2329         [EFX_FARCH_FILTER_UC_DEF]       = 4,
2330         [EFX_FARCH_FILTER_MC_DEF]       = 4,
2331 };
2332
2333 static const enum efx_farch_filter_table_id efx_farch_filter_range_table[] = {
2334         EFX_FARCH_FILTER_TABLE_RX_IP,   /* RX match pri 0 */
2335         EFX_FARCH_FILTER_TABLE_RX_IP,
2336         EFX_FARCH_FILTER_TABLE_RX_MAC,
2337         EFX_FARCH_FILTER_TABLE_RX_MAC,
2338         EFX_FARCH_FILTER_TABLE_RX_DEF,  /* RX match pri 4 */
2339         EFX_FARCH_FILTER_TABLE_TX_MAC,  /* TX match pri 0 */
2340         EFX_FARCH_FILTER_TABLE_TX_MAC,  /* TX match pri 1 */
2341 };
2342
2343 #define EFX_FARCH_FILTER_INDEX_WIDTH 13
2344 #define EFX_FARCH_FILTER_INDEX_MASK ((1 << EFX_FARCH_FILTER_INDEX_WIDTH) - 1)
2345
2346 static inline u32
2347 efx_farch_filter_make_id(const struct efx_farch_filter_spec *spec,
2348                          unsigned int index)
2349 {
2350         unsigned int range;
2351
2352         range = efx_farch_filter_type_match_pri[spec->type];
2353         if (!(spec->flags & EFX_FILTER_FLAG_RX))
2354                 range += EFX_FARCH_FILTER_MATCH_PRI_COUNT;
2355
2356         return range << EFX_FARCH_FILTER_INDEX_WIDTH | index;
2357 }
2358
2359 static inline enum efx_farch_filter_table_id
2360 efx_farch_filter_id_table_id(u32 id)
2361 {
2362         unsigned int range = id >> EFX_FARCH_FILTER_INDEX_WIDTH;
2363
2364         if (range < ARRAY_SIZE(efx_farch_filter_range_table))
2365                 return efx_farch_filter_range_table[range];
2366         else
2367                 return EFX_FARCH_FILTER_TABLE_COUNT; /* invalid */
2368 }
2369
2370 static inline unsigned int efx_farch_filter_id_index(u32 id)
2371 {
2372         return id & EFX_FARCH_FILTER_INDEX_MASK;
2373 }
2374
2375 u32 efx_farch_filter_get_rx_id_limit(struct efx_nic *efx)
2376 {
2377         struct efx_farch_filter_state *state = efx->filter_state;
2378         unsigned int range = EFX_FARCH_FILTER_MATCH_PRI_COUNT - 1;
2379         enum efx_farch_filter_table_id table_id;
2380
2381         do {
2382                 table_id = efx_farch_filter_range_table[range];
2383                 if (state->table[table_id].size != 0)
2384                         return range << EFX_FARCH_FILTER_INDEX_WIDTH |
2385                                 state->table[table_id].size;
2386         } while (range--);
2387
2388         return 0;
2389 }
2390
2391 s32 efx_farch_filter_insert(struct efx_nic *efx,
2392                             struct efx_filter_spec *gen_spec,
2393                             bool replace_equal)
2394 {
2395         struct efx_farch_filter_state *state = efx->filter_state;
2396         struct efx_farch_filter_table *table;
2397         struct efx_farch_filter_spec spec;
2398         efx_oword_t filter;
2399         int rep_index, ins_index;
2400         unsigned int depth = 0;
2401         int rc;
2402
2403         rc = efx_farch_filter_from_gen_spec(&spec, gen_spec);
2404         if (rc)
2405                 return rc;
2406
2407         table = &state->table[efx_farch_filter_spec_table_id(&spec)];
2408         if (table->size == 0)
2409                 return -EINVAL;
2410
2411         netif_vdbg(efx, hw, efx->net_dev,
2412                    "%s: type %d search_limit=%d", __func__, spec.type,
2413                    table->search_limit[spec.type]);
2414
2415         if (table->id == EFX_FARCH_FILTER_TABLE_RX_DEF) {
2416                 /* One filter spec per type */
2417                 BUILD_BUG_ON(EFX_FARCH_FILTER_INDEX_UC_DEF != 0);
2418                 BUILD_BUG_ON(EFX_FARCH_FILTER_INDEX_MC_DEF !=
2419                              EFX_FARCH_FILTER_MC_DEF - EFX_FARCH_FILTER_UC_DEF);
2420                 rep_index = spec.type - EFX_FARCH_FILTER_UC_DEF;
2421                 ins_index = rep_index;
2422
2423                 spin_lock_bh(&efx->filter_lock);
2424         } else {
2425                 /* Search concurrently for
2426                  * (1) a filter to be replaced (rep_index): any filter
2427                  *     with the same match values, up to the current
2428                  *     search depth for this type, and
2429                  * (2) the insertion point (ins_index): (1) or any
2430                  *     free slot before it or up to the maximum search
2431                  *     depth for this priority
2432                  * We fail if we cannot find (2).
2433                  *
2434                  * We can stop once either
2435                  * (a) we find (1), in which case we have definitely
2436                  *     found (2) as well; or
2437                  * (b) we have searched exhaustively for (1), and have
2438                  *     either found (2) or searched exhaustively for it
2439                  */
2440                 u32 key = efx_farch_filter_build(&filter, &spec);
2441                 unsigned int hash = efx_farch_filter_hash(key);
2442                 unsigned int incr = efx_farch_filter_increment(key);
2443                 unsigned int max_rep_depth = table->search_limit[spec.type];
2444                 unsigned int max_ins_depth =
2445                         spec.priority <= EFX_FILTER_PRI_HINT ?
2446                         EFX_FARCH_FILTER_CTL_SRCH_HINT_MAX :
2447                         EFX_FARCH_FILTER_CTL_SRCH_MAX;
2448                 unsigned int i = hash & (table->size - 1);
2449
2450                 ins_index = -1;
2451                 depth = 1;
2452
2453                 spin_lock_bh(&efx->filter_lock);
2454
2455                 for (;;) {
2456                         if (!test_bit(i, table->used_bitmap)) {
2457                                 if (ins_index < 0)
2458                                         ins_index = i;
2459                         } else if (efx_farch_filter_equal(&spec,
2460                                                           &table->spec[i])) {
2461                                 /* Case (a) */
2462                                 if (ins_index < 0)
2463                                         ins_index = i;
2464                                 rep_index = i;
2465                                 break;
2466                         }
2467
2468                         if (depth >= max_rep_depth &&
2469                             (ins_index >= 0 || depth >= max_ins_depth)) {
2470                                 /* Case (b) */
2471                                 if (ins_index < 0) {
2472                                         rc = -EBUSY;
2473                                         goto out;
2474                                 }
2475                                 rep_index = -1;
2476                                 break;
2477                         }
2478
2479                         i = (i + incr) & (table->size - 1);
2480                         ++depth;
2481                 }
2482         }
2483
2484         /* If we found a filter to be replaced, check whether we
2485          * should do so
2486          */
2487         if (rep_index >= 0) {
2488                 struct efx_farch_filter_spec *saved_spec =
2489                         &table->spec[rep_index];
2490
2491                 if (spec.priority == saved_spec->priority && !replace_equal) {
2492                         rc = -EEXIST;
2493                         goto out;
2494                 }
2495                 if (spec.priority < saved_spec->priority) {
2496                         rc = -EPERM;
2497                         goto out;
2498                 }
2499                 if (saved_spec->priority == EFX_FILTER_PRI_AUTO ||
2500                     saved_spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO)
2501                         spec.flags |= EFX_FILTER_FLAG_RX_OVER_AUTO;
2502         }
2503
2504         /* Insert the filter */
2505         if (ins_index != rep_index) {
2506                 __set_bit(ins_index, table->used_bitmap);
2507                 ++table->used;
2508         }
2509         table->spec[ins_index] = spec;
2510
2511         if (table->id == EFX_FARCH_FILTER_TABLE_RX_DEF) {
2512                 efx_farch_filter_push_rx_config(efx);
2513         } else {
2514                 if (table->search_limit[spec.type] < depth) {
2515                         table->search_limit[spec.type] = depth;
2516                         if (spec.flags & EFX_FILTER_FLAG_TX)
2517                                 efx_farch_filter_push_tx_limits(efx);
2518                         else
2519                                 efx_farch_filter_push_rx_config(efx);
2520                 }
2521
2522                 efx_writeo(efx, &filter,
2523                            table->offset + table->step * ins_index);
2524
2525                 /* If we were able to replace a filter by inserting
2526                  * at a lower depth, clear the replaced filter
2527                  */
2528                 if (ins_index != rep_index && rep_index >= 0)
2529                         efx_farch_filter_table_clear_entry(efx, table,
2530                                                            rep_index);
2531         }
2532
2533         netif_vdbg(efx, hw, efx->net_dev,
2534                    "%s: filter type %d index %d rxq %u set",
2535                    __func__, spec.type, ins_index, spec.dmaq_id);
2536         rc = efx_farch_filter_make_id(&spec, ins_index);
2537
2538 out:
2539         spin_unlock_bh(&efx->filter_lock);
2540         return rc;
2541 }
2542
2543 static void
2544 efx_farch_filter_table_clear_entry(struct efx_nic *efx,
2545                                    struct efx_farch_filter_table *table,
2546                                    unsigned int filter_idx)
2547 {
2548         static efx_oword_t filter;
2549
2550         EFX_WARN_ON_PARANOID(!test_bit(filter_idx, table->used_bitmap));
2551         BUG_ON(table->offset == 0); /* can't clear MAC default filters */
2552
2553         __clear_bit(filter_idx, table->used_bitmap);
2554         --table->used;
2555         memset(&table->spec[filter_idx], 0, sizeof(table->spec[0]));
2556
2557         efx_writeo(efx, &filter, table->offset + table->step * filter_idx);
2558
2559         /* If this filter required a greater search depth than
2560          * any other, the search limit for its type can now be
2561          * decreased.  However, it is hard to determine that
2562          * unless the table has become completely empty - in
2563          * which case, all its search limits can be set to 0.
2564          */
2565         if (unlikely(table->used == 0)) {
2566                 memset(table->search_limit, 0, sizeof(table->search_limit));
2567                 if (table->id == EFX_FARCH_FILTER_TABLE_TX_MAC)
2568                         efx_farch_filter_push_tx_limits(efx);
2569                 else
2570                         efx_farch_filter_push_rx_config(efx);
2571         }
2572 }
2573
2574 static int efx_farch_filter_remove(struct efx_nic *efx,
2575                                    struct efx_farch_filter_table *table,
2576                                    unsigned int filter_idx,
2577                                    enum efx_filter_priority priority)
2578 {
2579         struct efx_farch_filter_spec *spec = &table->spec[filter_idx];
2580
2581         if (!test_bit(filter_idx, table->used_bitmap) ||
2582             spec->priority != priority)
2583                 return -ENOENT;
2584
2585         if (spec->flags & EFX_FILTER_FLAG_RX_OVER_AUTO) {
2586                 efx_farch_filter_init_rx_auto(efx, spec);
2587                 efx_farch_filter_push_rx_config(efx);
2588         } else {
2589                 efx_farch_filter_table_clear_entry(efx, table, filter_idx);
2590         }
2591
2592         return 0;
2593 }
2594
2595 int efx_farch_filter_remove_safe(struct efx_nic *efx,
2596                                  enum efx_filter_priority priority,
2597                                  u32 filter_id)
2598 {
2599         struct efx_farch_filter_state *state = efx->filter_state;
2600         enum efx_farch_filter_table_id table_id;
2601         struct efx_farch_filter_table *table;
2602         unsigned int filter_idx;
2603         struct efx_farch_filter_spec *spec;
2604         int rc;
2605
2606         table_id = efx_farch_filter_id_table_id(filter_id);
2607         if ((unsigned int)table_id >= EFX_FARCH_FILTER_TABLE_COUNT)
2608                 return -ENOENT;
2609         table = &state->table[table_id];
2610
2611         filter_idx = efx_farch_filter_id_index(filter_id);
2612         if (filter_idx >= table->size)
2613                 return -ENOENT;
2614         spec = &table->spec[filter_idx];
2615
2616         spin_lock_bh(&efx->filter_lock);
2617         rc = efx_farch_filter_remove(efx, table, filter_idx, priority);
2618         spin_unlock_bh(&efx->filter_lock);
2619
2620         return rc;
2621 }
2622
2623 int efx_farch_filter_get_safe(struct efx_nic *efx,
2624                               enum efx_filter_priority priority,
2625                               u32 filter_id, struct efx_filter_spec *spec_buf)
2626 {
2627         struct efx_farch_filter_state *state = efx->filter_state;
2628         enum efx_farch_filter_table_id table_id;
2629         struct efx_farch_filter_table *table;
2630         struct efx_farch_filter_spec *spec;
2631         unsigned int filter_idx;
2632         int rc;
2633
2634         table_id = efx_farch_filter_id_table_id(filter_id);
2635         if ((unsigned int)table_id >= EFX_FARCH_FILTER_TABLE_COUNT)
2636                 return -ENOENT;
2637         table = &state->table[table_id];
2638
2639         filter_idx = efx_farch_filter_id_index(filter_id);
2640         if (filter_idx >= table->size)
2641                 return -ENOENT;
2642         spec = &table->spec[filter_idx];
2643
2644         spin_lock_bh(&efx->filter_lock);
2645
2646         if (test_bit(filter_idx, table->used_bitmap) &&
2647             spec->priority == priority) {
2648                 efx_farch_filter_to_gen_spec(spec_buf, spec);
2649                 rc = 0;
2650         } else {
2651                 rc = -ENOENT;
2652         }
2653
2654         spin_unlock_bh(&efx->filter_lock);
2655
2656         return rc;
2657 }
2658
2659 static void
2660 efx_farch_filter_table_clear(struct efx_nic *efx,
2661                              enum efx_farch_filter_table_id table_id,
2662                              enum efx_filter_priority priority)
2663 {
2664         struct efx_farch_filter_state *state = efx->filter_state;
2665         struct efx_farch_filter_table *table = &state->table[table_id];
2666         unsigned int filter_idx;
2667
2668         spin_lock_bh(&efx->filter_lock);
2669         for (filter_idx = 0; filter_idx < table->size; ++filter_idx) {
2670                 if (table->spec[filter_idx].priority != EFX_FILTER_PRI_AUTO)
2671                         efx_farch_filter_remove(efx, table,
2672                                                 filter_idx, priority);
2673         }
2674         spin_unlock_bh(&efx->filter_lock);
2675 }
2676
2677 int efx_farch_filter_clear_rx(struct efx_nic *efx,
2678                                enum efx_filter_priority priority)
2679 {
2680         efx_farch_filter_table_clear(efx, EFX_FARCH_FILTER_TABLE_RX_IP,
2681                                      priority);
2682         efx_farch_filter_table_clear(efx, EFX_FARCH_FILTER_TABLE_RX_MAC,
2683                                      priority);
2684         efx_farch_filter_table_clear(efx, EFX_FARCH_FILTER_TABLE_RX_DEF,
2685                                      priority);
2686         return 0;
2687 }
2688
2689 u32 efx_farch_filter_count_rx_used(struct efx_nic *efx,
2690                                    enum efx_filter_priority priority)
2691 {
2692         struct efx_farch_filter_state *state = efx->filter_state;
2693         enum efx_farch_filter_table_id table_id;
2694         struct efx_farch_filter_table *table;
2695         unsigned int filter_idx;
2696         u32 count = 0;
2697
2698         spin_lock_bh(&efx->filter_lock);
2699
2700         for (table_id = EFX_FARCH_FILTER_TABLE_RX_IP;
2701              table_id <= EFX_FARCH_FILTER_TABLE_RX_DEF;
2702              table_id++) {
2703                 table = &state->table[table_id];
2704                 for (filter_idx = 0; filter_idx < table->size; filter_idx++) {
2705                         if (test_bit(filter_idx, table->used_bitmap) &&
2706                             table->spec[filter_idx].priority == priority)
2707                                 ++count;
2708                 }
2709         }
2710
2711         spin_unlock_bh(&efx->filter_lock);
2712
2713         return count;
2714 }
2715
2716 s32 efx_farch_filter_get_rx_ids(struct efx_nic *efx,
2717                                 enum efx_filter_priority priority,
2718                                 u32 *buf, u32 size)
2719 {
2720         struct efx_farch_filter_state *state = efx->filter_state;
2721         enum efx_farch_filter_table_id table_id;
2722         struct efx_farch_filter_table *table;
2723         unsigned int filter_idx;
2724         s32 count = 0;
2725
2726         spin_lock_bh(&efx->filter_lock);
2727
2728         for (table_id = EFX_FARCH_FILTER_TABLE_RX_IP;
2729              table_id <= EFX_FARCH_FILTER_TABLE_RX_DEF;
2730              table_id++) {
2731                 table = &state->table[table_id];
2732                 for (filter_idx = 0; filter_idx < table->size; filter_idx++) {
2733                         if (test_bit(filter_idx, table->used_bitmap) &&
2734                             table->spec[filter_idx].priority == priority) {
2735                                 if (count == size) {
2736                                         count = -EMSGSIZE;
2737                                         goto out;
2738                                 }
2739                                 buf[count++] = efx_farch_filter_make_id(
2740                                         &table->spec[filter_idx], filter_idx);
2741                         }
2742                 }
2743         }
2744 out:
2745         spin_unlock_bh(&efx->filter_lock);
2746
2747         return count;
2748 }
2749
2750 /* Restore filter stater after reset */
2751 void efx_farch_filter_table_restore(struct efx_nic *efx)
2752 {
2753         struct efx_farch_filter_state *state = efx->filter_state;
2754         enum efx_farch_filter_table_id table_id;
2755         struct efx_farch_filter_table *table;
2756         efx_oword_t filter;
2757         unsigned int filter_idx;
2758
2759         spin_lock_bh(&efx->filter_lock);
2760
2761         for (table_id = 0; table_id < EFX_FARCH_FILTER_TABLE_COUNT; table_id++) {
2762                 table = &state->table[table_id];
2763
2764                 /* Check whether this is a regular register table */
2765                 if (table->step == 0)
2766                         continue;
2767
2768                 for (filter_idx = 0; filter_idx < table->size; filter_idx++) {
2769                         if (!test_bit(filter_idx, table->used_bitmap))
2770                                 continue;
2771                         efx_farch_filter_build(&filter, &table->spec[filter_idx]);
2772                         efx_writeo(efx, &filter,
2773                                    table->offset + table->step * filter_idx);
2774                 }
2775         }
2776
2777         efx_farch_filter_push_rx_config(efx);
2778         efx_farch_filter_push_tx_limits(efx);
2779
2780         spin_unlock_bh(&efx->filter_lock);
2781 }
2782
2783 void efx_farch_filter_table_remove(struct efx_nic *efx)
2784 {
2785         struct efx_farch_filter_state *state = efx->filter_state;
2786         enum efx_farch_filter_table_id table_id;
2787
2788         for (table_id = 0; table_id < EFX_FARCH_FILTER_TABLE_COUNT; table_id++) {
2789                 kfree(state->table[table_id].used_bitmap);
2790                 vfree(state->table[table_id].spec);
2791         }
2792         kfree(state);
2793 }
2794
2795 int efx_farch_filter_table_probe(struct efx_nic *efx)
2796 {
2797         struct efx_farch_filter_state *state;
2798         struct efx_farch_filter_table *table;
2799         unsigned table_id;
2800
2801         state = kzalloc(sizeof(struct efx_farch_filter_state), GFP_KERNEL);
2802         if (!state)
2803                 return -ENOMEM;
2804         efx->filter_state = state;
2805
2806         table = &state->table[EFX_FARCH_FILTER_TABLE_RX_IP];
2807         table->id = EFX_FARCH_FILTER_TABLE_RX_IP;
2808         table->offset = FR_BZ_RX_FILTER_TBL0;
2809         table->size = FR_BZ_RX_FILTER_TBL0_ROWS;
2810         table->step = FR_BZ_RX_FILTER_TBL0_STEP;
2811
2812         table = &state->table[EFX_FARCH_FILTER_TABLE_RX_MAC];
2813         table->id = EFX_FARCH_FILTER_TABLE_RX_MAC;
2814         table->offset = FR_CZ_RX_MAC_FILTER_TBL0;
2815         table->size = FR_CZ_RX_MAC_FILTER_TBL0_ROWS;
2816         table->step = FR_CZ_RX_MAC_FILTER_TBL0_STEP;
2817
2818         table = &state->table[EFX_FARCH_FILTER_TABLE_RX_DEF];
2819         table->id = EFX_FARCH_FILTER_TABLE_RX_DEF;
2820         table->size = EFX_FARCH_FILTER_SIZE_RX_DEF;
2821
2822         table = &state->table[EFX_FARCH_FILTER_TABLE_TX_MAC];
2823         table->id = EFX_FARCH_FILTER_TABLE_TX_MAC;
2824         table->offset = FR_CZ_TX_MAC_FILTER_TBL0;
2825         table->size = FR_CZ_TX_MAC_FILTER_TBL0_ROWS;
2826         table->step = FR_CZ_TX_MAC_FILTER_TBL0_STEP;
2827
2828         for (table_id = 0; table_id < EFX_FARCH_FILTER_TABLE_COUNT; table_id++) {
2829                 table = &state->table[table_id];
2830                 if (table->size == 0)
2831                         continue;
2832                 table->used_bitmap = kcalloc(BITS_TO_LONGS(table->size),
2833                                              sizeof(unsigned long),
2834                                              GFP_KERNEL);
2835                 if (!table->used_bitmap)
2836                         goto fail;
2837                 table->spec = vzalloc(table->size * sizeof(*table->spec));
2838                 if (!table->spec)
2839                         goto fail;
2840         }
2841
2842         table = &state->table[EFX_FARCH_FILTER_TABLE_RX_DEF];
2843         if (table->size) {
2844                 /* RX default filters must always exist */
2845                 struct efx_farch_filter_spec *spec;
2846                 unsigned i;
2847
2848                 for (i = 0; i < EFX_FARCH_FILTER_SIZE_RX_DEF; i++) {
2849                         spec = &table->spec[i];
2850                         spec->type = EFX_FARCH_FILTER_UC_DEF + i;
2851                         efx_farch_filter_init_rx_auto(efx, spec);
2852                         __set_bit(i, table->used_bitmap);
2853                 }
2854         }
2855
2856         efx_farch_filter_push_rx_config(efx);
2857
2858         return 0;
2859
2860 fail:
2861         efx_farch_filter_table_remove(efx);
2862         return -ENOMEM;
2863 }
2864
2865 /* Update scatter enable flags for filters pointing to our own RX queues */
2866 void efx_farch_filter_update_rx_scatter(struct efx_nic *efx)
2867 {
2868         struct efx_farch_filter_state *state = efx->filter_state;
2869         enum efx_farch_filter_table_id table_id;
2870         struct efx_farch_filter_table *table;
2871         efx_oword_t filter;
2872         unsigned int filter_idx;
2873
2874         spin_lock_bh(&efx->filter_lock);
2875
2876         for (table_id = EFX_FARCH_FILTER_TABLE_RX_IP;
2877              table_id <= EFX_FARCH_FILTER_TABLE_RX_DEF;
2878              table_id++) {
2879                 table = &state->table[table_id];
2880
2881                 for (filter_idx = 0; filter_idx < table->size; filter_idx++) {
2882                         if (!test_bit(filter_idx, table->used_bitmap) ||
2883                             table->spec[filter_idx].dmaq_id >=
2884                             efx->n_rx_channels)
2885                                 continue;
2886
2887                         if (efx->rx_scatter)
2888                                 table->spec[filter_idx].flags |=
2889                                         EFX_FILTER_FLAG_RX_SCATTER;
2890                         else
2891                                 table->spec[filter_idx].flags &=
2892                                         ~EFX_FILTER_FLAG_RX_SCATTER;
2893
2894                         if (table_id == EFX_FARCH_FILTER_TABLE_RX_DEF)
2895                                 /* Pushed by efx_farch_filter_push_rx_config() */
2896                                 continue;
2897
2898                         efx_farch_filter_build(&filter, &table->spec[filter_idx]);
2899                         efx_writeo(efx, &filter,
2900                                    table->offset + table->step * filter_idx);
2901                 }
2902         }
2903
2904         efx_farch_filter_push_rx_config(efx);
2905
2906         spin_unlock_bh(&efx->filter_lock);
2907 }
2908
2909 #ifdef CONFIG_RFS_ACCEL
2910
2911 s32 efx_farch_filter_rfs_insert(struct efx_nic *efx,
2912                                 struct efx_filter_spec *gen_spec)
2913 {
2914         return efx_farch_filter_insert(efx, gen_spec, true);
2915 }
2916
2917 bool efx_farch_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,
2918                                      unsigned int index)
2919 {
2920         struct efx_farch_filter_state *state = efx->filter_state;
2921         struct efx_farch_filter_table *table =
2922                 &state->table[EFX_FARCH_FILTER_TABLE_RX_IP];
2923
2924         if (test_bit(index, table->used_bitmap) &&
2925             table->spec[index].priority == EFX_FILTER_PRI_HINT &&
2926             rps_may_expire_flow(efx->net_dev, table->spec[index].dmaq_id,
2927                                 flow_id, index)) {
2928                 efx_farch_filter_table_clear_entry(efx, table, index);
2929                 return true;
2930         }
2931
2932         return false;
2933 }
2934
2935 #endif /* CONFIG_RFS_ACCEL */
2936
2937 void efx_farch_filter_sync_rx_mode(struct efx_nic *efx)
2938 {
2939         struct net_device *net_dev = efx->net_dev;
2940         struct netdev_hw_addr *ha;
2941         union efx_multicast_hash *mc_hash = &efx->multicast_hash;
2942         u32 crc;
2943         int bit;
2944
2945         if (!efx_dev_registered(efx))
2946                 return;
2947
2948         netif_addr_lock_bh(net_dev);
2949
2950         efx->unicast_filter = !(net_dev->flags & IFF_PROMISC);
2951
2952         /* Build multicast hash table */
2953         if (net_dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
2954                 memset(mc_hash, 0xff, sizeof(*mc_hash));
2955         } else {
2956                 memset(mc_hash, 0x00, sizeof(*mc_hash));
2957                 netdev_for_each_mc_addr(ha, net_dev) {
2958                         crc = ether_crc_le(ETH_ALEN, ha->addr);
2959                         bit = crc & (EFX_MCAST_HASH_ENTRIES - 1);
2960                         __set_bit_le(bit, mc_hash);
2961                 }
2962
2963                 /* Broadcast packets go through the multicast hash filter.
2964                  * ether_crc_le() of the broadcast address is 0xbe2612ff
2965                  * so we always add bit 0xff to the mask.
2966                  */
2967                 __set_bit_le(0xff, mc_hash);
2968         }
2969
2970         netif_addr_unlock_bh(net_dev);
2971 }