drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c

   1 /*
   2  * QLogic qlcnic NIC Driver
   3  * Copyright (c) 2009-2013 QLogic Corporation
   4  *
   5  * See LICENSE.qlcnic for copyright and licensing details.
   6  */
   7
   8 #include "qlcnic.h"
   9 #include "qlcnic_hdr.h"
  10 #include "qlcnic_83xx_hw.h"
  11 #include "qlcnic_hw.h"
  12
  13 #include <net/ip.h>
  14
  15 #define QLC_83XX_MINIDUMP_FLASH         0x520000
  16 #define QLC_83XX_OCM_INDEX                      3
  17 #define QLC_83XX_PCI_INDEX                      0
  18 #define QLC_83XX_DMA_ENGINE_INDEX               8
  19
  20 static const u32 qlcnic_ms_read_data[] = {
  21         0x410000A8, 0x410000AC, 0x410000B8, 0x410000BC
  22 };
  23
  24 #define QLCNIC_DUMP_WCRB        BIT_0
  25 #define QLCNIC_DUMP_RWCRB       BIT_1
  26 #define QLCNIC_DUMP_ANDCRB      BIT_2
  27 #define QLCNIC_DUMP_ORCRB       BIT_3
  28 #define QLCNIC_DUMP_POLLCRB     BIT_4
  29 #define QLCNIC_DUMP_RD_SAVE     BIT_5
  30 #define QLCNIC_DUMP_WRT_SAVED   BIT_6
  31 #define QLCNIC_DUMP_MOD_SAVE_ST BIT_7
  32 #define QLCNIC_DUMP_SKIP        BIT_7
  33
  34 #define QLCNIC_DUMP_MASK_MAX    0xff
  35
  36 struct qlcnic_pex_dma_descriptor {
  37         u32     read_data_size;
  38         u32     dma_desc_cmd;
  39         u32     src_addr_low;
  40         u32     src_addr_high;
  41         u32     dma_bus_addr_low;
  42         u32     dma_bus_addr_high;
  43         u32     rsvd[6];
  44 } __packed;
  45
  46 struct qlcnic_common_entry_hdr {
  47         u32     type;
  48         u32     offset;
  49         u32     cap_size;
  50         u8      mask;
  51         u8      rsvd[2];
  52         u8      flags;
  53 } __packed;
  54
  55 struct __crb {
  56         u32     addr;
  57         u8      stride;
  58         u8      rsvd1[3];
  59         u32     data_size;
  60         u32     no_ops;
  61         u32     rsvd2[4];
  62 } __packed;
  63
  64 struct __ctrl {
  65         u32     addr;
  66         u8      stride;
  67         u8      index_a;
  68         u16     timeout;
  69         u32     data_size;
  70         u32     no_ops;
  71         u8      opcode;
  72         u8      index_v;
  73         u8      shl_val;
  74         u8      shr_val;
  75         u32     val1;
  76         u32     val2;
  77         u32     val3;
  78 } __packed;
  79
  80 struct __cache {
  81         u32     addr;
  82         u16     stride;
  83         u16     init_tag_val;
  84         u32     size;
  85         u32     no_ops;
  86         u32     ctrl_addr;
  87         u32     ctrl_val;
  88         u32     read_addr;
  89         u8      read_addr_stride;
  90         u8      read_addr_num;
  91         u8      rsvd1[2];
  92 } __packed;
  93
  94 struct __ocm {
  95         u8      rsvd[8];
  96         u32     size;
  97         u32     no_ops;
  98         u8      rsvd1[8];
  99         u32     read_addr;
 100         u32     read_addr_stride;
 101 } __packed;
 102
 103 struct __mem {
 104         u32     desc_card_addr;
 105         u32     dma_desc_cmd;
 106         u32     start_dma_cmd;
 107         u32     rsvd[3];
 108         u32     addr;
 109         u32     size;
 110 } __packed;
 111
 112 struct __mux {
 113         u32     addr;
 114         u8      rsvd[4];
 115         u32     size;
 116         u32     no_ops;
 117         u32     val;
 118         u32     val_stride;
 119         u32     read_addr;
 120         u8      rsvd2[4];
 121 } __packed;
 122
 123 struct __queue {
 124         u32     sel_addr;
 125         u16     stride;
 126         u8      rsvd[2];
 127         u32     size;
 128         u32     no_ops;
 129         u8      rsvd2[8];
 130         u32     read_addr;
 131         u8      read_addr_stride;
 132         u8      read_addr_cnt;
 133         u8      rsvd3[2];
 134 } __packed;
 135
 136 struct __pollrd {
 137         u32     sel_addr;
 138         u32     read_addr;
 139         u32     sel_val;
 140         u16     sel_val_stride;
 141         u16     no_ops;
 142         u32     poll_wait;
 143         u32     poll_mask;
 144         u32     data_size;
 145         u8      rsvd[4];
 146 } __packed;
 147
 148 struct __mux2 {
 149         u32     sel_addr1;
 150         u32     sel_addr2;
 151         u32     sel_val1;
 152         u32     sel_val2;
 153         u32     no_ops;
 154         u32     sel_val_mask;
 155         u32     read_addr;
 156         u8      sel_val_stride;
 157         u8      data_size;
 158         u8      rsvd[2];
 159 } __packed;
 160
 161 struct __pollrdmwr {
 162         u32     addr1;
 163         u32     addr2;
 164         u32     val1;
 165         u32     val2;
 166         u32     poll_wait;
 167         u32     poll_mask;
 168         u32     mod_mask;
 169         u32     data_size;
 170 } __packed;
 171
 172 struct qlcnic_dump_entry {
 173         struct qlcnic_common_entry_hdr hdr;
 174         union {
 175                 struct __crb            crb;
 176                 struct __cache          cache;
 177                 struct __ocm            ocm;
 178                 struct __mem            mem;
 179                 struct __mux            mux;
 180                 struct __queue          que;
 181                 struct __ctrl           ctrl;
 182                 struct __pollrdmwr      pollrdmwr;
 183                 struct __mux2           mux2;
 184                 struct __pollrd         pollrd;
 185         } region;
 186 } __packed;
 187
 188 enum qlcnic_minidump_opcode {
 189         QLCNIC_DUMP_NOP         = 0,
 190         QLCNIC_DUMP_READ_CRB    = 1,
 191         QLCNIC_DUMP_READ_MUX    = 2,
 192         QLCNIC_DUMP_QUEUE       = 3,
 193         QLCNIC_DUMP_BRD_CONFIG  = 4,
 194         QLCNIC_DUMP_READ_OCM    = 6,
 195         QLCNIC_DUMP_PEG_REG     = 7,
 196         QLCNIC_DUMP_L1_DTAG     = 8,
 197         QLCNIC_DUMP_L1_ITAG     = 9,
 198         QLCNIC_DUMP_L1_DATA     = 11,
 199         QLCNIC_DUMP_L1_INST     = 12,
 200         QLCNIC_DUMP_L2_DTAG     = 21,
 201         QLCNIC_DUMP_L2_ITAG     = 22,
 202         QLCNIC_DUMP_L2_DATA     = 23,
 203         QLCNIC_DUMP_L2_INST     = 24,
 204         QLCNIC_DUMP_POLL_RD     = 35,
 205         QLCNIC_READ_MUX2        = 36,
 206         QLCNIC_READ_POLLRDMWR   = 37,
 207         QLCNIC_DUMP_READ_ROM    = 71,
 208         QLCNIC_DUMP_READ_MEM    = 72,
 209         QLCNIC_DUMP_READ_CTRL   = 98,
 210         QLCNIC_DUMP_TLHDR       = 99,
 211         QLCNIC_DUMP_RDEND       = 255
 212 };
 213
 214 inline u32 qlcnic_82xx_get_saved_state(void *t_hdr, u32 index)
 215 {
 216         struct qlcnic_82xx_dump_template_hdr *hdr = t_hdr;
 217
 218         return hdr->saved_state[index];
 219 }
 220
 221 inline void qlcnic_82xx_set_saved_state(void *t_hdr, u32 index,
 222                                         u32 value)
 223 {
 224         struct qlcnic_82xx_dump_template_hdr *hdr = t_hdr;
 225
 226         hdr->saved_state[index] = value;
 227 }
 228
 229 void qlcnic_82xx_cache_tmpl_hdr_values(struct qlcnic_fw_dump *fw_dump)
 230 {
 231         struct qlcnic_82xx_dump_template_hdr *hdr;
 232
 233         hdr = fw_dump->tmpl_hdr;
 234         fw_dump->tmpl_hdr_size = hdr->size;
 235         fw_dump->version = hdr->version;
 236         fw_dump->num_entries = hdr->num_entries;
 237         fw_dump->offset = hdr->offset;
 238
 239         hdr->drv_cap_mask = hdr->cap_mask;
 240         fw_dump->cap_mask = hdr->cap_mask;
 241
 242         fw_dump->use_pex_dma = (hdr->capabilities & BIT_0) ? true : false;
 243 }
 244
 245 inline u32 qlcnic_82xx_get_cap_size(void *t_hdr, int index)
 246 {
 247         struct qlcnic_82xx_dump_template_hdr *hdr = t_hdr;
 248
 249         return hdr->cap_sizes[index];
 250 }
 251
 252 void qlcnic_82xx_set_sys_info(void *t_hdr, int idx, u32 value)
 253 {
 254         struct qlcnic_82xx_dump_template_hdr *hdr = t_hdr;
 255
 256         hdr->sys_info[idx] = value;
 257 }
 258
 259 void qlcnic_82xx_store_cap_mask(void *tmpl_hdr, u32 mask)
 260 {
 261         struct qlcnic_82xx_dump_template_hdr *hdr = tmpl_hdr;
 262
 263         hdr->drv_cap_mask = mask;
 264 }
 265
 266 inline u32 qlcnic_83xx_get_saved_state(void *t_hdr, u32 index)
 267 {
 268         struct qlcnic_83xx_dump_template_hdr *hdr = t_hdr;
 269
 270         return hdr->saved_state[index];
 271 }
 272
 273 inline void qlcnic_83xx_set_saved_state(void *t_hdr, u32 index,
 274                                         u32 value)
 275 {
 276         struct qlcnic_83xx_dump_template_hdr *hdr = t_hdr;
 277
 278         hdr->saved_state[index] = value;
 279 }
 280
 281 #define QLCNIC_TEMPLATE_VERSION (0x20001)
 282
 283 void qlcnic_83xx_cache_tmpl_hdr_values(struct qlcnic_fw_dump *fw_dump)
 284 {
 285         struct qlcnic_83xx_dump_template_hdr *hdr;
 286
 287         hdr = fw_dump->tmpl_hdr;
 288         fw_dump->tmpl_hdr_size = hdr->size;
 289         fw_dump->version = hdr->version;
 290         fw_dump->num_entries = hdr->num_entries;
 291         fw_dump->offset = hdr->offset;
 292
 293         hdr->drv_cap_mask = hdr->cap_mask;
 294         fw_dump->cap_mask = hdr->cap_mask;
 295
 296         fw_dump->use_pex_dma = (fw_dump->version & 0xfffff) >=
 297                                QLCNIC_TEMPLATE_VERSION;
 298 }
 299
 300 inline u32 qlcnic_83xx_get_cap_size(void *t_hdr, int index)
 301 {
 302         struct qlcnic_83xx_dump_template_hdr *hdr = t_hdr;
 303
 304         return hdr->cap_sizes[index];
 305 }
 306
 307 void qlcnic_83xx_set_sys_info(void *t_hdr, int idx, u32 value)
 308 {
 309         struct qlcnic_83xx_dump_template_hdr *hdr = t_hdr;
 310
 311         hdr->sys_info[idx] = value;
 312 }
 313
 314 void qlcnic_83xx_store_cap_mask(void *tmpl_hdr, u32 mask)
 315 {
 316         struct qlcnic_83xx_dump_template_hdr *hdr;
 317
 318         hdr = tmpl_hdr;
 319         hdr->drv_cap_mask = mask;
 320 }
 321
 322 struct qlcnic_dump_operations {
 323         enum qlcnic_minidump_opcode opcode;
 324         u32 (*handler)(struct qlcnic_adapter *, struct qlcnic_dump_entry *,
 325                        __le32 *);
 326 };
 327
 328 static u32 qlcnic_dump_crb(struct qlcnic_adapter *adapter,
 329                            struct qlcnic_dump_entry *entry, __le32 *buffer)
 330 {
 331         int i;
 332         u32 addr, data;
 333         struct __crb *crb = &entry->region.crb;
 334
 335         addr = crb->addr;
 336
 337         for (i = 0; i < crb->no_ops; i++) {
 338                 data = qlcnic_ind_rd(adapter, addr);
 339                 *buffer++ = cpu_to_le32(addr);
 340                 *buffer++ = cpu_to_le32(data);
 341                 addr += crb->stride;
 342         }
 343         return crb->no_ops * 2 * sizeof(u32);
 344 }
 345
 346 static u32 qlcnic_dump_ctrl(struct qlcnic_adapter *adapter,
 347                             struct qlcnic_dump_entry *entry, __le32 *buffer)
 348 {
 349         void *hdr = adapter->ahw->fw_dump.tmpl_hdr;
 350         struct __ctrl *ctr = &entry->region.ctrl;
 351         int i, k, timeout = 0;
 352         u32 addr, data, temp;
 353         u8 no_ops;
 354
 355         addr = ctr->addr;
 356         no_ops = ctr->no_ops;
 357
 358         for (i = 0; i < no_ops; i++) {
 359                 k = 0;
 360                 for (k = 0; k < 8; k++) {
 361                         if (!(ctr->opcode & (1 << k)))
 362                                 continue;
 363                         switch (1 << k) {
 364                         case QLCNIC_DUMP_WCRB:
 365                                 qlcnic_ind_wr(adapter, addr, ctr->val1);
 366                                 break;
 367                         case QLCNIC_DUMP_RWCRB:
 368                                 data = qlcnic_ind_rd(adapter, addr);
 369                                 qlcnic_ind_wr(adapter, addr, data);
 370                                 break;
 371                         case QLCNIC_DUMP_ANDCRB:
 372                                 data = qlcnic_ind_rd(adapter, addr);
 373                                 qlcnic_ind_wr(adapter, addr,
 374                                               (data & ctr->val2));
 375                                 break;
 376                         case QLCNIC_DUMP_ORCRB:
 377                                 data = qlcnic_ind_rd(adapter, addr);
 378                                 qlcnic_ind_wr(adapter, addr,
 379                                               (data | ctr->val3));
 380                                 break;
 381                         case QLCNIC_DUMP_POLLCRB:
 382                                 while (timeout <= ctr->timeout) {
 383                                         data = qlcnic_ind_rd(adapter, addr);
 384                                         if ((data & ctr->val2) == ctr->val1)
 385                                                 break;
 386                                         usleep_range(1000, 2000);
 387                                         timeout++;
 388                                 }
 389                                 if (timeout > ctr->timeout) {
 390                                         dev_info(&adapter->pdev->dev,
 391                                         "Timed out, aborting poll CRB\n");
 392                                         return -EINVAL;
 393                                 }
 394                                 break;
 395                         case QLCNIC_DUMP_RD_SAVE:
 396                                 temp = ctr->index_a;
 397                                 if (temp)
 398                                         addr = qlcnic_get_saved_state(adapter,
 399                                                                       hdr,
 400                                                                       temp);
 401                                 data = qlcnic_ind_rd(adapter, addr);
 402                                 qlcnic_set_saved_state(adapter, hdr,
 403                                                        ctr->index_v, data);
 404                                 break;
 405                         case QLCNIC_DUMP_WRT_SAVED:
 406                                 temp = ctr->index_v;
 407                                 if (temp)
 408                                         data = qlcnic_get_saved_state(adapter,
 409                                                                       hdr,
 410                                                                       temp);
 411                                 else
 412                                         data = ctr->val1;
 413
 414                                 temp = ctr->index_a;
 415                                 if (temp)
 416                                         addr = qlcnic_get_saved_state(adapter,
 417                                                                       hdr,
 418                                                                       temp);
 419                                 qlcnic_ind_wr(adapter, addr, data);
 420                                 break;
 421                         case QLCNIC_DUMP_MOD_SAVE_ST:
 422                                 data = qlcnic_get_saved_state(adapter, hdr,
 423                                                               ctr->index_v);
 424                                 data <<= ctr->shl_val;
 425                                 data >>= ctr->shr_val;
 426                                 if (ctr->val2)
 427                                         data &= ctr->val2;
 428                                 data |= ctr->val3;
 429                                 data += ctr->val1;
 430                                 qlcnic_set_saved_state(adapter, hdr,
 431                                                        ctr->index_v, data);
 432                                 break;
 433                         default:
 434                                 dev_info(&adapter->pdev->dev,
 435                                          "Unknown opcode\n");
 436                                 break;
 437                         }
 438                 }
 439                 addr += ctr->stride;
 440         }
 441         return 0;
 442 }
 443
 444 static u32 qlcnic_dump_mux(struct qlcnic_adapter *adapter,
 445                            struct qlcnic_dump_entry *entry, __le32 *buffer)
 446 {
 447         int loop;
 448         u32 val, data = 0;
 449         struct __mux *mux = &entry->region.mux;
 450
 451         val = mux->val;
 452         for (loop = 0; loop < mux->no_ops; loop++) {
 453                 qlcnic_ind_wr(adapter, mux->addr, val);
 454                 data = qlcnic_ind_rd(adapter, mux->read_addr);
 455                 *buffer++ = cpu_to_le32(val);
 456                 *buffer++ = cpu_to_le32(data);
 457                 val += mux->val_stride;
 458         }
 459         return 2 * mux->no_ops * sizeof(u32);
 460 }
 461
 462 static u32 qlcnic_dump_que(struct qlcnic_adapter *adapter,
 463                            struct qlcnic_dump_entry *entry, __le32 *buffer)
 464 {
 465         int i, loop;
 466         u32 cnt, addr, data, que_id = 0;
 467         struct __queue *que = &entry->region.que;
 468
 469         addr = que->read_addr;
 470         cnt = que->read_addr_cnt;
 471
 472         for (loop = 0; loop < que->no_ops; loop++) {
 473                 qlcnic_ind_wr(adapter, que->sel_addr, que_id);
 474                 addr = que->read_addr;
 475                 for (i = 0; i < cnt; i++) {
 476                         data = qlcnic_ind_rd(adapter, addr);
 477                         *buffer++ = cpu_to_le32(data);
 478                         addr += que->read_addr_stride;
 479                 }
 480                 que_id += que->stride;
 481         }
 482         return que->no_ops * cnt * sizeof(u32);
 483 }
 484
 485 static u32 qlcnic_dump_ocm(struct qlcnic_adapter *adapter,
 486                            struct qlcnic_dump_entry *entry, __le32 *buffer)
 487 {
 488         int i;
 489         u32 data;
 490         void __iomem *addr;
 491         struct __ocm *ocm = &entry->region.ocm;
 492
 493         addr = adapter->ahw->pci_base0 + ocm->read_addr;
 494         for (i = 0; i < ocm->no_ops; i++) {
 495                 data = readl(addr);
 496                 *buffer++ = cpu_to_le32(data);
 497                 addr += ocm->read_addr_stride;
 498         }
 499         return ocm->no_ops * sizeof(u32);
 500 }
 501
 502 static u32 qlcnic_read_rom(struct qlcnic_adapter *adapter,
 503                            struct qlcnic_dump_entry *entry, __le32 *buffer)
 504 {
 505         int i, count = 0;
 506         u32 fl_addr, size, val, lck_val, addr;
 507         struct __mem *rom = &entry->region.mem;
 508
 509         fl_addr = rom->addr;
 510         size = rom->size / 4;
 511 lock_try:
 512         lck_val = QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_LOCK);
 513         if (!lck_val && count < MAX_CTL_CHECK) {
 514                 usleep_range(10000, 11000);
 515                 count++;
 516                 goto lock_try;
 517         }
 518         QLC_SHARED_REG_WR32(adapter, QLCNIC_FLASH_LOCK_OWNER,
 519                             adapter->ahw->pci_func);
 520         for (i = 0; i < size; i++) {
 521                 addr = fl_addr & 0xFFFF0000;
 522                 qlcnic_ind_wr(adapter, FLASH_ROM_WINDOW, addr);
 523                 addr = LSW(fl_addr) + FLASH_ROM_DATA;
 524                 val = qlcnic_ind_rd(adapter, addr);
 525                 fl_addr += 4;
 526                 *buffer++ = cpu_to_le32(val);
 527         }
 528         QLC_SHARED_REG_RD32(adapter, QLCNIC_FLASH_UNLOCK);
 529         return rom->size;
 530 }
 531
 532 static u32 qlcnic_dump_l1_cache(struct qlcnic_adapter *adapter,
 533                                 struct qlcnic_dump_entry *entry, __le32 *buffer)
 534 {
 535         int i;
 536         u32 cnt, val, data, addr;
 537         struct __cache *l1 = &entry->region.cache;
 538
 539         val = l1->init_tag_val;
 540
 541         for (i = 0; i < l1->no_ops; i++) {
 542                 qlcnic_ind_wr(adapter, l1->addr, val);
 543                 qlcnic_ind_wr(adapter, l1->ctrl_addr, LSW(l1->ctrl_val));
 544                 addr = l1->read_addr;
 545                 cnt = l1->read_addr_num;
 546                 while (cnt) {
 547                         data = qlcnic_ind_rd(adapter, addr);
 548                         *buffer++ = cpu_to_le32(data);
 549                         addr += l1->read_addr_stride;
 550                         cnt--;
 551                 }
 552                 val += l1->stride;
 553         }
 554         return l1->no_ops * l1->read_addr_num * sizeof(u32);
 555 }
 556
 557 static u32 qlcnic_dump_l2_cache(struct qlcnic_adapter *adapter,
 558                                 struct qlcnic_dump_entry *entry, __le32 *buffer)
 559 {
 560         int i;
 561         u32 cnt, val, data, addr;
 562         u8 poll_mask, poll_to, time_out = 0;
 563         struct __cache *l2 = &entry->region.cache;
 564
 565         val = l2->init_tag_val;
 566         poll_mask = LSB(MSW(l2->ctrl_val));
 567         poll_to = MSB(MSW(l2->ctrl_val));
 568
 569         for (i = 0; i < l2->no_ops; i++) {
 570                 qlcnic_ind_wr(adapter, l2->addr, val);
 571                 if (LSW(l2->ctrl_val))
 572                         qlcnic_ind_wr(adapter, l2->ctrl_addr,
 573                                       LSW(l2->ctrl_val));
 574                 if (!poll_mask)
 575                         goto skip_poll;
 576                 do {
 577                         data = qlcnic_ind_rd(adapter, l2->ctrl_addr);
 578                         if (!(data & poll_mask))
 579                                 break;
 580                         usleep_range(1000, 2000);
 581                         time_out++;
 582                 } while (time_out <= poll_to);
 583
 584                 if (time_out > poll_to) {
 585                         dev_err(&adapter->pdev->dev,
 586                                 "Timeout exceeded in %s, aborting dump\n",
 587                                 __func__);
 588                         return -EINVAL;
 589                 }
 590 skip_poll:
 591                 addr = l2->read_addr;
 592                 cnt = l2->read_addr_num;
 593                 while (cnt) {
 594                         data = qlcnic_ind_rd(adapter, addr);
 595                         *buffer++ = cpu_to_le32(data);
 596                         addr += l2->read_addr_stride;
 597                         cnt--;
 598                 }
 599                 val += l2->stride;
 600         }
 601         return l2->no_ops * l2->read_addr_num * sizeof(u32);
 602 }
 603
 604 static u32 qlcnic_read_memory_test_agent(struct qlcnic_adapter *adapter,
 605                                          struct __mem *mem, __le32 *buffer,
 606                                          int *ret)
 607 {
 608         u32 addr, data, test;
 609         int i, reg_read;
 610
 611         reg_read = mem->size;
 612         addr = mem->addr;
 613         /* check for data size of multiple of 16 and 16 byte alignment */
 614         if ((addr & 0xf) || (reg_read%16)) {
 615                 dev_info(&adapter->pdev->dev,
 616                          "Unaligned memory addr:0x%x size:0x%x\n",
 617                          addr, reg_read);
 618                 *ret = -EINVAL;
 619                 return 0;
 620         }
 621
 622         mutex_lock(&adapter->ahw->mem_lock);
 623
 624         while (reg_read != 0) {
 625                 qlcnic_ind_wr(adapter, QLCNIC_MS_ADDR_LO, addr);
 626                 qlcnic_ind_wr(adapter, QLCNIC_MS_ADDR_HI, 0);
 627                 qlcnic_ind_wr(adapter, QLCNIC_MS_CTRL, QLCNIC_TA_START_ENABLE);
 628
 629                 for (i = 0; i < MAX_CTL_CHECK; i++) {
 630                         test = qlcnic_ind_rd(adapter, QLCNIC_MS_CTRL);
 631                         if (!(test & TA_CTL_BUSY))
 632                                 break;
 633                 }
 634                 if (i == MAX_CTL_CHECK) {
 635                         if (printk_ratelimit()) {
 636                                 dev_err(&adapter->pdev->dev,
 637                                         "failed to read through agent\n");
 638                                 *ret = -EIO;
 639                                 goto out;
 640                         }
 641                 }
 642                 for (i = 0; i < 4; i++) {
 643                         data = qlcnic_ind_rd(adapter, qlcnic_ms_read_data[i]);
 644                         *buffer++ = cpu_to_le32(data);
 645                 }
 646                 addr += 16;
 647                 reg_read -= 16;
 648                 ret += 16;
 649         }
 650 out:
 651         mutex_unlock(&adapter->ahw->mem_lock);
 652         return mem->size;
 653 }
 654
 655 /* DMA register base address */
 656 #define QLC_DMA_REG_BASE_ADDR(dma_no)   (0x77320000 + (dma_no * 0x10000))
 657
 658 /* DMA register offsets w.r.t base address */
 659 #define QLC_DMA_CMD_BUFF_ADDR_LOW       0
 660 #define QLC_DMA_CMD_BUFF_ADDR_HI        4
 661 #define QLC_DMA_CMD_STATUS_CTRL         8
 662
 663 static int qlcnic_start_pex_dma(struct qlcnic_adapter *adapter,
 664                                 struct __mem *mem)
 665 {
 666         struct device *dev = &adapter->pdev->dev;
 667         u32 dma_no, dma_base_addr, temp_addr;
 668         int i, ret, dma_sts;
 669         void *tmpl_hdr;
 670
 671         tmpl_hdr = adapter->ahw->fw_dump.tmpl_hdr;
 672         dma_no = qlcnic_get_saved_state(adapter, tmpl_hdr,
 673                                         QLC_83XX_DMA_ENGINE_INDEX);
 674         dma_base_addr = QLC_DMA_REG_BASE_ADDR(dma_no);
 675
 676         temp_addr = dma_base_addr + QLC_DMA_CMD_BUFF_ADDR_LOW;
 677         ret = qlcnic_ind_wr(adapter, temp_addr, mem->desc_card_addr);
 678         if (ret)
 679                 return ret;
 680
 681         temp_addr = dma_base_addr + QLC_DMA_CMD_BUFF_ADDR_HI;
 682         ret = qlcnic_ind_wr(adapter, temp_addr, 0);
 683         if (ret)
 684                 return ret;
 685
 686         temp_addr = dma_base_addr + QLC_DMA_CMD_STATUS_CTRL;
 687         ret = qlcnic_ind_wr(adapter, temp_addr, mem->start_dma_cmd);
 688         if (ret)
 689                 return ret;
 690
 691         /* Wait for DMA to complete */
 692         temp_addr = dma_base_addr + QLC_DMA_CMD_STATUS_CTRL;
 693         for (i = 0; i < 400; i++) {
 694                 dma_sts = qlcnic_ind_rd(adapter, temp_addr);
 695
 696                 if (dma_sts & BIT_1)
 697                         usleep_range(250, 500);
 698                 else
 699                         break;
 700         }
 701
 702         if (i >= 400) {
 703                 dev_info(dev, "PEX DMA operation timed out");
 704                 ret = -EIO;
 705         }
 706
 707         return ret;
 708 }
 709
 710 static u32 qlcnic_read_memory_pexdma(struct qlcnic_adapter *adapter,
 711                                      struct __mem *mem,
 712                                      __le32 *buffer, int *ret)
 713 {
 714         struct qlcnic_fw_dump *fw_dump = &adapter->ahw->fw_dump;
 715         u32 temp, dma_base_addr, size = 0, read_size = 0;
 716         struct qlcnic_pex_dma_descriptor *dma_descr;
 717         struct device *dev = &adapter->pdev->dev;
 718         dma_addr_t dma_phys_addr;
 719         void *dma_buffer;
 720         void *tmpl_hdr;
 721
 722         tmpl_hdr = fw_dump->tmpl_hdr;
 723
 724         /* Check if DMA engine is available */
 725         temp = qlcnic_get_saved_state(adapter, tmpl_hdr,
 726                                       QLC_83XX_DMA_ENGINE_INDEX);
 727         dma_base_addr = QLC_DMA_REG_BASE_ADDR(temp);
 728         temp = qlcnic_ind_rd(adapter,
 729                              dma_base_addr + QLC_DMA_CMD_STATUS_CTRL);
 730
 731         if (!(temp & BIT_31)) {
 732                 dev_info(dev, "%s: DMA engine is not available\n", __func__);
 733                 *ret = -EIO;
 734                 return 0;
 735         }
 736
 737         /* Create DMA descriptor */
 738         dma_descr = kzalloc(sizeof(struct qlcnic_pex_dma_descriptor),
 739                             GFP_KERNEL);
 740         if (!dma_descr) {
 741                 *ret = -ENOMEM;
 742                 return 0;
 743         }
 744
 745         /* dma_desc_cmd  0:15  = 0
 746          * dma_desc_cmd 16:19  = mem->dma_desc_cmd 0:3
 747          * dma_desc_cmd 20:23  = pci function number
 748          * dma_desc_cmd 24:31  = mem->dma_desc_cmd 8:15
 749          */
 750         dma_phys_addr = fw_dump->phys_addr;
 751         dma_buffer = fw_dump->dma_buffer;
 752         temp = 0;
 753         temp = mem->dma_desc_cmd & 0xff0f;
 754         temp |= (adapter->ahw->pci_func & 0xf) << 4;
 755         dma_descr->dma_desc_cmd = (temp << 16) & 0xffff0000;
 756         dma_descr->dma_bus_addr_low = LSD(dma_phys_addr);
 757         dma_descr->dma_bus_addr_high = MSD(dma_phys_addr);
 758         dma_descr->src_addr_high = 0;
 759
 760         /* Collect memory dump using multiple DMA operations if required */
 761         while (read_size < mem->size) {
 762                 if (mem->size - read_size >= QLC_PEX_DMA_READ_SIZE)
 763                         size = QLC_PEX_DMA_READ_SIZE;
 764                 else
 765                         size = mem->size - read_size;
 766
 767                 dma_descr->src_addr_low = mem->addr + read_size;
 768                 dma_descr->read_data_size = size;
 769
 770                 /* Write DMA descriptor to MS memory*/
 771                 temp = sizeof(struct qlcnic_pex_dma_descriptor) / 16;
 772                 *ret = qlcnic_ms_mem_write128(adapter, mem->desc_card_addr,
 773                                               (u32 *)dma_descr, temp);
 774                 if (*ret) {
 775                         dev_info(dev, "Failed to write DMA descriptor to MS memory at address 0x%x\n",
 776                                  mem->desc_card_addr);
 777                         goto free_dma_descr;
 778                 }
 779
 780                 *ret = qlcnic_start_pex_dma(adapter, mem);
 781                 if (*ret) {
 782                         dev_info(dev, "Failed to start PEX DMA operation\n");
 783                         goto free_dma_descr;
 784                 }
 785
 786                 memcpy(buffer, dma_buffer, size);
 787                 buffer += size / 4;
 788                 read_size += size;
 789         }
 790
 791 free_dma_descr:
 792         kfree(dma_descr);
 793
 794         return read_size;
 795 }
 796
 797 static u32 qlcnic_read_memory(struct qlcnic_adapter *adapter,
 798                               struct qlcnic_dump_entry *entry, __le32 *buffer)
 799 {
 800         struct qlcnic_fw_dump *fw_dump = &adapter->ahw->fw_dump;
 801         struct device *dev = &adapter->pdev->dev;
 802         struct __mem *mem = &entry->region.mem;
 803         u32 data_size;
 804         int ret = 0;
 805
 806         if (fw_dump->use_pex_dma) {
 807                 data_size = qlcnic_read_memory_pexdma(adapter, mem, buffer,
 808                                                       &ret);
 809                 if (ret)
 810                         dev_info(dev,
 811                                  "Failed to read memory dump using PEX DMA: mask[0x%x]\n",
 812                                  entry->hdr.mask);
 813                 else
 814                         return data_size;
 815         }
 816
 817         data_size = qlcnic_read_memory_test_agent(adapter, mem, buffer, &ret);
 818         if (ret) {
 819                 dev_info(dev,
 820                          "Failed to read memory dump using test agent method: mask[0x%x]\n",
 821                          entry->hdr.mask);
 822                 return 0;
 823         } else {
 824                 return data_size;
 825         }
 826 }
 827
 828 static u32 qlcnic_dump_nop(struct qlcnic_adapter *adapter,
 829                            struct qlcnic_dump_entry *entry, __le32 *buffer)
 830 {
 831         entry->hdr.flags |= QLCNIC_DUMP_SKIP;
 832         return 0;
 833 }
 834
 835 static int qlcnic_valid_dump_entry(struct device *dev,
 836                                    struct qlcnic_dump_entry *entry, u32 size)
 837 {
 838         int ret = 1;
 839         if (size != entry->hdr.cap_size) {
 840                 dev_err(dev,
 841                         "Invalid entry, Type:%d\tMask:%d\tSize:%dCap_size:%d\n",
 842                         entry->hdr.type, entry->hdr.mask, size,
 843                         entry->hdr.cap_size);
 844                 ret = 0;
 845         }
 846         return ret;
 847 }
 848
 849 static u32 qlcnic_read_pollrdmwr(struct qlcnic_adapter *adapter,
 850                                  struct qlcnic_dump_entry *entry,
 851                                  __le32 *buffer)
 852 {
 853         struct __pollrdmwr *poll = &entry->region.pollrdmwr;
 854         u32 data, wait_count, poll_wait, temp;
 855
 856         poll_wait = poll->poll_wait;
 857
 858         qlcnic_ind_wr(adapter, poll->addr1, poll->val1);
 859         wait_count = 0;
 860
 861         while (wait_count < poll_wait) {
 862                 data = qlcnic_ind_rd(adapter, poll->addr1);
 863                 if ((data & poll->poll_mask) != 0)
 864                         break;
 865                 wait_count++;
 866         }
 867
 868         if (wait_count == poll_wait) {
 869                 dev_err(&adapter->pdev->dev,
 870                         "Timeout exceeded in %s, aborting dump\n",
 871                         __func__);
 872                 return 0;
 873         }
 874
 875         data = qlcnic_ind_rd(adapter, poll->addr2) & poll->mod_mask;
 876         qlcnic_ind_wr(adapter, poll->addr2, data);
 877         qlcnic_ind_wr(adapter, poll->addr1, poll->val2);
 878         wait_count = 0;
 879
 880         while (wait_count < poll_wait) {
 881                 temp = qlcnic_ind_rd(adapter, poll->addr1);
 882                 if ((temp & poll->poll_mask) != 0)
 883                         break;
 884                 wait_count++;
 885         }
 886
 887         *buffer++ = cpu_to_le32(poll->addr2);
 888         *buffer++ = cpu_to_le32(data);
 889
 890         return 2 * sizeof(u32);
 891
 892 }
 893
 894 static u32 qlcnic_read_pollrd(struct qlcnic_adapter *adapter,
 895                               struct qlcnic_dump_entry *entry, __le32 *buffer)
 896 {
 897         struct __pollrd *pollrd = &entry->region.pollrd;
 898         u32 data, wait_count, poll_wait, sel_val;
 899         int i;
 900
 901         poll_wait = pollrd->poll_wait;
 902         sel_val = pollrd->sel_val;
 903
 904         for (i = 0; i < pollrd->no_ops; i++) {
 905                 qlcnic_ind_wr(adapter, pollrd->sel_addr, sel_val);
 906                 wait_count = 0;
 907                 while (wait_count < poll_wait) {
 908                         data = qlcnic_ind_rd(adapter, pollrd->sel_addr);
 909                         if ((data & pollrd->poll_mask) != 0)
 910                                 break;
 911                         wait_count++;
 912                 }
 913
 914                 if (wait_count == poll_wait) {
 915                         dev_err(&adapter->pdev->dev,
 916                                 "Timeout exceeded in %s, aborting dump\n",
 917                                 __func__);
 918                         return 0;
 919                 }
 920
 921                 data = qlcnic_ind_rd(adapter, pollrd->read_addr);
 922                 *buffer++ = cpu_to_le32(sel_val);
 923                 *buffer++ = cpu_to_le32(data);
 924                 sel_val += pollrd->sel_val_stride;
 925         }
 926         return pollrd->no_ops * (2 * sizeof(u32));
 927 }
 928
 929 static u32 qlcnic_read_mux2(struct qlcnic_adapter *adapter,
 930                             struct qlcnic_dump_entry *entry, __le32 *buffer)
 931 {
 932         struct __mux2 *mux2 = &entry->region.mux2;
 933         u32 data;
 934         u32 t_sel_val, sel_val1, sel_val2;
 935         int i;
 936
 937         sel_val1 = mux2->sel_val1;
 938         sel_val2 = mux2->sel_val2;
 939
 940         for (i = 0; i < mux2->no_ops; i++) {
 941                 qlcnic_ind_wr(adapter, mux2->sel_addr1, sel_val1);
 942                 t_sel_val = sel_val1 & mux2->sel_val_mask;
 943                 qlcnic_ind_wr(adapter, mux2->sel_addr2, t_sel_val);
 944                 data = qlcnic_ind_rd(adapter, mux2->read_addr);
 945                 *buffer++ = cpu_to_le32(t_sel_val);
 946                 *buffer++ = cpu_to_le32(data);
 947                 qlcnic_ind_wr(adapter, mux2->sel_addr1, sel_val2);
 948                 t_sel_val = sel_val2 & mux2->sel_val_mask;
 949                 qlcnic_ind_wr(adapter, mux2->sel_addr2, t_sel_val);
 950                 data = qlcnic_ind_rd(adapter, mux2->read_addr);
 951                 *buffer++ = cpu_to_le32(t_sel_val);
 952                 *buffer++ = cpu_to_le32(data);
 953                 sel_val1 += mux2->sel_val_stride;
 954                 sel_val2 += mux2->sel_val_stride;
 955         }
 956
 957         return mux2->no_ops * (4 * sizeof(u32));
 958 }
 959
 960 static u32 qlcnic_83xx_dump_rom(struct qlcnic_adapter *adapter,
 961                                 struct qlcnic_dump_entry *entry, __le32 *buffer)
 962 {
 963         u32 fl_addr, size;
 964         struct __mem *rom = &entry->region.mem;
 965
 966         fl_addr = rom->addr;
 967         size = rom->size / 4;
 968
 969         if (!qlcnic_83xx_lockless_flash_read32(adapter, fl_addr,
 970                                                (u8 *)buffer, size))
 971                 return rom->size;
 972
 973         return 0;
 974 }
 975
 976 static const struct qlcnic_dump_operations qlcnic_fw_dump_ops[] = {
 977         {QLCNIC_DUMP_NOP, qlcnic_dump_nop},
 978         {QLCNIC_DUMP_READ_CRB, qlcnic_dump_crb},
 979         {QLCNIC_DUMP_READ_MUX, qlcnic_dump_mux},
 980         {QLCNIC_DUMP_QUEUE, qlcnic_dump_que},
 981         {QLCNIC_DUMP_BRD_CONFIG, qlcnic_read_rom},
 982         {QLCNIC_DUMP_READ_OCM, qlcnic_dump_ocm},
 983         {QLCNIC_DUMP_PEG_REG, qlcnic_dump_ctrl},
 984         {QLCNIC_DUMP_L1_DTAG, qlcnic_dump_l1_cache},
 985         {QLCNIC_DUMP_L1_ITAG, qlcnic_dump_l1_cache},
 986         {QLCNIC_DUMP_L1_DATA, qlcnic_dump_l1_cache},
 987         {QLCNIC_DUMP_L1_INST, qlcnic_dump_l1_cache},
 988         {QLCNIC_DUMP_L2_DTAG, qlcnic_dump_l2_cache},
 989         {QLCNIC_DUMP_L2_ITAG, qlcnic_dump_l2_cache},
 990         {QLCNIC_DUMP_L2_DATA, qlcnic_dump_l2_cache},
 991         {QLCNIC_DUMP_L2_INST, qlcnic_dump_l2_cache},
 992         {QLCNIC_DUMP_READ_ROM, qlcnic_read_rom},
 993         {QLCNIC_DUMP_READ_MEM, qlcnic_read_memory},
 994         {QLCNIC_DUMP_READ_CTRL, qlcnic_dump_ctrl},
 995         {QLCNIC_DUMP_TLHDR, qlcnic_dump_nop},
 996         {QLCNIC_DUMP_RDEND, qlcnic_dump_nop},
 997 };
 998
 999 static const struct qlcnic_dump_operations qlcnic_83xx_fw_dump_ops[] = {
1000         {QLCNIC_DUMP_NOP, qlcnic_dump_nop},
1001         {QLCNIC_DUMP_READ_CRB, qlcnic_dump_crb},
1002         {QLCNIC_DUMP_READ_MUX, qlcnic_dump_mux},
1003         {QLCNIC_DUMP_QUEUE, qlcnic_dump_que},
1004         {QLCNIC_DUMP_BRD_CONFIG, qlcnic_83xx_dump_rom},
1005         {QLCNIC_DUMP_READ_OCM, qlcnic_dump_ocm},
1006         {QLCNIC_DUMP_PEG_REG, qlcnic_dump_ctrl},
1007         {QLCNIC_DUMP_L1_DTAG, qlcnic_dump_l1_cache},
1008         {QLCNIC_DUMP_L1_ITAG, qlcnic_dump_l1_cache},
1009         {QLCNIC_DUMP_L1_DATA, qlcnic_dump_l1_cache},
1010         {QLCNIC_DUMP_L1_INST, qlcnic_dump_l1_cache},
1011         {QLCNIC_DUMP_L2_DTAG, qlcnic_dump_l2_cache},
1012         {QLCNIC_DUMP_L2_ITAG, qlcnic_dump_l2_cache},
1013         {QLCNIC_DUMP_L2_DATA, qlcnic_dump_l2_cache},
1014         {QLCNIC_DUMP_L2_INST, qlcnic_dump_l2_cache},
1015         {QLCNIC_DUMP_POLL_RD, qlcnic_read_pollrd},
1016         {QLCNIC_READ_MUX2, qlcnic_read_mux2},
1017         {QLCNIC_READ_POLLRDMWR, qlcnic_read_pollrdmwr},
1018         {QLCNIC_DUMP_READ_ROM, qlcnic_83xx_dump_rom},
1019         {QLCNIC_DUMP_READ_MEM, qlcnic_read_memory},
1020         {QLCNIC_DUMP_READ_CTRL, qlcnic_dump_ctrl},
1021         {QLCNIC_DUMP_TLHDR, qlcnic_dump_nop},
1022         {QLCNIC_DUMP_RDEND, qlcnic_dump_nop},
1023 };
1024
1025 static uint32_t qlcnic_temp_checksum(uint32_t *temp_buffer, u32 temp_size)
1026 {
1027         uint64_t sum = 0;
1028         int count = temp_size / sizeof(uint32_t);
1029         while (count-- > 0)
1030                 sum += *temp_buffer++;
1031         while (sum >> 32)
1032                 sum = (sum & 0xFFFFFFFF) + (sum >> 32);
1033         return ~sum;
1034 }
1035
1036 static int qlcnic_fw_flash_get_minidump_temp(struct qlcnic_adapter *adapter,
1037                                              u8 *buffer, u32 size)
1038 {
1039         int ret = 0;
1040
1041         if (qlcnic_82xx_check(adapter))
1042                 return -EIO;
1043
1044         if (qlcnic_83xx_lock_flash(adapter))
1045                 return -EIO;
1046
1047         ret = qlcnic_83xx_lockless_flash_read32(adapter,
1048                                                 QLC_83XX_MINIDUMP_FLASH,
1049                                                 buffer, size / sizeof(u32));
1050
1051         qlcnic_83xx_unlock_flash(adapter);
1052
1053         return ret;
1054 }
1055
1056 static int
1057 qlcnic_fw_flash_get_minidump_temp_size(struct qlcnic_adapter *adapter,
1058                                        struct qlcnic_cmd_args *cmd)
1059 {
1060         struct qlcnic_83xx_dump_template_hdr tmp_hdr;
1061         u32 size = sizeof(tmp_hdr) / sizeof(u32);
1062         int ret = 0;
1063
1064         if (qlcnic_82xx_check(adapter))
1065                 return -EIO;
1066
1067         if (qlcnic_83xx_lock_flash(adapter))
1068                 return -EIO;
1069
1070         ret = qlcnic_83xx_lockless_flash_read32(adapter,
1071                                                 QLC_83XX_MINIDUMP_FLASH,
1072                                                 (u8 *)&tmp_hdr, size);
1073
1074         qlcnic_83xx_unlock_flash(adapter);
1075
1076         cmd->rsp.arg[2] = tmp_hdr.size;
1077         cmd->rsp.arg[3] = tmp_hdr.version;
1078
1079         return ret;
1080 }
1081
1082 static int qlcnic_fw_get_minidump_temp_size(struct qlcnic_adapter *adapter,
1083                                             u32 *version, u32 *temp_size,
1084                                             u8 *use_flash_temp)
1085 {
1086         int err = 0;
1087         struct qlcnic_cmd_args cmd;
1088
1089         if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_TEMP_SIZE))
1090                 return -ENOMEM;
1091
1092         err = qlcnic_issue_cmd(adapter, &cmd);
1093         if (err != QLCNIC_RCODE_SUCCESS) {
1094                 if (qlcnic_fw_flash_get_minidump_temp_size(adapter, &cmd)) {
1095                         qlcnic_free_mbx_args(&cmd);
1096                         return -EIO;
1097                 }
1098                 *use_flash_temp = 1;
1099         }
1100
1101         *temp_size = cmd.rsp.arg[2];
1102         *version = cmd.rsp.arg[3];
1103         qlcnic_free_mbx_args(&cmd);
1104
1105         if (!(*temp_size))
1106                 return -EIO;
1107
1108         return 0;
1109 }
1110
1111 static int __qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter,
1112                                              u32 *buffer, u32 temp_size)
1113 {
1114         int err = 0, i;
1115         void *tmp_addr;
1116         __le32 *tmp_buf;
1117         struct qlcnic_cmd_args cmd;
1118         dma_addr_t tmp_addr_t = 0;
1119
1120         tmp_addr = dma_alloc_coherent(&adapter->pdev->dev, temp_size,
1121                                       &tmp_addr_t, GFP_KERNEL);
1122         if (!tmp_addr)
1123                 return -ENOMEM;
1124
1125         if (qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_GET_TEMP_HDR)) {
1126                 err = -ENOMEM;
1127                 goto free_mem;
1128         }
1129
1130         cmd.req.arg[1] = LSD(tmp_addr_t);
1131         cmd.req.arg[2] = MSD(tmp_addr_t);
1132         cmd.req.arg[3] = temp_size;
1133         err = qlcnic_issue_cmd(adapter, &cmd);
1134
1135         tmp_buf = tmp_addr;
1136         if (err == QLCNIC_RCODE_SUCCESS) {
1137                 for (i = 0; i < temp_size / sizeof(u32); i++)
1138                         *buffer++ = __le32_to_cpu(*tmp_buf++);
1139         }
1140
1141         qlcnic_free_mbx_args(&cmd);
1142
1143 free_mem:
1144         dma_free_coherent(&adapter->pdev->dev, temp_size, tmp_addr, tmp_addr_t);
1145
1146         return err;
1147 }
1148
1149 int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter)
1150 {
1151         struct qlcnic_hardware_context *ahw;
1152         struct qlcnic_fw_dump *fw_dump;
1153         u32 version, csum, *tmp_buf;
1154         u8 use_flash_temp = 0;
1155         u32 temp_size = 0;
1156         void *temp_buffer;
1157         int err;
1158
1159         ahw = adapter->ahw;
1160         fw_dump = &ahw->fw_dump;
1161         err = qlcnic_fw_get_minidump_temp_size(adapter, &version, &temp_size,
1162                                                &use_flash_temp);
1163         if (err) {
1164                 dev_err(&adapter->pdev->dev,
1165                         "Can't get template size %d\n", err);
1166                 return -EIO;
1167         }
1168
1169         fw_dump->tmpl_hdr = vzalloc(temp_size);
1170         if (!fw_dump->tmpl_hdr)
1171                 return -ENOMEM;
1172
1173         tmp_buf = (u32 *)fw_dump->tmpl_hdr;
1174         if (use_flash_temp)
1175                 goto flash_temp;
1176
1177         err = __qlcnic_fw_cmd_get_minidump_temp(adapter, tmp_buf, temp_size);
1178
1179         if (err) {
1180 flash_temp:
1181                 err = qlcnic_fw_flash_get_minidump_temp(adapter, (u8 *)tmp_buf,
1182                                                         temp_size);
1183
1184                 if (err) {
1185                         dev_err(&adapter->pdev->dev,
1186                                 "Failed to get minidump template header %d\n",
1187                                 err);
1188                         vfree(fw_dump->tmpl_hdr);
1189                         fw_dump->tmpl_hdr = NULL;
1190                         return -EIO;
1191                 }
1192         }
1193
1194         csum = qlcnic_temp_checksum((uint32_t *)tmp_buf, temp_size);
1195
1196         if (csum) {
1197                 dev_err(&adapter->pdev->dev,
1198                         "Template header checksum validation failed\n");
1199                 vfree(fw_dump->tmpl_hdr);
1200                 fw_dump->tmpl_hdr = NULL;
1201                 return -EIO;
1202         }
1203
1204         qlcnic_cache_tmpl_hdr_values(adapter, fw_dump);
1205
1206         if (fw_dump->use_pex_dma) {
1207                 fw_dump->dma_buffer = NULL;
1208                 temp_buffer = dma_alloc_coherent(&adapter->pdev->dev,
1209                                                  QLC_PEX_DMA_READ_SIZE,
1210                                                  &fw_dump->phys_addr,
1211                                                  GFP_KERNEL);
1212                 if (!temp_buffer)
1213                         fw_dump->use_pex_dma = false;
1214                 else
1215                         fw_dump->dma_buffer = temp_buffer;
1216         }
1217
1218
1219         dev_info(&adapter->pdev->dev,
1220                  "Default minidump capture mask 0x%x\n",
1221                  fw_dump->cap_mask);
1222
1223         qlcnic_enable_fw_dump_state(adapter);
1224
1225         return 0;
1226 }
1227
1228 int qlcnic_dump_fw(struct qlcnic_adapter *adapter)
1229 {
1230         struct qlcnic_fw_dump *fw_dump = &adapter->ahw->fw_dump;
1231         static const struct qlcnic_dump_operations *fw_dump_ops;
1232         struct qlcnic_83xx_dump_template_hdr *hdr_83xx;
1233         u32 entry_offset, dump, no_entries, buf_offset = 0;
1234         int i, k, ops_cnt, ops_index, dump_size = 0;
1235         struct device *dev = &adapter->pdev->dev;
1236         struct qlcnic_hardware_context *ahw;
1237         struct qlcnic_dump_entry *entry;
1238         void *tmpl_hdr;
1239         u32 ocm_window;
1240         __le32 *buffer;
1241         char mesg[64];
1242         char *msg[] = {mesg, NULL};
1243
1244         ahw = adapter->ahw;
1245         tmpl_hdr = fw_dump->tmpl_hdr;
1246
1247         /* Return if we don't have firmware dump template header */
1248         if (!tmpl_hdr)
1249                 return -EIO;
1250
1251         if (!qlcnic_check_fw_dump_state(adapter)) {
1252                 dev_info(&adapter->pdev->dev, "Dump not enabled\n");
1253                 return -EIO;
1254         }
1255
1256         if (fw_dump->clr) {
1257                 dev_info(&adapter->pdev->dev,
1258                          "Previous dump not cleared, not capturing dump\n");
1259                 return -EIO;
1260         }
1261
1262         netif_info(adapter->ahw, drv, adapter->netdev, "Take FW dump\n");
1263         /* Calculate the size for dump data area only */
1264         for (i = 2, k = 1; (i & QLCNIC_DUMP_MASK_MAX); i <<= 1, k++)
1265                 if (i & fw_dump->cap_mask)
1266                         dump_size += qlcnic_get_cap_size(adapter, tmpl_hdr, k);
1267
1268         if (!dump_size)
1269                 return -EIO;
1270
1271         fw_dump->data = vzalloc(dump_size);
1272         if (!fw_dump->data)
1273                 return -ENOMEM;
1274
1275         buffer = fw_dump->data;
1276         fw_dump->size = dump_size;
1277         no_entries = fw_dump->num_entries;
1278         entry_offset = fw_dump->offset;
1279         qlcnic_set_sys_info(adapter, tmpl_hdr, 0, QLCNIC_DRIVER_VERSION);
1280         qlcnic_set_sys_info(adapter, tmpl_hdr, 1, adapter->fw_version);
1281
1282         if (qlcnic_82xx_check(adapter)) {
1283                 ops_cnt = ARRAY_SIZE(qlcnic_fw_dump_ops);
1284                 fw_dump_ops = qlcnic_fw_dump_ops;
1285         } else {
1286                 hdr_83xx = tmpl_hdr;
1287                 ops_cnt = ARRAY_SIZE(qlcnic_83xx_fw_dump_ops);
1288                 fw_dump_ops = qlcnic_83xx_fw_dump_ops;
1289                 ocm_window = hdr_83xx->ocm_wnd_reg[ahw->pci_func];
1290                 hdr_83xx->saved_state[QLC_83XX_OCM_INDEX] = ocm_window;
1291                 hdr_83xx->saved_state[QLC_83XX_PCI_INDEX] = ahw->pci_func;
1292         }
1293
1294         for (i = 0; i < no_entries; i++) {
1295                 entry = tmpl_hdr + entry_offset;
1296                 if (!(entry->hdr.mask & fw_dump->cap_mask)) {
1297                         entry->hdr.flags |= QLCNIC_DUMP_SKIP;
1298                         entry_offset += entry->hdr.offset;
1299                         continue;
1300                 }
1301
1302                 /* Find the handler for this entry */
1303                 ops_index = 0;
1304                 while (ops_index < ops_cnt) {
1305                         if (entry->hdr.type == fw_dump_ops[ops_index].opcode)
1306                                 break;
1307                         ops_index++;
1308                 }
1309
1310                 if (ops_index == ops_cnt) {
1311                         dev_info(dev, "Skipping unknown entry opcode %d\n",
1312                                  entry->hdr.type);
1313                         entry->hdr.flags |= QLCNIC_DUMP_SKIP;
1314                         entry_offset += entry->hdr.offset;
1315                         continue;
1316                 }
1317
1318                 /* Collect dump for this entry */
1319                 dump = fw_dump_ops[ops_index].handler(adapter, entry, buffer);
1320                 if (!qlcnic_valid_dump_entry(dev, entry, dump)) {
1321                         entry->hdr.flags |= QLCNIC_DUMP_SKIP;
1322                         entry_offset += entry->hdr.offset;
1323                         continue;
1324                 }
1325
1326                 buf_offset += entry->hdr.cap_size;
1327                 entry_offset += entry->hdr.offset;
1328                 buffer = fw_dump->data + buf_offset;
1329         }
1330
1331         fw_dump->clr = 1;
1332         snprintf(mesg, sizeof(mesg), "FW_DUMP=%s", adapter->netdev->name);
1333         netdev_info(adapter->netdev,
1334                     "Dump data %d bytes captured, template header size %d bytes\n",
1335                     fw_dump->size, fw_dump->tmpl_hdr_size);
1336         /* Send a udev event to notify availability of FW dump */
1337         kobject_uevent_env(&dev->kobj, KOBJ_CHANGE, msg);
1338
1339         return 0;
1340 }
1341
1342 void qlcnic_83xx_get_minidump_template(struct qlcnic_adapter *adapter)
1343 {
1344         u32 prev_version, current_version;
1345         struct qlcnic_hardware_context *ahw = adapter->ahw;
1346         struct qlcnic_fw_dump *fw_dump = &ahw->fw_dump;
1347         struct pci_dev *pdev = adapter->pdev;
1348
1349         prev_version = adapter->fw_version;
1350         current_version = qlcnic_83xx_get_fw_version(adapter);
1351
1352         if (fw_dump->tmpl_hdr == NULL || current_version > prev_version) {
1353                 if (fw_dump->tmpl_hdr)
1354                         vfree(fw_dump->tmpl_hdr);
1355                 if (!qlcnic_fw_cmd_get_minidump_temp(adapter))
1356                         dev_info(&pdev->dev, "Supports FW dump capability\n");
1357         }
1358 }