drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c

   1 /*
   2  * QLogic qlcnic NIC Driver
   3  * Copyright (c) 2009-2013 QLogic Corporation
   4  *
   5  * See LICENSE.qlcnic for copyright and licensing details.
   6  */
   7
   8 #include "qlcnic.h"
   9 #include "qlcnic_hdr.h"
  10
  11 #include <linux/slab.h>
  12 #include <net/ip.h>
  13 #include <linux/bitops.h>
  14
  15 #define MASK(n) ((1ULL<<(n))-1)
  16 #define OCM_WIN_P3P(addr) (addr & 0xffc0000)
  17
  18 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
  19
  20 #define CRB_BLK(off)    ((off >> 20) & 0x3f)
  21 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
  22 #define CRB_WINDOW_2M   (0x130060)
  23 #define CRB_HI(off)     ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
  24 #define CRB_INDIRECT_2M (0x1e0000UL)
  25
  26 struct qlcnic_ms_reg_ctrl {
  27         u32 ocm_window;
  28         u32 control;
  29         u32 hi;
  30         u32 low;
  31         u32 rd[4];
  32         u32 wd[4];
  33         u64 off;
  34 };
  35
  36 #ifndef readq
  37 static inline u64 readq(void __iomem *addr)
  38 {
  39         return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
  40 }
  41 #endif
  42
  43 #ifndef writeq
  44 static inline void writeq(u64 val, void __iomem *addr)
  45 {
  46         writel(((u32) (val)), (addr));
  47         writel(((u32) (val >> 32)), (addr + 4));
  48 }
  49 #endif
  50
  51 static struct crb_128M_2M_block_map
  52 crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
  53     {{{0, 0,         0,         0} } },         /* 0: PCI */
  54     {{{1, 0x0100000, 0x0102000, 0x120000},      /* 1: PCIE */
  55           {1, 0x0110000, 0x0120000, 0x130000},
  56           {1, 0x0120000, 0x0122000, 0x124000},
  57           {1, 0x0130000, 0x0132000, 0x126000},
  58           {1, 0x0140000, 0x0142000, 0x128000},
  59           {1, 0x0150000, 0x0152000, 0x12a000},
  60           {1, 0x0160000, 0x0170000, 0x110000},
  61           {1, 0x0170000, 0x0172000, 0x12e000},
  62           {0, 0x0000000, 0x0000000, 0x000000},
  63           {0, 0x0000000, 0x0000000, 0x000000},
  64           {0, 0x0000000, 0x0000000, 0x000000},
  65           {0, 0x0000000, 0x0000000, 0x000000},
  66           {0, 0x0000000, 0x0000000, 0x000000},
  67           {0, 0x0000000, 0x0000000, 0x000000},
  68           {1, 0x01e0000, 0x01e0800, 0x122000},
  69           {0, 0x0000000, 0x0000000, 0x000000} } },
  70         {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
  71     {{{0, 0,         0,         0} } },     /* 3: */
  72     {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
  73     {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE   */
  74     {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU   */
  75     {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM    */
  76     {{{1, 0x0800000, 0x0802000, 0x170000},  /* 8: SQM0  */
  77       {0, 0x0000000, 0x0000000, 0x000000},
  78       {0, 0x0000000, 0x0000000, 0x000000},
  79       {0, 0x0000000, 0x0000000, 0x000000},
  80       {0, 0x0000000, 0x0000000, 0x000000},
  81       {0, 0x0000000, 0x0000000, 0x000000},
  82       {0, 0x0000000, 0x0000000, 0x000000},
  83       {0, 0x0000000, 0x0000000, 0x000000},
  84       {0, 0x0000000, 0x0000000, 0x000000},
  85       {0, 0x0000000, 0x0000000, 0x000000},
  86       {0, 0x0000000, 0x0000000, 0x000000},
  87       {0, 0x0000000, 0x0000000, 0x000000},
  88       {0, 0x0000000, 0x0000000, 0x000000},
  89       {0, 0x0000000, 0x0000000, 0x000000},
  90       {0, 0x0000000, 0x0000000, 0x000000},
  91       {1, 0x08f0000, 0x08f2000, 0x172000} } },
  92     {{{1, 0x0900000, 0x0902000, 0x174000},      /* 9: SQM1*/
  93       {0, 0x0000000, 0x0000000, 0x000000},
  94       {0, 0x0000000, 0x0000000, 0x000000},
  95       {0, 0x0000000, 0x0000000, 0x000000},
  96       {0, 0x0000000, 0x0000000, 0x000000},
  97       {0, 0x0000000, 0x0000000, 0x000000},
  98       {0, 0x0000000, 0x0000000, 0x000000},
  99       {0, 0x0000000, 0x0000000, 0x000000},
 100       {0, 0x0000000, 0x0000000, 0x000000},
 101       {0, 0x0000000, 0x0000000, 0x000000},
 102       {0, 0x0000000, 0x0000000, 0x000000},
 103       {0, 0x0000000, 0x0000000, 0x000000},
 104       {0, 0x0000000, 0x0000000, 0x000000},
 105       {0, 0x0000000, 0x0000000, 0x000000},
 106       {0, 0x0000000, 0x0000000, 0x000000},
 107       {1, 0x09f0000, 0x09f2000, 0x176000} } },
 108     {{{0, 0x0a00000, 0x0a02000, 0x178000},      /* 10: SQM2*/
 109       {0, 0x0000000, 0x0000000, 0x000000},
 110       {0, 0x0000000, 0x0000000, 0x000000},
 111       {0, 0x0000000, 0x0000000, 0x000000},
 112       {0, 0x0000000, 0x0000000, 0x000000},
 113       {0, 0x0000000, 0x0000000, 0x000000},
 114       {0, 0x0000000, 0x0000000, 0x000000},
 115       {0, 0x0000000, 0x0000000, 0x000000},
 116       {0, 0x0000000, 0x0000000, 0x000000},
 117       {0, 0x0000000, 0x0000000, 0x000000},
 118       {0, 0x0000000, 0x0000000, 0x000000},
 119       {0, 0x0000000, 0x0000000, 0x000000},
 120       {0, 0x0000000, 0x0000000, 0x000000},
 121       {0, 0x0000000, 0x0000000, 0x000000},
 122       {0, 0x0000000, 0x0000000, 0x000000},
 123       {1, 0x0af0000, 0x0af2000, 0x17a000} } },
 124     {{{0, 0x0b00000, 0x0b02000, 0x17c000},      /* 11: SQM3*/
 125       {0, 0x0000000, 0x0000000, 0x000000},
 126       {0, 0x0000000, 0x0000000, 0x000000},
 127       {0, 0x0000000, 0x0000000, 0x000000},
 128       {0, 0x0000000, 0x0000000, 0x000000},
 129       {0, 0x0000000, 0x0000000, 0x000000},
 130       {0, 0x0000000, 0x0000000, 0x000000},
 131       {0, 0x0000000, 0x0000000, 0x000000},
 132       {0, 0x0000000, 0x0000000, 0x000000},
 133       {0, 0x0000000, 0x0000000, 0x000000},
 134       {0, 0x0000000, 0x0000000, 0x000000},
 135       {0, 0x0000000, 0x0000000, 0x000000},
 136       {0, 0x0000000, 0x0000000, 0x000000},
 137       {0, 0x0000000, 0x0000000, 0x000000},
 138       {0, 0x0000000, 0x0000000, 0x000000},
 139       {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
 140         {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
 141         {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
 142         {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
 143         {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
 144         {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
 145         {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
 146         {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
 147         {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
 148         {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
 149         {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
 150         {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
 151         {{{0, 0,         0,         0} } },     /* 23: */
 152         {{{0, 0,         0,         0} } },     /* 24: */
 153         {{{0, 0,         0,         0} } },     /* 25: */
 154         {{{0, 0,         0,         0} } },     /* 26: */
 155         {{{0, 0,         0,         0} } },     /* 27: */
 156         {{{0, 0,         0,         0} } },     /* 28: */
 157         {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
 158     {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
 159     {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
 160         {{{0} } },                              /* 32: PCI */
 161         {{{1, 0x2100000, 0x2102000, 0x120000},  /* 33: PCIE */
 162           {1, 0x2110000, 0x2120000, 0x130000},
 163           {1, 0x2120000, 0x2122000, 0x124000},
 164           {1, 0x2130000, 0x2132000, 0x126000},
 165           {1, 0x2140000, 0x2142000, 0x128000},
 166           {1, 0x2150000, 0x2152000, 0x12a000},
 167           {1, 0x2160000, 0x2170000, 0x110000},
 168           {1, 0x2170000, 0x2172000, 0x12e000},
 169           {0, 0x0000000, 0x0000000, 0x000000},
 170           {0, 0x0000000, 0x0000000, 0x000000},
 171           {0, 0x0000000, 0x0000000, 0x000000},
 172           {0, 0x0000000, 0x0000000, 0x000000},
 173           {0, 0x0000000, 0x0000000, 0x000000},
 174           {0, 0x0000000, 0x0000000, 0x000000},
 175           {0, 0x0000000, 0x0000000, 0x000000},
 176           {0, 0x0000000, 0x0000000, 0x000000} } },
 177         {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
 178         {{{0} } },                              /* 35: */
 179         {{{0} } },                              /* 36: */
 180         {{{0} } },                              /* 37: */
 181         {{{0} } },                              /* 38: */
 182         {{{0} } },                              /* 39: */
 183         {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
 184         {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
 185         {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
 186         {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
 187         {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
 188         {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
 189         {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
 190         {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
 191         {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
 192         {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
 193         {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
 194         {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
 195         {{{0} } },                              /* 52: */
 196         {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
 197         {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
 198         {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
 199         {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
 200         {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
 201         {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
 202         {{{0} } },                              /* 59: I2C0 */
 203         {{{0} } },                              /* 60: I2C1 */
 204         {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
 205         {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
 206         {{{1, 0x3f00000, 0x3f01000, 0x168000} } }       /* 63: P2NR0 */
 207 };
 208
 209 /*
 210  * top 12 bits of crb internal address (hub, agent)
 211  */
 212 static const unsigned crb_hub_agt[64] = {
 213         0,
 214         QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
 215         QLCNIC_HW_CRB_HUB_AGT_ADR_MN,
 216         QLCNIC_HW_CRB_HUB_AGT_ADR_MS,
 217         0,
 218         QLCNIC_HW_CRB_HUB_AGT_ADR_SRE,
 219         QLCNIC_HW_CRB_HUB_AGT_ADR_NIU,
 220         QLCNIC_HW_CRB_HUB_AGT_ADR_QMN,
 221         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0,
 222         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1,
 223         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2,
 224         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3,
 225         QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
 226         QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
 227         QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
 228         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4,
 229         QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
 230         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0,
 231         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1,
 232         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2,
 233         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3,
 234         QLCNIC_HW_CRB_HUB_AGT_ADR_PGND,
 235         QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI,
 236         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0,
 237         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1,
 238         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2,
 239         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3,
 240         0,
 241         QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI,
 242         QLCNIC_HW_CRB_HUB_AGT_ADR_SN,
 243         0,
 244         QLCNIC_HW_CRB_HUB_AGT_ADR_EG,
 245         0,
 246         QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
 247         QLCNIC_HW_CRB_HUB_AGT_ADR_CAM,
 248         0,
 249         0,
 250         0,
 251         0,
 252         0,
 253         QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
 254         0,
 255         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1,
 256         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2,
 257         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3,
 258         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4,
 259         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5,
 260         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6,
 261         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7,
 262         QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
 263         QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
 264         QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
 265         0,
 266         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0,
 267         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8,
 268         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9,
 269         QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0,
 270         0,
 271         QLCNIC_HW_CRB_HUB_AGT_ADR_SMB,
 272         QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0,
 273         QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1,
 274         0,
 275         QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC,
 276         0,
 277 };
 278
 279 static const u32 msi_tgt_status[8] = {
 280         ISR_INT_TARGET_STATUS, ISR_INT_TARGET_STATUS_F1,
 281         ISR_INT_TARGET_STATUS_F2, ISR_INT_TARGET_STATUS_F3,
 282         ISR_INT_TARGET_STATUS_F4, ISR_INT_TARGET_STATUS_F5,
 283         ISR_INT_TARGET_STATUS_F6, ISR_INT_TARGET_STATUS_F7
 284 };
 285
 286 /*  PCI Windowing for DDR regions.  */
 287
 288 #define QLCNIC_PCIE_SEM_TIMEOUT 10000
 289
 290 static void qlcnic_read_window_reg(u32 addr, void __iomem *bar0, u32 *data)
 291 {
 292         u32 dest;
 293         void __iomem *val;
 294
 295         dest = addr & 0xFFFF0000;
 296         val = bar0 + QLCNIC_FW_DUMP_REG1;
 297         writel(dest, val);
 298         readl(val);
 299         val = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
 300         *data = readl(val);
 301 }
 302
 303 static void qlcnic_write_window_reg(u32 addr, void __iomem *bar0, u32 data)
 304 {
 305         u32 dest;
 306         void __iomem *val;
 307
 308         dest = addr & 0xFFFF0000;
 309         val = bar0 + QLCNIC_FW_DUMP_REG1;
 310         writel(dest, val);
 311         readl(val);
 312         val = bar0 + QLCNIC_FW_DUMP_REG2 + LSW(addr);
 313         writel(data, val);
 314         readl(val);
 315 }
 316
 317 int
 318 qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg)
 319 {
 320         int timeout = 0;
 321         int err = 0;
 322         u32 done = 0;
 323
 324         while (!done) {
 325                 done = QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem)),
 326                                &err);
 327                 if (done == 1)
 328                         break;
 329                 if (++timeout >= QLCNIC_PCIE_SEM_TIMEOUT) {
 330                         dev_err(&adapter->pdev->dev,
 331                                 "Failed to acquire sem=%d lock; holdby=%d\n",
 332                                 sem,
 333                                 id_reg ? QLCRD32(adapter, id_reg, &err) : -1);
 334                         return -EIO;
 335                 }
 336                 msleep(1);
 337         }
 338
 339         if (id_reg)
 340                 QLCWR32(adapter, id_reg, adapter->portnum);
 341
 342         return 0;
 343 }
 344
 345 void
 346 qlcnic_pcie_sem_unlock(struct qlcnic_adapter *adapter, int sem)
 347 {
 348         int err = 0;
 349
 350         QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem)), &err);
 351 }
 352
 353 int qlcnic_ind_rd(struct qlcnic_adapter *adapter, u32 addr)
 354 {
 355         int err = 0;
 356         u32 data;
 357
 358         if (qlcnic_82xx_check(adapter))
 359                 qlcnic_read_window_reg(addr, adapter->ahw->pci_base0, &data);
 360         else {
 361                 data = QLCRD32(adapter, addr, &err);
 362                 if (err == -EIO)
 363                         return err;
 364         }
 365         return data;
 366 }
 367
 368 void qlcnic_ind_wr(struct qlcnic_adapter *adapter, u32 addr, u32 data)
 369 {
 370         if (qlcnic_82xx_check(adapter))
 371                 qlcnic_write_window_reg(addr, adapter->ahw->pci_base0, data);
 372         else
 373                 qlcnic_83xx_wrt_reg_indirect(adapter, addr, data);
 374 }
 375
 376 static int
 377 qlcnic_send_cmd_descs(struct qlcnic_adapter *adapter,
 378                 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
 379 {
 380         u32 i, producer;
 381         struct qlcnic_cmd_buffer *pbuf;
 382         struct cmd_desc_type0 *cmd_desc;
 383         struct qlcnic_host_tx_ring *tx_ring;
 384
 385         i = 0;
 386
 387         if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 388                 return -EIO;
 389
 390         tx_ring = &adapter->tx_ring[0];
 391         __netif_tx_lock_bh(tx_ring->txq);
 392
 393         producer = tx_ring->producer;
 394
 395         if (nr_desc >= qlcnic_tx_avail(tx_ring)) {
 396                 netif_tx_stop_queue(tx_ring->txq);
 397                 smp_mb();
 398                 if (qlcnic_tx_avail(tx_ring) > nr_desc) {
 399                         if (qlcnic_tx_avail(tx_ring) > TX_STOP_THRESH)
 400                                 netif_tx_wake_queue(tx_ring->txq);
 401                 } else {
 402                         adapter->stats.xmit_off++;
 403                         __netif_tx_unlock_bh(tx_ring->txq);
 404                         return -EBUSY;
 405                 }
 406         }
 407
 408         do {
 409                 cmd_desc = &cmd_desc_arr[i];
 410
 411                 pbuf = &tx_ring->cmd_buf_arr[producer];
 412                 pbuf->skb = NULL;
 413                 pbuf->frag_count = 0;
 414
 415                 memcpy(&tx_ring->desc_head[producer],
 416                        cmd_desc, sizeof(struct cmd_desc_type0));
 417
 418                 producer = get_next_index(producer, tx_ring->num_desc);
 419                 i++;
 420
 421         } while (i != nr_desc);
 422
 423         tx_ring->producer = producer;
 424
 425         qlcnic_update_cmd_producer(tx_ring);
 426
 427         __netif_tx_unlock_bh(tx_ring->txq);
 428
 429         return 0;
 430 }
 431
 432 int qlcnic_82xx_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
 433                                    u16 vlan_id, u8 op)
 434 {
 435         struct qlcnic_nic_req req;
 436         struct qlcnic_mac_req *mac_req;
 437         struct qlcnic_vlan_req *vlan_req;
 438         u64 word;
 439
 440         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 441         req.qhdr = cpu_to_le64(QLCNIC_REQUEST << 23);
 442
 443         word = QLCNIC_MAC_EVENT | ((u64)adapter->portnum << 16);
 444         req.req_hdr = cpu_to_le64(word);
 445
 446         mac_req = (struct qlcnic_mac_req *)&req.words[0];
 447         mac_req->op = op;
 448         memcpy(mac_req->mac_addr, addr, ETH_ALEN);
 449
 450         vlan_req = (struct qlcnic_vlan_req *)&req.words[1];
 451         vlan_req->vlan_id = cpu_to_le16(vlan_id);
 452
 453         return qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 454 }
 455
 456 int qlcnic_nic_del_mac(struct qlcnic_adapter *adapter, const u8 *addr)
 457 {
 458         struct qlcnic_mac_vlan_list *cur;
 459         struct list_head *head;
 460         int err = -EINVAL;
 461
 462         /* Delete MAC from the existing list */
 463         list_for_each(head, &adapter->mac_list) {
 464                 cur = list_entry(head, struct qlcnic_mac_vlan_list, list);
 465                 if (ether_addr_equal(addr, cur->mac_addr)) {
 466                         err = qlcnic_sre_macaddr_change(adapter, cur->mac_addr,
 467                                                         0, QLCNIC_MAC_DEL);
 468                         if (err)
 469                                 return err;
 470                         list_del(&cur->list);
 471                         kfree(cur);
 472                         return err;
 473                 }
 474         }
 475         return err;
 476 }
 477
 478 int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter, const u8 *addr, u16 vlan)
 479 {
 480         struct qlcnic_mac_vlan_list *cur;
 481         struct list_head *head;
 482
 483         /* look up if already exists */
 484         list_for_each(head, &adapter->mac_list) {
 485                 cur = list_entry(head, struct qlcnic_mac_vlan_list, list);
 486                 if (ether_addr_equal(addr, cur->mac_addr) &&
 487                     cur->vlan_id == vlan)
 488                         return 0;
 489         }
 490
 491         cur = kzalloc(sizeof(*cur), GFP_ATOMIC);
 492         if (cur == NULL)
 493                 return -ENOMEM;
 494
 495         memcpy(cur->mac_addr, addr, ETH_ALEN);
 496
 497         if (qlcnic_sre_macaddr_change(adapter,
 498                                 cur->mac_addr, vlan, QLCNIC_MAC_ADD)) {
 499                 kfree(cur);
 500                 return -EIO;
 501         }
 502
 503         cur->vlan_id = vlan;
 504         list_add_tail(&cur->list, &adapter->mac_list);
 505         return 0;
 506 }
 507
 508 static void __qlcnic_set_multi(struct net_device *netdev, u16 vlan)
 509 {
 510         struct qlcnic_adapter *adapter = netdev_priv(netdev);
 511         struct qlcnic_hardware_context *ahw = adapter->ahw;
 512         struct netdev_hw_addr *ha;
 513         static const u8 bcast_addr[ETH_ALEN] = {
 514                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
 515         };
 516         u32 mode = VPORT_MISS_MODE_DROP;
 517
 518         if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 519                 return;
 520
 521         qlcnic_nic_add_mac(adapter, adapter->mac_addr, vlan);
 522         qlcnic_nic_add_mac(adapter, bcast_addr, vlan);
 523
 524         if (netdev->flags & IFF_PROMISC) {
 525                 if (!(adapter->flags & QLCNIC_PROMISC_DISABLED))
 526                         mode = VPORT_MISS_MODE_ACCEPT_ALL;
 527         } else if ((netdev->flags & IFF_ALLMULTI) ||
 528                    (netdev_mc_count(netdev) > ahw->max_mc_count)) {
 529                 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
 530         } else if (!netdev_mc_empty(netdev)) {
 531                 netdev_for_each_mc_addr(ha, netdev)
 532                         qlcnic_nic_add_mac(adapter, ha->addr, vlan);
 533         }
 534
 535         /* configure unicast MAC address, if there is not sufficient space
 536          * to store all the unicast addresses then enable promiscuous mode
 537          */
 538         if (netdev_uc_count(netdev) > ahw->max_uc_count) {
 539                 mode = VPORT_MISS_MODE_ACCEPT_ALL;
 540         } else if (!netdev_uc_empty(netdev)) {
 541                 netdev_for_each_uc_addr(ha, netdev)
 542                         qlcnic_nic_add_mac(adapter, ha->addr, vlan);
 543         }
 544
 545         if (mode == VPORT_MISS_MODE_ACCEPT_ALL &&
 546             !adapter->fdb_mac_learn) {
 547                 qlcnic_alloc_lb_filters_mem(adapter);
 548                 adapter->drv_mac_learn = 1;
 549                 if (adapter->flags & QLCNIC_ESWITCH_ENABLED)
 550                         adapter->rx_mac_learn = true;
 551         } else {
 552                 adapter->drv_mac_learn = 0;
 553                 adapter->rx_mac_learn = false;
 554         }
 555
 556         qlcnic_nic_set_promisc(adapter, mode);
 557 }
 558
 559 void qlcnic_set_multi(struct net_device *netdev)
 560 {
 561         struct qlcnic_adapter *adapter = netdev_priv(netdev);
 562         struct qlcnic_mac_vlan_list *cur;
 563         struct netdev_hw_addr *ha;
 564         size_t temp;
 565
 566         if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 567                 return;
 568         if (qlcnic_sriov_vf_check(adapter)) {
 569                 if (!netdev_mc_empty(netdev)) {
 570                         netdev_for_each_mc_addr(ha, netdev) {
 571                                 temp = sizeof(struct qlcnic_mac_vlan_list);
 572                                 cur = kzalloc(temp, GFP_ATOMIC);
 573                                 if (cur == NULL)
 574                                         break;
 575                                 memcpy(cur->mac_addr,
 576                                        ha->addr, ETH_ALEN);
 577                                 list_add_tail(&cur->list, &adapter->vf_mc_list);
 578                         }
 579                 }
 580                 qlcnic_sriov_vf_schedule_multi(adapter->netdev);
 581                 return;
 582         }
 583         __qlcnic_set_multi(netdev, 0);
 584 }
 585
 586 int qlcnic_82xx_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
 587 {
 588         struct qlcnic_nic_req req;
 589         u64 word;
 590
 591         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 592
 593         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 594
 595         word = QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE |
 596                         ((u64)adapter->portnum << 16);
 597         req.req_hdr = cpu_to_le64(word);
 598
 599         req.words[0] = cpu_to_le64(mode);
 600
 601         return qlcnic_send_cmd_descs(adapter,
 602                                 (struct cmd_desc_type0 *)&req, 1);
 603 }
 604
 605 void qlcnic_82xx_free_mac_list(struct qlcnic_adapter *adapter)
 606 {
 607         struct list_head *head = &adapter->mac_list;
 608         struct qlcnic_mac_vlan_list *cur;
 609
 610         while (!list_empty(head)) {
 611                 cur = list_entry(head->next, struct qlcnic_mac_vlan_list, list);
 612                 qlcnic_sre_macaddr_change(adapter,
 613                                 cur->mac_addr, 0, QLCNIC_MAC_DEL);
 614                 list_del(&cur->list);
 615                 kfree(cur);
 616         }
 617 }
 618
 619 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter)
 620 {
 621         struct qlcnic_filter *tmp_fil;
 622         struct hlist_node *n;
 623         struct hlist_head *head;
 624         int i;
 625         unsigned long time;
 626         u8 cmd;
 627
 628         for (i = 0; i < adapter->fhash.fbucket_size; i++) {
 629                 head = &(adapter->fhash.fhead[i]);
 630                 hlist_for_each_entry_safe(tmp_fil, n, head, fnode) {
 631                         cmd =  tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL :
 632                                                   QLCNIC_MAC_DEL;
 633                         time = tmp_fil->ftime;
 634                         if (jiffies > (QLCNIC_FILTER_AGE * HZ + time)) {
 635                                 qlcnic_sre_macaddr_change(adapter,
 636                                                           tmp_fil->faddr,
 637                                                           tmp_fil->vlan_id,
 638                                                           cmd);
 639                                 spin_lock_bh(&adapter->mac_learn_lock);
 640                                 adapter->fhash.fnum--;
 641                                 hlist_del(&tmp_fil->fnode);
 642                                 spin_unlock_bh(&adapter->mac_learn_lock);
 643                                 kfree(tmp_fil);
 644                         }
 645                 }
 646         }
 647         for (i = 0; i < adapter->rx_fhash.fbucket_size; i++) {
 648                 head = &(adapter->rx_fhash.fhead[i]);
 649
 650                 hlist_for_each_entry_safe(tmp_fil, n, head, fnode)
 651                 {
 652                         time = tmp_fil->ftime;
 653                         if (jiffies > (QLCNIC_FILTER_AGE * HZ + time)) {
 654                                 spin_lock_bh(&adapter->rx_mac_learn_lock);
 655                                 adapter->rx_fhash.fnum--;
 656                                 hlist_del(&tmp_fil->fnode);
 657                                 spin_unlock_bh(&adapter->rx_mac_learn_lock);
 658                                 kfree(tmp_fil);
 659                         }
 660                 }
 661         }
 662 }
 663
 664 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter)
 665 {
 666         struct qlcnic_filter *tmp_fil;
 667         struct hlist_node *n;
 668         struct hlist_head *head;
 669         int i;
 670         u8 cmd;
 671
 672         for (i = 0; i < adapter->fhash.fbucket_size; i++) {
 673                 head = &(adapter->fhash.fhead[i]);
 674                 hlist_for_each_entry_safe(tmp_fil, n, head, fnode) {
 675                         cmd =  tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL :
 676                                                   QLCNIC_MAC_DEL;
 677                         qlcnic_sre_macaddr_change(adapter,
 678                                                   tmp_fil->faddr,
 679                                                   tmp_fil->vlan_id,
 680                                                   cmd);
 681                         spin_lock_bh(&adapter->mac_learn_lock);
 682                         adapter->fhash.fnum--;
 683                         hlist_del(&tmp_fil->fnode);
 684                         spin_unlock_bh(&adapter->mac_learn_lock);
 685                         kfree(tmp_fil);
 686                 }
 687         }
 688 }
 689
 690 static int qlcnic_set_fw_loopback(struct qlcnic_adapter *adapter, u8 flag)
 691 {
 692         struct qlcnic_nic_req req;
 693         int rv;
 694
 695         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 696
 697         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 698         req.req_hdr = cpu_to_le64(QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK |
 699                 ((u64) adapter->portnum << 16) | ((u64) 0x1 << 32));
 700
 701         req.words[0] = cpu_to_le64(flag);
 702
 703         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 704         if (rv != 0)
 705                 dev_err(&adapter->pdev->dev, "%sting loopback mode failed\n",
 706                                 flag ? "Set" : "Reset");
 707         return rv;
 708 }
 709
 710 int qlcnic_82xx_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
 711 {
 712         if (qlcnic_set_fw_loopback(adapter, mode))
 713                 return -EIO;
 714
 715         if (qlcnic_nic_set_promisc(adapter,
 716                                    VPORT_MISS_MODE_ACCEPT_ALL)) {
 717                 qlcnic_set_fw_loopback(adapter, 0);
 718                 return -EIO;
 719         }
 720
 721         msleep(1000);
 722         return 0;
 723 }
 724
 725 int qlcnic_82xx_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
 726 {
 727         struct net_device *netdev = adapter->netdev;
 728
 729         mode = VPORT_MISS_MODE_DROP;
 730         qlcnic_set_fw_loopback(adapter, 0);
 731
 732         if (netdev->flags & IFF_PROMISC)
 733                 mode = VPORT_MISS_MODE_ACCEPT_ALL;
 734         else if (netdev->flags & IFF_ALLMULTI)
 735                 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
 736
 737         qlcnic_nic_set_promisc(adapter, mode);
 738         msleep(1000);
 739         return 0;
 740 }
 741
 742 int qlcnic_82xx_read_phys_port_id(struct qlcnic_adapter *adapter)
 743 {
 744         u8 mac[ETH_ALEN];
 745         int ret;
 746
 747         ret = qlcnic_get_mac_address(adapter, mac,
 748                                      adapter->ahw->physical_port);
 749         if (ret)
 750                 return ret;
 751
 752         memcpy(adapter->ahw->phys_port_id, mac, ETH_ALEN);
 753         adapter->flags |= QLCNIC_HAS_PHYS_PORT_ID;
 754
 755         return 0;
 756 }
 757
 758 int qlcnic_82xx_set_rx_coalesce(struct qlcnic_adapter *adapter)
 759 {
 760         struct qlcnic_nic_req req;
 761         int rv;
 762
 763         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 764
 765         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 766
 767         req.req_hdr = cpu_to_le64(QLCNIC_CONFIG_INTR_COALESCE |
 768                 ((u64) adapter->portnum << 16));
 769
 770         req.words[0] = cpu_to_le64(((u64) adapter->ahw->coal.flag) << 32);
 771         req.words[2] = cpu_to_le64(adapter->ahw->coal.rx_packets |
 772                         ((u64) adapter->ahw->coal.rx_time_us) << 16);
 773         req.words[5] = cpu_to_le64(adapter->ahw->coal.timer_out |
 774                         ((u64) adapter->ahw->coal.type) << 32 |
 775                         ((u64) adapter->ahw->coal.sts_ring_mask) << 40);
 776         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 777         if (rv != 0)
 778                 dev_err(&adapter->netdev->dev,
 779                         "Could not send interrupt coalescing parameters\n");
 780
 781         return rv;
 782 }
 783
 784 /* Send the interrupt coalescing parameter set by ethtool to the card. */
 785 int qlcnic_82xx_config_intr_coalesce(struct qlcnic_adapter *adapter,
 786                                      struct ethtool_coalesce *ethcoal)
 787 {
 788         struct qlcnic_nic_intr_coalesce *coal = &adapter->ahw->coal;
 789         int rv;
 790
 791         coal->flag = QLCNIC_INTR_DEFAULT;
 792         coal->rx_time_us = ethcoal->rx_coalesce_usecs;
 793         coal->rx_packets = ethcoal->rx_max_coalesced_frames;
 794
 795         rv = qlcnic_82xx_set_rx_coalesce(adapter);
 796
 797         if (rv)
 798                 netdev_err(adapter->netdev,
 799                            "Failed to set Rx coalescing parametrs\n");
 800
 801         return rv;
 802 }
 803
 804 #define QLCNIC_ENABLE_IPV4_LRO          BIT_0
 805 #define QLCNIC_ENABLE_IPV6_LRO          (BIT_1 | BIT_9)
 806
 807 int qlcnic_82xx_config_hw_lro(struct qlcnic_adapter *adapter, int enable)
 808 {
 809         struct qlcnic_nic_req req;
 810         u64 word;
 811         int rv;
 812
 813         if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 814                 return 0;
 815
 816         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 817
 818         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 819
 820         word = QLCNIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
 821         req.req_hdr = cpu_to_le64(word);
 822
 823         word = 0;
 824         if (enable) {
 825                 word = QLCNIC_ENABLE_IPV4_LRO;
 826                 if (adapter->ahw->extra_capability[0] &
 827                     QLCNIC_FW_CAP2_HW_LRO_IPV6)
 828                         word |= QLCNIC_ENABLE_IPV6_LRO;
 829         }
 830
 831         req.words[0] = cpu_to_le64(word);
 832
 833         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 834         if (rv != 0)
 835                 dev_err(&adapter->netdev->dev,
 836                         "Could not send configure hw lro request\n");
 837
 838         return rv;
 839 }
 840
 841 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable)
 842 {
 843         struct qlcnic_nic_req req;
 844         u64 word;
 845         int rv;
 846
 847         if (!!(adapter->flags & QLCNIC_BRIDGE_ENABLED) == enable)
 848                 return 0;
 849
 850         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 851
 852         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 853
 854         word = QLCNIC_H2C_OPCODE_CONFIG_BRIDGING |
 855                 ((u64)adapter->portnum << 16);
 856         req.req_hdr = cpu_to_le64(word);
 857
 858         req.words[0] = cpu_to_le64(enable);
 859
 860         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 861         if (rv != 0)
 862                 dev_err(&adapter->netdev->dev,
 863                         "Could not send configure bridge mode request\n");
 864
 865         adapter->flags ^= QLCNIC_BRIDGE_ENABLED;
 866
 867         return rv;
 868 }
 869
 870
 871 #define QLCNIC_RSS_HASHTYPE_IP_TCP      0x3
 872 #define QLCNIC_ENABLE_TYPE_C_RSS        BIT_10
 873 #define QLCNIC_RSS_FEATURE_FLAG (1ULL << 63)
 874 #define QLCNIC_RSS_IND_TABLE_MASK       0x7ULL
 875
 876 int qlcnic_82xx_config_rss(struct qlcnic_adapter *adapter, int enable)
 877 {
 878         struct qlcnic_nic_req req;
 879         u64 word;
 880         int i, rv;
 881
 882         static const u64 key[] = {
 883                 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
 884                 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
 885                 0x255b0ec26d5a56daULL
 886         };
 887
 888         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 889         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 890
 891         word = QLCNIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
 892         req.req_hdr = cpu_to_le64(word);
 893
 894         /*
 895          * RSS request:
 896          * bits 3-0: hash_method
 897          *      5-4: hash_type_ipv4
 898          *      7-6: hash_type_ipv6
 899          *        8: enable
 900          *        9: use indirection table
 901          *       10: type-c rss
 902          *       11: udp rss
 903          *    47-12: reserved
 904          *    62-48: indirection table mask
 905          *       63: feature flag
 906          */
 907         word =  ((u64)(QLCNIC_RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
 908                 ((u64)(QLCNIC_RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
 909                 ((u64)(enable & 0x1) << 8) |
 910                 ((u64)QLCNIC_RSS_IND_TABLE_MASK << 48) |
 911                 (u64)QLCNIC_ENABLE_TYPE_C_RSS |
 912                 (u64)QLCNIC_RSS_FEATURE_FLAG;
 913
 914         req.words[0] = cpu_to_le64(word);
 915         for (i = 0; i < 5; i++)
 916                 req.words[i+1] = cpu_to_le64(key[i]);
 917
 918         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 919         if (rv != 0)
 920                 dev_err(&adapter->netdev->dev, "could not configure RSS\n");
 921
 922         return rv;
 923 }
 924
 925 void qlcnic_82xx_config_ipaddr(struct qlcnic_adapter *adapter,
 926                                __be32 ip, int cmd)
 927 {
 928         struct qlcnic_nic_req req;
 929         struct qlcnic_ipaddr *ipa;
 930         u64 word;
 931         int rv;
 932
 933         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 934         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 935
 936         word = QLCNIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
 937         req.req_hdr = cpu_to_le64(word);
 938
 939         req.words[0] = cpu_to_le64(cmd);
 940         ipa = (struct qlcnic_ipaddr *)&req.words[1];
 941         ipa->ipv4 = ip;
 942
 943         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 944         if (rv != 0)
 945                 dev_err(&adapter->netdev->dev,
 946                                 "could not notify %s IP 0x%x reuqest\n",
 947                                 (cmd == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
 948 }
 949
 950 int qlcnic_82xx_linkevent_request(struct qlcnic_adapter *adapter, int enable)
 951 {
 952         struct qlcnic_nic_req req;
 953         u64 word;
 954         int rv;
 955         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 956         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 957
 958         word = QLCNIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
 959         req.req_hdr = cpu_to_le64(word);
 960         req.words[0] = cpu_to_le64(enable | (enable << 8));
 961         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 962         if (rv != 0)
 963                 dev_err(&adapter->netdev->dev,
 964                                 "could not configure link notification\n");
 965
 966         return rv;
 967 }
 968
 969 static int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter)
 970 {
 971         struct qlcnic_nic_req req;
 972         u64 word;
 973         int rv;
 974
 975         if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 976                 return 0;
 977
 978         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 979         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 980
 981         word = QLCNIC_H2C_OPCODE_LRO_REQUEST |
 982                 ((u64)adapter->portnum << 16) |
 983                 ((u64)QLCNIC_LRO_REQUEST_CLEANUP << 56) ;
 984
 985         req.req_hdr = cpu_to_le64(word);
 986
 987         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 988         if (rv != 0)
 989                 dev_err(&adapter->netdev->dev,
 990                                  "could not cleanup lro flows\n");
 991
 992         return rv;
 993 }
 994
 995 /*
 996  * qlcnic_change_mtu - Change the Maximum Transfer Unit
 997  * @returns 0 on success, negative on failure
 998  */
 999
1000 int qlcnic_change_mtu(struct net_device *netdev, int mtu)
1001 {
1002         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1003         int rc = 0;
1004
1005         if (mtu < P3P_MIN_MTU || mtu > P3P_MAX_MTU) {
1006                 dev_err(&adapter->netdev->dev, "%d bytes < mtu < %d bytes"
1007                         " not supported\n", P3P_MAX_MTU, P3P_MIN_MTU);
1008                 return -EINVAL;
1009         }
1010
1011         rc = qlcnic_fw_cmd_set_mtu(adapter, mtu);
1012
1013         if (!rc)
1014                 netdev->mtu = mtu;
1015
1016         return rc;
1017 }
1018
1019 static netdev_features_t qlcnic_process_flags(struct qlcnic_adapter *adapter,
1020                                               netdev_features_t features)
1021 {
1022         u32 offload_flags = adapter->offload_flags;
1023
1024         if (offload_flags & BIT_0) {
1025                 features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM |
1026                             NETIF_F_IPV6_CSUM;
1027                 adapter->rx_csum = 1;
1028                 if (QLCNIC_IS_TSO_CAPABLE(adapter)) {
1029                         if (!(offload_flags & BIT_1))
1030                                 features &= ~NETIF_F_TSO;
1031                         else
1032                                 features |= NETIF_F_TSO;
1033
1034                         if (!(offload_flags & BIT_2))
1035                                 features &= ~NETIF_F_TSO6;
1036                         else
1037                                 features |= NETIF_F_TSO6;
1038                 }
1039         } else {
1040                 features &= ~(NETIF_F_RXCSUM |
1041                               NETIF_F_IP_CSUM |
1042                               NETIF_F_IPV6_CSUM);
1043
1044                 if (QLCNIC_IS_TSO_CAPABLE(adapter))
1045                         features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
1046                 adapter->rx_csum = 0;
1047         }
1048
1049         return features;
1050 }
1051
1052 netdev_features_t qlcnic_fix_features(struct net_device *netdev,
1053         netdev_features_t features)
1054 {
1055         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1056         netdev_features_t changed;
1057
1058         if (qlcnic_82xx_check(adapter) &&
1059             (adapter->flags & QLCNIC_ESWITCH_ENABLED)) {
1060                 if (adapter->flags & QLCNIC_APP_CHANGED_FLAGS) {
1061                         features = qlcnic_process_flags(adapter, features);
1062                 } else {
1063                         changed = features ^ netdev->features;
1064                         features ^= changed & (NETIF_F_RXCSUM |
1065                                                NETIF_F_IP_CSUM |
1066                                                NETIF_F_IPV6_CSUM |
1067                                                NETIF_F_TSO |
1068                                                NETIF_F_TSO6);
1069                 }
1070         }
1071
1072         if (!(features & NETIF_F_RXCSUM))
1073                 features &= ~NETIF_F_LRO;
1074
1075         return features;
1076 }
1077
1078
1079 int qlcnic_set_features(struct net_device *netdev, netdev_features_t features)
1080 {
1081         struct qlcnic_adapter *adapter = netdev_priv(netdev);
1082         netdev_features_t changed = netdev->features ^ features;
1083         int hw_lro = (features & NETIF_F_LRO) ? QLCNIC_LRO_ENABLED : 0;
1084
1085         if (!(changed & NETIF_F_LRO))
1086                 return 0;
1087
1088         netdev->features ^= NETIF_F_LRO;
1089
1090         if (qlcnic_config_hw_lro(adapter, hw_lro))
1091                 return -EIO;
1092
1093         if (!hw_lro && qlcnic_82xx_check(adapter)) {
1094                 if (qlcnic_send_lro_cleanup(adapter))
1095                         return -EIO;
1096         }
1097
1098         return 0;
1099 }
1100
1101 /*
1102  * Changes the CRB window to the specified window.
1103  */
1104  /* Returns < 0 if off is not valid,
1105  *       1 if window access is needed. 'off' is set to offset from
1106  *         CRB space in 128M pci map
1107  *       0 if no window access is needed. 'off' is set to 2M addr
1108  * In: 'off' is offset from base in 128M pci map
1109  */
1110 static int qlcnic_pci_get_crb_addr_2M(struct qlcnic_hardware_context *ahw,
1111                                       ulong off, void __iomem **addr)
1112 {
1113         const struct crb_128M_2M_sub_block_map *m;
1114
1115         if ((off >= QLCNIC_CRB_MAX) || (off < QLCNIC_PCI_CRBSPACE))
1116                 return -EINVAL;
1117
1118         off -= QLCNIC_PCI_CRBSPACE;
1119
1120         /*
1121          * Try direct map
1122          */
1123         m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
1124
1125         if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
1126                 *addr = ahw->pci_base0 + m->start_2M +
1127                         (off - m->start_128M);
1128                 return 0;
1129         }
1130
1131         /*
1132          * Not in direct map, use crb window
1133          */
1134         *addr = ahw->pci_base0 + CRB_INDIRECT_2M + (off & MASK(16));
1135         return 1;
1136 }
1137
1138 /*
1139  * In: 'off' is offset from CRB space in 128M pci map
1140  * Out: 'off' is 2M pci map addr
1141  * side effect: lock crb window
1142  */
1143 static int
1144 qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter *adapter, ulong off)
1145 {
1146         u32 window;
1147         void __iomem *addr = adapter->ahw->pci_base0 + CRB_WINDOW_2M;
1148
1149         off -= QLCNIC_PCI_CRBSPACE;
1150
1151         window = CRB_HI(off);
1152         if (window == 0) {
1153                 dev_err(&adapter->pdev->dev, "Invalid offset 0x%lx\n", off);
1154                 return -EIO;
1155         }
1156
1157         writel(window, addr);
1158         if (readl(addr) != window) {
1159                 if (printk_ratelimit())
1160                         dev_warn(&adapter->pdev->dev,
1161                                 "failed to set CRB window to %d off 0x%lx\n",
1162                                 window, off);
1163                 return -EIO;
1164         }
1165         return 0;
1166 }
1167
1168 int qlcnic_82xx_hw_write_wx_2M(struct qlcnic_adapter *adapter, ulong off,
1169                                u32 data)
1170 {
1171         unsigned long flags;
1172         int rv;
1173         void __iomem *addr = NULL;
1174
1175         rv = qlcnic_pci_get_crb_addr_2M(adapter->ahw, off, &addr);
1176
1177         if (rv == 0) {
1178                 writel(data, addr);
1179                 return 0;
1180         }
1181
1182         if (rv > 0) {
1183                 /* indirect access */
1184                 write_lock_irqsave(&adapter->ahw->crb_lock, flags);
1185                 crb_win_lock(adapter);
1186                 rv = qlcnic_pci_set_crbwindow_2M(adapter, off);
1187                 if (!rv)
1188                         writel(data, addr);
1189                 crb_win_unlock(adapter);
1190                 write_unlock_irqrestore(&adapter->ahw->crb_lock, flags);
1191                 return rv;
1192         }
1193
1194         dev_err(&adapter->pdev->dev,
1195                         "%s: invalid offset: 0x%016lx\n", __func__, off);
1196         dump_stack();
1197         return -EIO;
1198 }
1199
1200 int qlcnic_82xx_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off,
1201                               int *err)
1202 {
1203         unsigned long flags;
1204         int rv;
1205         u32 data = -1;
1206         void __iomem *addr = NULL;
1207
1208         rv = qlcnic_pci_get_crb_addr_2M(adapter->ahw, off, &addr);
1209
1210         if (rv == 0)
1211                 return readl(addr);
1212
1213         if (rv > 0) {
1214                 /* indirect access */
1215                 write_lock_irqsave(&adapter->ahw->crb_lock, flags);
1216                 crb_win_lock(adapter);
1217                 if (!qlcnic_pci_set_crbwindow_2M(adapter, off))
1218                         data = readl(addr);
1219                 crb_win_unlock(adapter);
1220                 write_unlock_irqrestore(&adapter->ahw->crb_lock, flags);
1221                 return data;
1222         }
1223
1224         dev_err(&adapter->pdev->dev,
1225                         "%s: invalid offset: 0x%016lx\n", __func__, off);
1226         dump_stack();
1227         return -1;
1228 }
1229
1230 void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *ahw,
1231                                 u32 offset)
1232 {
1233         void __iomem *addr = NULL;
1234
1235         WARN_ON(qlcnic_pci_get_crb_addr_2M(ahw, offset, &addr));
1236
1237         return addr;
1238 }
1239
1240 static int qlcnic_pci_mem_access_direct(struct qlcnic_adapter *adapter,
1241                                         u32 window, u64 off, u64 *data, int op)
1242 {
1243         void __iomem *addr;
1244         u32 start;
1245
1246         mutex_lock(&adapter->ahw->mem_lock);
1247
1248         writel(window, adapter->ahw->ocm_win_crb);
1249         /* read back to flush */
1250         readl(adapter->ahw->ocm_win_crb);
1251         start = QLCNIC_PCI_OCM0_2M + off;
1252
1253         addr = adapter->ahw->pci_base0 + start;
1254
1255         if (op == 0)    /* read */
1256                 *data = readq(addr);
1257         else            /* write */
1258                 writeq(*data, addr);
1259
1260         /* Set window to 0 */
1261         writel(0, adapter->ahw->ocm_win_crb);
1262         readl(adapter->ahw->ocm_win_crb);
1263
1264         mutex_unlock(&adapter->ahw->mem_lock);
1265         return 0;
1266 }
1267
1268 static void
1269 qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
1270 {
1271         void __iomem *addr = adapter->ahw->pci_base0 +
1272                 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
1273
1274         mutex_lock(&adapter->ahw->mem_lock);
1275         *data = readq(addr);
1276         mutex_unlock(&adapter->ahw->mem_lock);
1277 }
1278
1279 static void
1280 qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
1281 {
1282         void __iomem *addr = adapter->ahw->pci_base0 +
1283                 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
1284
1285         mutex_lock(&adapter->ahw->mem_lock);
1286         writeq(data, addr);
1287         mutex_unlock(&adapter->ahw->mem_lock);
1288 }
1289
1290
1291
1292 /* Set MS memory control data for different adapters */
1293 static void qlcnic_set_ms_controls(struct qlcnic_adapter *adapter, u64 off,
1294                                    struct qlcnic_ms_reg_ctrl *ms)
1295 {
1296         ms->control = QLCNIC_MS_CTRL;
1297         ms->low = QLCNIC_MS_ADDR_LO;
1298         ms->hi = QLCNIC_MS_ADDR_HI;
1299         if (off & 0xf) {
1300                 ms->wd[0] = QLCNIC_MS_WRTDATA_LO;
1301                 ms->rd[0] = QLCNIC_MS_RDDATA_LO;
1302                 ms->wd[1] = QLCNIC_MS_WRTDATA_HI;
1303                 ms->rd[1] = QLCNIC_MS_RDDATA_HI;
1304                 ms->wd[2] = QLCNIC_MS_WRTDATA_ULO;
1305                 ms->wd[3] = QLCNIC_MS_WRTDATA_UHI;
1306                 ms->rd[2] = QLCNIC_MS_RDDATA_ULO;
1307                 ms->rd[3] = QLCNIC_MS_RDDATA_UHI;
1308         } else {
1309                 ms->wd[0] = QLCNIC_MS_WRTDATA_ULO;
1310                 ms->rd[0] = QLCNIC_MS_RDDATA_ULO;
1311                 ms->wd[1] = QLCNIC_MS_WRTDATA_UHI;
1312                 ms->rd[1] = QLCNIC_MS_RDDATA_UHI;
1313                 ms->wd[2] = QLCNIC_MS_WRTDATA_LO;
1314                 ms->wd[3] = QLCNIC_MS_WRTDATA_HI;
1315                 ms->rd[2] = QLCNIC_MS_RDDATA_LO;
1316                 ms->rd[3] = QLCNIC_MS_RDDATA_HI;
1317         }
1318
1319         ms->ocm_window = OCM_WIN_P3P(off);
1320         ms->off = GET_MEM_OFFS_2M(off);
1321 }
1322
1323 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
1324 {
1325         int j, ret = 0;
1326         u32 temp, off8;
1327         struct qlcnic_ms_reg_ctrl ms;
1328
1329         /* Only 64-bit aligned access */
1330         if (off & 7)
1331                 return -EIO;
1332
1333         memset(&ms, 0, sizeof(struct qlcnic_ms_reg_ctrl));
1334         if (!(ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1335                             QLCNIC_ADDR_QDR_NET_MAX) ||
1336               ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET,
1337                             QLCNIC_ADDR_DDR_NET_MAX)))
1338                 return -EIO;
1339
1340         qlcnic_set_ms_controls(adapter, off, &ms);
1341
1342         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
1343                 return qlcnic_pci_mem_access_direct(adapter, ms.ocm_window,
1344                                                     ms.off, &data, 1);
1345
1346         off8 = off & ~0xf;
1347
1348         mutex_lock(&adapter->ahw->mem_lock);
1349
1350         qlcnic_ind_wr(adapter, ms.low, off8);
1351         qlcnic_ind_wr(adapter, ms.hi, 0);
1352
1353         qlcnic_ind_wr(adapter, ms.control, TA_CTL_ENABLE);
1354         qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_START_ENABLE);
1355
1356         for (j = 0; j < MAX_CTL_CHECK; j++) {
1357                 temp = qlcnic_ind_rd(adapter, ms.control);
1358                 if ((temp & TA_CTL_BUSY) == 0)
1359                         break;
1360         }
1361
1362         if (j >= MAX_CTL_CHECK) {
1363                 ret = -EIO;
1364                 goto done;
1365         }
1366
1367         /* This is the modify part of read-modify-write */
1368         qlcnic_ind_wr(adapter, ms.wd[0], qlcnic_ind_rd(adapter, ms.rd[0]));
1369         qlcnic_ind_wr(adapter, ms.wd[1], qlcnic_ind_rd(adapter, ms.rd[1]));
1370         /* This is the write part of read-modify-write */
1371         qlcnic_ind_wr(adapter, ms.wd[2], data & 0xffffffff);
1372         qlcnic_ind_wr(adapter, ms.wd[3], (data >> 32) & 0xffffffff);
1373
1374         qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_WRITE_ENABLE);
1375         qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_WRITE_START);
1376
1377         for (j = 0; j < MAX_CTL_CHECK; j++) {
1378                 temp = qlcnic_ind_rd(adapter, ms.control);
1379                 if ((temp & TA_CTL_BUSY) == 0)
1380                         break;
1381         }
1382
1383         if (j >= MAX_CTL_CHECK) {
1384                 if (printk_ratelimit())
1385                         dev_err(&adapter->pdev->dev,
1386                                         "failed to write through agent\n");
1387                 ret = -EIO;
1388         } else
1389                 ret = 0;
1390
1391 done:
1392         mutex_unlock(&adapter->ahw->mem_lock);
1393
1394         return ret;
1395 }
1396
1397 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
1398 {
1399         int j, ret;
1400         u32 temp, off8;
1401         u64 val;
1402         struct qlcnic_ms_reg_ctrl ms;
1403
1404         /* Only 64-bit aligned access */
1405         if (off & 7)
1406                 return -EIO;
1407         if (!(ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1408                             QLCNIC_ADDR_QDR_NET_MAX) ||
1409               ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET,
1410                             QLCNIC_ADDR_DDR_NET_MAX)))
1411                 return -EIO;
1412
1413         memset(&ms, 0, sizeof(struct qlcnic_ms_reg_ctrl));
1414         qlcnic_set_ms_controls(adapter, off, &ms);
1415
1416         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
1417                 return qlcnic_pci_mem_access_direct(adapter, ms.ocm_window,
1418                                                     ms.off, data, 0);
1419
1420         mutex_lock(&adapter->ahw->mem_lock);
1421
1422         off8 = off & ~0xf;
1423
1424         qlcnic_ind_wr(adapter, ms.low, off8);
1425         qlcnic_ind_wr(adapter, ms.hi, 0);
1426
1427         qlcnic_ind_wr(adapter, ms.control, TA_CTL_ENABLE);
1428         qlcnic_ind_wr(adapter, ms.control, QLCNIC_TA_START_ENABLE);
1429
1430         for (j = 0; j < MAX_CTL_CHECK; j++) {
1431                 temp = qlcnic_ind_rd(adapter, ms.control);
1432                 if ((temp & TA_CTL_BUSY) == 0)
1433                         break;
1434         }
1435
1436         if (j >= MAX_CTL_CHECK) {
1437                 if (printk_ratelimit())
1438                         dev_err(&adapter->pdev->dev,
1439                                         "failed to read through agent\n");
1440                 ret = -EIO;
1441         } else {
1442
1443                 temp = qlcnic_ind_rd(adapter, ms.rd[3]);
1444                 val = (u64)temp << 32;
1445                 val |= qlcnic_ind_rd(adapter, ms.rd[2]);
1446                 *data = val;
1447                 ret = 0;
1448         }
1449
1450         mutex_unlock(&adapter->ahw->mem_lock);
1451
1452         return ret;
1453 }
1454
1455 int qlcnic_82xx_get_board_info(struct qlcnic_adapter *adapter)
1456 {
1457         int offset, board_type, magic, err = 0;
1458         struct pci_dev *pdev = adapter->pdev;
1459
1460         offset = QLCNIC_FW_MAGIC_OFFSET;
1461         if (qlcnic_rom_fast_read(adapter, offset, &magic))
1462                 return -EIO;
1463
1464         if (magic != QLCNIC_BDINFO_MAGIC) {
1465                 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1466                         magic);
1467                 return -EIO;
1468         }
1469
1470         offset = QLCNIC_BRDTYPE_OFFSET;
1471         if (qlcnic_rom_fast_read(adapter, offset, &board_type))
1472                 return -EIO;
1473
1474         adapter->ahw->board_type = board_type;
1475
1476         if (board_type == QLCNIC_BRDTYPE_P3P_4_GB_MM) {
1477                 u32 gpio = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_PAD_GPIO_I, &err);
1478                 if (err == -EIO)
1479                         return err;
1480                 if ((gpio & 0x8000) == 0)
1481                         board_type = QLCNIC_BRDTYPE_P3P_10G_TP;
1482         }
1483
1484         switch (board_type) {
1485         case QLCNIC_BRDTYPE_P3P_HMEZ:
1486         case QLCNIC_BRDTYPE_P3P_XG_LOM:
1487         case QLCNIC_BRDTYPE_P3P_10G_CX4:
1488         case QLCNIC_BRDTYPE_P3P_10G_CX4_LP:
1489         case QLCNIC_BRDTYPE_P3P_IMEZ:
1490         case QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS:
1491         case QLCNIC_BRDTYPE_P3P_10G_SFP_CT:
1492         case QLCNIC_BRDTYPE_P3P_10G_SFP_QT:
1493         case QLCNIC_BRDTYPE_P3P_10G_XFP:
1494         case QLCNIC_BRDTYPE_P3P_10000_BASE_T:
1495                 adapter->ahw->port_type = QLCNIC_XGBE;
1496                 break;
1497         case QLCNIC_BRDTYPE_P3P_REF_QG:
1498         case QLCNIC_BRDTYPE_P3P_4_GB:
1499         case QLCNIC_BRDTYPE_P3P_4_GB_MM:
1500                 adapter->ahw->port_type = QLCNIC_GBE;
1501                 break;
1502         case QLCNIC_BRDTYPE_P3P_10G_TP:
1503                 adapter->ahw->port_type = (adapter->portnum < 2) ?
1504                         QLCNIC_XGBE : QLCNIC_GBE;
1505                 break;
1506         default:
1507                 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1508                 adapter->ahw->port_type = QLCNIC_XGBE;
1509                 break;
1510         }
1511
1512         return 0;
1513 }
1514
1515 static int
1516 qlcnic_wol_supported(struct qlcnic_adapter *adapter)
1517 {
1518         u32 wol_cfg;
1519         int err = 0;
1520
1521         wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV, &err);
1522         if (wol_cfg & (1UL << adapter->portnum)) {
1523                 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG, &err);
1524                 if (err == -EIO)
1525                         return err;
1526                 if (wol_cfg & (1 << adapter->portnum))
1527                         return 1;
1528         }
1529
1530         return 0;
1531 }
1532
1533 int qlcnic_82xx_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate)
1534 {
1535         struct qlcnic_nic_req   req;
1536         int rv;
1537         u64 word;
1538
1539         memset(&req, 0, sizeof(struct qlcnic_nic_req));
1540         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1541
1542         word = QLCNIC_H2C_OPCODE_CONFIG_LED | ((u64)adapter->portnum << 16);
1543         req.req_hdr = cpu_to_le64(word);
1544
1545         req.words[0] = cpu_to_le64(((u64)rate << 32) | adapter->portnum);
1546         req.words[1] = cpu_to_le64(state);
1547
1548         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1549         if (rv)
1550                 dev_err(&adapter->pdev->dev, "LED configuration failed.\n");
1551
1552         return rv;
1553 }
1554
1555 void qlcnic_82xx_get_beacon_state(struct qlcnic_adapter *adapter)
1556 {
1557         struct qlcnic_hardware_context *ahw = adapter->ahw;
1558         struct qlcnic_cmd_args cmd;
1559         u8 beacon_state;
1560         int err = 0;
1561
1562         if (ahw->extra_capability[0] & QLCNIC_FW_CAPABILITY_2_BEACON) {
1563                 err = qlcnic_alloc_mbx_args(&cmd, adapter,
1564                                             QLCNIC_CMD_GET_LED_STATUS);
1565                 if (!err) {
1566                         err = qlcnic_issue_cmd(adapter, &cmd);
1567                         if (err) {
1568                                 netdev_err(adapter->netdev,
1569                                            "Failed to get current beacon state, err=%d\n",
1570                                            err);
1571                         } else {
1572                                 beacon_state = cmd.rsp.arg[1];
1573                                 if (beacon_state == QLCNIC_BEACON_DISABLE)
1574                                         ahw->beacon_state = QLCNIC_BEACON_OFF;
1575                                 else if (beacon_state == QLCNIC_BEACON_EANBLE)
1576                                         ahw->beacon_state = QLCNIC_BEACON_ON;
1577                         }
1578                 }
1579                 qlcnic_free_mbx_args(&cmd);
1580         }
1581
1582         return;
1583 }
1584
1585 void qlcnic_82xx_get_func_no(struct qlcnic_adapter *adapter)
1586 {
1587         void __iomem *msix_base_addr;
1588         u32 func;
1589         u32 msix_base;
1590
1591         pci_read_config_dword(adapter->pdev, QLCNIC_MSIX_TABLE_OFFSET, &func);
1592         msix_base_addr = adapter->ahw->pci_base0 + QLCNIC_MSIX_BASE;
1593         msix_base = readl(msix_base_addr);
1594         func = (func - msix_base) / QLCNIC_MSIX_TBL_PGSIZE;
1595         adapter->ahw->pci_func = func;
1596 }
1597
1598 void qlcnic_82xx_read_crb(struct qlcnic_adapter *adapter, char *buf,
1599                           loff_t offset, size_t size)
1600 {
1601         int err = 0;
1602         u32 data;
1603         u64 qmdata;
1604
1605         if (ADDR_IN_RANGE(offset, QLCNIC_PCI_CAMQM, QLCNIC_PCI_CAMQM_END)) {
1606                 qlcnic_pci_camqm_read_2M(adapter, offset, &qmdata);
1607                 memcpy(buf, &qmdata, size);
1608         } else {
1609                 data = QLCRD32(adapter, offset, &err);
1610                 memcpy(buf, &data, size);
1611         }
1612 }
1613
1614 void qlcnic_82xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
1615                            loff_t offset, size_t size)
1616 {
1617         u32 data;
1618         u64 qmdata;
1619
1620         if (ADDR_IN_RANGE(offset, QLCNIC_PCI_CAMQM, QLCNIC_PCI_CAMQM_END)) {
1621                 memcpy(&qmdata, buf, size);
1622                 qlcnic_pci_camqm_write_2M(adapter, offset, qmdata);
1623         } else {
1624                 memcpy(&data, buf, size);
1625                 QLCWR32(adapter, offset, data);
1626         }
1627 }
1628
1629 int qlcnic_82xx_api_lock(struct qlcnic_adapter *adapter)
1630 {
1631         return qlcnic_pcie_sem_lock(adapter, 5, 0);
1632 }
1633
1634 void qlcnic_82xx_api_unlock(struct qlcnic_adapter *adapter)
1635 {
1636         qlcnic_pcie_sem_unlock(adapter, 5);
1637 }
1638
1639 int qlcnic_82xx_shutdown(struct pci_dev *pdev)
1640 {
1641         struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
1642         struct net_device *netdev = adapter->netdev;
1643         int retval;
1644
1645         netif_device_detach(netdev);
1646
1647         qlcnic_cancel_idc_work(adapter);
1648
1649         if (netif_running(netdev))
1650                 qlcnic_down(adapter, netdev);
1651
1652         qlcnic_clr_all_drv_state(adapter, 0);
1653
1654         clear_bit(__QLCNIC_RESETTING, &adapter->state);
1655
1656         retval = pci_save_state(pdev);
1657         if (retval)
1658                 return retval;
1659
1660         if (qlcnic_wol_supported(adapter)) {
1661                 pci_enable_wake(pdev, PCI_D3cold, 1);
1662                 pci_enable_wake(pdev, PCI_D3hot, 1);
1663         }
1664
1665         return 0;
1666 }
1667
1668 int qlcnic_82xx_resume(struct qlcnic_adapter *adapter)
1669 {
1670         struct net_device *netdev = adapter->netdev;
1671         int err;
1672
1673         err = qlcnic_start_firmware(adapter);
1674         if (err) {
1675                 dev_err(&adapter->pdev->dev, "failed to start firmware\n");
1676                 return err;
1677         }
1678
1679         if (netif_running(netdev)) {
1680                 err = qlcnic_up(adapter, netdev);
1681                 if (!err)
1682                         qlcnic_restore_indev_addr(netdev, NETDEV_UP);
1683         }
1684
1685         netif_device_attach(netdev);
1686         qlcnic_schedule_work(adapter, qlcnic_fw_poll_work, FW_POLL_DELAY);
1687         return err;
1688 }