drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c

   1 /*
   2  * QLogic qlcnic NIC Driver
   3  * Copyright (c) 2009-2013 QLogic Corporation
   4  *
   5  * See LICENSE.qlcnic for copyright and licensing details.
   6  */
   7
   8 #include "qlcnic_sriov.h"
   9 #include "qlcnic.h"
  10 #include "qlcnic_hw.h"
  11
  12 /* Reset template definitions */
  13 #define QLC_83XX_RESTART_TEMPLATE_SIZE          0x2000
  14 #define QLC_83XX_RESET_TEMPLATE_ADDR            0x4F0000
  15 #define QLC_83XX_RESET_SEQ_VERSION              0x0101
  16
  17 #define QLC_83XX_OPCODE_NOP                     0x0000
  18 #define QLC_83XX_OPCODE_WRITE_LIST              0x0001
  19 #define QLC_83XX_OPCODE_READ_WRITE_LIST         0x0002
  20 #define QLC_83XX_OPCODE_POLL_LIST               0x0004
  21 #define QLC_83XX_OPCODE_POLL_WRITE_LIST         0x0008
  22 #define QLC_83XX_OPCODE_READ_MODIFY_WRITE       0x0010
  23 #define QLC_83XX_OPCODE_SEQ_PAUSE               0x0020
  24 #define QLC_83XX_OPCODE_SEQ_END                 0x0040
  25 #define QLC_83XX_OPCODE_TMPL_END                0x0080
  26 #define QLC_83XX_OPCODE_POLL_READ_LIST          0x0100
  27
  28 /* EPORT control registers */
  29 #define QLC_83XX_RESET_CONTROL                  0x28084E50
  30 #define QLC_83XX_RESET_REG                      0x28084E60
  31 #define QLC_83XX_RESET_PORT0                    0x28084E70
  32 #define QLC_83XX_RESET_PORT1                    0x28084E80
  33 #define QLC_83XX_RESET_PORT2                    0x28084E90
  34 #define QLC_83XX_RESET_PORT3                    0x28084EA0
  35 #define QLC_83XX_RESET_SRESHIM                  0x28084EB0
  36 #define QLC_83XX_RESET_EPGSHIM                  0x28084EC0
  37 #define QLC_83XX_RESET_ETHERPCS                 0x28084ED0
  38
  39 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter);
  40 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev);
  41 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter);
  42
  43 /* Template header */
  44 struct qlc_83xx_reset_hdr {
  45 #if defined(__LITTLE_ENDIAN)
  46         u16     version;
  47         u16     signature;
  48         u16     size;
  49         u16     entries;
  50         u16     hdr_size;
  51         u16     checksum;
  52         u16     init_offset;
  53         u16     start_offset;
  54 #elif defined(__BIG_ENDIAN)
  55         u16     signature;
  56         u16     version;
  57         u16     entries;
  58         u16     size;
  59         u16     checksum;
  60         u16     hdr_size;
  61         u16     start_offset;
  62         u16     init_offset;
  63 #endif
  64 } __packed;
  65
  66 /* Command entry header. */
  67 struct qlc_83xx_entry_hdr {
  68 #if defined(__LITTLE_ENDIAN)
  69         u16     cmd;
  70         u16     size;
  71         u16     count;
  72         u16     delay;
  73 #elif defined(__BIG_ENDIAN)
  74         u16     size;
  75         u16     cmd;
  76         u16     delay;
  77         u16     count;
  78 #endif
  79 } __packed;
  80
  81 /* Generic poll command */
  82 struct qlc_83xx_poll {
  83         u32     mask;
  84         u32     status;
  85 } __packed;
  86
  87 /* Read modify write command */
  88 struct qlc_83xx_rmw {
  89         u32     mask;
  90         u32     xor_value;
  91         u32     or_value;
  92 #if defined(__LITTLE_ENDIAN)
  93         u8      shl;
  94         u8      shr;
  95         u8      index_a;
  96         u8      rsvd;
  97 #elif defined(__BIG_ENDIAN)
  98         u8      rsvd;
  99         u8      index_a;
 100         u8      shr;
 101         u8      shl;
 102 #endif
 103 } __packed;
 104
 105 /* Generic command with 2 DWORD */
 106 struct qlc_83xx_entry {
 107         u32 arg1;
 108         u32 arg2;
 109 } __packed;
 110
 111 /* Generic command with 4 DWORD */
 112 struct qlc_83xx_quad_entry {
 113         u32 dr_addr;
 114         u32 dr_value;
 115         u32 ar_addr;
 116         u32 ar_value;
 117 } __packed;
 118 static const char *const qlc_83xx_idc_states[] = {
 119         "Unknown",
 120         "Cold",
 121         "Init",
 122         "Ready",
 123         "Need Reset",
 124         "Need Quiesce",
 125         "Failed",
 126         "Quiesce"
 127 };
 128
 129 static int
 130 qlcnic_83xx_idc_check_driver_presence_reg(struct qlcnic_adapter *adapter)
 131 {
 132         u32 val;
 133
 134         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 135         if ((val & 0xFFFF))
 136                 return 1;
 137         else
 138                 return 0;
 139 }
 140
 141 static void qlcnic_83xx_idc_log_state_history(struct qlcnic_adapter *adapter)
 142 {
 143         u32 cur, prev;
 144         cur = adapter->ahw->idc.curr_state;
 145         prev = adapter->ahw->idc.prev_state;
 146
 147         dev_info(&adapter->pdev->dev,
 148                  "current state  = %s,  prev state = %s\n",
 149                  adapter->ahw->idc.name[cur],
 150                  adapter->ahw->idc.name[prev]);
 151 }
 152
 153 static int qlcnic_83xx_idc_update_audit_reg(struct qlcnic_adapter *adapter,
 154                                             u8 mode, int lock)
 155 {
 156         u32 val;
 157         int seconds;
 158
 159         if (lock) {
 160                 if (qlcnic_83xx_lock_driver(adapter))
 161                         return -EBUSY;
 162         }
 163
 164         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
 165         val |= (adapter->portnum & 0xf);
 166         val |= mode << 7;
 167         if (mode)
 168                 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
 169         else
 170                 seconds = jiffies / HZ;
 171
 172         val |= seconds << 8;
 173         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT, val);
 174         adapter->ahw->idc.sec_counter = jiffies / HZ;
 175
 176         if (lock)
 177                 qlcnic_83xx_unlock_driver(adapter);
 178
 179         return 0;
 180 }
 181
 182 static void qlcnic_83xx_idc_update_minor_version(struct qlcnic_adapter *adapter)
 183 {
 184         u32 val;
 185
 186         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION);
 187         val = val & ~(0x3 << (adapter->portnum * 2));
 188         val = val | (QLC_83XX_IDC_MINOR_VERSION << (adapter->portnum * 2));
 189         QLCWRX(adapter->ahw, QLC_83XX_IDC_MIN_VERSION, val);
 190 }
 191
 192 static int qlcnic_83xx_idc_update_major_version(struct qlcnic_adapter *adapter,
 193                                                 int lock)
 194 {
 195         u32 val;
 196
 197         if (lock) {
 198                 if (qlcnic_83xx_lock_driver(adapter))
 199                         return -EBUSY;
 200         }
 201
 202         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
 203         val = val & ~0xFF;
 204         val = val | QLC_83XX_IDC_MAJOR_VERSION;
 205         QLCWRX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION, val);
 206
 207         if (lock)
 208                 qlcnic_83xx_unlock_driver(adapter);
 209
 210         return 0;
 211 }
 212
 213 static int
 214 qlcnic_83xx_idc_update_drv_presence_reg(struct qlcnic_adapter *adapter,
 215                                         int status, int lock)
 216 {
 217         u32 val;
 218
 219         if (lock) {
 220                 if (qlcnic_83xx_lock_driver(adapter))
 221                         return -EBUSY;
 222         }
 223
 224         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 225
 226         if (status)
 227                 val = val | (1 << adapter->portnum);
 228         else
 229                 val = val & ~(1 << adapter->portnum);
 230
 231         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
 232         qlcnic_83xx_idc_update_minor_version(adapter);
 233
 234         if (lock)
 235                 qlcnic_83xx_unlock_driver(adapter);
 236
 237         return 0;
 238 }
 239
 240 static int qlcnic_83xx_idc_check_major_version(struct qlcnic_adapter *adapter)
 241 {
 242         u32 val;
 243         u8 version;
 244
 245         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_MAJ_VERSION);
 246         version = val & 0xFF;
 247
 248         if (version != QLC_83XX_IDC_MAJOR_VERSION) {
 249                 dev_info(&adapter->pdev->dev,
 250                          "%s:mismatch. version 0x%x, expected version 0x%x\n",
 251                          __func__, version, QLC_83XX_IDC_MAJOR_VERSION);
 252                 return -EIO;
 253         }
 254
 255         return 0;
 256 }
 257
 258 static int qlcnic_83xx_idc_clear_registers(struct qlcnic_adapter *adapter,
 259                                            int lock)
 260 {
 261         u32 val;
 262
 263         if (lock) {
 264                 if (qlcnic_83xx_lock_driver(adapter))
 265                         return -EBUSY;
 266         }
 267
 268         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, 0);
 269         /* Clear gracefull reset bit */
 270         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
 271         val &= ~QLC_83XX_IDC_GRACEFULL_RESET;
 272         QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
 273
 274         if (lock)
 275                 qlcnic_83xx_unlock_driver(adapter);
 276
 277         return 0;
 278 }
 279
 280 static int qlcnic_83xx_idc_update_drv_ack_reg(struct qlcnic_adapter *adapter,
 281                                               int flag, int lock)
 282 {
 283         u32 val;
 284
 285         if (lock) {
 286                 if (qlcnic_83xx_lock_driver(adapter))
 287                         return -EBUSY;
 288         }
 289
 290         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
 291         if (flag)
 292                 val = val | (1 << adapter->portnum);
 293         else
 294                 val = val & ~(1 << adapter->portnum);
 295         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_ACK, val);
 296
 297         if (lock)
 298                 qlcnic_83xx_unlock_driver(adapter);
 299
 300         return 0;
 301 }
 302
 303 static int qlcnic_83xx_idc_check_timeout(struct qlcnic_adapter *adapter,
 304                                          int time_limit)
 305 {
 306         u64 seconds;
 307
 308         seconds = jiffies / HZ - adapter->ahw->idc.sec_counter;
 309         if (seconds <= time_limit)
 310                 return 0;
 311         else
 312                 return -EBUSY;
 313 }
 314
 315 /**
 316  * qlcnic_83xx_idc_check_reset_ack_reg
 317  *
 318  * @adapter: adapter structure
 319  *
 320  * Check ACK wait limit and clear the functions which failed to ACK
 321  *
 322  * Return 0 if all functions have acknowledged the reset request.
 323  **/
 324 static int qlcnic_83xx_idc_check_reset_ack_reg(struct qlcnic_adapter *adapter)
 325 {
 326         int timeout;
 327         u32 ack, presence, val;
 328
 329         timeout = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
 330         ack = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_ACK);
 331         presence = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 332         dev_info(&adapter->pdev->dev,
 333                  "%s: ack = 0x%x, presence = 0x%x\n", __func__, ack, presence);
 334         if (!((ack & presence) == presence)) {
 335                 if (qlcnic_83xx_idc_check_timeout(adapter, timeout)) {
 336                         /* Clear functions which failed to ACK */
 337                         dev_info(&adapter->pdev->dev,
 338                                  "%s: ACK wait exceeds time limit\n", __func__);
 339                         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
 340                         val = val & ~(ack ^ presence);
 341                         if (qlcnic_83xx_lock_driver(adapter))
 342                                 return -EBUSY;
 343                         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
 344                         dev_info(&adapter->pdev->dev,
 345                                  "%s: updated drv presence reg = 0x%x\n",
 346                                  __func__, val);
 347                         qlcnic_83xx_unlock_driver(adapter);
 348                         return 0;
 349
 350                 } else {
 351                         return 1;
 352                 }
 353         } else {
 354                 dev_info(&adapter->pdev->dev,
 355                          "%s: Reset ACK received from all functions\n",
 356                          __func__);
 357                 return 0;
 358         }
 359 }
 360
 361 /**
 362  * qlcnic_83xx_idc_tx_soft_reset
 363  *
 364  * @adapter: adapter structure
 365  *
 366  * Handle context deletion and recreation request from transmit routine
 367  *
 368  * Returns -EBUSY  or Success (0)
 369  *
 370  **/
 371 static int qlcnic_83xx_idc_tx_soft_reset(struct qlcnic_adapter *adapter)
 372 {
 373         struct net_device *netdev = adapter->netdev;
 374
 375         if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
 376                 return -EBUSY;
 377
 378         netif_device_detach(netdev);
 379         qlcnic_down(adapter, netdev);
 380         qlcnic_up(adapter, netdev);
 381         netif_device_attach(netdev);
 382         clear_bit(__QLCNIC_RESETTING, &adapter->state);
 383         dev_err(&adapter->pdev->dev, "%s:\n", __func__);
 384
 385         return 0;
 386 }
 387
 388 /**
 389  * qlcnic_83xx_idc_detach_driver
 390  *
 391  * @adapter: adapter structure
 392  * Detach net interface, stop TX and cleanup resources before the HW reset.
 393  * Returns: None
 394  *
 395  **/
 396 static void qlcnic_83xx_idc_detach_driver(struct qlcnic_adapter *adapter)
 397 {
 398         int i;
 399         struct net_device *netdev = adapter->netdev;
 400
 401         netif_device_detach(netdev);
 402
 403         /* Disable mailbox interrupt */
 404         qlcnic_83xx_disable_mbx_intr(adapter);
 405         qlcnic_down(adapter, netdev);
 406         for (i = 0; i < adapter->ahw->num_msix; i++) {
 407                 adapter->ahw->intr_tbl[i].id = i;
 408                 adapter->ahw->intr_tbl[i].enabled = 0;
 409                 adapter->ahw->intr_tbl[i].src = 0;
 410         }
 411
 412         if (qlcnic_sriov_pf_check(adapter))
 413                 qlcnic_sriov_pf_reset(adapter);
 414 }
 415
 416 /**
 417  * qlcnic_83xx_idc_attach_driver
 418  *
 419  * @adapter: adapter structure
 420  *
 421  * Re-attach and re-enable net interface
 422  * Returns: None
 423  *
 424  **/
 425 static void qlcnic_83xx_idc_attach_driver(struct qlcnic_adapter *adapter)
 426 {
 427         struct net_device *netdev = adapter->netdev;
 428
 429         if (netif_running(netdev)) {
 430                 if (qlcnic_up(adapter, netdev))
 431                         goto done;
 432                 qlcnic_restore_indev_addr(netdev, NETDEV_UP);
 433         }
 434 done:
 435         netif_device_attach(netdev);
 436 }
 437
 438 static int qlcnic_83xx_idc_enter_failed_state(struct qlcnic_adapter *adapter,
 439                                               int lock)
 440 {
 441         if (lock) {
 442                 if (qlcnic_83xx_lock_driver(adapter))
 443                         return -EBUSY;
 444         }
 445
 446         qlcnic_83xx_idc_clear_registers(adapter, 0);
 447         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_FAILED);
 448         if (lock)
 449                 qlcnic_83xx_unlock_driver(adapter);
 450
 451         qlcnic_83xx_idc_log_state_history(adapter);
 452         dev_info(&adapter->pdev->dev, "Device will enter failed state\n");
 453
 454         return 0;
 455 }
 456
 457 static int qlcnic_83xx_idc_enter_init_state(struct qlcnic_adapter *adapter,
 458                                             int lock)
 459 {
 460         if (lock) {
 461                 if (qlcnic_83xx_lock_driver(adapter))
 462                         return -EBUSY;
 463         }
 464
 465         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_INIT);
 466
 467         if (lock)
 468                 qlcnic_83xx_unlock_driver(adapter);
 469
 470         return 0;
 471 }
 472
 473 static int qlcnic_83xx_idc_enter_need_quiesce(struct qlcnic_adapter *adapter,
 474                                               int lock)
 475 {
 476         if (lock) {
 477                 if (qlcnic_83xx_lock_driver(adapter))
 478                         return -EBUSY;
 479         }
 480
 481         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
 482                QLC_83XX_IDC_DEV_NEED_QUISCENT);
 483
 484         if (lock)
 485                 qlcnic_83xx_unlock_driver(adapter);
 486
 487         return 0;
 488 }
 489
 490 static int
 491 qlcnic_83xx_idc_enter_need_reset_state(struct qlcnic_adapter *adapter, int lock)
 492 {
 493         if (lock) {
 494                 if (qlcnic_83xx_lock_driver(adapter))
 495                         return -EBUSY;
 496         }
 497
 498         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
 499                QLC_83XX_IDC_DEV_NEED_RESET);
 500
 501         if (lock)
 502                 qlcnic_83xx_unlock_driver(adapter);
 503
 504         return 0;
 505 }
 506
 507 static int qlcnic_83xx_idc_enter_ready_state(struct qlcnic_adapter *adapter,
 508                                              int lock)
 509 {
 510         if (lock) {
 511                 if (qlcnic_83xx_lock_driver(adapter))
 512                         return -EBUSY;
 513         }
 514
 515         QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE, QLC_83XX_IDC_DEV_READY);
 516         if (lock)
 517                 qlcnic_83xx_unlock_driver(adapter);
 518
 519         return 0;
 520 }
 521
 522 /**
 523  * qlcnic_83xx_idc_find_reset_owner_id
 524  *
 525  * @adapter: adapter structure
 526  *
 527  * NIC gets precedence over ISCSI and ISCSI has precedence over FCOE.
 528  * Within the same class, function with lowest PCI ID assumes ownership
 529  *
 530  * Returns: reset owner id or failure indication (-EIO)
 531  *
 532  **/
 533 static int qlcnic_83xx_idc_find_reset_owner_id(struct qlcnic_adapter *adapter)
 534 {
 535         u32 reg, reg1, reg2, i, j, owner, class;
 536
 537         reg1 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_1);
 538         reg2 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_2);
 539         owner = QLCNIC_TYPE_NIC;
 540         i = 0;
 541         j = 0;
 542         reg = reg1;
 543
 544         do {
 545                 class = (((reg & (0xF << j * 4)) >> j * 4) & 0x3);
 546                 if (class == owner)
 547                         break;
 548                 if (i == (QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO - 1)) {
 549                         reg = reg2;
 550                         j = 0;
 551                 } else {
 552                         j++;
 553                 }
 554
 555                 if (i == (QLC_83XX_IDC_MAX_CNA_FUNCTIONS - 1)) {
 556                         if (owner == QLCNIC_TYPE_NIC)
 557                                 owner = QLCNIC_TYPE_ISCSI;
 558                         else if (owner == QLCNIC_TYPE_ISCSI)
 559                                 owner = QLCNIC_TYPE_FCOE;
 560                         else if (owner == QLCNIC_TYPE_FCOE)
 561                                 return -EIO;
 562                         reg = reg1;
 563                         j = 0;
 564                         i = 0;
 565                 }
 566         } while (i++ < QLC_83XX_IDC_MAX_CNA_FUNCTIONS);
 567
 568         return i;
 569 }
 570
 571 static int qlcnic_83xx_idc_restart_hw(struct qlcnic_adapter *adapter, int lock)
 572 {
 573         int ret = 0;
 574
 575         ret = qlcnic_83xx_restart_hw(adapter);
 576
 577         if (ret) {
 578                 qlcnic_83xx_idc_enter_failed_state(adapter, lock);
 579         } else {
 580                 qlcnic_83xx_idc_clear_registers(adapter, lock);
 581                 ret = qlcnic_83xx_idc_enter_ready_state(adapter, lock);
 582         }
 583
 584         return ret;
 585 }
 586
 587 static int qlcnic_83xx_idc_check_fan_failure(struct qlcnic_adapter *adapter)
 588 {
 589         u32 status;
 590
 591         status = QLC_SHARED_REG_RD32(adapter, QLCNIC_PEG_HALT_STATUS1);
 592
 593         if (status & QLCNIC_RCODE_FATAL_ERROR) {
 594                 dev_err(&adapter->pdev->dev,
 595                         "peg halt status1=0x%x\n", status);
 596                 if (QLCNIC_FWERROR_CODE(status) == QLCNIC_FWERROR_FAN_FAILURE) {
 597                         dev_err(&adapter->pdev->dev,
 598                                 "On board active cooling fan failed. "
 599                                 "Device has been halted.\n");
 600                         dev_err(&adapter->pdev->dev,
 601                                 "Replace the adapter.\n");
 602                         return -EIO;
 603                 }
 604         }
 605
 606         return 0;
 607 }
 608
 609 static int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *adapter)
 610 {
 611         int err;
 612
 613         /* register for NIC IDC AEN Events */
 614         qlcnic_83xx_register_nic_idc_func(adapter, 1);
 615
 616         err = qlcnic_sriov_pf_reinit(adapter);
 617         if (err)
 618                 return err;
 619
 620         qlcnic_83xx_enable_mbx_intrpt(adapter);
 621
 622         if (qlcnic_83xx_configure_opmode(adapter)) {
 623                 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 624                 return -EIO;
 625         }
 626
 627         if (adapter->nic_ops->init_driver(adapter)) {
 628                 qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 629                 return -EIO;
 630         }
 631
 632         qlcnic_83xx_idc_attach_driver(adapter);
 633
 634         return 0;
 635 }
 636
 637 static void qlcnic_83xx_idc_update_idc_params(struct qlcnic_adapter *adapter)
 638 {
 639         struct qlcnic_hardware_context *ahw = adapter->ahw;
 640
 641         qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 1);
 642         set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
 643         qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
 644         set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
 645
 646         ahw->idc.quiesce_req = 0;
 647         ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
 648         ahw->idc.err_code = 0;
 649         ahw->idc.collect_dump = 0;
 650         ahw->reset_context = 0;
 651         adapter->tx_timeo_cnt = 0;
 652
 653         clear_bit(__QLCNIC_RESETTING, &adapter->state);
 654 }
 655
 656 /**
 657  * qlcnic_83xx_idc_ready_state_entry
 658  *
 659  * @adapter: adapter structure
 660  *
 661  * Perform ready state initialization, this routine will get invoked only
 662  * once from READY state.
 663  *
 664  * Returns: Error code or Success(0)
 665  *
 666  **/
 667 int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *adapter)
 668 {
 669         struct qlcnic_hardware_context *ahw = adapter->ahw;
 670
 671         if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY) {
 672                 qlcnic_83xx_idc_update_idc_params(adapter);
 673                 /* Re-attach the device if required */
 674                 if ((ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) ||
 675                     (ahw->idc.prev_state == QLC_83XX_IDC_DEV_INIT)) {
 676                         if (qlcnic_83xx_idc_reattach_driver(adapter))
 677                                 return -EIO;
 678                 }
 679         }
 680
 681         return 0;
 682 }
 683
 684 /**
 685  * qlcnic_83xx_idc_vnic_pf_entry
 686  *
 687  * @adapter: adapter structure
 688  *
 689  * Ensure vNIC mode privileged function starts only after vNIC mode is
 690  * enabled by management function.
 691  * If vNIC mode is ready, start initialization.
 692  *
 693  * Returns: -EIO or 0
 694  *
 695  **/
 696 int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *adapter)
 697 {
 698         u32 state;
 699         struct qlcnic_hardware_context *ahw = adapter->ahw;
 700
 701         /* Privileged function waits till mgmt function enables VNIC mode */
 702         state = QLCRDX(adapter->ahw, QLC_83XX_VNIC_STATE);
 703         if (state != QLCNIC_DEV_NPAR_OPER) {
 704                 if (!ahw->idc.vnic_wait_limit--) {
 705                         qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 706                         return -EIO;
 707                 }
 708                 dev_info(&adapter->pdev->dev, "vNIC mode disabled\n");
 709                 return -EIO;
 710
 711         } else {
 712                 /* Perform one time initialization from ready state */
 713                 if (ahw->idc.vnic_state != QLCNIC_DEV_NPAR_OPER) {
 714                         qlcnic_83xx_idc_update_idc_params(adapter);
 715
 716                         /* If the previous state is UNKNOWN, device will be
 717                            already attached properly by Init routine*/
 718                         if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_UNKNOWN) {
 719                                 if (qlcnic_83xx_idc_reattach_driver(adapter))
 720                                         return -EIO;
 721                         }
 722                         adapter->ahw->idc.vnic_state =  QLCNIC_DEV_NPAR_OPER;
 723                         dev_info(&adapter->pdev->dev, "vNIC mode enabled\n");
 724                 }
 725         }
 726
 727         return 0;
 728 }
 729
 730 static int qlcnic_83xx_idc_unknown_state(struct qlcnic_adapter *adapter)
 731 {
 732         adapter->ahw->idc.err_code = -EIO;
 733         dev_err(&adapter->pdev->dev,
 734                 "%s: Device in unknown state\n", __func__);
 735         return 0;
 736 }
 737
 738 /**
 739  * qlcnic_83xx_idc_cold_state
 740  *
 741  * @adapter: adapter structure
 742  *
 743  * If HW is up and running device will enter READY state.
 744  * If firmware image from host needs to be loaded, device is
 745  * forced to start with the file firmware image.
 746  *
 747  * Returns: Error code or Success(0)
 748  *
 749  **/
 750 static int qlcnic_83xx_idc_cold_state_handler(struct qlcnic_adapter *adapter)
 751 {
 752         qlcnic_83xx_idc_update_drv_presence_reg(adapter, 1, 0);
 753         qlcnic_83xx_idc_update_audit_reg(adapter, 1, 0);
 754
 755         if (qlcnic_load_fw_file) {
 756                 qlcnic_83xx_idc_restart_hw(adapter, 0);
 757         } else {
 758                 if (qlcnic_83xx_check_hw_status(adapter)) {
 759                         qlcnic_83xx_idc_enter_failed_state(adapter, 0);
 760                         return -EIO;
 761                 } else {
 762                         qlcnic_83xx_idc_enter_ready_state(adapter, 0);
 763                 }
 764         }
 765         return 0;
 766 }
 767
 768 /**
 769  * qlcnic_83xx_idc_init_state
 770  *
 771  * @adapter: adapter structure
 772  *
 773  * Reset owner will restart the device from this state.
 774  * Device will enter failed state if it remains
 775  * in this state for more than DEV_INIT time limit.
 776  *
 777  * Returns: Error code or Success(0)
 778  *
 779  **/
 780 static int qlcnic_83xx_idc_init_state(struct qlcnic_adapter *adapter)
 781 {
 782         int timeout, ret = 0;
 783         u32 owner;
 784
 785         timeout = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
 786         if (adapter->ahw->idc.prev_state == QLC_83XX_IDC_DEV_NEED_RESET) {
 787                 owner = qlcnic_83xx_idc_find_reset_owner_id(adapter);
 788                 if (adapter->ahw->pci_func == owner)
 789                         ret = qlcnic_83xx_idc_restart_hw(adapter, 1);
 790         } else {
 791                 ret = qlcnic_83xx_idc_check_timeout(adapter, timeout);
 792                 return ret;
 793         }
 794
 795         return ret;
 796 }
 797
 798 /**
 799  * qlcnic_83xx_idc_ready_state
 800  *
 801  * @adapter: adapter structure
 802  *
 803  * Perform IDC protocol specicifed actions after monitoring device state and
 804  * events.
 805  *
 806  * Returns: Error code or Success(0)
 807  *
 808  **/
 809 static int qlcnic_83xx_idc_ready_state(struct qlcnic_adapter *adapter)
 810 {
 811         u32 val;
 812         struct qlcnic_hardware_context *ahw = adapter->ahw;
 813         int ret = 0;
 814
 815         /* Perform NIC configuration based ready state entry actions */
 816         if (ahw->idc.state_entry(adapter))
 817                 return -EIO;
 818
 819         if (qlcnic_check_temp(adapter)) {
 820                 if (ahw->temp == QLCNIC_TEMP_PANIC) {
 821                         qlcnic_83xx_idc_check_fan_failure(adapter);
 822                         dev_err(&adapter->pdev->dev,
 823                                 "Error: device temperature %d above limits\n",
 824                                 adapter->ahw->temp);
 825                         clear_bit(QLC_83XX_MBX_READY, &ahw->idc.status);
 826                         set_bit(__QLCNIC_RESETTING, &adapter->state);
 827                         qlcnic_83xx_idc_detach_driver(adapter);
 828                         qlcnic_83xx_idc_enter_failed_state(adapter, 1);
 829                         return -EIO;
 830                 }
 831         }
 832
 833         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
 834         ret = qlcnic_83xx_check_heartbeat(adapter);
 835         if (ret) {
 836                 adapter->flags |= QLCNIC_FW_HANG;
 837                 if (!(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
 838                         clear_bit(QLC_83XX_MBX_READY, &ahw->idc.status);
 839                         set_bit(__QLCNIC_RESETTING, &adapter->state);
 840                         qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
 841                 }
 842                 return -EIO;
 843         }
 844
 845         if ((val & QLC_83XX_IDC_GRACEFULL_RESET) || ahw->idc.collect_dump) {
 846                 /* Move to need reset state and prepare for reset */
 847                 qlcnic_83xx_idc_enter_need_reset_state(adapter, 1);
 848                 return ret;
 849         }
 850
 851         /* Check for soft reset request */
 852         if (ahw->reset_context &&
 853             !(val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY)) {
 854                 adapter->ahw->reset_context = 0;
 855                 qlcnic_83xx_idc_tx_soft_reset(adapter);
 856                 return ret;
 857         }
 858
 859         /* Move to need quiesce state if requested */
 860         if (adapter->ahw->idc.quiesce_req) {
 861                 qlcnic_83xx_idc_enter_need_quiesce(adapter, 1);
 862                 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
 863                 return ret;
 864         }
 865
 866         return ret;
 867 }
 868
 869 /**
 870  * qlcnic_83xx_idc_need_reset_state
 871  *
 872  * @adapter: adapter structure
 873  *
 874  * Device will remain in this state until:
 875  *      Reset request ACK's are recieved from all the functions
 876  *      Wait time exceeds max time limit
 877  *
 878  * Returns: Error code or Success(0)
 879  *
 880  **/
 881 static int qlcnic_83xx_idc_need_reset_state(struct qlcnic_adapter *adapter)
 882 {
 883         int ret = 0;
 884
 885         if (adapter->ahw->idc.prev_state != QLC_83XX_IDC_DEV_NEED_RESET) {
 886                 qlcnic_83xx_idc_update_drv_ack_reg(adapter, 1, 1);
 887                 qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
 888                 set_bit(__QLCNIC_RESETTING, &adapter->state);
 889                 clear_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
 890                 if (adapter->ahw->nic_mode == QLC_83XX_VIRTUAL_NIC_MODE)
 891                         qlcnic_83xx_disable_vnic_mode(adapter, 1);
 892                 qlcnic_83xx_idc_detach_driver(adapter);
 893         }
 894
 895         /* Check ACK from other functions */
 896         ret = qlcnic_83xx_idc_check_reset_ack_reg(adapter);
 897         if (ret) {
 898                 dev_info(&adapter->pdev->dev,
 899                          "%s: Waiting for reset ACK\n", __func__);
 900                 return 0;
 901         }
 902
 903         /* Transit to INIT state and restart the HW */
 904         qlcnic_83xx_idc_enter_init_state(adapter, 1);
 905
 906         return ret;
 907 }
 908
 909 static int qlcnic_83xx_idc_need_quiesce_state(struct qlcnic_adapter *adapter)
 910 {
 911         dev_err(&adapter->pdev->dev, "%s: TBD\n", __func__);
 912         return 0;
 913 }
 914
 915 static int qlcnic_83xx_idc_failed_state(struct qlcnic_adapter *adapter)
 916 {
 917         dev_err(&adapter->pdev->dev, "%s: please restart!!\n", __func__);
 918         clear_bit(__QLCNIC_RESETTING, &adapter->state);
 919         adapter->ahw->idc.err_code = -EIO;
 920
 921         return 0;
 922 }
 923
 924 static int qlcnic_83xx_idc_quiesce_state(struct qlcnic_adapter *adapter)
 925 {
 926         dev_info(&adapter->pdev->dev, "%s: TBD\n", __func__);
 927         return 0;
 928 }
 929
 930 static int qlcnic_83xx_idc_check_state_validity(struct qlcnic_adapter *adapter,
 931                                                 u32 state)
 932 {
 933         u32 cur, prev, next;
 934
 935         cur = adapter->ahw->idc.curr_state;
 936         prev = adapter->ahw->idc.prev_state;
 937         next = state;
 938
 939         if ((next < QLC_83XX_IDC_DEV_COLD) ||
 940             (next > QLC_83XX_IDC_DEV_QUISCENT)) {
 941                 dev_err(&adapter->pdev->dev,
 942                         "%s: curr %d, prev %d, next state %d is  invalid\n",
 943                         __func__, cur, prev, state);
 944                 return 1;
 945         }
 946
 947         if ((cur == QLC_83XX_IDC_DEV_UNKNOWN) &&
 948             (prev == QLC_83XX_IDC_DEV_UNKNOWN)) {
 949                 if ((next != QLC_83XX_IDC_DEV_COLD) &&
 950                     (next != QLC_83XX_IDC_DEV_READY)) {
 951                         dev_err(&adapter->pdev->dev,
 952                                 "%s: failed, cur %d prev %d next %d\n",
 953                                 __func__, cur, prev, next);
 954                         return 1;
 955                 }
 956         }
 957
 958         if (next == QLC_83XX_IDC_DEV_INIT) {
 959                 if ((prev != QLC_83XX_IDC_DEV_INIT) &&
 960                     (prev != QLC_83XX_IDC_DEV_COLD) &&
 961                     (prev != QLC_83XX_IDC_DEV_NEED_RESET)) {
 962                         dev_err(&adapter->pdev->dev,
 963                                 "%s: failed, cur %d prev %d next %d\n",
 964                                 __func__, cur, prev, next);
 965                         return 1;
 966                 }
 967         }
 968
 969         return 0;
 970 }
 971
 972 static void qlcnic_83xx_periodic_tasks(struct qlcnic_adapter *adapter)
 973 {
 974         if (adapter->fhash.fnum)
 975                 qlcnic_prune_lb_filters(adapter);
 976 }
 977
 978 /**
 979  * qlcnic_83xx_idc_poll_dev_state
 980  *
 981  * @work: kernel work queue structure used to schedule the function
 982  *
 983  * Poll device state periodically and perform state specific
 984  * actions defined by Inter Driver Communication (IDC) protocol.
 985  *
 986  * Returns: None
 987  *
 988  **/
 989 void qlcnic_83xx_idc_poll_dev_state(struct work_struct *work)
 990 {
 991         struct qlcnic_adapter *adapter;
 992         u32 state;
 993
 994         adapter = container_of(work, struct qlcnic_adapter, fw_work.work);
 995         state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
 996
 997         if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
 998                 qlcnic_83xx_idc_log_state_history(adapter);
 999                 adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1000         } else {
1001                 adapter->ahw->idc.curr_state = state;
1002         }
1003
1004         switch (adapter->ahw->idc.curr_state) {
1005         case QLC_83XX_IDC_DEV_READY:
1006                 qlcnic_83xx_idc_ready_state(adapter);
1007                 break;
1008         case QLC_83XX_IDC_DEV_NEED_RESET:
1009                 qlcnic_83xx_idc_need_reset_state(adapter);
1010                 break;
1011         case QLC_83XX_IDC_DEV_NEED_QUISCENT:
1012                 qlcnic_83xx_idc_need_quiesce_state(adapter);
1013                 break;
1014         case QLC_83XX_IDC_DEV_FAILED:
1015                 qlcnic_83xx_idc_failed_state(adapter);
1016                 return;
1017         case QLC_83XX_IDC_DEV_INIT:
1018                 qlcnic_83xx_idc_init_state(adapter);
1019                 break;
1020         case QLC_83XX_IDC_DEV_QUISCENT:
1021                 qlcnic_83xx_idc_quiesce_state(adapter);
1022                 break;
1023         default:
1024                 qlcnic_83xx_idc_unknown_state(adapter);
1025                 return;
1026         }
1027         adapter->ahw->idc.prev_state = adapter->ahw->idc.curr_state;
1028         qlcnic_83xx_periodic_tasks(adapter);
1029
1030         /* Re-schedule the function */
1031         if (test_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status))
1032                 qlcnic_schedule_work(adapter, qlcnic_83xx_idc_poll_dev_state,
1033                                      adapter->ahw->idc.delay);
1034 }
1035
1036 static void qlcnic_83xx_setup_idc_parameters(struct qlcnic_adapter *adapter)
1037 {
1038         u32 idc_params, val;
1039
1040         if (qlcnic_83xx_lockless_flash_read32(adapter,
1041                                               QLC_83XX_IDC_FLASH_PARAM_ADDR,
1042                                               (u8 *)&idc_params, 1)) {
1043                 dev_info(&adapter->pdev->dev,
1044                          "%s:failed to get IDC params from flash\n", __func__);
1045                 adapter->dev_init_timeo = QLC_83XX_IDC_INIT_TIMEOUT_SECS;
1046                 adapter->reset_ack_timeo = QLC_83XX_IDC_RESET_TIMEOUT_SECS;
1047         } else {
1048                 adapter->dev_init_timeo = idc_params & 0xFFFF;
1049                 adapter->reset_ack_timeo = ((idc_params >> 16) & 0xFFFF);
1050         }
1051
1052         adapter->ahw->idc.curr_state = QLC_83XX_IDC_DEV_UNKNOWN;
1053         adapter->ahw->idc.prev_state = QLC_83XX_IDC_DEV_UNKNOWN;
1054         adapter->ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY;
1055         adapter->ahw->idc.err_code = 0;
1056         adapter->ahw->idc.collect_dump = 0;
1057         adapter->ahw->idc.name = (char **)qlc_83xx_idc_states;
1058
1059         clear_bit(__QLCNIC_RESETTING, &adapter->state);
1060         set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
1061         set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1062
1063         /* Check if reset recovery is disabled */
1064         if (!qlcnic_auto_fw_reset) {
1065                 /* Propagate do not reset request to other functions */
1066                 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1067                 val = val | QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1068                 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1069         }
1070 }
1071
1072 static int
1073 qlcnic_83xx_idc_first_to_load_function_handler(struct qlcnic_adapter *adapter)
1074 {
1075         u32 state, val;
1076
1077         if (qlcnic_83xx_lock_driver(adapter))
1078                 return -EIO;
1079
1080         /* Clear driver lock register */
1081         QLCWRX(adapter->ahw, QLC_83XX_RECOVER_DRV_LOCK, 0);
1082         if (qlcnic_83xx_idc_update_major_version(adapter, 0)) {
1083                 qlcnic_83xx_unlock_driver(adapter);
1084                 return -EIO;
1085         }
1086
1087         state = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_STATE);
1088         if (qlcnic_83xx_idc_check_state_validity(adapter, state)) {
1089                 qlcnic_83xx_unlock_driver(adapter);
1090                 return -EIO;
1091         }
1092
1093         if (state != QLC_83XX_IDC_DEV_COLD && qlcnic_load_fw_file) {
1094                 QLCWRX(adapter->ahw, QLC_83XX_IDC_DEV_STATE,
1095                        QLC_83XX_IDC_DEV_COLD);
1096                 state = QLC_83XX_IDC_DEV_COLD;
1097         }
1098
1099         adapter->ahw->idc.curr_state = state;
1100         /* First to load function should cold boot the device */
1101         if (state == QLC_83XX_IDC_DEV_COLD)
1102                 qlcnic_83xx_idc_cold_state_handler(adapter);
1103
1104         /* Check if reset recovery is enabled */
1105         if (qlcnic_auto_fw_reset) {
1106                 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1107                 val = val & ~QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY;
1108                 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1109         }
1110
1111         qlcnic_83xx_unlock_driver(adapter);
1112
1113         return 0;
1114 }
1115
1116 static int qlcnic_83xx_idc_init(struct qlcnic_adapter *adapter)
1117 {
1118         int ret = -EIO;
1119
1120         qlcnic_83xx_setup_idc_parameters(adapter);
1121
1122         if (qlcnic_83xx_get_reset_instruction_template(adapter))
1123                 return ret;
1124
1125         if (!qlcnic_83xx_idc_check_driver_presence_reg(adapter)) {
1126                 if (qlcnic_83xx_idc_first_to_load_function_handler(adapter))
1127                         return -EIO;
1128         } else {
1129                 if (qlcnic_83xx_idc_check_major_version(adapter))
1130                         return -EIO;
1131         }
1132
1133         qlcnic_83xx_idc_update_audit_reg(adapter, 0, 1);
1134
1135         return 0;
1136 }
1137
1138 void qlcnic_83xx_idc_exit(struct qlcnic_adapter *adapter)
1139 {
1140         int id;
1141         u32 val;
1142
1143         while (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
1144                 usleep_range(10000, 11000);
1145
1146         id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1147         id = id & 0xFF;
1148
1149         if (id == adapter->portnum) {
1150                 dev_err(&adapter->pdev->dev,
1151                         "%s: wait for lock recovery.. %d\n", __func__, id);
1152                 msleep(20);
1153                 id = QLCRDX(adapter->ahw, QLC_83XX_DRV_LOCK_ID);
1154                 id = id & 0xFF;
1155         }
1156
1157         /* Clear driver presence bit */
1158         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
1159         val = val & ~(1 << adapter->portnum);
1160         QLCWRX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE, val);
1161         clear_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status);
1162         clear_bit(__QLCNIC_RESETTING, &adapter->state);
1163
1164         cancel_delayed_work_sync(&adapter->fw_work);
1165 }
1166
1167 void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *adapter, u32 key)
1168 {
1169         u32 val;
1170
1171         if (qlcnic_83xx_lock_driver(adapter)) {
1172                 dev_err(&adapter->pdev->dev,
1173                         "%s:failed, please retry\n", __func__);
1174                 return;
1175         }
1176
1177         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1178         if ((val & QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY) ||
1179             !qlcnic_auto_fw_reset) {
1180                 dev_err(&adapter->pdev->dev,
1181                         "%s:failed, device in non reset mode\n", __func__);
1182                 qlcnic_83xx_unlock_driver(adapter);
1183                 return;
1184         }
1185
1186         if (key == QLCNIC_FORCE_FW_RESET) {
1187                 val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1188                 val = val | QLC_83XX_IDC_GRACEFULL_RESET;
1189                 QLCWRX(adapter->ahw, QLC_83XX_IDC_CTRL, val);
1190         } else if (key == QLCNIC_FORCE_FW_DUMP_KEY) {
1191                 adapter->ahw->idc.collect_dump = 1;
1192         }
1193
1194         qlcnic_83xx_unlock_driver(adapter);
1195         return;
1196 }
1197
1198 static int qlcnic_83xx_copy_bootloader(struct qlcnic_adapter *adapter)
1199 {
1200         u8 *p_cache;
1201         u32 src, size;
1202         u64 dest;
1203         int ret = -EIO;
1204
1205         src = QLC_83XX_BOOTLOADER_FLASH_ADDR;
1206         dest = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_ADDR);
1207         size = QLCRDX(adapter->ahw, QLCNIC_BOOTLOADER_SIZE);
1208
1209         /* alignment check */
1210         if (size & 0xF)
1211                 size = (size + 16) & ~0xF;
1212
1213         p_cache = kzalloc(size, GFP_KERNEL);
1214         if (p_cache == NULL)
1215                 return -ENOMEM;
1216
1217         ret = qlcnic_83xx_lockless_flash_read32(adapter, src, p_cache,
1218                                                 size / sizeof(u32));
1219         if (ret) {
1220                 kfree(p_cache);
1221                 return ret;
1222         }
1223         /* 16 byte write to MS memory */
1224         ret = qlcnic_83xx_ms_mem_write128(adapter, dest, (u32 *)p_cache,
1225                                           size / 16);
1226         if (ret) {
1227                 kfree(p_cache);
1228                 return ret;
1229         }
1230         kfree(p_cache);
1231
1232         return ret;
1233 }
1234
1235 static int qlcnic_83xx_copy_fw_file(struct qlcnic_adapter *adapter)
1236 {
1237         u32 dest, *p_cache;
1238         u64 addr;
1239         u8 data[16];
1240         size_t size;
1241         int i, ret = -EIO;
1242
1243         dest = QLCRDX(adapter->ahw, QLCNIC_FW_IMAGE_ADDR);
1244         size = (adapter->ahw->fw_info.fw->size & ~0xF);
1245         p_cache = (u32 *)adapter->ahw->fw_info.fw->data;
1246         addr = (u64)dest;
1247
1248         ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1249                                           (u32 *)p_cache, size / 16);
1250         if (ret) {
1251                 dev_err(&adapter->pdev->dev, "MS memory write failed\n");
1252                 release_firmware(adapter->ahw->fw_info.fw);
1253                 adapter->ahw->fw_info.fw = NULL;
1254                 return -EIO;
1255         }
1256
1257         /* alignment check */
1258         if (adapter->ahw->fw_info.fw->size & 0xF) {
1259                 addr = dest + size;
1260                 for (i = 0; i < (adapter->ahw->fw_info.fw->size & 0xF); i++)
1261                         data[i] = adapter->ahw->fw_info.fw->data[size + i];
1262                 for (; i < 16; i++)
1263                         data[i] = 0;
1264                 ret = qlcnic_83xx_ms_mem_write128(adapter, addr,
1265                                                   (u32 *)data, 1);
1266                 if (ret) {
1267                         dev_err(&adapter->pdev->dev,
1268                                 "MS memory write failed\n");
1269                         release_firmware(adapter->ahw->fw_info.fw);
1270                         adapter->ahw->fw_info.fw = NULL;
1271                         return -EIO;
1272                 }
1273         }
1274         release_firmware(adapter->ahw->fw_info.fw);
1275         adapter->ahw->fw_info.fw = NULL;
1276
1277         return 0;
1278 }
1279
1280 static void qlcnic_83xx_dump_pause_control_regs(struct qlcnic_adapter *adapter)
1281 {
1282         int i, j;
1283         u32 val = 0, val1 = 0, reg = 0;
1284
1285         val = QLCRD32(adapter, QLC_83XX_SRE_SHIM_REG);
1286         dev_info(&adapter->pdev->dev, "SRE-Shim Ctrl:0x%x\n", val);
1287
1288         for (j = 0; j < 2; j++) {
1289                 if (j == 0) {
1290                         dev_info(&adapter->pdev->dev,
1291                                  "Port 0 RxB Pause Threshold Regs[TC7..TC0]:");
1292                         reg = QLC_83XX_PORT0_THRESHOLD;
1293                 } else if (j == 1) {
1294                         dev_info(&adapter->pdev->dev,
1295                                  "Port 1 RxB Pause Threshold Regs[TC7..TC0]:");
1296                         reg = QLC_83XX_PORT1_THRESHOLD;
1297                 }
1298                 for (i = 0; i < 8; i++) {
1299                         val = QLCRD32(adapter, reg + (i * 0x4));
1300                         dev_info(&adapter->pdev->dev, "0x%x  ", val);
1301                 }
1302                 dev_info(&adapter->pdev->dev, "\n");
1303         }
1304
1305         for (j = 0; j < 2; j++) {
1306                 if (j == 0) {
1307                         dev_info(&adapter->pdev->dev,
1308                                  "Port 0 RxB TC Max Cell Registers[4..1]:");
1309                         reg = QLC_83XX_PORT0_TC_MC_REG;
1310                 } else if (j == 1) {
1311                         dev_info(&adapter->pdev->dev,
1312                                  "Port 1 RxB TC Max Cell Registers[4..1]:");
1313                         reg = QLC_83XX_PORT1_TC_MC_REG;
1314                 }
1315                 for (i = 0; i < 4; i++) {
1316                         val = QLCRD32(adapter, reg + (i * 0x4));
1317                          dev_info(&adapter->pdev->dev, "0x%x  ", val);
1318                 }
1319                 dev_info(&adapter->pdev->dev, "\n");
1320         }
1321
1322         for (j = 0; j < 2; j++) {
1323                 if (j == 0) {
1324                         dev_info(&adapter->pdev->dev,
1325                                  "Port 0 RxB Rx TC Stats[TC7..TC0]:");
1326                         reg = QLC_83XX_PORT0_TC_STATS;
1327                 } else if (j == 1) {
1328                         dev_info(&adapter->pdev->dev,
1329                                  "Port 1 RxB Rx TC Stats[TC7..TC0]:");
1330                         reg = QLC_83XX_PORT1_TC_STATS;
1331                 }
1332                 for (i = 7; i >= 0; i--) {
1333                         val = QLCRD32(adapter, reg);
1334                         val &= ~(0x7 << 29);    /* Reset bits 29 to 31 */
1335                         QLCWR32(adapter, reg, (val | (i << 29)));
1336                         val = QLCRD32(adapter, reg);
1337                         dev_info(&adapter->pdev->dev, "0x%x  ", val);
1338                 }
1339                 dev_info(&adapter->pdev->dev, "\n");
1340         }
1341
1342         val = QLCRD32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD);
1343         val1 = QLCRD32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD);
1344         dev_info(&adapter->pdev->dev,
1345                  "IFB-Pause Thresholds: Port 2:0x%x, Port 3:0x%x\n",
1346                  val, val1);
1347 }
1348
1349
1350 static void qlcnic_83xx_disable_pause_frames(struct qlcnic_adapter *adapter)
1351 {
1352         u32 reg = 0, i, j;
1353
1354         if (qlcnic_83xx_lock_driver(adapter)) {
1355                 dev_err(&adapter->pdev->dev,
1356                         "%s:failed to acquire driver lock\n", __func__);
1357                 return;
1358         }
1359
1360         qlcnic_83xx_dump_pause_control_regs(adapter);
1361         QLCWR32(adapter, QLC_83XX_SRE_SHIM_REG, 0x0);
1362
1363         for (j = 0; j < 2; j++) {
1364                 if (j == 0)
1365                         reg = QLC_83XX_PORT0_THRESHOLD;
1366                 else if (j == 1)
1367                         reg = QLC_83XX_PORT1_THRESHOLD;
1368
1369                 for (i = 0; i < 8; i++)
1370                         QLCWR32(adapter, reg + (i * 0x4), 0x0);
1371         }
1372
1373         for (j = 0; j < 2; j++) {
1374                 if (j == 0)
1375                         reg = QLC_83XX_PORT0_TC_MC_REG;
1376                 else if (j == 1)
1377                         reg = QLC_83XX_PORT1_TC_MC_REG;
1378
1379                 for (i = 0; i < 4; i++)
1380                         QLCWR32(adapter, reg + (i * 0x4), 0x03FF03FF);
1381         }
1382
1383         QLCWR32(adapter, QLC_83XX_PORT2_IFB_THRESHOLD, 0);
1384         QLCWR32(adapter, QLC_83XX_PORT3_IFB_THRESHOLD, 0);
1385         dev_info(&adapter->pdev->dev,
1386                  "Disabled pause frames successfully on all ports\n");
1387         qlcnic_83xx_unlock_driver(adapter);
1388 }
1389
1390 static void qlcnic_83xx_take_eport_out_of_reset(struct qlcnic_adapter *adapter)
1391 {
1392         QLCWR32(adapter, QLC_83XX_RESET_REG, 0);
1393         QLCWR32(adapter, QLC_83XX_RESET_PORT0, 0);
1394         QLCWR32(adapter, QLC_83XX_RESET_PORT1, 0);
1395         QLCWR32(adapter, QLC_83XX_RESET_PORT2, 0);
1396         QLCWR32(adapter, QLC_83XX_RESET_PORT3, 0);
1397         QLCWR32(adapter, QLC_83XX_RESET_SRESHIM, 0);
1398         QLCWR32(adapter, QLC_83XX_RESET_EPGSHIM, 0);
1399         QLCWR32(adapter, QLC_83XX_RESET_ETHERPCS, 0);
1400         QLCWR32(adapter, QLC_83XX_RESET_CONTROL, 1);
1401 }
1402
1403 static int qlcnic_83xx_check_heartbeat(struct qlcnic_adapter *p_dev)
1404 {
1405         u32 heartbeat, peg_status;
1406         int retries, ret = -EIO;
1407
1408         retries = QLCNIC_HEARTBEAT_CHECK_RETRY_COUNT;
1409         p_dev->heartbeat = QLC_SHARED_REG_RD32(p_dev,
1410                                                QLCNIC_PEG_ALIVE_COUNTER);
1411
1412         do {
1413                 msleep(QLCNIC_HEARTBEAT_PERIOD_MSECS);
1414                 heartbeat = QLC_SHARED_REG_RD32(p_dev,
1415                                                 QLCNIC_PEG_ALIVE_COUNTER);
1416                 if (heartbeat != p_dev->heartbeat) {
1417                         ret = QLCNIC_RCODE_SUCCESS;
1418                         break;
1419                 }
1420         } while (--retries);
1421
1422         if (ret) {
1423                 dev_err(&p_dev->pdev->dev, "firmware hang detected\n");
1424                 qlcnic_83xx_take_eport_out_of_reset(p_dev);
1425                 qlcnic_83xx_disable_pause_frames(p_dev);
1426                 peg_status = QLC_SHARED_REG_RD32(p_dev,
1427                                                  QLCNIC_PEG_HALT_STATUS1);
1428                 dev_info(&p_dev->pdev->dev, "Dumping HW/FW registers\n"
1429                          "PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,\n"
1430                          "PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,\n"
1431                          "PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,\n"
1432                          "PEG_NET_4_PC: 0x%x\n", peg_status,
1433                          QLC_SHARED_REG_RD32(p_dev, QLCNIC_PEG_HALT_STATUS2),
1434                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_0),
1435                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_1),
1436                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_2),
1437                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_3),
1438                          QLCRD32(p_dev, QLC_83XX_CRB_PEG_NET_4));
1439
1440                 if (QLCNIC_FWERROR_CODE(peg_status) == 0x67)
1441                         dev_err(&p_dev->pdev->dev,
1442                                 "Device is being reset err code 0x00006700.\n");
1443         }
1444
1445         return ret;
1446 }
1447
1448 static int qlcnic_83xx_check_cmd_peg_status(struct qlcnic_adapter *p_dev)
1449 {
1450         int retries = QLCNIC_CMDPEG_CHECK_RETRY_COUNT;
1451         u32 val;
1452
1453         do {
1454                 val = QLC_SHARED_REG_RD32(p_dev, QLCNIC_CMDPEG_STATE);
1455                 if (val == QLC_83XX_CMDPEG_COMPLETE)
1456                         return 0;
1457                 msleep(QLCNIC_CMDPEG_CHECK_DELAY);
1458         } while (--retries);
1459
1460         dev_err(&p_dev->pdev->dev, "%s: failed, state = 0x%x\n", __func__, val);
1461         return -EIO;
1462 }
1463
1464 int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev)
1465 {
1466         int err;
1467
1468         err = qlcnic_83xx_check_cmd_peg_status(p_dev);
1469         if (err)
1470                 return err;
1471
1472         err = qlcnic_83xx_check_heartbeat(p_dev);
1473         if (err)
1474                 return err;
1475
1476         return err;
1477 }
1478
1479 static int qlcnic_83xx_poll_reg(struct qlcnic_adapter *p_dev, u32 addr,
1480                                 int duration, u32 mask, u32 status)
1481 {
1482         u32 value;
1483         int timeout_error;
1484         u8 retries;
1485
1486         value = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1487         retries = duration / 10;
1488
1489         do {
1490                 if ((value & mask) != status) {
1491                         timeout_error = 1;
1492                         msleep(duration / 10);
1493                         value = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1494                 } else {
1495                         timeout_error = 0;
1496                         break;
1497                 }
1498         } while (retries--);
1499
1500         if (timeout_error) {
1501                 p_dev->ahw->reset.seq_error++;
1502                 dev_err(&p_dev->pdev->dev,
1503                         "%s: Timeout Err, entry_num = %d\n",
1504                         __func__, p_dev->ahw->reset.seq_index);
1505                 dev_err(&p_dev->pdev->dev,
1506                         "0x%08x 0x%08x 0x%08x\n",
1507                         value, mask, status);
1508         }
1509
1510         return timeout_error;
1511 }
1512
1513 static int qlcnic_83xx_reset_template_checksum(struct qlcnic_adapter *p_dev)
1514 {
1515         u32 sum = 0;
1516         u16 *buff = (u16 *)p_dev->ahw->reset.buff;
1517         int count = p_dev->ahw->reset.hdr->size / sizeof(u16);
1518
1519         while (count-- > 0)
1520                 sum += *buff++;
1521
1522         while (sum >> 16)
1523                 sum = (sum & 0xFFFF) + (sum >> 16);
1524
1525         if (~sum) {
1526                 return 0;
1527         } else {
1528                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1529                 return -1;
1530         }
1531 }
1532
1533 int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *p_dev)
1534 {
1535         u8 *p_buff;
1536         u32 addr, count;
1537         struct qlcnic_hardware_context *ahw = p_dev->ahw;
1538
1539         ahw->reset.seq_error = 0;
1540         ahw->reset.buff = kzalloc(QLC_83XX_RESTART_TEMPLATE_SIZE, GFP_KERNEL);
1541         if (p_dev->ahw->reset.buff == NULL)
1542                 return -ENOMEM;
1543
1544         p_buff = p_dev->ahw->reset.buff;
1545         addr = QLC_83XX_RESET_TEMPLATE_ADDR;
1546         count = sizeof(struct qlc_83xx_reset_hdr) / sizeof(u32);
1547
1548         /* Copy template header from flash */
1549         if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1550                 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1551                 return -EIO;
1552         }
1553         ahw->reset.hdr = (struct qlc_83xx_reset_hdr *)ahw->reset.buff;
1554         addr = QLC_83XX_RESET_TEMPLATE_ADDR + ahw->reset.hdr->hdr_size;
1555         p_buff = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1556         count = (ahw->reset.hdr->size - ahw->reset.hdr->hdr_size) / sizeof(u32);
1557
1558         /* Copy rest of the template */
1559         if (qlcnic_83xx_flash_read32(p_dev, addr, p_buff, count)) {
1560                 dev_err(&p_dev->pdev->dev, "%s: flash read failed\n", __func__);
1561                 return -EIO;
1562         }
1563
1564         if (qlcnic_83xx_reset_template_checksum(p_dev))
1565                 return -EIO;
1566         /* Get Stop, Start and Init command offsets */
1567         ahw->reset.init_offset = ahw->reset.buff + ahw->reset.hdr->init_offset;
1568         ahw->reset.start_offset = ahw->reset.buff +
1569                                   ahw->reset.hdr->start_offset;
1570         ahw->reset.stop_offset = ahw->reset.buff + ahw->reset.hdr->hdr_size;
1571         return 0;
1572 }
1573
1574 /* Read Write HW register command */
1575 static void qlcnic_83xx_read_write_crb_reg(struct qlcnic_adapter *p_dev,
1576                                            u32 raddr, u32 waddr)
1577 {
1578         int value;
1579
1580         value = qlcnic_83xx_rd_reg_indirect(p_dev, raddr);
1581         qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1582 }
1583
1584 /* Read Modify Write HW register command */
1585 static void qlcnic_83xx_rmw_crb_reg(struct qlcnic_adapter *p_dev,
1586                                     u32 raddr, u32 waddr,
1587                                     struct qlc_83xx_rmw *p_rmw_hdr)
1588 {
1589         int value;
1590
1591         if (p_rmw_hdr->index_a)
1592                 value = p_dev->ahw->reset.array[p_rmw_hdr->index_a];
1593         else
1594                 value = qlcnic_83xx_rd_reg_indirect(p_dev, raddr);
1595
1596         value &= p_rmw_hdr->mask;
1597         value <<= p_rmw_hdr->shl;
1598         value >>= p_rmw_hdr->shr;
1599         value |= p_rmw_hdr->or_value;
1600         value ^= p_rmw_hdr->xor_value;
1601         qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value);
1602 }
1603
1604 /* Write HW register command */
1605 static void qlcnic_83xx_write_list(struct qlcnic_adapter *p_dev,
1606                                    struct qlc_83xx_entry_hdr *p_hdr)
1607 {
1608         int i;
1609         struct qlc_83xx_entry *entry;
1610
1611         entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1612                                           sizeof(struct qlc_83xx_entry_hdr));
1613
1614         for (i = 0; i < p_hdr->count; i++, entry++) {
1615                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->arg1,
1616                                              entry->arg2);
1617                 if (p_hdr->delay)
1618                         udelay((u32)(p_hdr->delay));
1619         }
1620 }
1621
1622 /* Read and Write instruction */
1623 static void qlcnic_83xx_read_write_list(struct qlcnic_adapter *p_dev,
1624                                         struct qlc_83xx_entry_hdr *p_hdr)
1625 {
1626         int i;
1627         struct qlc_83xx_entry *entry;
1628
1629         entry = (struct qlc_83xx_entry *)((char *)p_hdr +
1630                                           sizeof(struct qlc_83xx_entry_hdr));
1631
1632         for (i = 0; i < p_hdr->count; i++, entry++) {
1633                 qlcnic_83xx_read_write_crb_reg(p_dev, entry->arg1,
1634                                                entry->arg2);
1635                 if (p_hdr->delay)
1636                         udelay((u32)(p_hdr->delay));
1637         }
1638 }
1639
1640 /* Poll HW register command */
1641 static void qlcnic_83xx_poll_list(struct qlcnic_adapter *p_dev,
1642                                   struct qlc_83xx_entry_hdr *p_hdr)
1643 {
1644         long delay;
1645         struct qlc_83xx_entry *entry;
1646         struct qlc_83xx_poll *poll;
1647         int i;
1648         unsigned long arg1, arg2;
1649
1650         poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1651                                         sizeof(struct qlc_83xx_entry_hdr));
1652
1653         entry = (struct qlc_83xx_entry *)((char *)poll +
1654                                           sizeof(struct qlc_83xx_poll));
1655         delay = (long)p_hdr->delay;
1656
1657         if (!delay) {
1658                 for (i = 0; i < p_hdr->count; i++, entry++)
1659                         qlcnic_83xx_poll_reg(p_dev, entry->arg1,
1660                                              delay, poll->mask,
1661                                              poll->status);
1662         } else {
1663                 for (i = 0; i < p_hdr->count; i++, entry++) {
1664                         arg1 = entry->arg1;
1665                         arg2 = entry->arg2;
1666                         if (delay) {
1667                                 if (qlcnic_83xx_poll_reg(p_dev,
1668                                                          arg1, delay,
1669                                                          poll->mask,
1670                                                          poll->status)){
1671                                         qlcnic_83xx_rd_reg_indirect(p_dev,
1672                                                                     arg1);
1673                                         qlcnic_83xx_rd_reg_indirect(p_dev,
1674                                                                     arg2);
1675                                 }
1676                         }
1677                 }
1678         }
1679 }
1680
1681 /* Poll and write HW register command */
1682 static void qlcnic_83xx_poll_write_list(struct qlcnic_adapter *p_dev,
1683                                         struct qlc_83xx_entry_hdr *p_hdr)
1684 {
1685         int i;
1686         long delay;
1687         struct qlc_83xx_quad_entry *entry;
1688         struct qlc_83xx_poll *poll;
1689
1690         poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1691                                         sizeof(struct qlc_83xx_entry_hdr));
1692         entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1693                                                sizeof(struct qlc_83xx_poll));
1694         delay = (long)p_hdr->delay;
1695
1696         for (i = 0; i < p_hdr->count; i++, entry++) {
1697                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->dr_addr,
1698                                              entry->dr_value);
1699                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1700                                              entry->ar_value);
1701                 if (delay)
1702                         qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1703                                              poll->mask, poll->status);
1704         }
1705 }
1706
1707 /* Read Modify Write register command */
1708 static void qlcnic_83xx_read_modify_write(struct qlcnic_adapter *p_dev,
1709                                           struct qlc_83xx_entry_hdr *p_hdr)
1710 {
1711         int i;
1712         struct qlc_83xx_entry *entry;
1713         struct qlc_83xx_rmw *rmw_hdr;
1714
1715         rmw_hdr = (struct qlc_83xx_rmw *)((char *)p_hdr +
1716                                           sizeof(struct qlc_83xx_entry_hdr));
1717
1718         entry = (struct qlc_83xx_entry *)((char *)rmw_hdr +
1719                                           sizeof(struct qlc_83xx_rmw));
1720
1721         for (i = 0; i < p_hdr->count; i++, entry++) {
1722                 qlcnic_83xx_rmw_crb_reg(p_dev, entry->arg1,
1723                                         entry->arg2, rmw_hdr);
1724                 if (p_hdr->delay)
1725                         udelay((u32)(p_hdr->delay));
1726         }
1727 }
1728
1729 static void qlcnic_83xx_pause(struct qlc_83xx_entry_hdr *p_hdr)
1730 {
1731         if (p_hdr->delay)
1732                 mdelay((u32)((long)p_hdr->delay));
1733 }
1734
1735 /* Read and poll register command */
1736 static void qlcnic_83xx_poll_read_list(struct qlcnic_adapter *p_dev,
1737                                        struct qlc_83xx_entry_hdr *p_hdr)
1738 {
1739         long delay;
1740         int index, i, j;
1741         struct qlc_83xx_quad_entry *entry;
1742         struct qlc_83xx_poll *poll;
1743         unsigned long addr;
1744
1745         poll = (struct qlc_83xx_poll *)((char *)p_hdr +
1746                                         sizeof(struct qlc_83xx_entry_hdr));
1747
1748         entry = (struct qlc_83xx_quad_entry *)((char *)poll +
1749                                                sizeof(struct qlc_83xx_poll));
1750         delay = (long)p_hdr->delay;
1751
1752         for (i = 0; i < p_hdr->count; i++, entry++) {
1753                 qlcnic_83xx_wrt_reg_indirect(p_dev, entry->ar_addr,
1754                                              entry->ar_value);
1755                 if (delay) {
1756                         if (!qlcnic_83xx_poll_reg(p_dev, entry->ar_addr, delay,
1757                                                   poll->mask, poll->status)){
1758                                 index = p_dev->ahw->reset.array_index;
1759                                 addr = entry->dr_addr;
1760                                 j = qlcnic_83xx_rd_reg_indirect(p_dev, addr);
1761                                 p_dev->ahw->reset.array[index++] = j;
1762
1763                                 if (index == QLC_83XX_MAX_RESET_SEQ_ENTRIES)
1764                                         p_dev->ahw->reset.array_index = 1;
1765                         }
1766                 }
1767         }
1768 }
1769
1770 static inline void qlcnic_83xx_seq_end(struct qlcnic_adapter *p_dev)
1771 {
1772         p_dev->ahw->reset.seq_end = 1;
1773 }
1774
1775 static void qlcnic_83xx_template_end(struct qlcnic_adapter *p_dev)
1776 {
1777         p_dev->ahw->reset.template_end = 1;
1778         if (p_dev->ahw->reset.seq_error == 0)
1779                 dev_err(&p_dev->pdev->dev,
1780                         "HW restart process completed successfully.\n");
1781         else
1782                 dev_err(&p_dev->pdev->dev,
1783                         "HW restart completed with timeout errors.\n");
1784 }
1785
1786 /**
1787 * qlcnic_83xx_exec_template_cmd
1788 *
1789 * @p_dev: adapter structure
1790 * @p_buff: Poiter to instruction template
1791 *
1792 * Template provides instructions to stop, restart and initalize firmware.
1793 * These instructions are abstracted as a series of read, write and
1794 * poll operations on hardware registers. Register information and operation
1795 * specifics are not exposed to the driver. Driver reads the template from
1796 * flash and executes the instructions located at pre-defined offsets.
1797 *
1798 * Returns: None
1799 * */
1800 static void qlcnic_83xx_exec_template_cmd(struct qlcnic_adapter *p_dev,
1801                                           char *p_buff)
1802 {
1803         int index, entries;
1804         struct qlc_83xx_entry_hdr *p_hdr;
1805         char *entry = p_buff;
1806
1807         p_dev->ahw->reset.seq_end = 0;
1808         p_dev->ahw->reset.template_end = 0;
1809         entries = p_dev->ahw->reset.hdr->entries;
1810         index = p_dev->ahw->reset.seq_index;
1811
1812         for (; (!p_dev->ahw->reset.seq_end) && (index < entries); index++) {
1813                 p_hdr = (struct qlc_83xx_entry_hdr *)entry;
1814
1815                 switch (p_hdr->cmd) {
1816                 case QLC_83XX_OPCODE_NOP:
1817                         break;
1818                 case QLC_83XX_OPCODE_WRITE_LIST:
1819                         qlcnic_83xx_write_list(p_dev, p_hdr);
1820                         break;
1821                 case QLC_83XX_OPCODE_READ_WRITE_LIST:
1822                         qlcnic_83xx_read_write_list(p_dev, p_hdr);
1823                         break;
1824                 case QLC_83XX_OPCODE_POLL_LIST:
1825                         qlcnic_83xx_poll_list(p_dev, p_hdr);
1826                         break;
1827                 case QLC_83XX_OPCODE_POLL_WRITE_LIST:
1828                         qlcnic_83xx_poll_write_list(p_dev, p_hdr);
1829                         break;
1830                 case QLC_83XX_OPCODE_READ_MODIFY_WRITE:
1831                         qlcnic_83xx_read_modify_write(p_dev, p_hdr);
1832                         break;
1833                 case QLC_83XX_OPCODE_SEQ_PAUSE:
1834                         qlcnic_83xx_pause(p_hdr);
1835                         break;
1836                 case QLC_83XX_OPCODE_SEQ_END:
1837                         qlcnic_83xx_seq_end(p_dev);
1838                         break;
1839                 case QLC_83XX_OPCODE_TMPL_END:
1840                         qlcnic_83xx_template_end(p_dev);
1841                         break;
1842                 case QLC_83XX_OPCODE_POLL_READ_LIST:
1843                         qlcnic_83xx_poll_read_list(p_dev, p_hdr);
1844                         break;
1845                 default:
1846                         dev_err(&p_dev->pdev->dev,
1847                                 "%s: Unknown opcode 0x%04x in template %d\n",
1848                                 __func__, p_hdr->cmd, index);
1849                         break;
1850                 }
1851                 entry += p_hdr->size;
1852         }
1853         p_dev->ahw->reset.seq_index = index;
1854 }
1855
1856 static void qlcnic_83xx_stop_hw(struct qlcnic_adapter *p_dev)
1857 {
1858         p_dev->ahw->reset.seq_index = 0;
1859
1860         qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.stop_offset);
1861         if (p_dev->ahw->reset.seq_end != 1)
1862                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1863 }
1864
1865 static void qlcnic_83xx_start_hw(struct qlcnic_adapter *p_dev)
1866 {
1867         qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.start_offset);
1868         if (p_dev->ahw->reset.template_end != 1)
1869                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1870 }
1871
1872 static void qlcnic_83xx_init_hw(struct qlcnic_adapter *p_dev)
1873 {
1874         qlcnic_83xx_exec_template_cmd(p_dev, p_dev->ahw->reset.init_offset);
1875         if (p_dev->ahw->reset.seq_end != 1)
1876                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
1877 }
1878
1879 static int qlcnic_83xx_load_fw_image_from_host(struct qlcnic_adapter *adapter)
1880 {
1881         int err = -EIO;
1882
1883         if (reject_firmware(&adapter->ahw->fw_info.fw,
1884                              QLC_83XX_FW_FILE_NAME, &(adapter->pdev->dev))) {
1885                 dev_err(&adapter->pdev->dev,
1886                         "No file FW image, loading flash FW image.\n");
1887                 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1888                                     QLC_83XX_BOOT_FROM_FLASH);
1889         } else {
1890                 if (qlcnic_83xx_copy_fw_file(adapter))
1891                         return err;
1892                 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1893                                     QLC_83XX_BOOT_FROM_FILE);
1894         }
1895
1896         return 0;
1897 }
1898
1899 static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter)
1900 {
1901         u32 val;
1902         int err = -EIO;
1903
1904         qlcnic_83xx_stop_hw(adapter);
1905
1906         /* Collect FW register dump if required */
1907         val = QLCRDX(adapter->ahw, QLC_83XX_IDC_CTRL);
1908         if (!(val & QLC_83XX_IDC_GRACEFULL_RESET))
1909                 qlcnic_dump_fw(adapter);
1910         qlcnic_83xx_init_hw(adapter);
1911
1912         if (qlcnic_83xx_copy_bootloader(adapter))
1913                 return err;
1914         /* Boot either flash image or firmware image from host file system */
1915         if (qlcnic_load_fw_file) {
1916                 if (qlcnic_83xx_load_fw_image_from_host(adapter))
1917                         return err;
1918         } else {
1919                 QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
1920                                     QLC_83XX_BOOT_FROM_FLASH);
1921         }
1922
1923         qlcnic_83xx_start_hw(adapter);
1924         if (qlcnic_83xx_check_hw_status(adapter))
1925                 return -EIO;
1926
1927         return 0;
1928 }
1929
1930 /**
1931 * qlcnic_83xx_config_default_opmode
1932 *
1933 * @adapter: adapter structure
1934 *
1935 * Configure default driver operating mode
1936 *
1937 * Returns: Error code or Success(0)
1938 * */
1939 int qlcnic_83xx_config_default_opmode(struct qlcnic_adapter *adapter)
1940 {
1941         u32 op_mode;
1942         struct qlcnic_hardware_context *ahw = adapter->ahw;
1943
1944         qlcnic_get_func_no(adapter);
1945         op_mode = QLCRDX(ahw, QLC_83XX_DRV_OP_MODE);
1946
1947         if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state))
1948                 op_mode = QLC_83XX_DEFAULT_OPMODE;
1949
1950         if (op_mode == QLC_83XX_DEFAULT_OPMODE) {
1951                 adapter->nic_ops->init_driver = qlcnic_83xx_init_default_driver;
1952                 ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry;
1953         } else {
1954                 return -EIO;
1955         }
1956
1957         return 0;
1958 }
1959
1960 int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *adapter)
1961 {
1962         int err;
1963         struct qlcnic_info nic_info;
1964         struct qlcnic_hardware_context *ahw = adapter->ahw;
1965
1966         memset(&nic_info, 0, sizeof(struct qlcnic_info));
1967         err = qlcnic_get_nic_info(adapter, &nic_info, ahw->pci_func);
1968         if (err)
1969                 return -EIO;
1970
1971         ahw->physical_port = (u8) nic_info.phys_port;
1972         ahw->switch_mode = nic_info.switch_mode;
1973         ahw->max_tx_ques = nic_info.max_tx_ques;
1974         ahw->max_rx_ques = nic_info.max_rx_ques;
1975         ahw->capabilities = nic_info.capabilities;
1976         ahw->max_mac_filters = nic_info.max_mac_filters;
1977         ahw->max_mtu = nic_info.max_mtu;
1978
1979         /* VNIC mode is detected by BIT_23 in capabilities. This bit is also
1980          * set in case device is SRIOV capable. VNIC and SRIOV are mutually
1981          * exclusive. So in case of sriov capable device load driver in
1982          * default mode
1983          */
1984         if (test_bit(__QLCNIC_SRIOV_CAPABLE, &adapter->state)) {
1985                 ahw->nic_mode = QLC_83XX_DEFAULT_MODE;
1986                 return ahw->nic_mode;
1987         }
1988
1989         if (ahw->capabilities & BIT_23)
1990                 ahw->nic_mode = QLC_83XX_VIRTUAL_NIC_MODE;
1991         else
1992                 ahw->nic_mode = QLC_83XX_DEFAULT_MODE;
1993
1994         return ahw->nic_mode;
1995 }
1996
1997 int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter)
1998 {
1999         int ret;
2000
2001         ret = qlcnic_83xx_get_nic_configuration(adapter);
2002         if (ret == -EIO)
2003                 return -EIO;
2004
2005         if (ret == QLC_83XX_VIRTUAL_NIC_MODE) {
2006                 if (qlcnic_83xx_config_vnic_opmode(adapter))
2007                         return -EIO;
2008         } else if (ret == QLC_83XX_DEFAULT_MODE) {
2009                 if (qlcnic_83xx_config_default_opmode(adapter))
2010                         return -EIO;
2011         }
2012
2013         return 0;
2014 }
2015
2016 static void qlcnic_83xx_config_buff_descriptors(struct qlcnic_adapter *adapter)
2017 {
2018         struct qlcnic_hardware_context *ahw = adapter->ahw;
2019
2020         if (ahw->port_type == QLCNIC_XGBE) {
2021                 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_10G;
2022                 adapter->max_rxd = MAX_RCV_DESCRIPTORS_10G;
2023                 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
2024                 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_10G;
2025
2026         } else if (ahw->port_type == QLCNIC_GBE) {
2027                 adapter->num_rxd = DEFAULT_RCV_DESCRIPTORS_1G;
2028                 adapter->num_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2029                 adapter->max_jumbo_rxd = MAX_JUMBO_RCV_DESCRIPTORS_1G;
2030                 adapter->max_rxd = MAX_RCV_DESCRIPTORS_1G;
2031         }
2032         adapter->num_txd = MAX_CMD_DESCRIPTORS;
2033         adapter->max_rds_rings = MAX_RDS_RINGS;
2034 }
2035
2036 static int qlcnic_83xx_init_default_driver(struct qlcnic_adapter *adapter)
2037 {
2038         int err = -EIO;
2039
2040         qlcnic_83xx_get_minidump_template(adapter);
2041         if (qlcnic_83xx_get_port_info(adapter))
2042                 return err;
2043
2044         qlcnic_83xx_config_buff_descriptors(adapter);
2045         adapter->ahw->msix_supported = !!qlcnic_use_msi_x;
2046         adapter->flags |= QLCNIC_ADAPTER_INITIALIZED;
2047
2048         dev_info(&adapter->pdev->dev, "HAL Version: %d\n",
2049                  adapter->ahw->fw_hal_version);
2050
2051         return 0;
2052 }
2053
2054 #define IS_QLC_83XX_USED(a, b, c) (((1 << a->portnum) & b) || ((c >> 6) & 0x1))
2055 static void qlcnic_83xx_clear_function_resources(struct qlcnic_adapter *adapter)
2056 {
2057         struct qlcnic_cmd_args cmd;
2058         u32 presence_mask, audit_mask;
2059         int status;
2060
2061         presence_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_PRESENCE);
2062         audit_mask = QLCRDX(adapter->ahw, QLC_83XX_IDC_DRV_AUDIT);
2063
2064         if (IS_QLC_83XX_USED(adapter, presence_mask, audit_mask)) {
2065                 qlcnic_alloc_mbx_args(&cmd, adapter, QLCNIC_CMD_STOP_NIC_FUNC);
2066                 cmd.req.arg[1] = BIT_31;
2067                 status = qlcnic_issue_cmd(adapter, &cmd);
2068                 if (status)
2069                         dev_err(&adapter->pdev->dev,
2070                                 "Failed to clean up the function resources\n");
2071                 qlcnic_free_mbx_args(&cmd);
2072         }
2073 }
2074
2075 int qlcnic_83xx_init(struct qlcnic_adapter *adapter, int pci_using_dac)
2076 {
2077         struct qlcnic_hardware_context *ahw = adapter->ahw;
2078
2079         if (qlcnic_sriov_vf_check(adapter))
2080                 return qlcnic_sriov_vf_init(adapter, pci_using_dac);
2081
2082         if (qlcnic_83xx_check_hw_status(adapter))
2083                 return -EIO;
2084
2085         /* Initilaize 83xx mailbox spinlock */
2086         spin_lock_init(&ahw->mbx_lock);
2087
2088         set_bit(QLC_83XX_MBX_READY, &adapter->ahw->idc.status);
2089         qlcnic_83xx_clear_function_resources(adapter);
2090
2091         /* register for NIC IDC AEN Events */
2092         qlcnic_83xx_register_nic_idc_func(adapter, 1);
2093
2094         if (!qlcnic_83xx_read_flash_descriptor_table(adapter))
2095                 qlcnic_83xx_read_flash_mfg_id(adapter);
2096
2097         if (qlcnic_83xx_idc_init(adapter))
2098                 return -EIO;
2099
2100         /* Configure default, SR-IOV or Virtual NIC mode of operation */
2101         if (qlcnic_83xx_configure_opmode(adapter))
2102                 return -EIO;
2103
2104         /* Perform operating mode specific initialization */
2105         if (adapter->nic_ops->init_driver(adapter))
2106                 return -EIO;
2107
2108         INIT_DELAYED_WORK(&adapter->idc_aen_work, qlcnic_83xx_idc_aen_work);
2109
2110         /* Periodically monitor device status */
2111         qlcnic_83xx_idc_poll_dev_state(&adapter->fw_work.work);
2112
2113         return adapter->ahw->idc.err_code;
2114 }