2 * Copyright (C) 2015-2017 Netronome Systems, Inc.
4 * This software is dual licensed under the GNU General License Version 2,
5 * June 1991 as shown in the file COPYING in the top-level directory of this
6 * source tree or the BSD 2-Clause License provided below. You have the
7 * option to license this software under the complete terms of either license.
9 * The BSD 2-Clause License:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * 1. Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * 2. Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 * Definitions for ARM-based registers and memory spaces
42 #define NFP_ARM_QUEUE(_q) (0x100000 + (0x800 * ((_q) & 0xff)))
43 #define NFP_ARM_IM 0x200000
44 #define NFP_ARM_EM 0x300000
45 #define NFP_ARM_GCSR 0x400000
46 #define NFP_ARM_MPCORE 0x800000
47 #define NFP_ARM_PL310 0xa00000
48 /* Register Type: BulkBARConfig */
49 #define NFP_ARM_GCSR_BULK_BAR(_bar) (0x0 + (0x4 * ((_bar) & 0x7)))
50 #define NFP_ARM_GCSR_BULK_BAR_TYPE (0x1 << 31)
51 #define NFP_ARM_GCSR_BULK_BAR_TYPE_BULK (0x0)
52 #define NFP_ARM_GCSR_BULK_BAR_TYPE_EXPA (0x80000000)
53 #define NFP_ARM_GCSR_BULK_BAR_TGT(_x) (((_x) & 0xf) << 27)
54 #define NFP_ARM_GCSR_BULK_BAR_TGT_of(_x) (((_x) >> 27) & 0xf)
55 #define NFP_ARM_GCSR_BULK_BAR_TOK(_x) (((_x) & 0x3) << 25)
56 #define NFP_ARM_GCSR_BULK_BAR_TOK_of(_x) (((_x) >> 25) & 0x3)
57 #define NFP_ARM_GCSR_BULK_BAR_LEN (0x1 << 24)
58 #define NFP_ARM_GCSR_BULK_BAR_LEN_32BIT (0x0)
59 #define NFP_ARM_GCSR_BULK_BAR_LEN_64BIT (0x1000000)
60 #define NFP_ARM_GCSR_BULK_BAR_ADDR(_x) ((_x) & 0x7ff)
61 #define NFP_ARM_GCSR_BULK_BAR_ADDR_of(_x) ((_x) & 0x7ff)
62 /* Register Type: ExpansionBARConfig */
63 #define NFP_ARM_GCSR_EXPA_BAR(_bar) (0x20 + (0x4 * ((_bar) & 0xf)))
64 #define NFP_ARM_GCSR_EXPA_BAR_TYPE (0x1 << 31)
65 #define NFP_ARM_GCSR_EXPA_BAR_TYPE_EXPA (0x0)
66 #define NFP_ARM_GCSR_EXPA_BAR_TYPE_EXPL (0x80000000)
67 #define NFP_ARM_GCSR_EXPA_BAR_TGT(_x) (((_x) & 0xf) << 27)
68 #define NFP_ARM_GCSR_EXPA_BAR_TGT_of(_x) (((_x) >> 27) & 0xf)
69 #define NFP_ARM_GCSR_EXPA_BAR_TOK(_x) (((_x) & 0x3) << 25)
70 #define NFP_ARM_GCSR_EXPA_BAR_TOK_of(_x) (((_x) >> 25) & 0x3)
71 #define NFP_ARM_GCSR_EXPA_BAR_LEN (0x1 << 24)
72 #define NFP_ARM_GCSR_EXPA_BAR_LEN_32BIT (0x0)
73 #define NFP_ARM_GCSR_EXPA_BAR_LEN_64BIT (0x1000000)
74 #define NFP_ARM_GCSR_EXPA_BAR_ACT(_x) (((_x) & 0x1f) << 19)
75 #define NFP_ARM_GCSR_EXPA_BAR_ACT_of(_x) (((_x) >> 19) & 0x1f)
76 #define NFP_ARM_GCSR_EXPA_BAR_ACT_DERIVED (0)
77 #define NFP_ARM_GCSR_EXPA_BAR_ADDR(_x) ((_x) & 0x7fff)
78 #define NFP_ARM_GCSR_EXPA_BAR_ADDR_of(_x) ((_x) & 0x7fff)
79 /* Register Type: ExplicitBARConfig0_Reg */
80 #define NFP_ARM_GCSR_EXPL0_BAR(_bar) (0x60 + (0x4 * ((_bar) & 0x7)))
81 #define NFP_ARM_GCSR_EXPL0_BAR_ADDR(_x) ((_x) & 0x3ffff)
82 #define NFP_ARM_GCSR_EXPL0_BAR_ADDR_of(_x) ((_x) & 0x3ffff)
83 /* Register Type: ExplicitBARConfig1_Reg */
84 #define NFP_ARM_GCSR_EXPL1_BAR(_bar) (0x80 + (0x4 * ((_bar) & 0x7)))
85 #define NFP_ARM_GCSR_EXPL1_BAR_POSTED (0x1 << 31)
86 #define NFP_ARM_GCSR_EXPL1_BAR_SIGNAL_REF(_x) (((_x) & 0x7f) << 24)
87 #define NFP_ARM_GCSR_EXPL1_BAR_SIGNAL_REF_of(_x) (((_x) >> 24) & 0x7f)
88 #define NFP_ARM_GCSR_EXPL1_BAR_DATA_MASTER(_x) (((_x) & 0xff) << 16)
89 #define NFP_ARM_GCSR_EXPL1_BAR_DATA_MASTER_of(_x) (((_x) >> 16) & 0xff)
90 #define NFP_ARM_GCSR_EXPL1_BAR_DATA_REF(_x) ((_x) & 0x3fff)
91 #define NFP_ARM_GCSR_EXPL1_BAR_DATA_REF_of(_x) ((_x) & 0x3fff)
92 /* Register Type: ExplicitBARConfig2_Reg */
93 #define NFP_ARM_GCSR_EXPL2_BAR(_bar) (0xa0 + (0x4 * ((_bar) & 0x7)))
94 #define NFP_ARM_GCSR_EXPL2_BAR_TGT(_x) (((_x) & 0xf) << 28)
95 #define NFP_ARM_GCSR_EXPL2_BAR_TGT_of(_x) (((_x) >> 28) & 0xf)
96 #define NFP_ARM_GCSR_EXPL2_BAR_ACT(_x) (((_x) & 0x1f) << 23)
97 #define NFP_ARM_GCSR_EXPL2_BAR_ACT_of(_x) (((_x) >> 23) & 0x1f)
98 #define NFP_ARM_GCSR_EXPL2_BAR_LEN(_x) (((_x) & 0x1f) << 18)
99 #define NFP_ARM_GCSR_EXPL2_BAR_LEN_of(_x) (((_x) >> 18) & 0x1f)
100 #define NFP_ARM_GCSR_EXPL2_BAR_BYTE_MASK(_x) (((_x) & 0xff) << 10)
101 #define NFP_ARM_GCSR_EXPL2_BAR_BYTE_MASK_of(_x) (((_x) >> 10) & 0xff)
102 #define NFP_ARM_GCSR_EXPL2_BAR_TOK(_x) (((_x) & 0x3) << 8)
103 #define NFP_ARM_GCSR_EXPL2_BAR_TOK_of(_x) (((_x) >> 8) & 0x3)
104 #define NFP_ARM_GCSR_EXPL2_BAR_SIGNAL_MASTER(_x) ((_x) & 0xff)
105 #define NFP_ARM_GCSR_EXPL2_BAR_SIGNAL_MASTER_of(_x) ((_x) & 0xff)
106 /* Register Type: PostedCommandSignal */
107 #define NFP_ARM_GCSR_EXPL_POST(_bar) (0xc0 + (0x4 * ((_bar) & 0x7)))
108 #define NFP_ARM_GCSR_EXPL_POST_SIG_B(_x) (((_x) & 0x7f) << 25)
109 #define NFP_ARM_GCSR_EXPL_POST_SIG_B_of(_x) (((_x) >> 25) & 0x7f)
110 #define NFP_ARM_GCSR_EXPL_POST_SIG_B_BUS (0x1 << 24)
111 #define NFP_ARM_GCSR_EXPL_POST_SIG_B_BUS_PULL (0x0)
112 #define NFP_ARM_GCSR_EXPL_POST_SIG_B_BUS_PUSH (0x1000000)
113 #define NFP_ARM_GCSR_EXPL_POST_SIG_A(_x) (((_x) & 0x7f) << 17)
114 #define NFP_ARM_GCSR_EXPL_POST_SIG_A_of(_x) (((_x) >> 17) & 0x7f)
115 #define NFP_ARM_GCSR_EXPL_POST_SIG_A_BUS (0x1 << 16)
116 #define NFP_ARM_GCSR_EXPL_POST_SIG_A_BUS_PULL (0x0)
117 #define NFP_ARM_GCSR_EXPL_POST_SIG_A_BUS_PUSH (0x10000)
118 #define NFP_ARM_GCSR_EXPL_POST_SIG_B_RCVD (0x1 << 7)
119 #define NFP_ARM_GCSR_EXPL_POST_SIG_B_VALID (0x1 << 6)
120 #define NFP_ARM_GCSR_EXPL_POST_SIG_A_RCVD (0x1 << 5)
121 #define NFP_ARM_GCSR_EXPL_POST_SIG_A_VALID (0x1 << 4)
122 #define NFP_ARM_GCSR_EXPL_POST_CMD_COMPLETE (0x1)
123 /* Register Type: MPCoreBaseAddress */
124 #define NFP_ARM_GCSR_MPCORE_BASE 0x00e0
125 #define NFP_ARM_GCSR_MPCORE_BASE_ADDR(_x) (((_x) & 0x7ffff) << 13)
126 #define NFP_ARM_GCSR_MPCORE_BASE_ADDR_of(_x) (((_x) >> 13) & 0x7ffff)
127 /* Register Type: PL310BaseAddress */
128 #define NFP_ARM_GCSR_PL310_BASE 0x00e4
129 #define NFP_ARM_GCSR_PL310_BASE_ADDR(_x) (((_x) & 0xfffff) << 12)
130 #define NFP_ARM_GCSR_PL310_BASE_ADDR_of(_x) (((_x) >> 12) & 0xfffff)
131 /* Register Type: MPCoreConfig */
132 #define NFP_ARM_GCSR_MP0_CFG 0x00e8
133 #define NFP_ARM_GCSR_MP0_CFG_SPI_BOOT (0x1 << 14)
134 #define NFP_ARM_GCSR_MP0_CFG_ENDIAN(_x) (((_x) & 0x3) << 12)
135 #define NFP_ARM_GCSR_MP0_CFG_ENDIAN_of(_x) (((_x) >> 12) & 0x3)
136 #define NFP_ARM_GCSR_MP0_CFG_ENDIAN_LITTLE (0)
137 #define NFP_ARM_GCSR_MP0_CFG_ENDIAN_BIG (1)
138 #define NFP_ARM_GCSR_MP0_CFG_RESET_VECTOR (0x1 << 8)
139 #define NFP_ARM_GCSR_MP0_CFG_RESET_VECTOR_LO (0x0)
140 #define NFP_ARM_GCSR_MP0_CFG_RESET_VECTOR_HI (0x100)
141 #define NFP_ARM_GCSR_MP0_CFG_OUTCLK_EN(_x) (((_x) & 0xf) << 4)
142 #define NFP_ARM_GCSR_MP0_CFG_OUTCLK_EN_of(_x) (((_x) >> 4) & 0xf)
143 #define NFP_ARM_GCSR_MP0_CFG_ARMID(_x) ((_x) & 0xf)
144 #define NFP_ARM_GCSR_MP0_CFG_ARMID_of(_x) ((_x) & 0xf)
145 /* Register Type: MPCoreIDCacheDataError */
146 #define NFP_ARM_GCSR_MP0_CACHE_ERR 0x00ec
147 #define NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_D7 (0x1 << 15)
148 #define NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_D6 (0x1 << 14)
149 #define NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_D5 (0x1 << 13)
150 #define NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_D4 (0x1 << 12)
151 #define NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_D3 (0x1 << 11)
152 #define NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_D2 (0x1 << 10)
153 #define NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_D1 (0x1 << 9)
154 #define NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_D0 (0x1 << 8)
155 #define NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_I7 (0x1 << 7)
156 #define NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_I6 (0x1 << 6)
157 #define NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_I5 (0x1 << 5)
158 #define NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_I4 (0x1 << 4)
159 #define NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_I3 (0x1 << 3)
160 #define NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_I2 (0x1 << 2)
161 #define NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_I1 (0x1 << 1)
162 #define NFP_ARM_GCSR_MP0_CACHE_ERR_MP0_I0 (0x1)
163 /* Register Type: ARMDFT */
164 #define NFP_ARM_GCSR_DFT 0x0100
165 #define NFP_ARM_GCSR_DFT_DBG_REQ (0x1 << 20)
166 #define NFP_ARM_GCSR_DFT_DBG_EN (0x1 << 19)
167 #define NFP_ARM_GCSR_DFT_WFE_EVT_TRG (0x1 << 18)
168 #define NFP_ARM_GCSR_DFT_ETM_WFI_RDY (0x1 << 17)
169 #define NFP_ARM_GCSR_DFT_ETM_PWR_ON (0x1 << 16)
170 #define NFP_ARM_GCSR_DFT_BIST_FAIL_of(_x) (((_x) >> 8) & 0xf)
171 #define NFP_ARM_GCSR_DFT_BIST_DONE_of(_x) (((_x) >> 4) & 0xf)
172 #define NFP_ARM_GCSR_DFT_BIST_RUN(_x) ((_x) & 0x7)
173 #define NFP_ARM_GCSR_DFT_BIST_RUN_of(_x) ((_x) & 0x7)
176 /* NOTE: These cannot be remapped, and are always at this location.
178 #define NFP_ARM_GCSR_START (0xd6000000 + NFP_ARM_GCSR)
179 #define NFP_ARM_GCSR_SIZE SZ_64K
183 #define NFP_ARM_GCSR_BULK_BITS 11
184 #define NFP_ARM_GCSR_EXPA_BITS 15
185 #define NFP_ARM_GCSR_EXPL_BITS 18
187 #define NFP_ARM_GCSR_BULK_SHIFT (40 - 11)
188 #define NFP_ARM_GCSR_EXPA_SHIFT (40 - 15)
189 #define NFP_ARM_GCSR_EXPL_SHIFT (40 - 18)
191 #define NFP_ARM_GCSR_BULK_SIZE (1 << NFP_ARM_GCSR_BULK_SHIFT)
192 #define NFP_ARM_GCSR_EXPA_SIZE (1 << NFP_ARM_GCSR_EXPA_SHIFT)
193 #define NFP_ARM_GCSR_EXPL_SIZE (1 << NFP_ARM_GCSR_EXPL_SHIFT)
195 #define NFP_ARM_GCSR_EXPL2_CSR(target, action, length, \
196 byte_mask, token, signal_master) \
197 (NFP_ARM_GCSR_EXPL2_BAR_TGT(target) | \
198 NFP_ARM_GCSR_EXPL2_BAR_ACT(action) | \
199 NFP_ARM_GCSR_EXPL2_BAR_LEN(length) | \
200 NFP_ARM_GCSR_EXPL2_BAR_BYTE_MASK(byte_mask) | \
201 NFP_ARM_GCSR_EXPL2_BAR_TOK(token) | \
202 NFP_ARM_GCSR_EXPL2_BAR_SIGNAL_MASTER(signal_master))
203 #define NFP_ARM_GCSR_EXPL1_CSR(posted, signal_ref, data_master, data_ref) \
204 (((posted) ? NFP_ARM_GCSR_EXPL1_BAR_POSTED : 0) | \
205 NFP_ARM_GCSR_EXPL1_BAR_SIGNAL_REF(signal_ref) | \
206 NFP_ARM_GCSR_EXPL1_BAR_DATA_MASTER(data_master) | \
207 NFP_ARM_GCSR_EXPL1_BAR_DATA_REF(data_ref))
208 #define NFP_ARM_GCSR_EXPL0_CSR(address) \
209 NFP_ARM_GCSR_EXPL0_BAR_ADDR((address) >> NFP_ARM_GCSR_EXPL_SHIFT)
210 #define NFP_ARM_GCSR_EXPL_POST_EXPECT_A(sig_ref, is_push, is_required) \
211 (NFP_ARM_GCSR_EXPL_POST_SIG_A(sig_ref) | \
212 ((is_push) ? NFP_ARM_GCSR_EXPL_POST_SIG_A_BUS_PUSH : \
213 NFP_ARM_GCSR_EXPL_POST_SIG_A_BUS_PULL) | \
214 ((is_required) ? NFP_ARM_GCSR_EXPL_POST_SIG_A_VALID : 0))
215 #define NFP_ARM_GCSR_EXPL_POST_EXPECT_B(sig_ref, is_push, is_required) \
216 (NFP_ARM_GCSR_EXPL_POST_SIG_B(sig_ref) | \
217 ((is_push) ? NFP_ARM_GCSR_EXPL_POST_SIG_B_BUS_PUSH : \
218 NFP_ARM_GCSR_EXPL_POST_SIG_B_BUS_PULL) | \
219 ((is_required) ? NFP_ARM_GCSR_EXPL_POST_SIG_B_VALID : 0))
221 #define NFP_ARM_GCSR_EXPA_CSR(mode, target, token, is_64, action, address) \
222 (((mode) ? NFP_ARM_GCSR_EXPA_BAR_TYPE_EXPL : \
223 NFP_ARM_GCSR_EXPA_BAR_TYPE_EXPA) | \
224 NFP_ARM_GCSR_EXPA_BAR_TGT(target) | \
225 NFP_ARM_GCSR_EXPA_BAR_TOK(token) | \
226 ((is_64) ? NFP_ARM_GCSR_EXPA_BAR_LEN_64BIT : \
227 NFP_ARM_GCSR_EXPA_BAR_LEN_32BIT) | \
228 NFP_ARM_GCSR_EXPA_BAR_ACT(action) | \
229 NFP_ARM_GCSR_EXPA_BAR_ADDR((address) >> NFP_ARM_GCSR_EXPA_SHIFT))
231 #define NFP_ARM_GCSR_BULK_CSR(mode, target, token, is_64, address) \
232 (((mode) ? NFP_ARM_GCSR_BULK_BAR_TYPE_EXPA : \
233 NFP_ARM_GCSR_BULK_BAR_TYPE_BULK) | \
234 NFP_ARM_GCSR_BULK_BAR_TGT(target) | \
235 NFP_ARM_GCSR_BULK_BAR_TOK(token) | \
236 ((is_64) ? NFP_ARM_GCSR_BULK_BAR_LEN_64BIT : \
237 NFP_ARM_GCSR_BULK_BAR_LEN_32BIT) | \
238 NFP_ARM_GCSR_BULK_BAR_ADDR((address) >> NFP_ARM_GCSR_BULK_SHIFT))
241 #define NFP_ARM_MPCORE_SIZE SZ_128K
244 #define NFP_ARM_PCSR_SIZE SZ_64K
246 #endif /* NFP_ARM_H */