drivers/net/ethernet/mellanox/mlxsw/spectrum.c

   1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
   2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
   3
   4 #include <linux/kernel.h>
   5 #include <linux/module.h>
   6 #include <linux/types.h>
   7 #include <linux/pci.h>
   8 #include <linux/netdevice.h>
   9 #include <linux/etherdevice.h>
  10 #include <linux/ethtool.h>
  11 #include <linux/slab.h>
  12 #include <linux/device.h>
  13 #include <linux/skbuff.h>
  14 #include <linux/if_vlan.h>
  15 #include <linux/if_bridge.h>
  16 #include <linux/workqueue.h>
  17 #include <linux/jiffies.h>
  18 #include <linux/bitops.h>
  19 #include <linux/list.h>
  20 #include <linux/notifier.h>
  21 #include <linux/dcbnl.h>
  22 #include <linux/inetdevice.h>
  23 #include <linux/netlink.h>
  24 #include <linux/jhash.h>
  25 #include <net/switchdev.h>
  26 #include <net/pkt_cls.h>
  27 #include <net/tc_act/tc_mirred.h>
  28 #include <net/netevent.h>
  29 #include <net/tc_act/tc_sample.h>
  30 #include <net/addrconf.h>
  31
  32 #include "spectrum.h"
  33 #include "pci.h"
  34 #include "core.h"
  35 #include "core_env.h"
  36 #include "reg.h"
  37 #include "port.h"
  38 #include "trap.h"
  39 #include "txheader.h"
  40 #include "spectrum_cnt.h"
  41 #include "spectrum_dpipe.h"
  42 #include "spectrum_acl_flex_actions.h"
  43 #include "spectrum_span.h"
  44 #include "spectrum_ptp.h"
  45 #include "../mlxfw/mlxfw.h"
  46
  47 #define MLXSW_SP_FWREV_MINOR_TO_BRANCH(minor) ((minor) / 100)
  48
  49 #define MLXSW_SP1_FWREV_MAJOR 13
  50 #define MLXSW_SP1_FWREV_MINOR 2000
  51 #define MLXSW_SP1_FWREV_SUBMINOR 1886
  52 #define MLXSW_SP1_FWREV_CAN_RESET_MINOR 1702
  53
  54 static const struct mlxsw_fw_rev mlxsw_sp1_fw_rev = {
  55         .major = MLXSW_SP1_FWREV_MAJOR,
  56         .minor = MLXSW_SP1_FWREV_MINOR,
  57         .subminor = MLXSW_SP1_FWREV_SUBMINOR,
  58         .can_reset_minor = MLXSW_SP1_FWREV_CAN_RESET_MINOR,
  59 };
  60
  61 #define MLXSW_SP1_FW_FILENAME \
  62         "/*(DEBLOBBED)*/"
  63
  64 static const char mlxsw_sp1_driver_name[] = "mlxsw_spectrum";
  65 static const char mlxsw_sp2_driver_name[] = "mlxsw_spectrum2";
  66 static const char mlxsw_sp3_driver_name[] = "mlxsw_spectrum3";
  67 static const char mlxsw_sp_driver_version[] = "1.0";
  68
  69 static const unsigned char mlxsw_sp1_mac_mask[ETH_ALEN] = {
  70         0xff, 0xff, 0xff, 0xff, 0xfc, 0x00
  71 };
  72 static const unsigned char mlxsw_sp2_mac_mask[ETH_ALEN] = {
  73         0xff, 0xff, 0xff, 0xff, 0xf0, 0x00
  74 };
  75
  76 /* tx_hdr_version
  77  * Tx header version.
  78  * Must be set to 1.
  79  */
  80 MLXSW_ITEM32(tx, hdr, version, 0x00, 28, 4);
  81
  82 /* tx_hdr_ctl
  83  * Packet control type.
  84  * 0 - Ethernet control (e.g. EMADs, LACP)
  85  * 1 - Ethernet data
  86  */
  87 MLXSW_ITEM32(tx, hdr, ctl, 0x00, 26, 2);
  88
  89 /* tx_hdr_proto
  90  * Packet protocol type. Must be set to 1 (Ethernet).
  91  */
  92 MLXSW_ITEM32(tx, hdr, proto, 0x00, 21, 3);
  93
  94 /* tx_hdr_rx_is_router
  95  * Packet is sent from the router. Valid for data packets only.
  96  */
  97 MLXSW_ITEM32(tx, hdr, rx_is_router, 0x00, 19, 1);
  98
  99 /* tx_hdr_fid_valid
 100  * Indicates if the 'fid' field is valid and should be used for
 101  * forwarding lookup. Valid for data packets only.
 102  */
 103 MLXSW_ITEM32(tx, hdr, fid_valid, 0x00, 16, 1);
 104
 105 /* tx_hdr_swid
 106  * Switch partition ID. Must be set to 0.
 107  */
 108 MLXSW_ITEM32(tx, hdr, swid, 0x00, 12, 3);
 109
 110 /* tx_hdr_control_tclass
 111  * Indicates if the packet should use the control TClass and not one
 112  * of the data TClasses.
 113  */
 114 MLXSW_ITEM32(tx, hdr, control_tclass, 0x00, 6, 1);
 115
 116 /* tx_hdr_etclass
 117  * Egress TClass to be used on the egress device on the egress port.
 118  */
 119 MLXSW_ITEM32(tx, hdr, etclass, 0x00, 0, 4);
 120
 121 /* tx_hdr_port_mid
 122  * Destination local port for unicast packets.
 123  * Destination multicast ID for multicast packets.
 124  *
 125  * Control packets are directed to a specific egress port, while data
 126  * packets are transmitted through the CPU port (0) into the switch partition,
 127  * where forwarding rules are applied.
 128  */
 129 MLXSW_ITEM32(tx, hdr, port_mid, 0x04, 16, 16);
 130
 131 /* tx_hdr_fid
 132  * Forwarding ID used for L2 forwarding lookup. Valid only if 'fid_valid' is
 133  * set, otherwise calculated based on the packet's VID using VID to FID mapping.
 134  * Valid for data packets only.
 135  */
 136 MLXSW_ITEM32(tx, hdr, fid, 0x08, 0, 16);
 137
 138 /* tx_hdr_type
 139  * 0 - Data packets
 140  * 6 - Control packets
 141  */
 142 MLXSW_ITEM32(tx, hdr, type, 0x0C, 0, 4);
 143
 144 struct mlxsw_sp_mlxfw_dev {
 145         struct mlxfw_dev mlxfw_dev;
 146         struct mlxsw_sp *mlxsw_sp;
 147 };
 148
 149 struct mlxsw_sp_ptp_ops {
 150         struct mlxsw_sp_ptp_clock *
 151                 (*clock_init)(struct mlxsw_sp *mlxsw_sp, struct device *dev);
 152         void (*clock_fini)(struct mlxsw_sp_ptp_clock *clock);
 153
 154         struct mlxsw_sp_ptp_state *(*init)(struct mlxsw_sp *mlxsw_sp);
 155         void (*fini)(struct mlxsw_sp_ptp_state *ptp_state);
 156
 157         /* Notify a driver that a packet that might be PTP was received. Driver
 158          * is responsible for freeing the passed-in SKB.
 159          */
 160         void (*receive)(struct mlxsw_sp *mlxsw_sp, struct sk_buff *skb,
 161                         u8 local_port);
 162
 163         /* Notify a driver that a timestamped packet was transmitted. Driver
 164          * is responsible for freeing the passed-in SKB.
 165          */
 166         void (*transmitted)(struct mlxsw_sp *mlxsw_sp, struct sk_buff *skb,
 167                             u8 local_port);
 168
 169         int (*hwtstamp_get)(struct mlxsw_sp_port *mlxsw_sp_port,
 170                             struct hwtstamp_config *config);
 171         int (*hwtstamp_set)(struct mlxsw_sp_port *mlxsw_sp_port,
 172                             struct hwtstamp_config *config);
 173         void (*shaper_work)(struct work_struct *work);
 174         int (*get_ts_info)(struct mlxsw_sp *mlxsw_sp,
 175                            struct ethtool_ts_info *info);
 176         int (*get_stats_count)(void);
 177         void (*get_stats_strings)(u8 **p);
 178         void (*get_stats)(struct mlxsw_sp_port *mlxsw_sp_port,
 179                           u64 *data, int data_index);
 180 };
 181
 182 static int mlxsw_sp_component_query(struct mlxfw_dev *mlxfw_dev,
 183                                     u16 component_index, u32 *p_max_size,
 184                                     u8 *p_align_bits, u16 *p_max_write_size)
 185 {
 186         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 187                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 188         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 189         char mcqi_pl[MLXSW_REG_MCQI_LEN];
 190         int err;
 191
 192         mlxsw_reg_mcqi_pack(mcqi_pl, component_index);
 193         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcqi), mcqi_pl);
 194         if (err)
 195                 return err;
 196         mlxsw_reg_mcqi_unpack(mcqi_pl, p_max_size, p_align_bits,
 197                               p_max_write_size);
 198
 199         *p_align_bits = max_t(u8, *p_align_bits, 2);
 200         *p_max_write_size = min_t(u16, *p_max_write_size,
 201                                   MLXSW_REG_MCDA_MAX_DATA_LEN);
 202         return 0;
 203 }
 204
 205 static int mlxsw_sp_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
 206 {
 207         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 208                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 209         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 210         char mcc_pl[MLXSW_REG_MCC_LEN];
 211         u8 control_state;
 212         int err;
 213
 214         mlxsw_reg_mcc_pack(mcc_pl, 0, 0, 0, 0);
 215         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 216         if (err)
 217                 return err;
 218
 219         mlxsw_reg_mcc_unpack(mcc_pl, fwhandle, NULL, &control_state);
 220         if (control_state != MLXFW_FSM_STATE_IDLE)
 221                 return -EBUSY;
 222
 223         mlxsw_reg_mcc_pack(mcc_pl,
 224                            MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
 225                            0, *fwhandle, 0);
 226         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 227 }
 228
 229 static int mlxsw_sp_fsm_component_update(struct mlxfw_dev *mlxfw_dev,
 230                                          u32 fwhandle, u16 component_index,
 231                                          u32 component_size)
 232 {
 233         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 234                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 235         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 236         char mcc_pl[MLXSW_REG_MCC_LEN];
 237
 238         mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
 239                            component_index, fwhandle, component_size);
 240         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 241 }
 242
 243 static int mlxsw_sp_fsm_block_download(struct mlxfw_dev *mlxfw_dev,
 244                                        u32 fwhandle, u8 *data, u16 size,
 245                                        u32 offset)
 246 {
 247         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 248                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 249         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 250         char mcda_pl[MLXSW_REG_MCDA_LEN];
 251
 252         mlxsw_reg_mcda_pack(mcda_pl, fwhandle, offset, size, data);
 253         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcda), mcda_pl);
 254 }
 255
 256 static int mlxsw_sp_fsm_component_verify(struct mlxfw_dev *mlxfw_dev,
 257                                          u32 fwhandle, u16 component_index)
 258 {
 259         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 260                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 261         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 262         char mcc_pl[MLXSW_REG_MCC_LEN];
 263
 264         mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
 265                            component_index, fwhandle, 0);
 266         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 267 }
 268
 269 static int mlxsw_sp_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
 270 {
 271         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 272                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 273         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 274         char mcc_pl[MLXSW_REG_MCC_LEN];
 275
 276         mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_ACTIVATE, 0,
 277                            fwhandle, 0);
 278         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 279 }
 280
 281 static int mlxsw_sp_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
 282                                     enum mlxfw_fsm_state *fsm_state,
 283                                     enum mlxfw_fsm_state_err *fsm_state_err)
 284 {
 285         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 286                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 287         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 288         char mcc_pl[MLXSW_REG_MCC_LEN];
 289         u8 control_state;
 290         u8 error_code;
 291         int err;
 292
 293         mlxsw_reg_mcc_pack(mcc_pl, 0, 0, fwhandle, 0);
 294         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 295         if (err)
 296                 return err;
 297
 298         mlxsw_reg_mcc_unpack(mcc_pl, NULL, &error_code, &control_state);
 299         *fsm_state = control_state;
 300         *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
 301                                MLXFW_FSM_STATE_ERR_MAX);
 302         return 0;
 303 }
 304
 305 static void mlxsw_sp_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
 306 {
 307         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 308                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 309         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 310         char mcc_pl[MLXSW_REG_MCC_LEN];
 311
 312         mlxsw_reg_mcc_pack(mcc_pl, MLXSW_REG_MCC_INSTRUCTION_CANCEL, 0,
 313                            fwhandle, 0);
 314         mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 315 }
 316
 317 static void mlxsw_sp_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
 318 {
 319         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 320                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 321         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 322         char mcc_pl[MLXSW_REG_MCC_LEN];
 323
 324         mlxsw_reg_mcc_pack(mcc_pl,
 325                            MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
 326                            fwhandle, 0);
 327         mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mcc), mcc_pl);
 328 }
 329
 330 static void mlxsw_sp_status_notify(struct mlxfw_dev *mlxfw_dev,
 331                                    const char *msg, const char *comp_name,
 332                                    u32 done_bytes, u32 total_bytes)
 333 {
 334         struct mlxsw_sp_mlxfw_dev *mlxsw_sp_mlxfw_dev =
 335                 container_of(mlxfw_dev, struct mlxsw_sp_mlxfw_dev, mlxfw_dev);
 336         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_mlxfw_dev->mlxsw_sp;
 337
 338         devlink_flash_update_status_notify(priv_to_devlink(mlxsw_sp->core),
 339                                            msg, comp_name,
 340                                            done_bytes, total_bytes);
 341 }
 342
 343 static const struct mlxfw_dev_ops mlxsw_sp_mlxfw_dev_ops = {
 344         .component_query        = mlxsw_sp_component_query,
 345         .fsm_lock               = mlxsw_sp_fsm_lock,
 346         .fsm_component_update   = mlxsw_sp_fsm_component_update,
 347         .fsm_block_download     = mlxsw_sp_fsm_block_download,
 348         .fsm_component_verify   = mlxsw_sp_fsm_component_verify,
 349         .fsm_activate           = mlxsw_sp_fsm_activate,
 350         .fsm_query_state        = mlxsw_sp_fsm_query_state,
 351         .fsm_cancel             = mlxsw_sp_fsm_cancel,
 352         .fsm_release            = mlxsw_sp_fsm_release,
 353         .status_notify          = mlxsw_sp_status_notify,
 354 };
 355
 356 static int mlxsw_sp_firmware_flash(struct mlxsw_sp *mlxsw_sp,
 357                                    const struct firmware *firmware,
 358                                    struct netlink_ext_ack *extack)
 359 {
 360         struct mlxsw_sp_mlxfw_dev mlxsw_sp_mlxfw_dev = {
 361                 .mlxfw_dev = {
 362                         .ops = &mlxsw_sp_mlxfw_dev_ops,
 363                         .psid = mlxsw_sp->bus_info->psid,
 364                         .psid_size = strlen(mlxsw_sp->bus_info->psid),
 365                 },
 366                 .mlxsw_sp = mlxsw_sp
 367         };
 368         int err;
 369
 370         mlxsw_core_fw_flash_start(mlxsw_sp->core);
 371         devlink_flash_update_begin_notify(priv_to_devlink(mlxsw_sp->core));
 372         err = mlxfw_firmware_flash(&mlxsw_sp_mlxfw_dev.mlxfw_dev,
 373                                    firmware, extack);
 374         devlink_flash_update_end_notify(priv_to_devlink(mlxsw_sp->core));
 375         mlxsw_core_fw_flash_end(mlxsw_sp->core);
 376
 377         return err;
 378 }
 379
 380 static int mlxsw_sp_fw_rev_validate(struct mlxsw_sp *mlxsw_sp)
 381 {
 382         const struct mlxsw_fw_rev *rev = &mlxsw_sp->bus_info->fw_rev;
 383         const struct mlxsw_fw_rev *req_rev = mlxsw_sp->req_rev;
 384         const char *fw_filename = mlxsw_sp->fw_filename;
 385         union devlink_param_value value;
 386         const struct firmware *firmware;
 387         int err;
 388
 389         /* Don't check if driver does not require it */
 390         if (!req_rev || !fw_filename)
 391                 return 0;
 392
 393         /* Don't check if devlink 'fw_load_policy' param is 'flash' */
 394         err = devlink_param_driverinit_value_get(priv_to_devlink(mlxsw_sp->core),
 395                                                  DEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY,
 396                                                  &value);
 397         if (err)
 398                 return err;
 399         if (value.vu8 == DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_FLASH)
 400                 return 0;
 401
 402         /* Validate driver & FW are compatible */
 403         if (rev->major != req_rev->major) {
 404                 WARN(1, "Mismatch in major FW version [%d:%d] is never expected; Please contact support\n",
 405                      rev->major, req_rev->major);
 406                 return -EINVAL;
 407         }
 408         if (MLXSW_SP_FWREV_MINOR_TO_BRANCH(rev->minor) ==
 409             MLXSW_SP_FWREV_MINOR_TO_BRANCH(req_rev->minor) &&
 410             (rev->minor > req_rev->minor ||
 411              (rev->minor == req_rev->minor &&
 412               rev->subminor >= req_rev->subminor)))
 413                 return 0;
 414
 415         dev_info(mlxsw_sp->bus_info->dev, "The firmware version %d.%d.%d is incompatible with the driver\n",
 416                  rev->major, rev->minor, rev->subminor);
 417         dev_info(mlxsw_sp->bus_info->dev, "Flashing firmware using file %s\n",
 418                  fw_filename);
 419
 420         err = reject_firmware_direct(&firmware, fw_filename,
 421                                       mlxsw_sp->bus_info->dev);
 422         if (err) {
 423                 dev_err(mlxsw_sp->bus_info->dev, "Could not request firmware file %s\n",
 424                         fw_filename);
 425                 return err;
 426         }
 427
 428         err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware, NULL);
 429         release_firmware(firmware);
 430         if (err)
 431                 dev_err(mlxsw_sp->bus_info->dev, "Could not upgrade firmware\n");
 432
 433         /* On FW flash success, tell the caller FW reset is needed
 434          * if current FW supports it.
 435          */
 436         if (rev->minor >= req_rev->can_reset_minor)
 437                 return err ? err : -EAGAIN;
 438         else
 439                 return 0;
 440 }
 441
 442 static int mlxsw_sp_flash_update(struct mlxsw_core *mlxsw_core,
 443                                  const char *file_name, const char *component,
 444                                  struct netlink_ext_ack *extack)
 445 {
 446         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
 447         const struct firmware *firmware;
 448         int err;
 449
 450         if (component)
 451                 return -EOPNOTSUPP;
 452
 453         err = request_firmware_direct(&firmware, file_name,
 454                                       mlxsw_sp->bus_info->dev);
 455         if (err)
 456                 return err;
 457         err = mlxsw_sp_firmware_flash(mlxsw_sp, firmware, extack);
 458         release_firmware(firmware);
 459
 460         return err;
 461 }
 462
 463 int mlxsw_sp_flow_counter_get(struct mlxsw_sp *mlxsw_sp,
 464                               unsigned int counter_index, u64 *packets,
 465                               u64 *bytes)
 466 {
 467         char mgpc_pl[MLXSW_REG_MGPC_LEN];
 468         int err;
 469
 470         mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_NOP,
 471                             MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
 472         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
 473         if (err)
 474                 return err;
 475         if (packets)
 476                 *packets = mlxsw_reg_mgpc_packet_counter_get(mgpc_pl);
 477         if (bytes)
 478                 *bytes = mlxsw_reg_mgpc_byte_counter_get(mgpc_pl);
 479         return 0;
 480 }
 481
 482 static int mlxsw_sp_flow_counter_clear(struct mlxsw_sp *mlxsw_sp,
 483                                        unsigned int counter_index)
 484 {
 485         char mgpc_pl[MLXSW_REG_MGPC_LEN];
 486
 487         mlxsw_reg_mgpc_pack(mgpc_pl, counter_index, MLXSW_REG_MGPC_OPCODE_CLEAR,
 488                             MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
 489         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mgpc), mgpc_pl);
 490 }
 491
 492 int mlxsw_sp_flow_counter_alloc(struct mlxsw_sp *mlxsw_sp,
 493                                 unsigned int *p_counter_index)
 494 {
 495         int err;
 496
 497         err = mlxsw_sp_counter_alloc(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
 498                                      p_counter_index);
 499         if (err)
 500                 return err;
 501         err = mlxsw_sp_flow_counter_clear(mlxsw_sp, *p_counter_index);
 502         if (err)
 503                 goto err_counter_clear;
 504         return 0;
 505
 506 err_counter_clear:
 507         mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
 508                               *p_counter_index);
 509         return err;
 510 }
 511
 512 void mlxsw_sp_flow_counter_free(struct mlxsw_sp *mlxsw_sp,
 513                                 unsigned int counter_index)
 514 {
 515          mlxsw_sp_counter_free(mlxsw_sp, MLXSW_SP_COUNTER_SUB_POOL_FLOW,
 516                                counter_index);
 517 }
 518
 519 static void mlxsw_sp_txhdr_construct(struct sk_buff *skb,
 520                                      const struct mlxsw_tx_info *tx_info)
 521 {
 522         char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
 523
 524         memset(txhdr, 0, MLXSW_TXHDR_LEN);
 525
 526         mlxsw_tx_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
 527         mlxsw_tx_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
 528         mlxsw_tx_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
 529         mlxsw_tx_hdr_swid_set(txhdr, 0);
 530         mlxsw_tx_hdr_control_tclass_set(txhdr, 1);
 531         mlxsw_tx_hdr_port_mid_set(txhdr, tx_info->local_port);
 532         mlxsw_tx_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
 533 }
 534
 535 enum mlxsw_reg_spms_state mlxsw_sp_stp_spms_state(u8 state)
 536 {
 537         switch (state) {
 538         case BR_STATE_FORWARDING:
 539                 return MLXSW_REG_SPMS_STATE_FORWARDING;
 540         case BR_STATE_LEARNING:
 541                 return MLXSW_REG_SPMS_STATE_LEARNING;
 542         case BR_STATE_LISTENING: /* fall-through */
 543         case BR_STATE_DISABLED: /* fall-through */
 544         case BR_STATE_BLOCKING:
 545                 return MLXSW_REG_SPMS_STATE_DISCARDING;
 546         default:
 547                 BUG();
 548         }
 549 }
 550
 551 int mlxsw_sp_port_vid_stp_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
 552                               u8 state)
 553 {
 554         enum mlxsw_reg_spms_state spms_state = mlxsw_sp_stp_spms_state(state);
 555         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 556         char *spms_pl;
 557         int err;
 558
 559         spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
 560         if (!spms_pl)
 561                 return -ENOMEM;
 562         mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
 563         mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
 564
 565         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
 566         kfree(spms_pl);
 567         return err;
 568 }
 569
 570 static int mlxsw_sp_base_mac_get(struct mlxsw_sp *mlxsw_sp)
 571 {
 572         char spad_pl[MLXSW_REG_SPAD_LEN] = {0};
 573         int err;
 574
 575         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(spad), spad_pl);
 576         if (err)
 577                 return err;
 578         mlxsw_reg_spad_base_mac_memcpy_from(spad_pl, mlxsw_sp->base_mac);
 579         return 0;
 580 }
 581
 582 static int mlxsw_sp_port_sample_set(struct mlxsw_sp_port *mlxsw_sp_port,
 583                                     bool enable, u32 rate)
 584 {
 585         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 586         char mpsc_pl[MLXSW_REG_MPSC_LEN];
 587
 588         mlxsw_reg_mpsc_pack(mpsc_pl, mlxsw_sp_port->local_port, enable, rate);
 589         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mpsc), mpsc_pl);
 590 }
 591
 592 static int mlxsw_sp_port_admin_status_set(struct mlxsw_sp_port *mlxsw_sp_port,
 593                                           bool is_up)
 594 {
 595         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 596         char paos_pl[MLXSW_REG_PAOS_LEN];
 597
 598         mlxsw_reg_paos_pack(paos_pl, mlxsw_sp_port->local_port,
 599                             is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
 600                             MLXSW_PORT_ADMIN_STATUS_DOWN);
 601         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(paos), paos_pl);
 602 }
 603
 604 static int mlxsw_sp_port_dev_addr_set(struct mlxsw_sp_port *mlxsw_sp_port,
 605                                       unsigned char *addr)
 606 {
 607         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 608         char ppad_pl[MLXSW_REG_PPAD_LEN];
 609
 610         mlxsw_reg_ppad_pack(ppad_pl, true, mlxsw_sp_port->local_port);
 611         mlxsw_reg_ppad_mac_memcpy_to(ppad_pl, addr);
 612         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ppad), ppad_pl);
 613 }
 614
 615 static int mlxsw_sp_port_dev_addr_init(struct mlxsw_sp_port *mlxsw_sp_port)
 616 {
 617         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 618         unsigned char *addr = mlxsw_sp_port->dev->dev_addr;
 619
 620         ether_addr_copy(addr, mlxsw_sp->base_mac);
 621         addr[ETH_ALEN - 1] += mlxsw_sp_port->local_port;
 622         return mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr);
 623 }
 624
 625 static int mlxsw_sp_port_mtu_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 mtu)
 626 {
 627         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 628         char pmtu_pl[MLXSW_REG_PMTU_LEN];
 629         int max_mtu;
 630         int err;
 631
 632         mtu += MLXSW_TXHDR_LEN + ETH_HLEN;
 633         mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, 0);
 634         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
 635         if (err)
 636                 return err;
 637         max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
 638
 639         if (mtu > max_mtu)
 640                 return -EINVAL;
 641
 642         mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sp_port->local_port, mtu);
 643         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmtu), pmtu_pl);
 644 }
 645
 646 static int mlxsw_sp_port_swid_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 swid)
 647 {
 648         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 649         char pspa_pl[MLXSW_REG_PSPA_LEN];
 650
 651         mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sp_port->local_port);
 652         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pspa), pspa_pl);
 653 }
 654
 655 int mlxsw_sp_port_vp_mode_set(struct mlxsw_sp_port *mlxsw_sp_port, bool enable)
 656 {
 657         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 658         char svpe_pl[MLXSW_REG_SVPE_LEN];
 659
 660         mlxsw_reg_svpe_pack(svpe_pl, mlxsw_sp_port->local_port, enable);
 661         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(svpe), svpe_pl);
 662 }
 663
 664 int mlxsw_sp_port_vid_learning_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid,
 665                                    bool learn_enable)
 666 {
 667         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 668         char *spvmlr_pl;
 669         int err;
 670
 671         spvmlr_pl = kmalloc(MLXSW_REG_SPVMLR_LEN, GFP_KERNEL);
 672         if (!spvmlr_pl)
 673                 return -ENOMEM;
 674         mlxsw_reg_spvmlr_pack(spvmlr_pl, mlxsw_sp_port->local_port, vid, vid,
 675                               learn_enable);
 676         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvmlr), spvmlr_pl);
 677         kfree(spvmlr_pl);
 678         return err;
 679 }
 680
 681 static int __mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port,
 682                                     u16 vid)
 683 {
 684         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 685         char spvid_pl[MLXSW_REG_SPVID_LEN];
 686
 687         mlxsw_reg_spvid_pack(spvid_pl, mlxsw_sp_port->local_port, vid);
 688         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvid), spvid_pl);
 689 }
 690
 691 static int mlxsw_sp_port_allow_untagged_set(struct mlxsw_sp_port *mlxsw_sp_port,
 692                                             bool allow)
 693 {
 694         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 695         char spaft_pl[MLXSW_REG_SPAFT_LEN];
 696
 697         mlxsw_reg_spaft_pack(spaft_pl, mlxsw_sp_port->local_port, allow);
 698         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spaft), spaft_pl);
 699 }
 700
 701 int mlxsw_sp_port_pvid_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
 702 {
 703         int err;
 704
 705         if (!vid) {
 706                 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, false);
 707                 if (err)
 708                         return err;
 709         } else {
 710                 err = __mlxsw_sp_port_pvid_set(mlxsw_sp_port, vid);
 711                 if (err)
 712                         return err;
 713                 err = mlxsw_sp_port_allow_untagged_set(mlxsw_sp_port, true);
 714                 if (err)
 715                         goto err_port_allow_untagged_set;
 716         }
 717
 718         mlxsw_sp_port->pvid = vid;
 719         return 0;
 720
 721 err_port_allow_untagged_set:
 722         __mlxsw_sp_port_pvid_set(mlxsw_sp_port, mlxsw_sp_port->pvid);
 723         return err;
 724 }
 725
 726 static int
 727 mlxsw_sp_port_system_port_mapping_set(struct mlxsw_sp_port *mlxsw_sp_port)
 728 {
 729         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 730         char sspr_pl[MLXSW_REG_SSPR_LEN];
 731
 732         mlxsw_reg_sspr_pack(sspr_pl, mlxsw_sp_port->local_port);
 733         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sspr), sspr_pl);
 734 }
 735
 736 static int mlxsw_sp_port_module_info_get(struct mlxsw_sp *mlxsw_sp,
 737                                          u8 local_port, u8 *p_module,
 738                                          u8 *p_width, u8 *p_lane)
 739 {
 740         char pmlp_pl[MLXSW_REG_PMLP_LEN];
 741         int err;
 742
 743         mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
 744         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
 745         if (err)
 746                 return err;
 747         *p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
 748         *p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
 749         *p_lane = mlxsw_reg_pmlp_tx_lane_get(pmlp_pl, 0);
 750         return 0;
 751 }
 752
 753 static int mlxsw_sp_port_module_map(struct mlxsw_sp_port *mlxsw_sp_port,
 754                                     u8 module, u8 width, u8 lane)
 755 {
 756         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 757         char pmlp_pl[MLXSW_REG_PMLP_LEN];
 758         int i;
 759
 760         mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
 761         mlxsw_reg_pmlp_width_set(pmlp_pl, width);
 762         for (i = 0; i < width; i++) {
 763                 mlxsw_reg_pmlp_module_set(pmlp_pl, i, module);
 764                 mlxsw_reg_pmlp_tx_lane_set(pmlp_pl, i, lane + i);  /* Rx & Tx */
 765         }
 766
 767         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
 768 }
 769
 770 static int mlxsw_sp_port_module_unmap(struct mlxsw_sp_port *mlxsw_sp_port)
 771 {
 772         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 773         char pmlp_pl[MLXSW_REG_PMLP_LEN];
 774
 775         mlxsw_reg_pmlp_pack(pmlp_pl, mlxsw_sp_port->local_port);
 776         mlxsw_reg_pmlp_width_set(pmlp_pl, 0);
 777         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pmlp), pmlp_pl);
 778 }
 779
 780 static int mlxsw_sp_port_open(struct net_device *dev)
 781 {
 782         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 783         int err;
 784
 785         err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
 786         if (err)
 787                 return err;
 788         netif_start_queue(dev);
 789         return 0;
 790 }
 791
 792 static int mlxsw_sp_port_stop(struct net_device *dev)
 793 {
 794         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 795
 796         netif_stop_queue(dev);
 797         return mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
 798 }
 799
 800 static netdev_tx_t mlxsw_sp_port_xmit(struct sk_buff *skb,
 801                                       struct net_device *dev)
 802 {
 803         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 804         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 805         struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
 806         const struct mlxsw_tx_info tx_info = {
 807                 .local_port = mlxsw_sp_port->local_port,
 808                 .is_emad = false,
 809         };
 810         u64 len;
 811         int err;
 812
 813         if (skb_cow_head(skb, MLXSW_TXHDR_LEN)) {
 814                 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
 815                 dev_kfree_skb_any(skb);
 816                 return NETDEV_TX_OK;
 817         }
 818
 819         memset(skb->cb, 0, sizeof(struct mlxsw_skb_cb));
 820
 821         if (mlxsw_core_skb_transmit_busy(mlxsw_sp->core, &tx_info))
 822                 return NETDEV_TX_BUSY;
 823
 824         if (eth_skb_pad(skb)) {
 825                 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
 826                 return NETDEV_TX_OK;
 827         }
 828
 829         mlxsw_sp_txhdr_construct(skb, &tx_info);
 830         /* TX header is consumed by HW on the way so we shouldn't count its
 831          * bytes as being sent.
 832          */
 833         len = skb->len - MLXSW_TXHDR_LEN;
 834
 835         /* Due to a race we might fail here because of a full queue. In that
 836          * unlikely case we simply drop the packet.
 837          */
 838         err = mlxsw_core_skb_transmit(mlxsw_sp->core, skb, &tx_info);
 839
 840         if (!err) {
 841                 pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
 842                 u64_stats_update_begin(&pcpu_stats->syncp);
 843                 pcpu_stats->tx_packets++;
 844                 pcpu_stats->tx_bytes += len;
 845                 u64_stats_update_end(&pcpu_stats->syncp);
 846         } else {
 847                 this_cpu_inc(mlxsw_sp_port->pcpu_stats->tx_dropped);
 848                 dev_kfree_skb_any(skb);
 849         }
 850         return NETDEV_TX_OK;
 851 }
 852
 853 static void mlxsw_sp_set_rx_mode(struct net_device *dev)
 854 {
 855 }
 856
 857 static int mlxsw_sp_port_set_mac_address(struct net_device *dev, void *p)
 858 {
 859         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 860         struct sockaddr *addr = p;
 861         int err;
 862
 863         if (!is_valid_ether_addr(addr->sa_data))
 864                 return -EADDRNOTAVAIL;
 865
 866         err = mlxsw_sp_port_dev_addr_set(mlxsw_sp_port, addr->sa_data);
 867         if (err)
 868                 return err;
 869         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
 870         return 0;
 871 }
 872
 873 static u16 mlxsw_sp_pg_buf_threshold_get(const struct mlxsw_sp *mlxsw_sp,
 874                                          int mtu)
 875 {
 876         return 2 * mlxsw_sp_bytes_cells(mlxsw_sp, mtu);
 877 }
 878
 879 #define MLXSW_SP_CELL_FACTOR 2  /* 2 * cell_size / (IPG + cell_size + 1) */
 880
 881 static u16 mlxsw_sp_pfc_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
 882                                   u16 delay)
 883 {
 884         delay = mlxsw_sp_bytes_cells(mlxsw_sp, DIV_ROUND_UP(delay,
 885                                                             BITS_PER_BYTE));
 886         return MLXSW_SP_CELL_FACTOR * delay + mlxsw_sp_bytes_cells(mlxsw_sp,
 887                                                                    mtu);
 888 }
 889
 890 /* Maximum delay buffer needed in case of PAUSE frames, in bytes.
 891  * Assumes 100m cable and maximum MTU.
 892  */
 893 #define MLXSW_SP_PAUSE_DELAY 58752
 894
 895 static u16 mlxsw_sp_pg_buf_delay_get(const struct mlxsw_sp *mlxsw_sp, int mtu,
 896                                      u16 delay, bool pfc, bool pause)
 897 {
 898         if (pfc)
 899                 return mlxsw_sp_pfc_delay_get(mlxsw_sp, mtu, delay);
 900         else if (pause)
 901                 return mlxsw_sp_bytes_cells(mlxsw_sp, MLXSW_SP_PAUSE_DELAY);
 902         else
 903                 return 0;
 904 }
 905
 906 static void mlxsw_sp_pg_buf_pack(char *pbmc_pl, int index, u16 size, u16 thres,
 907                                  bool lossy)
 908 {
 909         if (lossy)
 910                 mlxsw_reg_pbmc_lossy_buffer_pack(pbmc_pl, index, size);
 911         else
 912                 mlxsw_reg_pbmc_lossless_buffer_pack(pbmc_pl, index, size,
 913                                                     thres);
 914 }
 915
 916 int __mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port, int mtu,
 917                                  u8 *prio_tc, bool pause_en,
 918                                  struct ieee_pfc *my_pfc)
 919 {
 920         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
 921         u8 pfc_en = !!my_pfc ? my_pfc->pfc_en : 0;
 922         u16 delay = !!my_pfc ? my_pfc->delay : 0;
 923         char pbmc_pl[MLXSW_REG_PBMC_LEN];
 924         u32 taken_headroom_cells = 0;
 925         u32 max_headroom_cells;
 926         int i, j, err;
 927
 928         max_headroom_cells = mlxsw_sp_sb_max_headroom_cells(mlxsw_sp);
 929
 930         mlxsw_reg_pbmc_pack(pbmc_pl, mlxsw_sp_port->local_port, 0, 0);
 931         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
 932         if (err)
 933                 return err;
 934
 935         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
 936                 bool configure = false;
 937                 bool pfc = false;
 938                 u16 thres_cells;
 939                 u16 delay_cells;
 940                 u16 total_cells;
 941                 bool lossy;
 942
 943                 for (j = 0; j < IEEE_8021QAZ_MAX_TCS; j++) {
 944                         if (prio_tc[j] == i) {
 945                                 pfc = pfc_en & BIT(j);
 946                                 configure = true;
 947                                 break;
 948                         }
 949                 }
 950
 951                 if (!configure)
 952                         continue;
 953
 954                 lossy = !(pfc || pause_en);
 955                 thres_cells = mlxsw_sp_pg_buf_threshold_get(mlxsw_sp, mtu);
 956                 delay_cells = mlxsw_sp_pg_buf_delay_get(mlxsw_sp, mtu, delay,
 957                                                         pfc, pause_en);
 958                 total_cells = thres_cells + delay_cells;
 959
 960                 taken_headroom_cells += total_cells;
 961                 if (taken_headroom_cells > max_headroom_cells)
 962                         return -ENOBUFS;
 963
 964                 mlxsw_sp_pg_buf_pack(pbmc_pl, i, total_cells,
 965                                      thres_cells, lossy);
 966         }
 967
 968         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(pbmc), pbmc_pl);
 969 }
 970
 971 static int mlxsw_sp_port_headroom_set(struct mlxsw_sp_port *mlxsw_sp_port,
 972                                       int mtu, bool pause_en)
 973 {
 974         u8 def_prio_tc[IEEE_8021QAZ_MAX_TCS] = {0};
 975         bool dcb_en = !!mlxsw_sp_port->dcb.ets;
 976         struct ieee_pfc *my_pfc;
 977         u8 *prio_tc;
 978
 979         prio_tc = dcb_en ? mlxsw_sp_port->dcb.ets->prio_tc : def_prio_tc;
 980         my_pfc = dcb_en ? mlxsw_sp_port->dcb.pfc : NULL;
 981
 982         return __mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, prio_tc,
 983                                             pause_en, my_pfc);
 984 }
 985
 986 static int mlxsw_sp_port_change_mtu(struct net_device *dev, int mtu)
 987 {
 988         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
 989         bool pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
 990         int err;
 991
 992         err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, mtu, pause_en);
 993         if (err)
 994                 return err;
 995         err = mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, mtu);
 996         if (err)
 997                 goto err_span_port_mtu_update;
 998         err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, mtu);
 999         if (err)
1000                 goto err_port_mtu_set;
1001         dev->mtu = mtu;
1002         return 0;
1003
1004 err_port_mtu_set:
1005         mlxsw_sp_span_port_mtu_update(mlxsw_sp_port, dev->mtu);
1006 err_span_port_mtu_update:
1007         mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1008         return err;
1009 }
1010
1011 static int
1012 mlxsw_sp_port_get_sw_stats64(const struct net_device *dev,
1013                              struct rtnl_link_stats64 *stats)
1014 {
1015         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1016         struct mlxsw_sp_port_pcpu_stats *p;
1017         u64 rx_packets, rx_bytes, tx_packets, tx_bytes;
1018         u32 tx_dropped = 0;
1019         unsigned int start;
1020         int i;
1021
1022         for_each_possible_cpu(i) {
1023                 p = per_cpu_ptr(mlxsw_sp_port->pcpu_stats, i);
1024                 do {
1025                         start = u64_stats_fetch_begin_irq(&p->syncp);
1026                         rx_packets      = p->rx_packets;
1027                         rx_bytes        = p->rx_bytes;
1028                         tx_packets      = p->tx_packets;
1029                         tx_bytes        = p->tx_bytes;
1030                 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
1031
1032                 stats->rx_packets       += rx_packets;
1033                 stats->rx_bytes         += rx_bytes;
1034                 stats->tx_packets       += tx_packets;
1035                 stats->tx_bytes         += tx_bytes;
1036                 /* tx_dropped is u32, updated without syncp protection. */
1037                 tx_dropped      += p->tx_dropped;
1038         }
1039         stats->tx_dropped       = tx_dropped;
1040         return 0;
1041 }
1042
1043 static bool mlxsw_sp_port_has_offload_stats(const struct net_device *dev, int attr_id)
1044 {
1045         switch (attr_id) {
1046         case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1047                 return true;
1048         }
1049
1050         return false;
1051 }
1052
1053 static int mlxsw_sp_port_get_offload_stats(int attr_id, const struct net_device *dev,
1054                                            void *sp)
1055 {
1056         switch (attr_id) {
1057         case IFLA_OFFLOAD_XSTATS_CPU_HIT:
1058                 return mlxsw_sp_port_get_sw_stats64(dev, sp);
1059         }
1060
1061         return -EINVAL;
1062 }
1063
1064 static int mlxsw_sp_port_get_stats_raw(struct net_device *dev, int grp,
1065                                        int prio, char *ppcnt_pl)
1066 {
1067         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1068         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1069
1070         mlxsw_reg_ppcnt_pack(ppcnt_pl, mlxsw_sp_port->local_port, grp, prio);
1071         return mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ppcnt), ppcnt_pl);
1072 }
1073
1074 static int mlxsw_sp_port_get_hw_stats(struct net_device *dev,
1075                                       struct rtnl_link_stats64 *stats)
1076 {
1077         char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1078         int err;
1079
1080         err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT,
1081                                           0, ppcnt_pl);
1082         if (err)
1083                 goto out;
1084
1085         stats->tx_packets =
1086                 mlxsw_reg_ppcnt_a_frames_transmitted_ok_get(ppcnt_pl);
1087         stats->rx_packets =
1088                 mlxsw_reg_ppcnt_a_frames_received_ok_get(ppcnt_pl);
1089         stats->tx_bytes =
1090                 mlxsw_reg_ppcnt_a_octets_transmitted_ok_get(ppcnt_pl);
1091         stats->rx_bytes =
1092                 mlxsw_reg_ppcnt_a_octets_received_ok_get(ppcnt_pl);
1093         stats->multicast =
1094                 mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get(ppcnt_pl);
1095
1096         stats->rx_crc_errors =
1097                 mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get(ppcnt_pl);
1098         stats->rx_frame_errors =
1099                 mlxsw_reg_ppcnt_a_alignment_errors_get(ppcnt_pl);
1100
1101         stats->rx_length_errors = (
1102                 mlxsw_reg_ppcnt_a_in_range_length_errors_get(ppcnt_pl) +
1103                 mlxsw_reg_ppcnt_a_out_of_range_length_field_get(ppcnt_pl) +
1104                 mlxsw_reg_ppcnt_a_frame_too_long_errors_get(ppcnt_pl));
1105
1106         stats->rx_errors = (stats->rx_crc_errors +
1107                 stats->rx_frame_errors + stats->rx_length_errors);
1108
1109 out:
1110         return err;
1111 }
1112
1113 static void
1114 mlxsw_sp_port_get_hw_xstats(struct net_device *dev,
1115                             struct mlxsw_sp_port_xstats *xstats)
1116 {
1117         char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
1118         int err, i;
1119
1120         err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_EXT_CNT, 0,
1121                                           ppcnt_pl);
1122         if (!err)
1123                 xstats->ecn = mlxsw_reg_ppcnt_ecn_marked_get(ppcnt_pl);
1124
1125         for (i = 0; i < TC_MAX_QUEUE; i++) {
1126                 err = mlxsw_sp_port_get_stats_raw(dev,
1127                                                   MLXSW_REG_PPCNT_TC_CONG_TC,
1128                                                   i, ppcnt_pl);
1129                 if (!err)
1130                         xstats->wred_drop[i] =
1131                                 mlxsw_reg_ppcnt_wred_discard_get(ppcnt_pl);
1132
1133                 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_TC_CNT,
1134                                                   i, ppcnt_pl);
1135                 if (err)
1136                         continue;
1137
1138                 xstats->backlog[i] =
1139                         mlxsw_reg_ppcnt_tc_transmit_queue_get(ppcnt_pl);
1140                 xstats->tail_drop[i] =
1141                         mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get(ppcnt_pl);
1142         }
1143
1144         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
1145                 err = mlxsw_sp_port_get_stats_raw(dev, MLXSW_REG_PPCNT_PRIO_CNT,
1146                                                   i, ppcnt_pl);
1147                 if (err)
1148                         continue;
1149
1150                 xstats->tx_packets[i] = mlxsw_reg_ppcnt_tx_frames_get(ppcnt_pl);
1151                 xstats->tx_bytes[i] = mlxsw_reg_ppcnt_tx_octets_get(ppcnt_pl);
1152         }
1153 }
1154
1155 static void update_stats_cache(struct work_struct *work)
1156 {
1157         struct mlxsw_sp_port *mlxsw_sp_port =
1158                 container_of(work, struct mlxsw_sp_port,
1159                              periodic_hw_stats.update_dw.work);
1160
1161         if (!netif_carrier_ok(mlxsw_sp_port->dev))
1162                 /* Note: mlxsw_sp_port_down_wipe_counters() clears the cache as
1163                  * necessary when port goes down.
1164                  */
1165                 goto out;
1166
1167         mlxsw_sp_port_get_hw_stats(mlxsw_sp_port->dev,
1168                                    &mlxsw_sp_port->periodic_hw_stats.stats);
1169         mlxsw_sp_port_get_hw_xstats(mlxsw_sp_port->dev,
1170                                     &mlxsw_sp_port->periodic_hw_stats.xstats);
1171
1172 out:
1173         mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw,
1174                                MLXSW_HW_STATS_UPDATE_TIME);
1175 }
1176
1177 /* Return the stats from a cache that is updated periodically,
1178  * as this function might get called in an atomic context.
1179  */
1180 static void
1181 mlxsw_sp_port_get_stats64(struct net_device *dev,
1182                           struct rtnl_link_stats64 *stats)
1183 {
1184         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1185
1186         memcpy(stats, &mlxsw_sp_port->periodic_hw_stats.stats, sizeof(*stats));
1187 }
1188
1189 static int __mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port,
1190                                     u16 vid_begin, u16 vid_end,
1191                                     bool is_member, bool untagged)
1192 {
1193         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1194         char *spvm_pl;
1195         int err;
1196
1197         spvm_pl = kmalloc(MLXSW_REG_SPVM_LEN, GFP_KERNEL);
1198         if (!spvm_pl)
1199                 return -ENOMEM;
1200
1201         mlxsw_reg_spvm_pack(spvm_pl, mlxsw_sp_port->local_port, vid_begin,
1202                             vid_end, is_member, untagged);
1203         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spvm), spvm_pl);
1204         kfree(spvm_pl);
1205         return err;
1206 }
1207
1208 int mlxsw_sp_port_vlan_set(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid_begin,
1209                            u16 vid_end, bool is_member, bool untagged)
1210 {
1211         u16 vid, vid_e;
1212         int err;
1213
1214         for (vid = vid_begin; vid <= vid_end;
1215              vid += MLXSW_REG_SPVM_REC_MAX_COUNT) {
1216                 vid_e = min((u16) (vid + MLXSW_REG_SPVM_REC_MAX_COUNT - 1),
1217                             vid_end);
1218
1219                 err = __mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid_e,
1220                                                is_member, untagged);
1221                 if (err)
1222                         return err;
1223         }
1224
1225         return 0;
1226 }
1227
1228 static void mlxsw_sp_port_vlan_flush(struct mlxsw_sp_port *mlxsw_sp_port,
1229                                      bool flush_default)
1230 {
1231         struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan, *tmp;
1232
1233         list_for_each_entry_safe(mlxsw_sp_port_vlan, tmp,
1234                                  &mlxsw_sp_port->vlans_list, list) {
1235                 if (!flush_default &&
1236                     mlxsw_sp_port_vlan->vid == MLXSW_SP_DEFAULT_VID)
1237                         continue;
1238                 mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
1239         }
1240 }
1241
1242 static void
1243 mlxsw_sp_port_vlan_cleanup(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1244 {
1245         if (mlxsw_sp_port_vlan->bridge_port)
1246                 mlxsw_sp_port_vlan_bridge_leave(mlxsw_sp_port_vlan);
1247         else if (mlxsw_sp_port_vlan->fid)
1248                 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port_vlan);
1249 }
1250
1251 struct mlxsw_sp_port_vlan *
1252 mlxsw_sp_port_vlan_create(struct mlxsw_sp_port *mlxsw_sp_port, u16 vid)
1253 {
1254         struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1255         bool untagged = vid == MLXSW_SP_DEFAULT_VID;
1256         int err;
1257
1258         mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1259         if (mlxsw_sp_port_vlan)
1260                 return ERR_PTR(-EEXIST);
1261
1262         err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, true, untagged);
1263         if (err)
1264                 return ERR_PTR(err);
1265
1266         mlxsw_sp_port_vlan = kzalloc(sizeof(*mlxsw_sp_port_vlan), GFP_KERNEL);
1267         if (!mlxsw_sp_port_vlan) {
1268                 err = -ENOMEM;
1269                 goto err_port_vlan_alloc;
1270         }
1271
1272         mlxsw_sp_port_vlan->mlxsw_sp_port = mlxsw_sp_port;
1273         mlxsw_sp_port_vlan->vid = vid;
1274         list_add(&mlxsw_sp_port_vlan->list, &mlxsw_sp_port->vlans_list);
1275
1276         return mlxsw_sp_port_vlan;
1277
1278 err_port_vlan_alloc:
1279         mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1280         return ERR_PTR(err);
1281 }
1282
1283 void mlxsw_sp_port_vlan_destroy(struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan)
1284 {
1285         struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp_port_vlan->mlxsw_sp_port;
1286         u16 vid = mlxsw_sp_port_vlan->vid;
1287
1288         mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port_vlan);
1289         list_del(&mlxsw_sp_port_vlan->list);
1290         kfree(mlxsw_sp_port_vlan);
1291         mlxsw_sp_port_vlan_set(mlxsw_sp_port, vid, vid, false, false);
1292 }
1293
1294 static int mlxsw_sp_port_add_vid(struct net_device *dev,
1295                                  __be16 __always_unused proto, u16 vid)
1296 {
1297         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1298
1299         /* VLAN 0 is added to HW filter when device goes up, but it is
1300          * reserved in our case, so simply return.
1301          */
1302         if (!vid)
1303                 return 0;
1304
1305         return PTR_ERR_OR_ZERO(mlxsw_sp_port_vlan_create(mlxsw_sp_port, vid));
1306 }
1307
1308 static int mlxsw_sp_port_kill_vid(struct net_device *dev,
1309                                   __be16 __always_unused proto, u16 vid)
1310 {
1311         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1312         struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
1313
1314         /* VLAN 0 is removed from HW filter when device goes down, but
1315          * it is reserved in our case, so simply return.
1316          */
1317         if (!vid)
1318                 return 0;
1319
1320         mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_find_by_vid(mlxsw_sp_port, vid);
1321         if (!mlxsw_sp_port_vlan)
1322                 return 0;
1323         mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
1324
1325         return 0;
1326 }
1327
1328 static struct mlxsw_sp_port_mall_tc_entry *
1329 mlxsw_sp_port_mall_tc_entry_find(struct mlxsw_sp_port *port,
1330                                  unsigned long cookie) {
1331         struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1332
1333         list_for_each_entry(mall_tc_entry, &port->mall_tc_list, list)
1334                 if (mall_tc_entry->cookie == cookie)
1335                         return mall_tc_entry;
1336
1337         return NULL;
1338 }
1339
1340 static int
1341 mlxsw_sp_port_add_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1342                                       struct mlxsw_sp_port_mall_mirror_tc_entry *mirror,
1343                                       const struct flow_action_entry *act,
1344                                       bool ingress)
1345 {
1346         enum mlxsw_sp_span_type span_type;
1347
1348         if (!act->dev) {
1349                 netdev_err(mlxsw_sp_port->dev, "Could not find requested device\n");
1350                 return -EINVAL;
1351         }
1352
1353         mirror->ingress = ingress;
1354         span_type = ingress ? MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1355         return mlxsw_sp_span_mirror_add(mlxsw_sp_port, act->dev, span_type,
1356                                         true, &mirror->span_id);
1357 }
1358
1359 static void
1360 mlxsw_sp_port_del_cls_matchall_mirror(struct mlxsw_sp_port *mlxsw_sp_port,
1361                                       struct mlxsw_sp_port_mall_mirror_tc_entry *mirror)
1362 {
1363         enum mlxsw_sp_span_type span_type;
1364
1365         span_type = mirror->ingress ?
1366                         MLXSW_SP_SPAN_INGRESS : MLXSW_SP_SPAN_EGRESS;
1367         mlxsw_sp_span_mirror_del(mlxsw_sp_port, mirror->span_id,
1368                                  span_type, true);
1369 }
1370
1371 static int
1372 mlxsw_sp_port_add_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port,
1373                                       struct tc_cls_matchall_offload *cls,
1374                                       const struct flow_action_entry *act,
1375                                       bool ingress)
1376 {
1377         int err;
1378
1379         if (!mlxsw_sp_port->sample)
1380                 return -EOPNOTSUPP;
1381         if (rtnl_dereference(mlxsw_sp_port->sample->psample_group)) {
1382                 netdev_err(mlxsw_sp_port->dev, "sample already active\n");
1383                 return -EEXIST;
1384         }
1385         if (act->sample.rate > MLXSW_REG_MPSC_RATE_MAX) {
1386                 netdev_err(mlxsw_sp_port->dev, "sample rate not supported\n");
1387                 return -EOPNOTSUPP;
1388         }
1389
1390         rcu_assign_pointer(mlxsw_sp_port->sample->psample_group,
1391                            act->sample.psample_group);
1392         mlxsw_sp_port->sample->truncate = act->sample.truncate;
1393         mlxsw_sp_port->sample->trunc_size = act->sample.trunc_size;
1394         mlxsw_sp_port->sample->rate = act->sample.rate;
1395
1396         err = mlxsw_sp_port_sample_set(mlxsw_sp_port, true, act->sample.rate);
1397         if (err)
1398                 goto err_port_sample_set;
1399         return 0;
1400
1401 err_port_sample_set:
1402         RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1403         return err;
1404 }
1405
1406 static void
1407 mlxsw_sp_port_del_cls_matchall_sample(struct mlxsw_sp_port *mlxsw_sp_port)
1408 {
1409         if (!mlxsw_sp_port->sample)
1410                 return;
1411
1412         mlxsw_sp_port_sample_set(mlxsw_sp_port, false, 1);
1413         RCU_INIT_POINTER(mlxsw_sp_port->sample->psample_group, NULL);
1414 }
1415
1416 static int mlxsw_sp_port_add_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1417                                           struct tc_cls_matchall_offload *f,
1418                                           bool ingress)
1419 {
1420         struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1421         __be16 protocol = f->common.protocol;
1422         struct flow_action_entry *act;
1423         int err;
1424
1425         if (!flow_offload_has_one_action(&f->rule->action)) {
1426                 netdev_err(mlxsw_sp_port->dev, "only singular actions are supported\n");
1427                 return -EOPNOTSUPP;
1428         }
1429
1430         mall_tc_entry = kzalloc(sizeof(*mall_tc_entry), GFP_KERNEL);
1431         if (!mall_tc_entry)
1432                 return -ENOMEM;
1433         mall_tc_entry->cookie = f->cookie;
1434
1435         act = &f->rule->action.entries[0];
1436
1437         if (act->id == FLOW_ACTION_MIRRED && protocol == htons(ETH_P_ALL)) {
1438                 struct mlxsw_sp_port_mall_mirror_tc_entry *mirror;
1439
1440                 mall_tc_entry->type = MLXSW_SP_PORT_MALL_MIRROR;
1441                 mirror = &mall_tc_entry->mirror;
1442                 err = mlxsw_sp_port_add_cls_matchall_mirror(mlxsw_sp_port,
1443                                                             mirror, act,
1444                                                             ingress);
1445         } else if (act->id == FLOW_ACTION_SAMPLE &&
1446                    protocol == htons(ETH_P_ALL)) {
1447                 mall_tc_entry->type = MLXSW_SP_PORT_MALL_SAMPLE;
1448                 err = mlxsw_sp_port_add_cls_matchall_sample(mlxsw_sp_port, f,
1449                                                             act, ingress);
1450         } else {
1451                 err = -EOPNOTSUPP;
1452         }
1453
1454         if (err)
1455                 goto err_add_action;
1456
1457         list_add_tail(&mall_tc_entry->list, &mlxsw_sp_port->mall_tc_list);
1458         return 0;
1459
1460 err_add_action:
1461         kfree(mall_tc_entry);
1462         return err;
1463 }
1464
1465 static void mlxsw_sp_port_del_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1466                                            struct tc_cls_matchall_offload *f)
1467 {
1468         struct mlxsw_sp_port_mall_tc_entry *mall_tc_entry;
1469
1470         mall_tc_entry = mlxsw_sp_port_mall_tc_entry_find(mlxsw_sp_port,
1471                                                          f->cookie);
1472         if (!mall_tc_entry) {
1473                 netdev_dbg(mlxsw_sp_port->dev, "tc entry not found on port\n");
1474                 return;
1475         }
1476         list_del(&mall_tc_entry->list);
1477
1478         switch (mall_tc_entry->type) {
1479         case MLXSW_SP_PORT_MALL_MIRROR:
1480                 mlxsw_sp_port_del_cls_matchall_mirror(mlxsw_sp_port,
1481                                                       &mall_tc_entry->mirror);
1482                 break;
1483         case MLXSW_SP_PORT_MALL_SAMPLE:
1484                 mlxsw_sp_port_del_cls_matchall_sample(mlxsw_sp_port);
1485                 break;
1486         default:
1487                 WARN_ON(1);
1488         }
1489
1490         kfree(mall_tc_entry);
1491 }
1492
1493 static int mlxsw_sp_setup_tc_cls_matchall(struct mlxsw_sp_port *mlxsw_sp_port,
1494                                           struct tc_cls_matchall_offload *f,
1495                                           bool ingress)
1496 {
1497         switch (f->command) {
1498         case TC_CLSMATCHALL_REPLACE:
1499                 return mlxsw_sp_port_add_cls_matchall(mlxsw_sp_port, f,
1500                                                       ingress);
1501         case TC_CLSMATCHALL_DESTROY:
1502                 mlxsw_sp_port_del_cls_matchall(mlxsw_sp_port, f);
1503                 return 0;
1504         default:
1505                 return -EOPNOTSUPP;
1506         }
1507 }
1508
1509 static int
1510 mlxsw_sp_setup_tc_cls_flower(struct mlxsw_sp_acl_block *acl_block,
1511                              struct flow_cls_offload *f)
1512 {
1513         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_acl_block_mlxsw_sp(acl_block);
1514
1515         switch (f->command) {
1516         case FLOW_CLS_REPLACE:
1517                 return mlxsw_sp_flower_replace(mlxsw_sp, acl_block, f);
1518         case FLOW_CLS_DESTROY:
1519                 mlxsw_sp_flower_destroy(mlxsw_sp, acl_block, f);
1520                 return 0;
1521         case FLOW_CLS_STATS:
1522                 return mlxsw_sp_flower_stats(mlxsw_sp, acl_block, f);
1523         case FLOW_CLS_TMPLT_CREATE:
1524                 return mlxsw_sp_flower_tmplt_create(mlxsw_sp, acl_block, f);
1525         case FLOW_CLS_TMPLT_DESTROY:
1526                 mlxsw_sp_flower_tmplt_destroy(mlxsw_sp, acl_block, f);
1527                 return 0;
1528         default:
1529                 return -EOPNOTSUPP;
1530         }
1531 }
1532
1533 static int mlxsw_sp_setup_tc_block_cb_matchall(enum tc_setup_type type,
1534                                                void *type_data,
1535                                                void *cb_priv, bool ingress)
1536 {
1537         struct mlxsw_sp_port *mlxsw_sp_port = cb_priv;
1538
1539         switch (type) {
1540         case TC_SETUP_CLSMATCHALL:
1541                 if (!tc_cls_can_offload_and_chain0(mlxsw_sp_port->dev,
1542                                                    type_data))
1543                         return -EOPNOTSUPP;
1544
1545                 return mlxsw_sp_setup_tc_cls_matchall(mlxsw_sp_port, type_data,
1546                                                       ingress);
1547         case TC_SETUP_CLSFLOWER:
1548                 return 0;
1549         default:
1550                 return -EOPNOTSUPP;
1551         }
1552 }
1553
1554 static int mlxsw_sp_setup_tc_block_cb_matchall_ig(enum tc_setup_type type,
1555                                                   void *type_data,
1556                                                   void *cb_priv)
1557 {
1558         return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1559                                                    cb_priv, true);
1560 }
1561
1562 static int mlxsw_sp_setup_tc_block_cb_matchall_eg(enum tc_setup_type type,
1563                                                   void *type_data,
1564                                                   void *cb_priv)
1565 {
1566         return mlxsw_sp_setup_tc_block_cb_matchall(type, type_data,
1567                                                    cb_priv, false);
1568 }
1569
1570 static int mlxsw_sp_setup_tc_block_cb_flower(enum tc_setup_type type,
1571                                              void *type_data, void *cb_priv)
1572 {
1573         struct mlxsw_sp_acl_block *acl_block = cb_priv;
1574
1575         switch (type) {
1576         case TC_SETUP_CLSMATCHALL:
1577                 return 0;
1578         case TC_SETUP_CLSFLOWER:
1579                 if (mlxsw_sp_acl_block_disabled(acl_block))
1580                         return -EOPNOTSUPP;
1581
1582                 return mlxsw_sp_setup_tc_cls_flower(acl_block, type_data);
1583         default:
1584                 return -EOPNOTSUPP;
1585         }
1586 }
1587
1588 static void mlxsw_sp_tc_block_flower_release(void *cb_priv)
1589 {
1590         struct mlxsw_sp_acl_block *acl_block = cb_priv;
1591
1592         mlxsw_sp_acl_block_destroy(acl_block);
1593 }
1594
1595 static LIST_HEAD(mlxsw_sp_block_cb_list);
1596
1597 static int
1598 mlxsw_sp_setup_tc_block_flower_bind(struct mlxsw_sp_port *mlxsw_sp_port,
1599                                     struct flow_block_offload *f, bool ingress)
1600 {
1601         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1602         struct mlxsw_sp_acl_block *acl_block;
1603         struct flow_block_cb *block_cb;
1604         bool register_block = false;
1605         int err;
1606
1607         block_cb = flow_block_cb_lookup(f->block,
1608                                         mlxsw_sp_setup_tc_block_cb_flower,
1609                                         mlxsw_sp);
1610         if (!block_cb) {
1611                 acl_block = mlxsw_sp_acl_block_create(mlxsw_sp, f->net);
1612                 if (!acl_block)
1613                         return -ENOMEM;
1614                 block_cb = flow_block_cb_alloc(mlxsw_sp_setup_tc_block_cb_flower,
1615                                                mlxsw_sp, acl_block,
1616                                                mlxsw_sp_tc_block_flower_release);
1617                 if (IS_ERR(block_cb)) {
1618                         mlxsw_sp_acl_block_destroy(acl_block);
1619                         err = PTR_ERR(block_cb);
1620                         goto err_cb_register;
1621                 }
1622                 register_block = true;
1623         } else {
1624                 acl_block = flow_block_cb_priv(block_cb);
1625         }
1626         flow_block_cb_incref(block_cb);
1627         err = mlxsw_sp_acl_block_bind(mlxsw_sp, acl_block,
1628                                       mlxsw_sp_port, ingress, f->extack);
1629         if (err)
1630                 goto err_block_bind;
1631
1632         if (ingress)
1633                 mlxsw_sp_port->ing_acl_block = acl_block;
1634         else
1635                 mlxsw_sp_port->eg_acl_block = acl_block;
1636
1637         if (register_block) {
1638                 flow_block_cb_add(block_cb, f);
1639                 list_add_tail(&block_cb->driver_list, &mlxsw_sp_block_cb_list);
1640         }
1641
1642         return 0;
1643
1644 err_block_bind:
1645         if (!flow_block_cb_decref(block_cb))
1646                 flow_block_cb_free(block_cb);
1647 err_cb_register:
1648         return err;
1649 }
1650
1651 static void
1652 mlxsw_sp_setup_tc_block_flower_unbind(struct mlxsw_sp_port *mlxsw_sp_port,
1653                                       struct flow_block_offload *f, bool ingress)
1654 {
1655         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1656         struct mlxsw_sp_acl_block *acl_block;
1657         struct flow_block_cb *block_cb;
1658         int err;
1659
1660         block_cb = flow_block_cb_lookup(f->block,
1661                                         mlxsw_sp_setup_tc_block_cb_flower,
1662                                         mlxsw_sp);
1663         if (!block_cb)
1664                 return;
1665
1666         if (ingress)
1667                 mlxsw_sp_port->ing_acl_block = NULL;
1668         else
1669                 mlxsw_sp_port->eg_acl_block = NULL;
1670
1671         acl_block = flow_block_cb_priv(block_cb);
1672         err = mlxsw_sp_acl_block_unbind(mlxsw_sp, acl_block,
1673                                         mlxsw_sp_port, ingress);
1674         if (!err && !flow_block_cb_decref(block_cb)) {
1675                 flow_block_cb_remove(block_cb, f);
1676                 list_del(&block_cb->driver_list);
1677         }
1678 }
1679
1680 static int mlxsw_sp_setup_tc_block(struct mlxsw_sp_port *mlxsw_sp_port,
1681                                    struct flow_block_offload *f)
1682 {
1683         struct flow_block_cb *block_cb;
1684         flow_setup_cb_t *cb;
1685         bool ingress;
1686         int err;
1687
1688         if (f->binder_type == FLOW_BLOCK_BINDER_TYPE_CLSACT_INGRESS) {
1689                 cb = mlxsw_sp_setup_tc_block_cb_matchall_ig;
1690                 ingress = true;
1691         } else if (f->binder_type == FLOW_BLOCK_BINDER_TYPE_CLSACT_EGRESS) {
1692                 cb = mlxsw_sp_setup_tc_block_cb_matchall_eg;
1693                 ingress = false;
1694         } else {
1695                 return -EOPNOTSUPP;
1696         }
1697
1698         f->driver_block_list = &mlxsw_sp_block_cb_list;
1699
1700         switch (f->command) {
1701         case FLOW_BLOCK_BIND:
1702                 if (flow_block_cb_is_busy(cb, mlxsw_sp_port,
1703                                           &mlxsw_sp_block_cb_list))
1704                         return -EBUSY;
1705
1706                 block_cb = flow_block_cb_alloc(cb, mlxsw_sp_port,
1707                                                mlxsw_sp_port, NULL);
1708                 if (IS_ERR(block_cb))
1709                         return PTR_ERR(block_cb);
1710                 err = mlxsw_sp_setup_tc_block_flower_bind(mlxsw_sp_port, f,
1711                                                           ingress);
1712                 if (err) {
1713                         flow_block_cb_free(block_cb);
1714                         return err;
1715                 }
1716                 flow_block_cb_add(block_cb, f);
1717                 list_add_tail(&block_cb->driver_list, &mlxsw_sp_block_cb_list);
1718                 return 0;
1719         case FLOW_BLOCK_UNBIND:
1720                 mlxsw_sp_setup_tc_block_flower_unbind(mlxsw_sp_port,
1721                                                       f, ingress);
1722                 block_cb = flow_block_cb_lookup(f->block, cb, mlxsw_sp_port);
1723                 if (!block_cb)
1724                         return -ENOENT;
1725
1726                 flow_block_cb_remove(block_cb, f);
1727                 list_del(&block_cb->driver_list);
1728                 return 0;
1729         default:
1730                 return -EOPNOTSUPP;
1731         }
1732 }
1733
1734 static int mlxsw_sp_setup_tc(struct net_device *dev, enum tc_setup_type type,
1735                              void *type_data)
1736 {
1737         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1738
1739         switch (type) {
1740         case TC_SETUP_BLOCK:
1741                 return mlxsw_sp_setup_tc_block(mlxsw_sp_port, type_data);
1742         case TC_SETUP_QDISC_RED:
1743                 return mlxsw_sp_setup_tc_red(mlxsw_sp_port, type_data);
1744         case TC_SETUP_QDISC_PRIO:
1745                 return mlxsw_sp_setup_tc_prio(mlxsw_sp_port, type_data);
1746         default:
1747                 return -EOPNOTSUPP;
1748         }
1749 }
1750
1751
1752 static int mlxsw_sp_feature_hw_tc(struct net_device *dev, bool enable)
1753 {
1754         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1755
1756         if (!enable) {
1757                 if (mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->ing_acl_block) ||
1758                     mlxsw_sp_acl_block_rule_count(mlxsw_sp_port->eg_acl_block) ||
1759                     !list_empty(&mlxsw_sp_port->mall_tc_list)) {
1760                         netdev_err(dev, "Active offloaded tc filters, can't turn hw_tc_offload off\n");
1761                         return -EINVAL;
1762                 }
1763                 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->ing_acl_block);
1764                 mlxsw_sp_acl_block_disable_inc(mlxsw_sp_port->eg_acl_block);
1765         } else {
1766                 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->ing_acl_block);
1767                 mlxsw_sp_acl_block_disable_dec(mlxsw_sp_port->eg_acl_block);
1768         }
1769         return 0;
1770 }
1771
1772 static int mlxsw_sp_feature_loopback(struct net_device *dev, bool enable)
1773 {
1774         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1775         char pplr_pl[MLXSW_REG_PPLR_LEN];
1776         int err;
1777
1778         if (netif_running(dev))
1779                 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
1780
1781         mlxsw_reg_pplr_pack(pplr_pl, mlxsw_sp_port->local_port, enable);
1782         err = mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pplr),
1783                               pplr_pl);
1784
1785         if (netif_running(dev))
1786                 mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
1787
1788         return err;
1789 }
1790
1791 typedef int (*mlxsw_sp_feature_handler)(struct net_device *dev, bool enable);
1792
1793 static int mlxsw_sp_handle_feature(struct net_device *dev,
1794                                    netdev_features_t wanted_features,
1795                                    netdev_features_t feature,
1796                                    mlxsw_sp_feature_handler feature_handler)
1797 {
1798         netdev_features_t changes = wanted_features ^ dev->features;
1799         bool enable = !!(wanted_features & feature);
1800         int err;
1801
1802         if (!(changes & feature))
1803                 return 0;
1804
1805         err = feature_handler(dev, enable);
1806         if (err) {
1807                 netdev_err(dev, "%s feature %pNF failed, err %d\n",
1808                            enable ? "Enable" : "Disable", &feature, err);
1809                 return err;
1810         }
1811
1812         if (enable)
1813                 dev->features |= feature;
1814         else
1815                 dev->features &= ~feature;
1816
1817         return 0;
1818 }
1819 static int mlxsw_sp_set_features(struct net_device *dev,
1820                                  netdev_features_t features)
1821 {
1822         netdev_features_t oper_features = dev->features;
1823         int err = 0;
1824
1825         err |= mlxsw_sp_handle_feature(dev, features, NETIF_F_HW_TC,
1826                                        mlxsw_sp_feature_hw_tc);
1827         err |= mlxsw_sp_handle_feature(dev, features, NETIF_F_LOOPBACK,
1828                                        mlxsw_sp_feature_loopback);
1829
1830         if (err) {
1831                 dev->features = oper_features;
1832                 return -EINVAL;
1833         }
1834
1835         return 0;
1836 }
1837
1838 static struct devlink_port *
1839 mlxsw_sp_port_get_devlink_port(struct net_device *dev)
1840 {
1841         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1842         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1843
1844         return mlxsw_core_port_devlink_port_get(mlxsw_sp->core,
1845                                                 mlxsw_sp_port->local_port);
1846 }
1847
1848 static int mlxsw_sp_port_hwtstamp_set(struct mlxsw_sp_port *mlxsw_sp_port,
1849                                       struct ifreq *ifr)
1850 {
1851         struct hwtstamp_config config;
1852         int err;
1853
1854         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1855                 return -EFAULT;
1856
1857         err = mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port,
1858                                                              &config);
1859         if (err)
1860                 return err;
1861
1862         if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
1863                 return -EFAULT;
1864
1865         return 0;
1866 }
1867
1868 static int mlxsw_sp_port_hwtstamp_get(struct mlxsw_sp_port *mlxsw_sp_port,
1869                                       struct ifreq *ifr)
1870 {
1871         struct hwtstamp_config config;
1872         int err;
1873
1874         err = mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_get(mlxsw_sp_port,
1875                                                              &config);
1876         if (err)
1877                 return err;
1878
1879         if (copy_to_user(ifr->ifr_data, &config, sizeof(config)))
1880                 return -EFAULT;
1881
1882         return 0;
1883 }
1884
1885 static inline void mlxsw_sp_port_ptp_clear(struct mlxsw_sp_port *mlxsw_sp_port)
1886 {
1887         struct hwtstamp_config config = {0};
1888
1889         mlxsw_sp_port->mlxsw_sp->ptp_ops->hwtstamp_set(mlxsw_sp_port, &config);
1890 }
1891
1892 static int
1893 mlxsw_sp_port_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1894 {
1895         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1896
1897         switch (cmd) {
1898         case SIOCSHWTSTAMP:
1899                 return mlxsw_sp_port_hwtstamp_set(mlxsw_sp_port, ifr);
1900         case SIOCGHWTSTAMP:
1901                 return mlxsw_sp_port_hwtstamp_get(mlxsw_sp_port, ifr);
1902         default:
1903                 return -EOPNOTSUPP;
1904         }
1905 }
1906
1907 static const struct net_device_ops mlxsw_sp_port_netdev_ops = {
1908         .ndo_open               = mlxsw_sp_port_open,
1909         .ndo_stop               = mlxsw_sp_port_stop,
1910         .ndo_start_xmit         = mlxsw_sp_port_xmit,
1911         .ndo_setup_tc           = mlxsw_sp_setup_tc,
1912         .ndo_set_rx_mode        = mlxsw_sp_set_rx_mode,
1913         .ndo_set_mac_address    = mlxsw_sp_port_set_mac_address,
1914         .ndo_change_mtu         = mlxsw_sp_port_change_mtu,
1915         .ndo_get_stats64        = mlxsw_sp_port_get_stats64,
1916         .ndo_has_offload_stats  = mlxsw_sp_port_has_offload_stats,
1917         .ndo_get_offload_stats  = mlxsw_sp_port_get_offload_stats,
1918         .ndo_vlan_rx_add_vid    = mlxsw_sp_port_add_vid,
1919         .ndo_vlan_rx_kill_vid   = mlxsw_sp_port_kill_vid,
1920         .ndo_set_features       = mlxsw_sp_set_features,
1921         .ndo_get_devlink_port   = mlxsw_sp_port_get_devlink_port,
1922         .ndo_do_ioctl           = mlxsw_sp_port_ioctl,
1923 };
1924
1925 static void mlxsw_sp_port_get_drvinfo(struct net_device *dev,
1926                                       struct ethtool_drvinfo *drvinfo)
1927 {
1928         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1929         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
1930
1931         strlcpy(drvinfo->driver, mlxsw_sp->bus_info->device_kind,
1932                 sizeof(drvinfo->driver));
1933         strlcpy(drvinfo->version, mlxsw_sp_driver_version,
1934                 sizeof(drvinfo->version));
1935         snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1936                  "%d.%d.%d",
1937                  mlxsw_sp->bus_info->fw_rev.major,
1938                  mlxsw_sp->bus_info->fw_rev.minor,
1939                  mlxsw_sp->bus_info->fw_rev.subminor);
1940         strlcpy(drvinfo->bus_info, mlxsw_sp->bus_info->device_name,
1941                 sizeof(drvinfo->bus_info));
1942 }
1943
1944 static void mlxsw_sp_port_get_pauseparam(struct net_device *dev,
1945                                          struct ethtool_pauseparam *pause)
1946 {
1947         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1948
1949         pause->rx_pause = mlxsw_sp_port->link.rx_pause;
1950         pause->tx_pause = mlxsw_sp_port->link.tx_pause;
1951 }
1952
1953 static int mlxsw_sp_port_pause_set(struct mlxsw_sp_port *mlxsw_sp_port,
1954                                    struct ethtool_pauseparam *pause)
1955 {
1956         char pfcc_pl[MLXSW_REG_PFCC_LEN];
1957
1958         mlxsw_reg_pfcc_pack(pfcc_pl, mlxsw_sp_port->local_port);
1959         mlxsw_reg_pfcc_pprx_set(pfcc_pl, pause->rx_pause);
1960         mlxsw_reg_pfcc_pptx_set(pfcc_pl, pause->tx_pause);
1961
1962         return mlxsw_reg_write(mlxsw_sp_port->mlxsw_sp->core, MLXSW_REG(pfcc),
1963                                pfcc_pl);
1964 }
1965
1966 static int mlxsw_sp_port_set_pauseparam(struct net_device *dev,
1967                                         struct ethtool_pauseparam *pause)
1968 {
1969         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
1970         bool pause_en = pause->tx_pause || pause->rx_pause;
1971         int err;
1972
1973         if (mlxsw_sp_port->dcb.pfc && mlxsw_sp_port->dcb.pfc->pfc_en) {
1974                 netdev_err(dev, "PFC already enabled on port\n");
1975                 return -EINVAL;
1976         }
1977
1978         if (pause->autoneg) {
1979                 netdev_err(dev, "PAUSE frames autonegotiation isn't supported\n");
1980                 return -EINVAL;
1981         }
1982
1983         err = mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
1984         if (err) {
1985                 netdev_err(dev, "Failed to configure port's headroom\n");
1986                 return err;
1987         }
1988
1989         err = mlxsw_sp_port_pause_set(mlxsw_sp_port, pause);
1990         if (err) {
1991                 netdev_err(dev, "Failed to set PAUSE parameters\n");
1992                 goto err_port_pause_configure;
1993         }
1994
1995         mlxsw_sp_port->link.rx_pause = pause->rx_pause;
1996         mlxsw_sp_port->link.tx_pause = pause->tx_pause;
1997
1998         return 0;
1999
2000 err_port_pause_configure:
2001         pause_en = mlxsw_sp_port_is_pause_en(mlxsw_sp_port);
2002         mlxsw_sp_port_headroom_set(mlxsw_sp_port, dev->mtu, pause_en);
2003         return err;
2004 }
2005
2006 struct mlxsw_sp_port_hw_stats {
2007         char str[ETH_GSTRING_LEN];
2008         u64 (*getter)(const char *payload);
2009         bool cells_bytes;
2010 };
2011
2012 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_stats[] = {
2013         {
2014                 .str = "a_frames_transmitted_ok",
2015                 .getter = mlxsw_reg_ppcnt_a_frames_transmitted_ok_get,
2016         },
2017         {
2018                 .str = "a_frames_received_ok",
2019                 .getter = mlxsw_reg_ppcnt_a_frames_received_ok_get,
2020         },
2021         {
2022                 .str = "a_frame_check_sequence_errors",
2023                 .getter = mlxsw_reg_ppcnt_a_frame_check_sequence_errors_get,
2024         },
2025         {
2026                 .str = "a_alignment_errors",
2027                 .getter = mlxsw_reg_ppcnt_a_alignment_errors_get,
2028         },
2029         {
2030                 .str = "a_octets_transmitted_ok",
2031                 .getter = mlxsw_reg_ppcnt_a_octets_transmitted_ok_get,
2032         },
2033         {
2034                 .str = "a_octets_received_ok",
2035                 .getter = mlxsw_reg_ppcnt_a_octets_received_ok_get,
2036         },
2037         {
2038                 .str = "a_multicast_frames_xmitted_ok",
2039                 .getter = mlxsw_reg_ppcnt_a_multicast_frames_xmitted_ok_get,
2040         },
2041         {
2042                 .str = "a_broadcast_frames_xmitted_ok",
2043                 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_xmitted_ok_get,
2044         },
2045         {
2046                 .str = "a_multicast_frames_received_ok",
2047                 .getter = mlxsw_reg_ppcnt_a_multicast_frames_received_ok_get,
2048         },
2049         {
2050                 .str = "a_broadcast_frames_received_ok",
2051                 .getter = mlxsw_reg_ppcnt_a_broadcast_frames_received_ok_get,
2052         },
2053         {
2054                 .str = "a_in_range_length_errors",
2055                 .getter = mlxsw_reg_ppcnt_a_in_range_length_errors_get,
2056         },
2057         {
2058                 .str = "a_out_of_range_length_field",
2059                 .getter = mlxsw_reg_ppcnt_a_out_of_range_length_field_get,
2060         },
2061         {
2062                 .str = "a_frame_too_long_errors",
2063                 .getter = mlxsw_reg_ppcnt_a_frame_too_long_errors_get,
2064         },
2065         {
2066                 .str = "a_symbol_error_during_carrier",
2067                 .getter = mlxsw_reg_ppcnt_a_symbol_error_during_carrier_get,
2068         },
2069         {
2070                 .str = "a_mac_control_frames_transmitted",
2071                 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_transmitted_get,
2072         },
2073         {
2074                 .str = "a_mac_control_frames_received",
2075                 .getter = mlxsw_reg_ppcnt_a_mac_control_frames_received_get,
2076         },
2077         {
2078                 .str = "a_unsupported_opcodes_received",
2079                 .getter = mlxsw_reg_ppcnt_a_unsupported_opcodes_received_get,
2080         },
2081         {
2082                 .str = "a_pause_mac_ctrl_frames_received",
2083                 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_received_get,
2084         },
2085         {
2086                 .str = "a_pause_mac_ctrl_frames_xmitted",
2087                 .getter = mlxsw_reg_ppcnt_a_pause_mac_ctrl_frames_transmitted_get,
2088         },
2089 };
2090
2091 #define MLXSW_SP_PORT_HW_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_stats)
2092
2093 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_2863_stats[] = {
2094         {
2095                 .str = "if_in_discards",
2096                 .getter = mlxsw_reg_ppcnt_if_in_discards_get,
2097         },
2098         {
2099                 .str = "if_out_discards",
2100                 .getter = mlxsw_reg_ppcnt_if_out_discards_get,
2101         },
2102         {
2103                 .str = "if_out_errors",
2104                 .getter = mlxsw_reg_ppcnt_if_out_errors_get,
2105         },
2106 };
2107
2108 #define MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN \
2109         ARRAY_SIZE(mlxsw_sp_port_hw_rfc_2863_stats)
2110
2111 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_2819_stats[] = {
2112         {
2113                 .str = "ether_stats_undersize_pkts",
2114                 .getter = mlxsw_reg_ppcnt_ether_stats_undersize_pkts_get,
2115         },
2116         {
2117                 .str = "ether_stats_oversize_pkts",
2118                 .getter = mlxsw_reg_ppcnt_ether_stats_oversize_pkts_get,
2119         },
2120         {
2121                 .str = "ether_stats_fragments",
2122                 .getter = mlxsw_reg_ppcnt_ether_stats_fragments_get,
2123         },
2124         {
2125                 .str = "ether_pkts64octets",
2126                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts64octets_get,
2127         },
2128         {
2129                 .str = "ether_pkts65to127octets",
2130                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts65to127octets_get,
2131         },
2132         {
2133                 .str = "ether_pkts128to255octets",
2134                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts128to255octets_get,
2135         },
2136         {
2137                 .str = "ether_pkts256to511octets",
2138                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts256to511octets_get,
2139         },
2140         {
2141                 .str = "ether_pkts512to1023octets",
2142                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts512to1023octets_get,
2143         },
2144         {
2145                 .str = "ether_pkts1024to1518octets",
2146                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts1024to1518octets_get,
2147         },
2148         {
2149                 .str = "ether_pkts1519to2047octets",
2150                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts1519to2047octets_get,
2151         },
2152         {
2153                 .str = "ether_pkts2048to4095octets",
2154                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts2048to4095octets_get,
2155         },
2156         {
2157                 .str = "ether_pkts4096to8191octets",
2158                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts4096to8191octets_get,
2159         },
2160         {
2161                 .str = "ether_pkts8192to10239octets",
2162                 .getter = mlxsw_reg_ppcnt_ether_stats_pkts8192to10239octets_get,
2163         },
2164 };
2165
2166 #define MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN \
2167         ARRAY_SIZE(mlxsw_sp_port_hw_rfc_2819_stats)
2168
2169 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_rfc_3635_stats[] = {
2170         {
2171                 .str = "dot3stats_fcs_errors",
2172                 .getter = mlxsw_reg_ppcnt_dot3stats_fcs_errors_get,
2173         },
2174         {
2175                 .str = "dot3stats_symbol_errors",
2176                 .getter = mlxsw_reg_ppcnt_dot3stats_symbol_errors_get,
2177         },
2178         {
2179                 .str = "dot3control_in_unknown_opcodes",
2180                 .getter = mlxsw_reg_ppcnt_dot3control_in_unknown_opcodes_get,
2181         },
2182         {
2183                 .str = "dot3in_pause_frames",
2184                 .getter = mlxsw_reg_ppcnt_dot3in_pause_frames_get,
2185         },
2186 };
2187
2188 #define MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN \
2189         ARRAY_SIZE(mlxsw_sp_port_hw_rfc_3635_stats)
2190
2191 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_discard_stats[] = {
2192         {
2193                 .str = "discard_ingress_general",
2194                 .getter = mlxsw_reg_ppcnt_ingress_general_get,
2195         },
2196         {
2197                 .str = "discard_ingress_policy_engine",
2198                 .getter = mlxsw_reg_ppcnt_ingress_policy_engine_get,
2199         },
2200         {
2201                 .str = "discard_ingress_vlan_membership",
2202                 .getter = mlxsw_reg_ppcnt_ingress_vlan_membership_get,
2203         },
2204         {
2205                 .str = "discard_ingress_tag_frame_type",
2206                 .getter = mlxsw_reg_ppcnt_ingress_tag_frame_type_get,
2207         },
2208         {
2209                 .str = "discard_egress_vlan_membership",
2210                 .getter = mlxsw_reg_ppcnt_egress_vlan_membership_get,
2211         },
2212         {
2213                 .str = "discard_loopback_filter",
2214                 .getter = mlxsw_reg_ppcnt_loopback_filter_get,
2215         },
2216         {
2217                 .str = "discard_egress_general",
2218                 .getter = mlxsw_reg_ppcnt_egress_general_get,
2219         },
2220         {
2221                 .str = "discard_egress_hoq",
2222                 .getter = mlxsw_reg_ppcnt_egress_hoq_get,
2223         },
2224         {
2225                 .str = "discard_egress_policy_engine",
2226                 .getter = mlxsw_reg_ppcnt_egress_policy_engine_get,
2227         },
2228         {
2229                 .str = "discard_ingress_tx_link_down",
2230                 .getter = mlxsw_reg_ppcnt_ingress_tx_link_down_get,
2231         },
2232         {
2233                 .str = "discard_egress_stp_filter",
2234                 .getter = mlxsw_reg_ppcnt_egress_stp_filter_get,
2235         },
2236         {
2237                 .str = "discard_egress_sll",
2238                 .getter = mlxsw_reg_ppcnt_egress_sll_get,
2239         },
2240 };
2241
2242 #define MLXSW_SP_PORT_HW_DISCARD_STATS_LEN \
2243         ARRAY_SIZE(mlxsw_sp_port_hw_discard_stats)
2244
2245 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_prio_stats[] = {
2246         {
2247                 .str = "rx_octets_prio",
2248                 .getter = mlxsw_reg_ppcnt_rx_octets_get,
2249         },
2250         {
2251                 .str = "rx_frames_prio",
2252                 .getter = mlxsw_reg_ppcnt_rx_frames_get,
2253         },
2254         {
2255                 .str = "tx_octets_prio",
2256                 .getter = mlxsw_reg_ppcnt_tx_octets_get,
2257         },
2258         {
2259                 .str = "tx_frames_prio",
2260                 .getter = mlxsw_reg_ppcnt_tx_frames_get,
2261         },
2262         {
2263                 .str = "rx_pause_prio",
2264                 .getter = mlxsw_reg_ppcnt_rx_pause_get,
2265         },
2266         {
2267                 .str = "rx_pause_duration_prio",
2268                 .getter = mlxsw_reg_ppcnt_rx_pause_duration_get,
2269         },
2270         {
2271                 .str = "tx_pause_prio",
2272                 .getter = mlxsw_reg_ppcnt_tx_pause_get,
2273         },
2274         {
2275                 .str = "tx_pause_duration_prio",
2276                 .getter = mlxsw_reg_ppcnt_tx_pause_duration_get,
2277         },
2278 };
2279
2280 #define MLXSW_SP_PORT_HW_PRIO_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_prio_stats)
2281
2282 static struct mlxsw_sp_port_hw_stats mlxsw_sp_port_hw_tc_stats[] = {
2283         {
2284                 .str = "tc_transmit_queue_tc",
2285                 .getter = mlxsw_reg_ppcnt_tc_transmit_queue_get,
2286                 .cells_bytes = true,
2287         },
2288         {
2289                 .str = "tc_no_buffer_discard_uc_tc",
2290                 .getter = mlxsw_reg_ppcnt_tc_no_buffer_discard_uc_get,
2291         },
2292 };
2293
2294 #define MLXSW_SP_PORT_HW_TC_STATS_LEN ARRAY_SIZE(mlxsw_sp_port_hw_tc_stats)
2295
2296 #define MLXSW_SP_PORT_ETHTOOL_STATS_LEN (MLXSW_SP_PORT_HW_STATS_LEN + \
2297                                          MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN + \
2298                                          MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN + \
2299                                          MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN + \
2300                                          MLXSW_SP_PORT_HW_DISCARD_STATS_LEN + \
2301                                          (MLXSW_SP_PORT_HW_PRIO_STATS_LEN * \
2302                                           IEEE_8021QAZ_MAX_TCS) + \
2303                                          (MLXSW_SP_PORT_HW_TC_STATS_LEN * \
2304                                           TC_MAX_QUEUE))
2305
2306 static void mlxsw_sp_port_get_prio_strings(u8 **p, int prio)
2307 {
2308         int i;
2309
2310         for (i = 0; i < MLXSW_SP_PORT_HW_PRIO_STATS_LEN; i++) {
2311                 snprintf(*p, ETH_GSTRING_LEN, "%.29s_%.1d",
2312                          mlxsw_sp_port_hw_prio_stats[i].str, prio);
2313                 *p += ETH_GSTRING_LEN;
2314         }
2315 }
2316
2317 static void mlxsw_sp_port_get_tc_strings(u8 **p, int tc)
2318 {
2319         int i;
2320
2321         for (i = 0; i < MLXSW_SP_PORT_HW_TC_STATS_LEN; i++) {
2322                 snprintf(*p, ETH_GSTRING_LEN, "%.29s_%.1d",
2323                          mlxsw_sp_port_hw_tc_stats[i].str, tc);
2324                 *p += ETH_GSTRING_LEN;
2325         }
2326 }
2327
2328 static void mlxsw_sp_port_get_strings(struct net_device *dev,
2329                                       u32 stringset, u8 *data)
2330 {
2331         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2332         u8 *p = data;
2333         int i;
2334
2335         switch (stringset) {
2336         case ETH_SS_STATS:
2337                 for (i = 0; i < MLXSW_SP_PORT_HW_STATS_LEN; i++) {
2338                         memcpy(p, mlxsw_sp_port_hw_stats[i].str,
2339                                ETH_GSTRING_LEN);
2340                         p += ETH_GSTRING_LEN;
2341                 }
2342
2343                 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN; i++) {
2344                         memcpy(p, mlxsw_sp_port_hw_rfc_2863_stats[i].str,
2345                                ETH_GSTRING_LEN);
2346                         p += ETH_GSTRING_LEN;
2347                 }
2348
2349                 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN; i++) {
2350                         memcpy(p, mlxsw_sp_port_hw_rfc_2819_stats[i].str,
2351                                ETH_GSTRING_LEN);
2352                         p += ETH_GSTRING_LEN;
2353                 }
2354
2355                 for (i = 0; i < MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN; i++) {
2356                         memcpy(p, mlxsw_sp_port_hw_rfc_3635_stats[i].str,
2357                                ETH_GSTRING_LEN);
2358                         p += ETH_GSTRING_LEN;
2359                 }
2360
2361                 for (i = 0; i < MLXSW_SP_PORT_HW_DISCARD_STATS_LEN; i++) {
2362                         memcpy(p, mlxsw_sp_port_hw_discard_stats[i].str,
2363                                ETH_GSTRING_LEN);
2364                         p += ETH_GSTRING_LEN;
2365                 }
2366
2367                 for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++)
2368                         mlxsw_sp_port_get_prio_strings(&p, i);
2369
2370                 for (i = 0; i < TC_MAX_QUEUE; i++)
2371                         mlxsw_sp_port_get_tc_strings(&p, i);
2372
2373                 mlxsw_sp_port->mlxsw_sp->ptp_ops->get_stats_strings(&p);
2374                 break;
2375         }
2376 }
2377
2378 static int mlxsw_sp_port_set_phys_id(struct net_device *dev,
2379                                      enum ethtool_phys_id_state state)
2380 {
2381         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2382         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2383         char mlcr_pl[MLXSW_REG_MLCR_LEN];
2384         bool active;
2385
2386         switch (state) {
2387         case ETHTOOL_ID_ACTIVE:
2388                 active = true;
2389                 break;
2390         case ETHTOOL_ID_INACTIVE:
2391                 active = false;
2392                 break;
2393         default:
2394                 return -EOPNOTSUPP;
2395         }
2396
2397         mlxsw_reg_mlcr_pack(mlcr_pl, mlxsw_sp_port->local_port, active);
2398         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(mlcr), mlcr_pl);
2399 }
2400
2401 static int
2402 mlxsw_sp_get_hw_stats_by_group(struct mlxsw_sp_port_hw_stats **p_hw_stats,
2403                                int *p_len, enum mlxsw_reg_ppcnt_grp grp)
2404 {
2405         switch (grp) {
2406         case MLXSW_REG_PPCNT_IEEE_8023_CNT:
2407                 *p_hw_stats = mlxsw_sp_port_hw_stats;
2408                 *p_len = MLXSW_SP_PORT_HW_STATS_LEN;
2409                 break;
2410         case MLXSW_REG_PPCNT_RFC_2863_CNT:
2411                 *p_hw_stats = mlxsw_sp_port_hw_rfc_2863_stats;
2412                 *p_len = MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN;
2413                 break;
2414         case MLXSW_REG_PPCNT_RFC_2819_CNT:
2415                 *p_hw_stats = mlxsw_sp_port_hw_rfc_2819_stats;
2416                 *p_len = MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN;
2417                 break;
2418         case MLXSW_REG_PPCNT_RFC_3635_CNT:
2419                 *p_hw_stats = mlxsw_sp_port_hw_rfc_3635_stats;
2420                 *p_len = MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN;
2421                 break;
2422         case MLXSW_REG_PPCNT_DISCARD_CNT:
2423                 *p_hw_stats = mlxsw_sp_port_hw_discard_stats;
2424                 *p_len = MLXSW_SP_PORT_HW_DISCARD_STATS_LEN;
2425                 break;
2426         case MLXSW_REG_PPCNT_PRIO_CNT:
2427                 *p_hw_stats = mlxsw_sp_port_hw_prio_stats;
2428                 *p_len = MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2429                 break;
2430         case MLXSW_REG_PPCNT_TC_CNT:
2431                 *p_hw_stats = mlxsw_sp_port_hw_tc_stats;
2432                 *p_len = MLXSW_SP_PORT_HW_TC_STATS_LEN;
2433                 break;
2434         default:
2435                 WARN_ON(1);
2436                 return -EOPNOTSUPP;
2437         }
2438         return 0;
2439 }
2440
2441 static void __mlxsw_sp_port_get_stats(struct net_device *dev,
2442                                       enum mlxsw_reg_ppcnt_grp grp, int prio,
2443                                       u64 *data, int data_index)
2444 {
2445         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2446         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
2447         struct mlxsw_sp_port_hw_stats *hw_stats;
2448         char ppcnt_pl[MLXSW_REG_PPCNT_LEN];
2449         int i, len;
2450         int err;
2451
2452         err = mlxsw_sp_get_hw_stats_by_group(&hw_stats, &len, grp);
2453         if (err)
2454                 return;
2455         mlxsw_sp_port_get_stats_raw(dev, grp, prio, ppcnt_pl);
2456         for (i = 0; i < len; i++) {
2457                 data[data_index + i] = hw_stats[i].getter(ppcnt_pl);
2458                 if (!hw_stats[i].cells_bytes)
2459                         continue;
2460                 data[data_index + i] = mlxsw_sp_cells_bytes(mlxsw_sp,
2461                                                             data[data_index + i]);
2462         }
2463 }
2464
2465 static void mlxsw_sp_port_get_stats(struct net_device *dev,
2466                                     struct ethtool_stats *stats, u64 *data)
2467 {
2468         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2469         int i, data_index = 0;
2470
2471         /* IEEE 802.3 Counters */
2472         __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_IEEE_8023_CNT, 0,
2473                                   data, data_index);
2474         data_index = MLXSW_SP_PORT_HW_STATS_LEN;
2475
2476         /* RFC 2863 Counters */
2477         __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_2863_CNT, 0,
2478                                   data, data_index);
2479         data_index += MLXSW_SP_PORT_HW_RFC_2863_STATS_LEN;
2480
2481         /* RFC 2819 Counters */
2482         __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_2819_CNT, 0,
2483                                   data, data_index);
2484         data_index += MLXSW_SP_PORT_HW_RFC_2819_STATS_LEN;
2485
2486         /* RFC 3635 Counters */
2487         __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_RFC_3635_CNT, 0,
2488                                   data, data_index);
2489         data_index += MLXSW_SP_PORT_HW_RFC_3635_STATS_LEN;
2490
2491         /* Discard Counters */
2492         __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_DISCARD_CNT, 0,
2493                                   data, data_index);
2494         data_index += MLXSW_SP_PORT_HW_DISCARD_STATS_LEN;
2495
2496         /* Per-Priority Counters */
2497         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
2498                 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_PRIO_CNT, i,
2499                                           data, data_index);
2500                 data_index += MLXSW_SP_PORT_HW_PRIO_STATS_LEN;
2501         }
2502
2503         /* Per-TC Counters */
2504         for (i = 0; i < TC_MAX_QUEUE; i++) {
2505                 __mlxsw_sp_port_get_stats(dev, MLXSW_REG_PPCNT_TC_CNT, i,
2506                                           data, data_index);
2507                 data_index += MLXSW_SP_PORT_HW_TC_STATS_LEN;
2508         }
2509
2510         /* PTP counters */
2511         mlxsw_sp_port->mlxsw_sp->ptp_ops->get_stats(mlxsw_sp_port,
2512                                                     data, data_index);
2513         data_index += mlxsw_sp_port->mlxsw_sp->ptp_ops->get_stats_count();
2514 }
2515
2516 static int mlxsw_sp_port_get_sset_count(struct net_device *dev, int sset)
2517 {
2518         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
2519
2520         switch (sset) {
2521         case ETH_SS_STATS:
2522                 return MLXSW_SP_PORT_ETHTOOL_STATS_LEN +
2523                        mlxsw_sp_port->mlxsw_sp->ptp_ops->get_stats_count();
2524         default:
2525                 return -EOPNOTSUPP;
2526         }
2527 }
2528
2529 struct mlxsw_sp1_port_link_mode {
2530         enum ethtool_link_mode_bit_indices mask_ethtool;
2531         u32 mask;
2532         u32 speed;
2533 };
2534
2535 static const struct mlxsw_sp1_port_link_mode mlxsw_sp1_port_link_mode[] = {
2536         {
2537                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100BASE_T,
2538                 .mask_ethtool   = ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2539                 .speed          = SPEED_100,
2540         },
2541         {
2542                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_SGMII |
2543                                   MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX,
2544                 .mask_ethtool   = ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2545                 .speed          = SPEED_1000,
2546         },
2547         {
2548                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T,
2549                 .mask_ethtool   = ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2550                 .speed          = SPEED_10000,
2551         },
2552         {
2553                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 |
2554                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4,
2555                 .mask_ethtool   = ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT,
2556                 .speed          = SPEED_10000,
2557         },
2558         {
2559                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2560                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2561                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2562                                   MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR,
2563                 .mask_ethtool   = ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2564                 .speed          = SPEED_10000,
2565         },
2566         {
2567                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2,
2568                 .mask_ethtool   = ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT,
2569                 .speed          = SPEED_20000,
2570         },
2571         {
2572                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4,
2573                 .mask_ethtool   = ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2574                 .speed          = SPEED_40000,
2575         },
2576         {
2577                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4,
2578                 .mask_ethtool   = ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2579                 .speed          = SPEED_40000,
2580         },
2581         {
2582                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4,
2583                 .mask_ethtool   = ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2584                 .speed          = SPEED_40000,
2585         },
2586         {
2587                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4,
2588                 .mask_ethtool   = ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2589                 .speed          = SPEED_40000,
2590         },
2591         {
2592                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR,
2593                 .mask_ethtool   = ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2594                 .speed          = SPEED_25000,
2595         },
2596         {
2597                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR,
2598                 .mask_ethtool   = ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2599                 .speed          = SPEED_25000,
2600         },
2601         {
2602                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR,
2603                 .mask_ethtool   = ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2604                 .speed          = SPEED_25000,
2605         },
2606         {
2607                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2,
2608                 .mask_ethtool   = ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2609                 .speed          = SPEED_50000,
2610         },
2611         {
2612                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2,
2613                 .mask_ethtool   = ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2614                 .speed          = SPEED_50000,
2615         },
2616         {
2617                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2,
2618                 .mask_ethtool   = ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2619                 .speed          = SPEED_50000,
2620         },
2621         {
2622                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4,
2623                 .mask_ethtool   = ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2624                 .speed          = SPEED_100000,
2625         },
2626         {
2627                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4,
2628                 .mask_ethtool   = ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2629                 .speed          = SPEED_100000,
2630         },
2631         {
2632                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4,
2633                 .mask_ethtool   = ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2634                 .speed          = SPEED_100000,
2635         },
2636         {
2637                 .mask           = MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4,
2638                 .mask_ethtool   = ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2639                 .speed          = SPEED_100000,
2640         },
2641 };
2642
2643 #define MLXSW_SP1_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp1_port_link_mode)
2644
2645 static void
2646 mlxsw_sp1_from_ptys_supported_port(struct mlxsw_sp *mlxsw_sp,
2647                                    u32 ptys_eth_proto,
2648                                    struct ethtool_link_ksettings *cmd)
2649 {
2650         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR |
2651                               MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR |
2652                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 |
2653                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 |
2654                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 |
2655                               MLXSW_REG_PTYS_ETH_SPEED_SGMII))
2656                 ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
2657
2658         if (ptys_eth_proto & (MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR |
2659                               MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 |
2660                               MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 |
2661                               MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 |
2662                               MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX))
2663                 ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
2664 }
2665
2666 static void
2667 mlxsw_sp1_from_ptys_link(struct mlxsw_sp *mlxsw_sp, u32 ptys_eth_proto,
2668                          u8 width, unsigned long *mode)
2669 {
2670         int i;
2671
2672         for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
2673                 if (ptys_eth_proto & mlxsw_sp1_port_link_mode[i].mask)
2674                         __set_bit(mlxsw_sp1_port_link_mode[i].mask_ethtool,
2675                                   mode);
2676         }
2677 }
2678
2679 static u32
2680 mlxsw_sp1_from_ptys_speed(struct mlxsw_sp *mlxsw_sp, u32 ptys_eth_proto)
2681 {
2682         int i;
2683
2684         for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
2685                 if (ptys_eth_proto & mlxsw_sp1_port_link_mode[i].mask)
2686                         return mlxsw_sp1_port_link_mode[i].speed;
2687         }
2688
2689         return SPEED_UNKNOWN;
2690 }
2691
2692 static void
2693 mlxsw_sp1_from_ptys_speed_duplex(struct mlxsw_sp *mlxsw_sp, bool carrier_ok,
2694                                  u32 ptys_eth_proto,
2695                                  struct ethtool_link_ksettings *cmd)
2696 {
2697         cmd->base.speed = SPEED_UNKNOWN;
2698         cmd->base.duplex = DUPLEX_UNKNOWN;
2699
2700         if (!carrier_ok)
2701                 return;
2702
2703         cmd->base.speed = mlxsw_sp1_from_ptys_speed(mlxsw_sp, ptys_eth_proto);
2704         if (cmd->base.speed != SPEED_UNKNOWN)
2705                 cmd->base.duplex = DUPLEX_FULL;
2706 }
2707
2708 static u32
2709 mlxsw_sp1_to_ptys_advert_link(struct mlxsw_sp *mlxsw_sp, u8 width,
2710                               const struct ethtool_link_ksettings *cmd)
2711 {
2712         u32 ptys_proto = 0;
2713         int i;
2714
2715         for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
2716                 if (test_bit(mlxsw_sp1_port_link_mode[i].mask_ethtool,
2717                              cmd->link_modes.advertising))
2718                         ptys_proto |= mlxsw_sp1_port_link_mode[i].mask;
2719         }
2720         return ptys_proto;
2721 }
2722
2723 static u32 mlxsw_sp1_to_ptys_speed(struct mlxsw_sp *mlxsw_sp, u8 width,
2724                                    u32 speed)
2725 {
2726         u32 ptys_proto = 0;
2727         int i;
2728
2729         for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
2730                 if (speed == mlxsw_sp1_port_link_mode[i].speed)
2731                         ptys_proto |= mlxsw_sp1_port_link_mode[i].mask;
2732         }
2733         return ptys_proto;
2734 }
2735
2736 static u32
2737 mlxsw_sp1_to_ptys_upper_speed(struct mlxsw_sp *mlxsw_sp, u32 upper_speed)
2738 {
2739         u32 ptys_proto = 0;
2740         int i;
2741
2742         for (i = 0; i < MLXSW_SP1_PORT_LINK_MODE_LEN; i++) {
2743                 if (mlxsw_sp1_port_link_mode[i].speed <= upper_speed)
2744                         ptys_proto |= mlxsw_sp1_port_link_mode[i].mask;
2745         }
2746         return ptys_proto;
2747 }
2748
2749 static int
2750 mlxsw_sp1_port_speed_base(struct mlxsw_sp *mlxsw_sp, u8 local_port,
2751                           u32 *base_speed)
2752 {
2753         *base_speed = MLXSW_SP_PORT_BASE_SPEED_25G;
2754         return 0;
2755 }
2756
2757 static void
2758 mlxsw_sp1_reg_ptys_eth_pack(struct mlxsw_sp *mlxsw_sp, char *payload,
2759                             u8 local_port, u32 proto_admin, bool autoneg)
2760 {
2761         mlxsw_reg_ptys_eth_pack(payload, local_port, proto_admin, autoneg);
2762 }
2763
2764 static void
2765 mlxsw_sp1_reg_ptys_eth_unpack(struct mlxsw_sp *mlxsw_sp, char *payload,
2766                               u32 *p_eth_proto_cap, u32 *p_eth_proto_admin,
2767                               u32 *p_eth_proto_oper)
2768 {
2769         mlxsw_reg_ptys_eth_unpack(payload, p_eth_proto_cap, p_eth_proto_admin,
2770                                   p_eth_proto_oper);
2771 }
2772
2773 static const struct mlxsw_sp_port_type_speed_ops
2774 mlxsw_sp1_port_type_speed_ops = {
2775         .from_ptys_supported_port       = mlxsw_sp1_from_ptys_supported_port,
2776         .from_ptys_link                 = mlxsw_sp1_from_ptys_link,
2777         .from_ptys_speed                = mlxsw_sp1_from_ptys_speed,
2778         .from_ptys_speed_duplex         = mlxsw_sp1_from_ptys_speed_duplex,
2779         .to_ptys_advert_link            = mlxsw_sp1_to_ptys_advert_link,
2780         .to_ptys_speed                  = mlxsw_sp1_to_ptys_speed,
2781         .to_ptys_upper_speed            = mlxsw_sp1_to_ptys_upper_speed,
2782         .port_speed_base                = mlxsw_sp1_port_speed_base,
2783         .reg_ptys_eth_pack              = mlxsw_sp1_reg_ptys_eth_pack,
2784         .reg_ptys_eth_unpack            = mlxsw_sp1_reg_ptys_eth_unpack,
2785 };
2786
2787 static const enum ethtool_link_mode_bit_indices
2788 mlxsw_sp2_mask_ethtool_sgmii_100m[] = {
2789         ETHTOOL_LINK_MODE_100baseT_Full_BIT,
2790 };
2791
2792 #define MLXSW_SP2_MASK_ETHTOOL_SGMII_100M_LEN \
2793         ARRAY_SIZE(mlxsw_sp2_mask_ethtool_sgmii_100m)
2794
2795 static const enum ethtool_link_mode_bit_indices
2796 mlxsw_sp2_mask_ethtool_1000base_x_sgmii[] = {
2797         ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
2798         ETHTOOL_LINK_MODE_1000baseKX_Full_BIT,
2799 };
2800
2801 #define MLXSW_SP2_MASK_ETHTOOL_1000BASE_X_SGMII_LEN \
2802         ARRAY_SIZE(mlxsw_sp2_mask_ethtool_1000base_x_sgmii)
2803
2804 static const enum ethtool_link_mode_bit_indices
2805 mlxsw_sp2_mask_ethtool_2_5gbase_x_2_5gmii[] = {
2806         ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
2807 };
2808
2809 #define MLXSW_SP2_MASK_ETHTOOL_2_5GBASE_X_2_5GMII_LEN \
2810         ARRAY_SIZE(mlxsw_sp2_mask_ethtool_2_5gbase_x_2_5gmii)
2811
2812 static const enum ethtool_link_mode_bit_indices
2813 mlxsw_sp2_mask_ethtool_5gbase_r[] = {
2814         ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
2815 };
2816
2817 #define MLXSW_SP2_MASK_ETHTOOL_5GBASE_R_LEN \
2818         ARRAY_SIZE(mlxsw_sp2_mask_ethtool_5gbase_r)
2819
2820 static const enum ethtool_link_mode_bit_indices
2821 mlxsw_sp2_mask_ethtool_xfi_xaui_1_10g[] = {
2822         ETHTOOL_LINK_MODE_10000baseT_Full_BIT,
2823         ETHTOOL_LINK_MODE_10000baseKR_Full_BIT,
2824         ETHTOOL_LINK_MODE_10000baseR_FEC_BIT,
2825         ETHTOOL_LINK_MODE_10000baseCR_Full_BIT,
2826         ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
2827         ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
2828         ETHTOOL_LINK_MODE_10000baseER_Full_BIT,
2829 };
2830
2831 #define MLXSW_SP2_MASK_ETHTOOL_XFI_XAUI_1_10G_LEN \
2832         ARRAY_SIZE(mlxsw_sp2_mask_ethtool_xfi_xaui_1_10g)
2833
2834 static const enum ethtool_link_mode_bit_indices
2835 mlxsw_sp2_mask_ethtool_xlaui_4_xlppi_4_40g[] = {
2836         ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT,
2837         ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT,
2838         ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT,
2839         ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT,
2840 };
2841
2842 #define MLXSW_SP2_MASK_ETHTOOL_XLAUI_4_XLPPI_4_40G_LEN \
2843         ARRAY_SIZE(mlxsw_sp2_mask_ethtool_xlaui_4_xlppi_4_40g)
2844
2845 static const enum ethtool_link_mode_bit_indices
2846 mlxsw_sp2_mask_ethtool_25gaui_1_25gbase_cr_kr[] = {
2847         ETHTOOL_LINK_MODE_25000baseCR_Full_BIT,
2848         ETHTOOL_LINK_MODE_25000baseKR_Full_BIT,
2849         ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
2850 };
2851
2852 #define MLXSW_SP2_MASK_ETHTOOL_25GAUI_1_25GBASE_CR_KR_LEN \
2853         ARRAY_SIZE(mlxsw_sp2_mask_ethtool_25gaui_1_25gbase_cr_kr)
2854
2855 static const enum ethtool_link_mode_bit_indices
2856 mlxsw_sp2_mask_ethtool_50gaui_2_laui_2_50gbase_cr2_kr2[] = {
2857         ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT,
2858         ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT,
2859         ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
2860 };
2861
2862 #define MLXSW_SP2_MASK_ETHTOOL_50GAUI_2_LAUI_2_50GBASE_CR2_KR2_LEN \
2863         ARRAY_SIZE(mlxsw_sp2_mask_ethtool_50gaui_2_laui_2_50gbase_cr2_kr2)
2864
2865 static const enum ethtool_link_mode_bit_indices
2866 mlxsw_sp2_mask_ethtool_50gaui_1_laui_1_50gbase_cr_kr[] = {
2867         ETHTOOL_LINK_MODE_50000baseKR_Full_BIT,
2868         ETHTOOL_LINK_MODE_50000baseSR_Full_BIT,
2869         ETHTOOL_LINK_MODE_50000baseCR_Full_BIT,
2870         ETHTOOL_LINK_MODE_50000baseLR_ER_FR_Full_BIT,
2871         ETHTOOL_LINK_MODE_50000baseDR_Full_BIT,
2872 };
2873
2874 #define MLXSW_SP2_MASK_ETHTOOL_50GAUI_1_LAUI_1_50GBASE_CR_KR_LEN \
2875         ARRAY_SIZE(mlxsw_sp2_mask_ethtool_50gaui_1_laui_1_50gbase_cr_kr)
2876
2877 static const enum ethtool_link_mode_bit_indices
2878 mlxsw_sp2_mask_ethtool_caui_4_100gbase_cr4_kr4[] = {
2879         ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT,
2880         ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
2881         ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT,
2882         ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT,
2883 };
2884
2885 #define MLXSW_SP2_MASK_ETHTOOL_CAUI_4_100GBASE_CR4_KR4_LEN \
2886         ARRAY_SIZE(mlxsw_sp2_mask_ethtool_caui_4_100gbase_cr4_kr4)
2887
2888 static const enum ethtool_link_mode_bit_indices
2889 mlxsw_sp2_mask_ethtool_100gaui_2_100gbase_cr2_kr2[] = {
2890         ETHTOOL_LINK_MODE_100000baseKR2_Full_BIT,
2891         ETHTOOL_LINK_MODE_100000baseSR2_Full_BIT,
2892         ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT,
2893         ETHTOOL_LINK_MODE_100000baseLR2_ER2_FR2_Full_BIT,
2894         ETHTOOL_LINK_MODE_100000baseDR2_Full_BIT,
2895 };
2896
2897 #define MLXSW_SP2_MASK_ETHTOOL_100GAUI_2_100GBASE_CR2_KR2_LEN \
2898         ARRAY_SIZE(mlxsw_sp2_mask_ethtool_100gaui_2_100gbase_cr2_kr2)
2899
2900 static const enum ethtool_link_mode_bit_indices
2901 mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4[] = {
2902         ETHTOOL_LINK_MODE_200000baseKR4_Full_BIT,
2903         ETHTOOL_LINK_MODE_200000baseSR4_Full_BIT,
2904         ETHTOOL_LINK_MODE_200000baseLR4_ER4_FR4_Full_BIT,
2905         ETHTOOL_LINK_MODE_200000baseDR4_Full_BIT,
2906         ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT,
2907 };
2908
2909 #define MLXSW_SP2_MASK_ETHTOOL_200GAUI_4_200GBASE_CR4_KR4_LEN \
2910         ARRAY_SIZE(mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4)
2911
2912 #define MLXSW_SP_PORT_MASK_WIDTH_1X     BIT(0)
2913 #define MLXSW_SP_PORT_MASK_WIDTH_2X     BIT(1)
2914 #define MLXSW_SP_PORT_MASK_WIDTH_4X     BIT(2)
2915
2916 static u8 mlxsw_sp_port_mask_width_get(u8 width)
2917 {
2918         switch (width) {
2919         case 1:
2920                 return MLXSW_SP_PORT_MASK_WIDTH_1X;
2921         case 2:
2922                 return MLXSW_SP_PORT_MASK_WIDTH_2X;
2923         case 4:
2924                 return MLXSW_SP_PORT_MASK_WIDTH_4X;
2925         default:
2926                 WARN_ON_ONCE(1);
2927                 return 0;
2928         }
2929 }
2930
2931 struct mlxsw_sp2_port_link_mode {
2932         const enum ethtool_link_mode_bit_indices *mask_ethtool;
2933         int m_ethtool_len;
2934         u32 mask;
2935         u32 speed;
2936         u8 mask_width;
2937 };
2938
2939 static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = {
2940         {
2941                 .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M,
2942                 .mask_ethtool   = mlxsw_sp2_mask_ethtool_sgmii_100m,
2943                 .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_SGMII_100M_LEN,
2944                 .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_1X |
2945                                   MLXSW_SP_PORT_MASK_WIDTH_2X |
2946                                   MLXSW_SP_PORT_MASK_WIDTH_4X,
2947                 .speed          = SPEED_100,
2948         },
2949         {
2950                 .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII,
2951                 .mask_ethtool   = mlxsw_sp2_mask_ethtool_1000base_x_sgmii,
2952                 .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_1000BASE_X_SGMII_LEN,
2953                 .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_1X |
2954                                   MLXSW_SP_PORT_MASK_WIDTH_2X |
2955                                   MLXSW_SP_PORT_MASK_WIDTH_4X,
2956                 .speed          = SPEED_1000,
2957         },
2958         {
2959                 .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_2_5GBASE_X_2_5GMII,
2960                 .mask_ethtool   = mlxsw_sp2_mask_ethtool_2_5gbase_x_2_5gmii,
2961                 .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_2_5GBASE_X_2_5GMII_LEN,
2962                 .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_1X |
2963                                   MLXSW_SP_PORT_MASK_WIDTH_2X |
2964                                   MLXSW_SP_PORT_MASK_WIDTH_4X,
2965                 .speed          = SPEED_2500,
2966         },
2967         {
2968                 .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R,
2969                 .mask_ethtool   = mlxsw_sp2_mask_ethtool_5gbase_r,
2970                 .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_5GBASE_R_LEN,
2971                 .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_1X |
2972                                   MLXSW_SP_PORT_MASK_WIDTH_2X |
2973                                   MLXSW_SP_PORT_MASK_WIDTH_4X,
2974                 .speed          = SPEED_5000,
2975         },
2976         {
2977                 .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G,
2978                 .mask_ethtool   = mlxsw_sp2_mask_ethtool_xfi_xaui_1_10g,
2979                 .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_XFI_XAUI_1_10G_LEN,
2980                 .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_1X |
2981                                   MLXSW_SP_PORT_MASK_WIDTH_2X |
2982                                   MLXSW_SP_PORT_MASK_WIDTH_4X,
2983                 .speed          = SPEED_10000,
2984         },
2985         {
2986                 .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G,
2987                 .mask_ethtool   = mlxsw_sp2_mask_ethtool_xlaui_4_xlppi_4_40g,
2988                 .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_XLAUI_4_XLPPI_4_40G_LEN,
2989                 .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_4X,
2990                 .speed          = SPEED_40000,
2991         },
2992         {
2993                 .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR,
2994                 .mask_ethtool   = mlxsw_sp2_mask_ethtool_25gaui_1_25gbase_cr_kr,
2995                 .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_25GAUI_1_25GBASE_CR_KR_LEN,
2996                 .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_1X |
2997                                   MLXSW_SP_PORT_MASK_WIDTH_2X |
2998                                   MLXSW_SP_PORT_MASK_WIDTH_4X,
2999                 .speed          = SPEED_25000,
3000         },
3001         {
3002                 .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2,
3003                 .mask_ethtool   = mlxsw_sp2_mask_ethtool_50gaui_2_laui_2_50gbase_cr2_kr2,
3004                 .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_50GAUI_2_LAUI_2_50GBASE_CR2_KR2_LEN,
3005                 .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_2X |
3006                                   MLXSW_SP_PORT_MASK_WIDTH_4X,
3007                 .speed          = SPEED_50000,
3008         },
3009         {
3010                 .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR,
3011                 .mask_ethtool   = mlxsw_sp2_mask_ethtool_50gaui_1_laui_1_50gbase_cr_kr,
3012                 .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_50GAUI_1_LAUI_1_50GBASE_CR_KR_LEN,
3013                 .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_1X,
3014                 .speed          = SPEED_50000,
3015         },
3016         {
3017                 .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4,
3018                 .mask_ethtool   = mlxsw_sp2_mask_ethtool_caui_4_100gbase_cr4_kr4,
3019                 .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_CAUI_4_100GBASE_CR4_KR4_LEN,
3020                 .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_4X,
3021                 .speed          = SPEED_100000,
3022         },
3023         {
3024                 .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2,
3025                 .mask_ethtool   = mlxsw_sp2_mask_ethtool_100gaui_2_100gbase_cr2_kr2,
3026                 .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_100GAUI_2_100GBASE_CR2_KR2_LEN,
3027                 .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_2X,
3028                 .speed          = SPEED_100000,
3029         },
3030         {
3031                 .mask           = MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4,
3032                 .mask_ethtool   = mlxsw_sp2_mask_ethtool_200gaui_4_200gbase_cr4_kr4,
3033                 .m_ethtool_len  = MLXSW_SP2_MASK_ETHTOOL_200GAUI_4_200GBASE_CR4_KR4_LEN,
3034                 .mask_width     = MLXSW_SP_PORT_MASK_WIDTH_4X,
3035                 .speed          = SPEED_200000,
3036         },
3037 };
3038
3039 #define MLXSW_SP2_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp2_port_link_mode)
3040
3041 static void
3042 mlxsw_sp2_from_ptys_supported_port(struct mlxsw_sp *mlxsw_sp,
3043                                    u32 ptys_eth_proto,
3044                                    struct ethtool_link_ksettings *cmd)
3045 {
3046         ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
3047         ethtool_link_ksettings_add_link_mode(cmd, supported, Backplane);
3048 }
3049
3050 static void
3051 mlxsw_sp2_set_bit_ethtool(const struct mlxsw_sp2_port_link_mode *link_mode,
3052                           unsigned long *mode)
3053 {
3054         int i;
3055
3056         for (i = 0; i < link_mode->m_ethtool_len; i++)
3057                 __set_bit(link_mode->mask_ethtool[i], mode);
3058 }
3059
3060 static void
3061 mlxsw_sp2_from_ptys_link(struct mlxsw_sp *mlxsw_sp, u32 ptys_eth_proto,
3062                          u8 width, unsigned long *mode)
3063 {
3064         u8 mask_width = mlxsw_sp_port_mask_width_get(width);
3065         int i;
3066
3067         for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
3068                 if ((ptys_eth_proto & mlxsw_sp2_port_link_mode[i].mask) &&
3069                     (mask_width & mlxsw_sp2_port_link_mode[i].mask_width))
3070                         mlxsw_sp2_set_bit_ethtool(&mlxsw_sp2_port_link_mode[i],
3071                                                   mode);
3072         }
3073 }
3074
3075 static u32
3076 mlxsw_sp2_from_ptys_speed(struct mlxsw_sp *mlxsw_sp, u32 ptys_eth_proto)
3077 {
3078         int i;
3079
3080         for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
3081                 if (ptys_eth_proto & mlxsw_sp2_port_link_mode[i].mask)
3082                         return mlxsw_sp2_port_link_mode[i].speed;
3083         }
3084
3085         return SPEED_UNKNOWN;
3086 }
3087
3088 static void
3089 mlxsw_sp2_from_ptys_speed_duplex(struct mlxsw_sp *mlxsw_sp, bool carrier_ok,
3090                                  u32 ptys_eth_proto,
3091                                  struct ethtool_link_ksettings *cmd)
3092 {
3093         cmd->base.speed = SPEED_UNKNOWN;
3094         cmd->base.duplex = DUPLEX_UNKNOWN;
3095
3096         if (!carrier_ok)
3097                 return;
3098
3099         cmd->base.speed = mlxsw_sp2_from_ptys_speed(mlxsw_sp, ptys_eth_proto);
3100         if (cmd->base.speed != SPEED_UNKNOWN)
3101                 cmd->base.duplex = DUPLEX_FULL;
3102 }
3103
3104 static bool
3105 mlxsw_sp2_test_bit_ethtool(const struct mlxsw_sp2_port_link_mode *link_mode,
3106                            const unsigned long *mode)
3107 {
3108         int cnt = 0;
3109         int i;
3110
3111         for (i = 0; i < link_mode->m_ethtool_len; i++) {
3112                 if (test_bit(link_mode->mask_ethtool[i], mode))
3113                         cnt++;
3114         }
3115
3116         return cnt == link_mode->m_ethtool_len;
3117 }
3118
3119 static u32
3120 mlxsw_sp2_to_ptys_advert_link(struct mlxsw_sp *mlxsw_sp, u8 width,
3121                               const struct ethtool_link_ksettings *cmd)
3122 {
3123         u8 mask_width = mlxsw_sp_port_mask_width_get(width);
3124         u32 ptys_proto = 0;
3125         int i;
3126
3127         for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
3128                 if ((mask_width & mlxsw_sp2_port_link_mode[i].mask_width) &&
3129                     mlxsw_sp2_test_bit_ethtool(&mlxsw_sp2_port_link_mode[i],
3130                                                cmd->link_modes.advertising))
3131                         ptys_proto |= mlxsw_sp2_port_link_mode[i].mask;
3132         }
3133         return ptys_proto;
3134 }
3135
3136 static u32 mlxsw_sp2_to_ptys_speed(struct mlxsw_sp *mlxsw_sp,
3137                                    u8 width, u32 speed)
3138 {
3139         u8 mask_width = mlxsw_sp_port_mask_width_get(width);
3140         u32 ptys_proto = 0;
3141         int i;
3142
3143         for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
3144                 if ((speed == mlxsw_sp2_port_link_mode[i].speed) &&
3145                     (mask_width & mlxsw_sp2_port_link_mode[i].mask_width))
3146                         ptys_proto |= mlxsw_sp2_port_link_mode[i].mask;
3147         }
3148         return ptys_proto;
3149 }
3150
3151 static u32
3152 mlxsw_sp2_to_ptys_upper_speed(struct mlxsw_sp *mlxsw_sp, u32 upper_speed)
3153 {
3154         u32 ptys_proto = 0;
3155         int i;
3156
3157         for (i = 0; i < MLXSW_SP2_PORT_LINK_MODE_LEN; i++) {
3158                 if (mlxsw_sp2_port_link_mode[i].speed <= upper_speed)
3159                         ptys_proto |= mlxsw_sp2_port_link_mode[i].mask;
3160         }
3161         return ptys_proto;
3162 }
3163
3164 static int
3165 mlxsw_sp2_port_speed_base(struct mlxsw_sp *mlxsw_sp, u8 local_port,
3166                           u32 *base_speed)
3167 {
3168         char ptys_pl[MLXSW_REG_PTYS_LEN];
3169         u32 eth_proto_cap;
3170         int err;
3171
3172         /* In Spectrum-2, the speed of 1x can change from port to port, so query
3173          * it from firmware.
3174          */
3175         mlxsw_reg_ptys_ext_eth_pack(ptys_pl, local_port, 0, false);
3176         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
3177         if (err)
3178                 return err;
3179         mlxsw_reg_ptys_ext_eth_unpack(ptys_pl, &eth_proto_cap, NULL, NULL);
3180
3181         if (eth_proto_cap &
3182             MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR) {
3183                 *base_speed = MLXSW_SP_PORT_BASE_SPEED_50G;
3184                 return 0;
3185         }
3186
3187         if (eth_proto_cap &
3188             MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR) {
3189                 *base_speed = MLXSW_SP_PORT_BASE_SPEED_25G;
3190                 return 0;
3191         }
3192
3193         return -EIO;
3194 }
3195
3196 static void
3197 mlxsw_sp2_reg_ptys_eth_pack(struct mlxsw_sp *mlxsw_sp, char *payload,
3198                             u8 local_port, u32 proto_admin,
3199                             bool autoneg)
3200 {
3201         mlxsw_reg_ptys_ext_eth_pack(payload, local_port, proto_admin, autoneg);
3202 }
3203
3204 static void
3205 mlxsw_sp2_reg_ptys_eth_unpack(struct mlxsw_sp *mlxsw_sp, char *payload,
3206                               u32 *p_eth_proto_cap, u32 *p_eth_proto_admin,
3207                               u32 *p_eth_proto_oper)
3208 {
3209         mlxsw_reg_ptys_ext_eth_unpack(payload, p_eth_proto_cap,
3210                                       p_eth_proto_admin, p_eth_proto_oper);
3211 }
3212
3213 static const struct mlxsw_sp_port_type_speed_ops
3214 mlxsw_sp2_port_type_speed_ops = {
3215         .from_ptys_supported_port       = mlxsw_sp2_from_ptys_supported_port,
3216         .from_ptys_link                 = mlxsw_sp2_from_ptys_link,
3217         .from_ptys_speed                = mlxsw_sp2_from_ptys_speed,
3218         .from_ptys_speed_duplex         = mlxsw_sp2_from_ptys_speed_duplex,
3219         .to_ptys_advert_link            = mlxsw_sp2_to_ptys_advert_link,
3220         .to_ptys_speed                  = mlxsw_sp2_to_ptys_speed,
3221         .to_ptys_upper_speed            = mlxsw_sp2_to_ptys_upper_speed,
3222         .port_speed_base                = mlxsw_sp2_port_speed_base,
3223         .reg_ptys_eth_pack              = mlxsw_sp2_reg_ptys_eth_pack,
3224         .reg_ptys_eth_unpack            = mlxsw_sp2_reg_ptys_eth_unpack,
3225 };
3226
3227 static void
3228 mlxsw_sp_port_get_link_supported(struct mlxsw_sp *mlxsw_sp, u32 eth_proto_cap,
3229                                  u8 width, struct ethtool_link_ksettings *cmd)
3230 {
3231         const struct mlxsw_sp_port_type_speed_ops *ops;
3232
3233         ops = mlxsw_sp->port_type_speed_ops;
3234
3235         ethtool_link_ksettings_add_link_mode(cmd, supported, Asym_Pause);
3236         ethtool_link_ksettings_add_link_mode(cmd, supported, Autoneg);
3237         ethtool_link_ksettings_add_link_mode(cmd, supported, Pause);
3238
3239         ops->from_ptys_supported_port(mlxsw_sp, eth_proto_cap, cmd);
3240         ops->from_ptys_link(mlxsw_sp, eth_proto_cap, width,
3241                             cmd->link_modes.supported);
3242 }
3243
3244 static void
3245 mlxsw_sp_port_get_link_advertise(struct mlxsw_sp *mlxsw_sp,
3246                                  u32 eth_proto_admin, bool autoneg, u8 width,
3247                                  struct ethtool_link_ksettings *cmd)
3248 {
3249         const struct mlxsw_sp_port_type_speed_ops *ops;
3250
3251         ops = mlxsw_sp->port_type_speed_ops;
3252
3253         if (!autoneg)
3254                 return;
3255
3256         ethtool_link_ksettings_add_link_mode(cmd, advertising, Autoneg);
3257         ops->from_ptys_link(mlxsw_sp, eth_proto_admin, width,
3258                             cmd->link_modes.advertising);
3259 }
3260
3261 static u8
3262 mlxsw_sp_port_connector_port(enum mlxsw_reg_ptys_connector_type connector_type)
3263 {
3264         switch (connector_type) {
3265         case MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR:
3266                 return PORT_OTHER;
3267         case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE:
3268                 return PORT_NONE;
3269         case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP:
3270                 return PORT_TP;
3271         case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI:
3272                 return PORT_AUI;
3273         case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC:
3274                 return PORT_BNC;
3275         case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII:
3276                 return PORT_MII;
3277         case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE:
3278                 return PORT_FIBRE;
3279         case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA:
3280                 return PORT_DA;
3281         case MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER:
3282                 return PORT_OTHER;
3283         default:
3284                 WARN_ON_ONCE(1);
3285                 return PORT_OTHER;
3286         }
3287 }
3288
3289 static int mlxsw_sp_port_get_link_ksettings(struct net_device *dev,
3290                                             struct ethtool_link_ksettings *cmd)
3291 {
3292         u32 eth_proto_cap, eth_proto_admin, eth_proto_oper;
3293         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
3294         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3295         const struct mlxsw_sp_port_type_speed_ops *ops;
3296         char ptys_pl[MLXSW_REG_PTYS_LEN];
3297         u8 connector_type;
3298         bool autoneg;
3299         int err;
3300
3301         ops = mlxsw_sp->port_type_speed_ops;
3302
3303         autoneg = mlxsw_sp_port->link.autoneg;
3304         ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
3305                                0, false);
3306         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
3307         if (err)
3308                 return err;
3309         ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, &eth_proto_cap,
3310                                  &eth_proto_admin, &eth_proto_oper);
3311
3312         mlxsw_sp_port_get_link_supported(mlxsw_sp, eth_proto_cap,
3313                                          mlxsw_sp_port->mapping.width, cmd);
3314
3315         mlxsw_sp_port_get_link_advertise(mlxsw_sp, eth_proto_admin, autoneg,
3316                                          mlxsw_sp_port->mapping.width, cmd);
3317
3318         cmd->base.autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3319         connector_type = mlxsw_reg_ptys_connector_type_get(ptys_pl);
3320         cmd->base.port = mlxsw_sp_port_connector_port(connector_type);
3321         ops->from_ptys_speed_duplex(mlxsw_sp, netif_carrier_ok(dev),
3322                                     eth_proto_oper, cmd);
3323
3324         return 0;
3325 }
3326
3327 static int
3328 mlxsw_sp_port_set_link_ksettings(struct net_device *dev,
3329                                  const struct ethtool_link_ksettings *cmd)
3330 {
3331         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
3332         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3333         const struct mlxsw_sp_port_type_speed_ops *ops;
3334         char ptys_pl[MLXSW_REG_PTYS_LEN];
3335         u32 eth_proto_cap, eth_proto_new;
3336         bool autoneg;
3337         int err;
3338
3339         ops = mlxsw_sp->port_type_speed_ops;
3340
3341         ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
3342                                0, false);
3343         err = mlxsw_reg_query(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
3344         if (err)
3345                 return err;
3346         ops->reg_ptys_eth_unpack(mlxsw_sp, ptys_pl, &eth_proto_cap, NULL, NULL);
3347
3348         autoneg = cmd->base.autoneg == AUTONEG_ENABLE;
3349         eth_proto_new = autoneg ?
3350                 ops->to_ptys_advert_link(mlxsw_sp, mlxsw_sp_port->mapping.width,
3351                                          cmd) :
3352                 ops->to_ptys_speed(mlxsw_sp, mlxsw_sp_port->mapping.width,
3353                                    cmd->base.speed);
3354
3355         eth_proto_new = eth_proto_new & eth_proto_cap;
3356         if (!eth_proto_new) {
3357                 netdev_err(dev, "No supported speed requested\n");
3358                 return -EINVAL;
3359         }
3360
3361         ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
3362                                eth_proto_new, autoneg);
3363         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
3364         if (err)
3365                 return err;
3366
3367         mlxsw_sp_port->link.autoneg = autoneg;
3368
3369         if (!netif_running(dev))
3370                 return 0;
3371
3372         mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
3373         mlxsw_sp_port_admin_status_set(mlxsw_sp_port, true);
3374
3375         return 0;
3376 }
3377
3378 static int mlxsw_sp_get_module_info(struct net_device *netdev,
3379                                     struct ethtool_modinfo *modinfo)
3380 {
3381         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
3382         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3383         int err;
3384
3385         err = mlxsw_env_get_module_info(mlxsw_sp->core,
3386                                         mlxsw_sp_port->mapping.module,
3387                                         modinfo);
3388
3389         return err;
3390 }
3391
3392 static int mlxsw_sp_get_module_eeprom(struct net_device *netdev,
3393                                       struct ethtool_eeprom *ee,
3394                                       u8 *data)
3395 {
3396         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
3397         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3398         int err;
3399
3400         err = mlxsw_env_get_module_eeprom(netdev, mlxsw_sp->core,
3401                                           mlxsw_sp_port->mapping.module, ee,
3402                                           data);
3403
3404         return err;
3405 }
3406
3407 static int
3408 mlxsw_sp_get_ts_info(struct net_device *netdev, struct ethtool_ts_info *info)
3409 {
3410         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(netdev);
3411         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3412
3413         return mlxsw_sp->ptp_ops->get_ts_info(mlxsw_sp, info);
3414 }
3415
3416 static const struct ethtool_ops mlxsw_sp_port_ethtool_ops = {
3417         .get_drvinfo            = mlxsw_sp_port_get_drvinfo,
3418         .get_link               = ethtool_op_get_link,
3419         .get_pauseparam         = mlxsw_sp_port_get_pauseparam,
3420         .set_pauseparam         = mlxsw_sp_port_set_pauseparam,
3421         .get_strings            = mlxsw_sp_port_get_strings,
3422         .set_phys_id            = mlxsw_sp_port_set_phys_id,
3423         .get_ethtool_stats      = mlxsw_sp_port_get_stats,
3424         .get_sset_count         = mlxsw_sp_port_get_sset_count,
3425         .get_link_ksettings     = mlxsw_sp_port_get_link_ksettings,
3426         .set_link_ksettings     = mlxsw_sp_port_set_link_ksettings,
3427         .get_module_info        = mlxsw_sp_get_module_info,
3428         .get_module_eeprom      = mlxsw_sp_get_module_eeprom,
3429         .get_ts_info            = mlxsw_sp_get_ts_info,
3430 };
3431
3432 static int
3433 mlxsw_sp_port_speed_by_width_set(struct mlxsw_sp_port *mlxsw_sp_port, u8 width)
3434 {
3435         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3436         const struct mlxsw_sp_port_type_speed_ops *ops;
3437         char ptys_pl[MLXSW_REG_PTYS_LEN];
3438         u32 eth_proto_admin;
3439         u32 upper_speed;
3440         u32 base_speed;
3441         int err;
3442
3443         ops = mlxsw_sp->port_type_speed_ops;
3444
3445         err = ops->port_speed_base(mlxsw_sp, mlxsw_sp_port->local_port,
3446                                    &base_speed);
3447         if (err)
3448                 return err;
3449         upper_speed = base_speed * width;
3450
3451         eth_proto_admin = ops->to_ptys_upper_speed(mlxsw_sp, upper_speed);
3452         ops->reg_ptys_eth_pack(mlxsw_sp, ptys_pl, mlxsw_sp_port->local_port,
3453                                eth_proto_admin, mlxsw_sp_port->link.autoneg);
3454         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(ptys), ptys_pl);
3455 }
3456
3457 int mlxsw_sp_port_ets_set(struct mlxsw_sp_port *mlxsw_sp_port,
3458                           enum mlxsw_reg_qeec_hr hr, u8 index, u8 next_index,
3459                           bool dwrr, u8 dwrr_weight)
3460 {
3461         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3462         char qeec_pl[MLXSW_REG_QEEC_LEN];
3463
3464         mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
3465                             next_index);
3466         mlxsw_reg_qeec_de_set(qeec_pl, true);
3467         mlxsw_reg_qeec_dwrr_set(qeec_pl, dwrr);
3468         mlxsw_reg_qeec_dwrr_weight_set(qeec_pl, dwrr_weight);
3469         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
3470 }
3471
3472 int mlxsw_sp_port_ets_maxrate_set(struct mlxsw_sp_port *mlxsw_sp_port,
3473                                   enum mlxsw_reg_qeec_hr hr, u8 index,
3474                                   u8 next_index, u32 maxrate)
3475 {
3476         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3477         char qeec_pl[MLXSW_REG_QEEC_LEN];
3478
3479         mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
3480                             next_index);
3481         mlxsw_reg_qeec_mase_set(qeec_pl, true);
3482         mlxsw_reg_qeec_max_shaper_rate_set(qeec_pl, maxrate);
3483         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
3484 }
3485
3486 static int mlxsw_sp_port_min_bw_set(struct mlxsw_sp_port *mlxsw_sp_port,
3487                                     enum mlxsw_reg_qeec_hr hr, u8 index,
3488                                     u8 next_index, u32 minrate)
3489 {
3490         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3491         char qeec_pl[MLXSW_REG_QEEC_LEN];
3492
3493         mlxsw_reg_qeec_pack(qeec_pl, mlxsw_sp_port->local_port, hr, index,
3494                             next_index);
3495         mlxsw_reg_qeec_mise_set(qeec_pl, true);
3496         mlxsw_reg_qeec_min_shaper_rate_set(qeec_pl, minrate);
3497
3498         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qeec), qeec_pl);
3499 }
3500
3501 int mlxsw_sp_port_prio_tc_set(struct mlxsw_sp_port *mlxsw_sp_port,
3502                               u8 switch_prio, u8 tclass)
3503 {
3504         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3505         char qtct_pl[MLXSW_REG_QTCT_LEN];
3506
3507         mlxsw_reg_qtct_pack(qtct_pl, mlxsw_sp_port->local_port, switch_prio,
3508                             tclass);
3509         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtct), qtct_pl);
3510 }
3511
3512 static int mlxsw_sp_port_ets_init(struct mlxsw_sp_port *mlxsw_sp_port)
3513 {
3514         int err, i;
3515
3516         /* Setup the elements hierarcy, so that each TC is linked to
3517          * one subgroup, which are all member in the same group.
3518          */
3519         err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3520                                     MLXSW_REG_QEEC_HIERARCY_GROUP, 0, 0, false,
3521                                     0);
3522         if (err)
3523                 return err;
3524         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3525                 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3526                                             MLXSW_REG_QEEC_HIERARCY_SUBGROUP, i,
3527                                             0, false, 0);
3528                 if (err)
3529                         return err;
3530         }
3531         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3532                 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3533                                             MLXSW_REG_QEEC_HIERARCY_TC, i, i,
3534                                             false, 0);
3535                 if (err)
3536                         return err;
3537
3538                 err = mlxsw_sp_port_ets_set(mlxsw_sp_port,
3539                                             MLXSW_REG_QEEC_HIERARCY_TC,
3540                                             i + 8, i,
3541                                             true, 100);
3542                 if (err)
3543                         return err;
3544         }
3545
3546         /* Make sure the max shaper is disabled in all hierarchies that support
3547          * it. Note that this disables ptps (PTP shaper), but that is intended
3548          * for the initial configuration.
3549          */
3550         err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3551                                             MLXSW_REG_QEEC_HIERARCY_PORT, 0, 0,
3552                                             MLXSW_REG_QEEC_MAS_DIS);
3553         if (err)
3554                 return err;
3555         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3556                 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3557                                                     MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
3558                                                     i, 0,
3559                                                     MLXSW_REG_QEEC_MAS_DIS);
3560                 if (err)
3561                         return err;
3562         }
3563         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3564                 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3565                                                     MLXSW_REG_QEEC_HIERARCY_TC,
3566                                                     i, i,
3567                                                     MLXSW_REG_QEEC_MAS_DIS);
3568                 if (err)
3569                         return err;
3570
3571                 err = mlxsw_sp_port_ets_maxrate_set(mlxsw_sp_port,
3572                                                     MLXSW_REG_QEEC_HIERARCY_TC,
3573                                                     i + 8, i,
3574                                                     MLXSW_REG_QEEC_MAS_DIS);
3575                 if (err)
3576                         return err;
3577         }
3578
3579         /* Configure the min shaper for multicast TCs. */
3580         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3581                 err = mlxsw_sp_port_min_bw_set(mlxsw_sp_port,
3582                                                MLXSW_REG_QEEC_HIERARCY_TC,
3583                                                i + 8, i,
3584                                                MLXSW_REG_QEEC_MIS_MIN);
3585                 if (err)
3586                         return err;
3587         }
3588
3589         /* Map all priorities to traffic class 0. */
3590         for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
3591                 err = mlxsw_sp_port_prio_tc_set(mlxsw_sp_port, i, 0);
3592                 if (err)
3593                         return err;
3594         }
3595
3596         return 0;
3597 }
3598
3599 static int mlxsw_sp_port_tc_mc_mode_set(struct mlxsw_sp_port *mlxsw_sp_port,
3600                                         bool enable)
3601 {
3602         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
3603         char qtctm_pl[MLXSW_REG_QTCTM_LEN];
3604
3605         mlxsw_reg_qtctm_pack(qtctm_pl, mlxsw_sp_port->local_port, enable);
3606         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(qtctm), qtctm_pl);
3607 }
3608
3609 static int mlxsw_sp_port_create(struct mlxsw_sp *mlxsw_sp, u8 local_port,
3610                                 bool split, u8 module, u8 width, u8 lane)
3611 {
3612         struct mlxsw_sp_port_vlan *mlxsw_sp_port_vlan;
3613         struct mlxsw_sp_port *mlxsw_sp_port;
3614         struct net_device *dev;
3615         int err;
3616
3617         err = mlxsw_core_port_init(mlxsw_sp->core, local_port,
3618                                    module + 1, split, lane / width,
3619                                    mlxsw_sp->base_mac,
3620                                    sizeof(mlxsw_sp->base_mac));
3621         if (err) {
3622                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to init core port\n",
3623                         local_port);
3624                 return err;
3625         }
3626
3627         dev = alloc_etherdev(sizeof(struct mlxsw_sp_port));
3628         if (!dev) {
3629                 err = -ENOMEM;
3630                 goto err_alloc_etherdev;
3631         }
3632         SET_NETDEV_DEV(dev, mlxsw_sp->bus_info->dev);
3633         mlxsw_sp_port = netdev_priv(dev);
3634         mlxsw_sp_port->dev = dev;
3635         mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
3636         mlxsw_sp_port->local_port = local_port;
3637         mlxsw_sp_port->pvid = MLXSW_SP_DEFAULT_VID;
3638         mlxsw_sp_port->split = split;
3639         mlxsw_sp_port->mapping.module = module;
3640         mlxsw_sp_port->mapping.width = width;
3641         mlxsw_sp_port->mapping.lane = lane;
3642         mlxsw_sp_port->link.autoneg = 1;
3643         INIT_LIST_HEAD(&mlxsw_sp_port->vlans_list);
3644         INIT_LIST_HEAD(&mlxsw_sp_port->mall_tc_list);
3645
3646         mlxsw_sp_port->pcpu_stats =
3647                 netdev_alloc_pcpu_stats(struct mlxsw_sp_port_pcpu_stats);
3648         if (!mlxsw_sp_port->pcpu_stats) {
3649                 err = -ENOMEM;
3650                 goto err_alloc_stats;
3651         }
3652
3653         mlxsw_sp_port->sample = kzalloc(sizeof(*mlxsw_sp_port->sample),
3654                                         GFP_KERNEL);
3655         if (!mlxsw_sp_port->sample) {
3656                 err = -ENOMEM;
3657                 goto err_alloc_sample;
3658         }
3659
3660         INIT_DELAYED_WORK(&mlxsw_sp_port->periodic_hw_stats.update_dw,
3661                           &update_stats_cache);
3662
3663         dev->netdev_ops = &mlxsw_sp_port_netdev_ops;
3664         dev->ethtool_ops = &mlxsw_sp_port_ethtool_ops;
3665
3666         err = mlxsw_sp_port_module_map(mlxsw_sp_port, module, width, lane);
3667         if (err) {
3668                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to map module\n",
3669                         mlxsw_sp_port->local_port);
3670                 goto err_port_module_map;
3671         }
3672
3673         err = mlxsw_sp_port_swid_set(mlxsw_sp_port, 0);
3674         if (err) {
3675                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set SWID\n",
3676                         mlxsw_sp_port->local_port);
3677                 goto err_port_swid_set;
3678         }
3679
3680         err = mlxsw_sp_port_dev_addr_init(mlxsw_sp_port);
3681         if (err) {
3682                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Unable to init port mac address\n",
3683                         mlxsw_sp_port->local_port);
3684                 goto err_dev_addr_init;
3685         }
3686
3687         netif_carrier_off(dev);
3688
3689         dev->features |= NETIF_F_NETNS_LOCAL | NETIF_F_LLTX | NETIF_F_SG |
3690                          NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_TC;
3691         dev->hw_features |= NETIF_F_HW_TC | NETIF_F_LOOPBACK;
3692
3693         dev->min_mtu = 0;
3694         dev->max_mtu = ETH_MAX_MTU;
3695
3696         /* Each packet needs to have a Tx header (metadata) on top all other
3697          * headers.
3698          */
3699         dev->needed_headroom = MLXSW_TXHDR_LEN;
3700
3701         err = mlxsw_sp_port_system_port_mapping_set(mlxsw_sp_port);
3702         if (err) {
3703                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set system port mapping\n",
3704                         mlxsw_sp_port->local_port);
3705                 goto err_port_system_port_mapping_set;
3706         }
3707
3708         err = mlxsw_sp_port_speed_by_width_set(mlxsw_sp_port, width);
3709         if (err) {
3710                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to enable speeds\n",
3711                         mlxsw_sp_port->local_port);
3712                 goto err_port_speed_by_width_set;
3713         }
3714
3715         err = mlxsw_sp_port_mtu_set(mlxsw_sp_port, ETH_DATA_LEN);
3716         if (err) {
3717                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set MTU\n",
3718                         mlxsw_sp_port->local_port);
3719                 goto err_port_mtu_set;
3720         }
3721
3722         err = mlxsw_sp_port_admin_status_set(mlxsw_sp_port, false);
3723         if (err)
3724                 goto err_port_admin_status_set;
3725
3726         err = mlxsw_sp_port_buffers_init(mlxsw_sp_port);
3727         if (err) {
3728                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize buffers\n",
3729                         mlxsw_sp_port->local_port);
3730                 goto err_port_buffers_init;
3731         }
3732
3733         err = mlxsw_sp_port_ets_init(mlxsw_sp_port);
3734         if (err) {
3735                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize ETS\n",
3736                         mlxsw_sp_port->local_port);
3737                 goto err_port_ets_init;
3738         }
3739
3740         err = mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, true);
3741         if (err) {
3742                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC MC mode\n",
3743                         mlxsw_sp_port->local_port);
3744                 goto err_port_tc_mc_mode;
3745         }
3746
3747         /* ETS and buffers must be initialized before DCB. */
3748         err = mlxsw_sp_port_dcb_init(mlxsw_sp_port);
3749         if (err) {
3750                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize DCB\n",
3751                         mlxsw_sp_port->local_port);
3752                 goto err_port_dcb_init;
3753         }
3754
3755         err = mlxsw_sp_port_fids_init(mlxsw_sp_port);
3756         if (err) {
3757                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize FIDs\n",
3758                         mlxsw_sp_port->local_port);
3759                 goto err_port_fids_init;
3760         }
3761
3762         err = mlxsw_sp_tc_qdisc_init(mlxsw_sp_port);
3763         if (err) {
3764                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize TC qdiscs\n",
3765                         mlxsw_sp_port->local_port);
3766                 goto err_port_qdiscs_init;
3767         }
3768
3769         err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 0, VLAN_N_VID - 1, false,
3770                                      false);
3771         if (err) {
3772                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to clear VLAN filter\n",
3773                         mlxsw_sp_port->local_port);
3774                 goto err_port_vlan_clear;
3775         }
3776
3777         err = mlxsw_sp_port_nve_init(mlxsw_sp_port);
3778         if (err) {
3779                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to initialize NVE\n",
3780                         mlxsw_sp_port->local_port);
3781                 goto err_port_nve_init;
3782         }
3783
3784         err = mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID);
3785         if (err) {
3786                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to set PVID\n",
3787                         mlxsw_sp_port->local_port);
3788                 goto err_port_pvid_set;
3789         }
3790
3791         mlxsw_sp_port_vlan = mlxsw_sp_port_vlan_create(mlxsw_sp_port,
3792                                                        MLXSW_SP_DEFAULT_VID);
3793         if (IS_ERR(mlxsw_sp_port_vlan)) {
3794                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to create VID 1\n",
3795                         mlxsw_sp_port->local_port);
3796                 err = PTR_ERR(mlxsw_sp_port_vlan);
3797                 goto err_port_vlan_create;
3798         }
3799         mlxsw_sp_port->default_vlan = mlxsw_sp_port_vlan;
3800
3801         INIT_DELAYED_WORK(&mlxsw_sp_port->ptp.shaper_dw,
3802                           mlxsw_sp->ptp_ops->shaper_work);
3803
3804         mlxsw_sp->ports[local_port] = mlxsw_sp_port;
3805         err = register_netdev(dev);
3806         if (err) {
3807                 dev_err(mlxsw_sp->bus_info->dev, "Port %d: Failed to register netdev\n",
3808                         mlxsw_sp_port->local_port);
3809                 goto err_register_netdev;
3810         }
3811
3812         mlxsw_core_port_eth_set(mlxsw_sp->core, mlxsw_sp_port->local_port,
3813                                 mlxsw_sp_port, dev);
3814         mlxsw_core_schedule_dw(&mlxsw_sp_port->periodic_hw_stats.update_dw, 0);
3815         return 0;
3816
3817 err_register_netdev:
3818         mlxsw_sp->ports[local_port] = NULL;
3819         mlxsw_sp_port_vlan_destroy(mlxsw_sp_port_vlan);
3820 err_port_vlan_create:
3821 err_port_pvid_set:
3822         mlxsw_sp_port_nve_fini(mlxsw_sp_port);
3823 err_port_nve_init:
3824 err_port_vlan_clear:
3825         mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
3826 err_port_qdiscs_init:
3827         mlxsw_sp_port_fids_fini(mlxsw_sp_port);
3828 err_port_fids_init:
3829         mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
3830 err_port_dcb_init:
3831         mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
3832 err_port_tc_mc_mode:
3833 err_port_ets_init:
3834 err_port_buffers_init:
3835 err_port_admin_status_set:
3836 err_port_mtu_set:
3837 err_port_speed_by_width_set:
3838 err_port_system_port_mapping_set:
3839 err_dev_addr_init:
3840         mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
3841 err_port_swid_set:
3842         mlxsw_sp_port_module_unmap(mlxsw_sp_port);
3843 err_port_module_map:
3844         kfree(mlxsw_sp_port->sample);
3845 err_alloc_sample:
3846         free_percpu(mlxsw_sp_port->pcpu_stats);
3847 err_alloc_stats:
3848         free_netdev(dev);
3849 err_alloc_etherdev:
3850         mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3851         return err;
3852 }
3853
3854 static void mlxsw_sp_port_remove(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3855 {
3856         struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
3857
3858         cancel_delayed_work_sync(&mlxsw_sp_port->periodic_hw_stats.update_dw);
3859         cancel_delayed_work_sync(&mlxsw_sp_port->ptp.shaper_dw);
3860         mlxsw_sp_port_ptp_clear(mlxsw_sp_port);
3861         mlxsw_core_port_clear(mlxsw_sp->core, local_port, mlxsw_sp);
3862         unregister_netdev(mlxsw_sp_port->dev); /* This calls ndo_stop */
3863         mlxsw_sp->ports[local_port] = NULL;
3864         mlxsw_sp_port_vlan_flush(mlxsw_sp_port, true);
3865         mlxsw_sp_port_nve_fini(mlxsw_sp_port);
3866         mlxsw_sp_tc_qdisc_fini(mlxsw_sp_port);
3867         mlxsw_sp_port_fids_fini(mlxsw_sp_port);
3868         mlxsw_sp_port_dcb_fini(mlxsw_sp_port);
3869         mlxsw_sp_port_tc_mc_mode_set(mlxsw_sp_port, false);
3870         mlxsw_sp_port_swid_set(mlxsw_sp_port, MLXSW_PORT_SWID_DISABLED_PORT);
3871         mlxsw_sp_port_module_unmap(mlxsw_sp_port);
3872         kfree(mlxsw_sp_port->sample);
3873         free_percpu(mlxsw_sp_port->pcpu_stats);
3874         WARN_ON_ONCE(!list_empty(&mlxsw_sp_port->vlans_list));
3875         free_netdev(mlxsw_sp_port->dev);
3876         mlxsw_core_port_fini(mlxsw_sp->core, local_port);
3877 }
3878
3879 static int mlxsw_sp_cpu_port_create(struct mlxsw_sp *mlxsw_sp)
3880 {
3881         struct mlxsw_sp_port *mlxsw_sp_port;
3882         int err;
3883
3884         mlxsw_sp_port = kzalloc(sizeof(*mlxsw_sp_port), GFP_KERNEL);
3885         if (!mlxsw_sp_port)
3886                 return -ENOMEM;
3887
3888         mlxsw_sp_port->mlxsw_sp = mlxsw_sp;
3889         mlxsw_sp_port->local_port = MLXSW_PORT_CPU_PORT;
3890
3891         err = mlxsw_core_cpu_port_init(mlxsw_sp->core,
3892                                        mlxsw_sp_port,
3893                                        mlxsw_sp->base_mac,
3894                                        sizeof(mlxsw_sp->base_mac));
3895         if (err) {
3896                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize core CPU port\n");
3897                 goto err_core_cpu_port_init;
3898         }
3899
3900         mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = mlxsw_sp_port;
3901         return 0;
3902
3903 err_core_cpu_port_init:
3904         kfree(mlxsw_sp_port);
3905         return err;
3906 }
3907
3908 static void mlxsw_sp_cpu_port_remove(struct mlxsw_sp *mlxsw_sp)
3909 {
3910         struct mlxsw_sp_port *mlxsw_sp_port =
3911                                 mlxsw_sp->ports[MLXSW_PORT_CPU_PORT];
3912
3913         mlxsw_core_cpu_port_fini(mlxsw_sp->core);
3914         mlxsw_sp->ports[MLXSW_PORT_CPU_PORT] = NULL;
3915         kfree(mlxsw_sp_port);
3916 }
3917
3918 static bool mlxsw_sp_port_created(struct mlxsw_sp *mlxsw_sp, u8 local_port)
3919 {
3920         return mlxsw_sp->ports[local_port] != NULL;
3921 }
3922
3923 static void mlxsw_sp_ports_remove(struct mlxsw_sp *mlxsw_sp)
3924 {
3925         int i;
3926
3927         for (i = 1; i < mlxsw_core_max_ports(mlxsw_sp->core); i++)
3928                 if (mlxsw_sp_port_created(mlxsw_sp, i))
3929                         mlxsw_sp_port_remove(mlxsw_sp, i);
3930         mlxsw_sp_cpu_port_remove(mlxsw_sp);
3931         kfree(mlxsw_sp->port_to_module);
3932         kfree(mlxsw_sp->ports);
3933         mlxsw_sp->ports = NULL;
3934 }
3935
3936 static int mlxsw_sp_ports_create(struct mlxsw_sp *mlxsw_sp)
3937 {
3938         unsigned int max_ports = mlxsw_core_max_ports(mlxsw_sp->core);
3939         u8 module, width, lane;
3940         size_t alloc_size;
3941         int i;
3942         int err;
3943
3944         alloc_size = sizeof(struct mlxsw_sp_port *) * max_ports;
3945         mlxsw_sp->ports = kzalloc(alloc_size, GFP_KERNEL);
3946         if (!mlxsw_sp->ports)
3947                 return -ENOMEM;
3948
3949         mlxsw_sp->port_to_module = kmalloc_array(max_ports, sizeof(int),
3950                                                  GFP_KERNEL);
3951         if (!mlxsw_sp->port_to_module) {
3952                 err = -ENOMEM;
3953                 goto err_port_to_module_alloc;
3954         }
3955
3956         err = mlxsw_sp_cpu_port_create(mlxsw_sp);
3957         if (err)
3958                 goto err_cpu_port_create;
3959
3960         for (i = 1; i < max_ports; i++) {
3961                 /* Mark as invalid */
3962                 mlxsw_sp->port_to_module[i] = -1;
3963
3964                 err = mlxsw_sp_port_module_info_get(mlxsw_sp, i, &module,
3965                                                     &width, &lane);
3966                 if (err)
3967                         goto err_port_module_info_get;
3968                 if (!width)
3969                         continue;
3970                 mlxsw_sp->port_to_module[i] = module;
3971                 err = mlxsw_sp_port_create(mlxsw_sp, i, false,
3972                                            module, width, lane);
3973                 if (err)
3974                         goto err_port_create;
3975         }
3976         return 0;
3977
3978 err_port_create:
3979 err_port_module_info_get:
3980         for (i--; i >= 1; i--)
3981                 if (mlxsw_sp_port_created(mlxsw_sp, i))
3982                         mlxsw_sp_port_remove(mlxsw_sp, i);
3983         mlxsw_sp_cpu_port_remove(mlxsw_sp);
3984 err_cpu_port_create:
3985         kfree(mlxsw_sp->port_to_module);
3986 err_port_to_module_alloc:
3987         kfree(mlxsw_sp->ports);
3988         mlxsw_sp->ports = NULL;
3989         return err;
3990 }
3991
3992 static u8 mlxsw_sp_cluster_base_port_get(u8 local_port)
3993 {
3994         u8 offset = (local_port - 1) % MLXSW_SP_PORTS_PER_CLUSTER_MAX;
3995
3996         return local_port - offset;
3997 }
3998
3999 static int mlxsw_sp_port_split_create(struct mlxsw_sp *mlxsw_sp, u8 base_port,
4000                                       u8 module, unsigned int count, u8 offset)
4001 {
4002         u8 width = MLXSW_PORT_MODULE_MAX_WIDTH / count;
4003         int err, i;
4004
4005         for (i = 0; i < count; i++) {
4006                 err = mlxsw_sp_port_create(mlxsw_sp, base_port + i * offset,
4007                                            true, module, width, i * width);
4008                 if (err)
4009                         goto err_port_create;
4010         }
4011
4012         return 0;
4013
4014 err_port_create:
4015         for (i--; i >= 0; i--)
4016                 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i * offset))
4017                         mlxsw_sp_port_remove(mlxsw_sp, base_port + i * offset);
4018         return err;
4019 }
4020
4021 static void mlxsw_sp_port_unsplit_create(struct mlxsw_sp *mlxsw_sp,
4022                                          u8 base_port, unsigned int count)
4023 {
4024         u8 local_port, module, width = MLXSW_PORT_MODULE_MAX_WIDTH;
4025         int i;
4026
4027         /* Split by four means we need to re-create two ports, otherwise
4028          * only one.
4029          */
4030         count = count / 2;
4031
4032         for (i = 0; i < count; i++) {
4033                 local_port = base_port + i * 2;
4034                 if (mlxsw_sp->port_to_module[local_port] < 0)
4035                         continue;
4036                 module = mlxsw_sp->port_to_module[local_port];
4037
4038                 mlxsw_sp_port_create(mlxsw_sp, local_port, false, module,
4039                                      width, 0);
4040         }
4041 }
4042
4043 static struct mlxsw_sp_port *
4044 mlxsw_sp_port_get_by_local_port(struct mlxsw_sp *mlxsw_sp, u8 local_port)
4045 {
4046         if (mlxsw_sp->ports && mlxsw_sp->ports[local_port])
4047                 return mlxsw_sp->ports[local_port];
4048         return NULL;
4049 }
4050
4051 static int mlxsw_sp_port_split(struct mlxsw_core *mlxsw_core, u8 local_port,
4052                                unsigned int count,
4053                                struct netlink_ext_ack *extack)
4054 {
4055         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4056         u8 local_ports_in_1x, local_ports_in_2x, offset;
4057         struct mlxsw_sp_port *mlxsw_sp_port;
4058         u8 module, cur_width, base_port;
4059         int i;
4060         int err;
4061
4062         if (!MLXSW_CORE_RES_VALID(mlxsw_core, LOCAL_PORTS_IN_1X) ||
4063             !MLXSW_CORE_RES_VALID(mlxsw_core, LOCAL_PORTS_IN_2X))
4064                 return -EIO;
4065
4066         local_ports_in_1x = MLXSW_CORE_RES_GET(mlxsw_core, LOCAL_PORTS_IN_1X);
4067         local_ports_in_2x = MLXSW_CORE_RES_GET(mlxsw_core, LOCAL_PORTS_IN_2X);
4068
4069         mlxsw_sp_port = mlxsw_sp_port_get_by_local_port(mlxsw_sp, local_port);
4070         if (!mlxsw_sp_port) {
4071                 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
4072                         local_port);
4073                 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
4074                 return -EINVAL;
4075         }
4076
4077         module = mlxsw_sp_port->mapping.module;
4078         cur_width = mlxsw_sp_port->mapping.width;
4079
4080         if (count != 2 && count != 4) {
4081                 netdev_err(mlxsw_sp_port->dev, "Port can only be split into 2 or 4 ports\n");
4082                 NL_SET_ERR_MSG_MOD(extack, "Port can only be split into 2 or 4 ports");
4083                 return -EINVAL;
4084         }
4085
4086         if (cur_width != MLXSW_PORT_MODULE_MAX_WIDTH) {
4087                 netdev_err(mlxsw_sp_port->dev, "Port cannot be split further\n");
4088                 NL_SET_ERR_MSG_MOD(extack, "Port cannot be split further");
4089                 return -EINVAL;
4090         }
4091
4092         /* Make sure we have enough slave (even) ports for the split. */
4093         if (count == 2) {
4094                 offset = local_ports_in_2x;
4095                 base_port = local_port;
4096                 if (mlxsw_sp->ports[base_port + local_ports_in_2x]) {
4097                         netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
4098                         NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration");
4099                         return -EINVAL;
4100                 }
4101         } else {
4102                 offset = local_ports_in_1x;
4103                 base_port = mlxsw_sp_cluster_base_port_get(local_port);
4104                 if (mlxsw_sp->ports[base_port + 1] ||
4105                     mlxsw_sp->ports[base_port + 3]) {
4106                         netdev_err(mlxsw_sp_port->dev, "Invalid split configuration\n");
4107                         NL_SET_ERR_MSG_MOD(extack, "Invalid split configuration");
4108                         return -EINVAL;
4109                 }
4110         }
4111
4112         for (i = 0; i < count; i++)
4113                 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i * offset))
4114                         mlxsw_sp_port_remove(mlxsw_sp, base_port + i * offset);
4115
4116         err = mlxsw_sp_port_split_create(mlxsw_sp, base_port, module, count,
4117                                          offset);
4118         if (err) {
4119                 dev_err(mlxsw_sp->bus_info->dev, "Failed to create split ports\n");
4120                 goto err_port_split_create;
4121         }
4122
4123         return 0;
4124
4125 err_port_split_create:
4126         mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
4127         return err;
4128 }
4129
4130 static int mlxsw_sp_port_unsplit(struct mlxsw_core *mlxsw_core, u8 local_port,
4131                                  struct netlink_ext_ack *extack)
4132 {
4133         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4134         u8 local_ports_in_1x, local_ports_in_2x, offset;
4135         struct mlxsw_sp_port *mlxsw_sp_port;
4136         u8 cur_width, base_port;
4137         unsigned int count;
4138         int i;
4139
4140         if (!MLXSW_CORE_RES_VALID(mlxsw_core, LOCAL_PORTS_IN_1X) ||
4141             !MLXSW_CORE_RES_VALID(mlxsw_core, LOCAL_PORTS_IN_2X))
4142                 return -EIO;
4143
4144         local_ports_in_1x = MLXSW_CORE_RES_GET(mlxsw_core, LOCAL_PORTS_IN_1X);
4145         local_ports_in_2x = MLXSW_CORE_RES_GET(mlxsw_core, LOCAL_PORTS_IN_2X);
4146
4147         mlxsw_sp_port = mlxsw_sp_port_get_by_local_port(mlxsw_sp, local_port);
4148         if (!mlxsw_sp_port) {
4149                 dev_err(mlxsw_sp->bus_info->dev, "Port number \"%d\" does not exist\n",
4150                         local_port);
4151                 NL_SET_ERR_MSG_MOD(extack, "Port number does not exist");
4152                 return -EINVAL;
4153         }
4154
4155         if (!mlxsw_sp_port->split) {
4156                 netdev_err(mlxsw_sp_port->dev, "Port was not split\n");
4157                 NL_SET_ERR_MSG_MOD(extack, "Port was not split");
4158                 return -EINVAL;
4159         }
4160
4161         cur_width = mlxsw_sp_port->mapping.width;
4162         count = cur_width == 1 ? 4 : 2;
4163
4164         if (count == 2)
4165                 offset = local_ports_in_2x;
4166         else
4167                 offset = local_ports_in_1x;
4168
4169         base_port = mlxsw_sp_cluster_base_port_get(local_port);
4170
4171         /* Determine which ports to remove. */
4172         if (count == 2 && local_port >= base_port + 2)
4173                 base_port = base_port + 2;
4174
4175         for (i = 0; i < count; i++)
4176                 if (mlxsw_sp_port_created(mlxsw_sp, base_port + i * offset))
4177                         mlxsw_sp_port_remove(mlxsw_sp, base_port + i * offset);
4178
4179         mlxsw_sp_port_unsplit_create(mlxsw_sp, base_port, count);
4180
4181         return 0;
4182 }
4183
4184 static void
4185 mlxsw_sp_port_down_wipe_counters(struct mlxsw_sp_port *mlxsw_sp_port)
4186 {
4187         int i;
4188
4189         for (i = 0; i < TC_MAX_QUEUE; i++)
4190                 mlxsw_sp_port->periodic_hw_stats.xstats.backlog[i] = 0;
4191 }
4192
4193 static void mlxsw_sp_pude_event_func(const struct mlxsw_reg_info *reg,
4194                                      char *pude_pl, void *priv)
4195 {
4196         struct mlxsw_sp *mlxsw_sp = priv;
4197         struct mlxsw_sp_port *mlxsw_sp_port;
4198         enum mlxsw_reg_pude_oper_status status;
4199         u8 local_port;
4200
4201         local_port = mlxsw_reg_pude_local_port_get(pude_pl);
4202         mlxsw_sp_port = mlxsw_sp->ports[local_port];
4203         if (!mlxsw_sp_port)
4204                 return;
4205
4206         status = mlxsw_reg_pude_oper_status_get(pude_pl);
4207         if (status == MLXSW_PORT_OPER_STATUS_UP) {
4208                 netdev_info(mlxsw_sp_port->dev, "link up\n");
4209                 netif_carrier_on(mlxsw_sp_port->dev);
4210                 mlxsw_core_schedule_dw(&mlxsw_sp_port->ptp.shaper_dw, 0);
4211         } else {
4212                 netdev_info(mlxsw_sp_port->dev, "link down\n");
4213                 netif_carrier_off(mlxsw_sp_port->dev);
4214                 mlxsw_sp_port_down_wipe_counters(mlxsw_sp_port);
4215         }
4216 }
4217
4218 static void mlxsw_sp1_ptp_fifo_event_func(struct mlxsw_sp *mlxsw_sp,
4219                                           char *mtpptr_pl, bool ingress)
4220 {
4221         u8 local_port;
4222         u8 num_rec;
4223         int i;
4224
4225         local_port = mlxsw_reg_mtpptr_local_port_get(mtpptr_pl);
4226         num_rec = mlxsw_reg_mtpptr_num_rec_get(mtpptr_pl);
4227         for (i = 0; i < num_rec; i++) {
4228                 u8 domain_number;
4229                 u8 message_type;
4230                 u16 sequence_id;
4231                 u64 timestamp;
4232
4233                 mlxsw_reg_mtpptr_unpack(mtpptr_pl, i, &message_type,
4234                                         &domain_number, &sequence_id,
4235                                         &timestamp);
4236                 mlxsw_sp1_ptp_got_timestamp(mlxsw_sp, ingress, local_port,
4237                                             message_type, domain_number,
4238                                             sequence_id, timestamp);
4239         }
4240 }
4241
4242 static void mlxsw_sp1_ptp_ing_fifo_event_func(const struct mlxsw_reg_info *reg,
4243                                               char *mtpptr_pl, void *priv)
4244 {
4245         struct mlxsw_sp *mlxsw_sp = priv;
4246
4247         mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, true);
4248 }
4249
4250 static void mlxsw_sp1_ptp_egr_fifo_event_func(const struct mlxsw_reg_info *reg,
4251                                               char *mtpptr_pl, void *priv)
4252 {
4253         struct mlxsw_sp *mlxsw_sp = priv;
4254
4255         mlxsw_sp1_ptp_fifo_event_func(mlxsw_sp, mtpptr_pl, false);
4256 }
4257
4258 void mlxsw_sp_rx_listener_no_mark_func(struct sk_buff *skb,
4259                                        u8 local_port, void *priv)
4260 {
4261         struct mlxsw_sp *mlxsw_sp = priv;
4262         struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
4263         struct mlxsw_sp_port_pcpu_stats *pcpu_stats;
4264
4265         if (unlikely(!mlxsw_sp_port)) {
4266                 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: skb received for non-existent port\n",
4267                                      local_port);
4268                 return;
4269         }
4270
4271         skb->dev = mlxsw_sp_port->dev;
4272
4273         pcpu_stats = this_cpu_ptr(mlxsw_sp_port->pcpu_stats);
4274         u64_stats_update_begin(&pcpu_stats->syncp);
4275         pcpu_stats->rx_packets++;
4276         pcpu_stats->rx_bytes += skb->len;
4277         u64_stats_update_end(&pcpu_stats->syncp);
4278
4279         skb->protocol = eth_type_trans(skb, skb->dev);
4280         netif_receive_skb(skb);
4281 }
4282
4283 static void mlxsw_sp_rx_listener_mark_func(struct sk_buff *skb, u8 local_port,
4284                                            void *priv)
4285 {
4286         skb->offload_fwd_mark = 1;
4287         return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
4288 }
4289
4290 static void mlxsw_sp_rx_listener_l3_mark_func(struct sk_buff *skb,
4291                                               u8 local_port, void *priv)
4292 {
4293         skb->offload_l3_fwd_mark = 1;
4294         skb->offload_fwd_mark = 1;
4295         return mlxsw_sp_rx_listener_no_mark_func(skb, local_port, priv);
4296 }
4297
4298 static void mlxsw_sp_rx_listener_sample_func(struct sk_buff *skb, u8 local_port,
4299                                              void *priv)
4300 {
4301         struct mlxsw_sp *mlxsw_sp = priv;
4302         struct mlxsw_sp_port *mlxsw_sp_port = mlxsw_sp->ports[local_port];
4303         struct psample_group *psample_group;
4304         u32 size;
4305
4306         if (unlikely(!mlxsw_sp_port)) {
4307                 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received for non-existent port\n",
4308                                      local_port);
4309                 goto out;
4310         }
4311         if (unlikely(!mlxsw_sp_port->sample)) {
4312                 dev_warn_ratelimited(mlxsw_sp->bus_info->dev, "Port %d: sample skb received on unsupported port\n",
4313                                      local_port);
4314                 goto out;
4315         }
4316
4317         size = mlxsw_sp_port->sample->truncate ?
4318                   mlxsw_sp_port->sample->trunc_size : skb->len;
4319
4320         rcu_read_lock();
4321         psample_group = rcu_dereference(mlxsw_sp_port->sample->psample_group);
4322         if (!psample_group)
4323                 goto out_unlock;
4324         psample_sample_packet(psample_group, skb, size,
4325                               mlxsw_sp_port->dev->ifindex, 0,
4326                               mlxsw_sp_port->sample->rate);
4327 out_unlock:
4328         rcu_read_unlock();
4329 out:
4330         consume_skb(skb);
4331 }
4332
4333 static void mlxsw_sp_rx_listener_ptp(struct sk_buff *skb, u8 local_port,
4334                                      void *priv)
4335 {
4336         struct mlxsw_sp *mlxsw_sp = priv;
4337
4338         mlxsw_sp->ptp_ops->receive(mlxsw_sp, skb, local_port);
4339 }
4340
4341 #define MLXSW_SP_RXL_NO_MARK(_trap_id, _action, _trap_group, _is_ctrl)  \
4342         MLXSW_RXL(mlxsw_sp_rx_listener_no_mark_func, _trap_id, _action, \
4343                   _is_ctrl, SP_##_trap_group, DISCARD)
4344
4345 #define MLXSW_SP_RXL_MARK(_trap_id, _action, _trap_group, _is_ctrl)     \
4346         MLXSW_RXL(mlxsw_sp_rx_listener_mark_func, _trap_id, _action,    \
4347                 _is_ctrl, SP_##_trap_group, DISCARD)
4348
4349 #define MLXSW_SP_RXL_L3_MARK(_trap_id, _action, _trap_group, _is_ctrl)  \
4350         MLXSW_RXL(mlxsw_sp_rx_listener_l3_mark_func, _trap_id, _action, \
4351                 _is_ctrl, SP_##_trap_group, DISCARD)
4352
4353 #define MLXSW_SP_EVENTL(_func, _trap_id)                \
4354         MLXSW_EVENTL(_func, _trap_id, SP_EVENT)
4355
4356 static const struct mlxsw_listener mlxsw_sp_listener[] = {
4357         /* Events */
4358         MLXSW_SP_EVENTL(mlxsw_sp_pude_event_func, PUDE),
4359         /* L2 traps */
4360         MLXSW_SP_RXL_NO_MARK(STP, TRAP_TO_CPU, STP, true),
4361         MLXSW_SP_RXL_NO_MARK(LACP, TRAP_TO_CPU, LACP, true),
4362         MLXSW_RXL(mlxsw_sp_rx_listener_ptp, LLDP, TRAP_TO_CPU,
4363                   false, SP_LLDP, DISCARD),
4364         MLXSW_SP_RXL_MARK(DHCP, MIRROR_TO_CPU, DHCP, false),
4365         MLXSW_SP_RXL_MARK(IGMP_QUERY, MIRROR_TO_CPU, IGMP, false),
4366         MLXSW_SP_RXL_NO_MARK(IGMP_V1_REPORT, TRAP_TO_CPU, IGMP, false),
4367         MLXSW_SP_RXL_NO_MARK(IGMP_V2_REPORT, TRAP_TO_CPU, IGMP, false),
4368         MLXSW_SP_RXL_NO_MARK(IGMP_V2_LEAVE, TRAP_TO_CPU, IGMP, false),
4369         MLXSW_SP_RXL_NO_MARK(IGMP_V3_REPORT, TRAP_TO_CPU, IGMP, false),
4370         MLXSW_SP_RXL_MARK(ARPBC, MIRROR_TO_CPU, ARP, false),
4371         MLXSW_SP_RXL_MARK(ARPUC, MIRROR_TO_CPU, ARP, false),
4372         MLXSW_SP_RXL_NO_MARK(FID_MISS, TRAP_TO_CPU, IP2ME, false),
4373         MLXSW_SP_RXL_MARK(IPV6_MLDV12_LISTENER_QUERY, MIRROR_TO_CPU, IPV6_MLD,
4374                           false),
4375         MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
4376                              false),
4377         MLXSW_SP_RXL_NO_MARK(IPV6_MLDV1_LISTENER_DONE, TRAP_TO_CPU, IPV6_MLD,
4378                              false),
4379         MLXSW_SP_RXL_NO_MARK(IPV6_MLDV2_LISTENER_REPORT, TRAP_TO_CPU, IPV6_MLD,
4380                              false),
4381         /* L3 traps */
4382         MLXSW_SP_RXL_MARK(MTUERROR, TRAP_TO_CPU, ROUTER_EXP, false),
4383         MLXSW_SP_RXL_MARK(TTLERROR, TRAP_TO_CPU, ROUTER_EXP, false),
4384         MLXSW_SP_RXL_L3_MARK(LBERROR, MIRROR_TO_CPU, LBERROR, false),
4385         MLXSW_SP_RXL_MARK(IP2ME, TRAP_TO_CPU, IP2ME, false),
4386         MLXSW_SP_RXL_MARK(IPV6_UNSPECIFIED_ADDRESS, TRAP_TO_CPU, ROUTER_EXP,
4387                           false),
4388         MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP, false),
4389         MLXSW_SP_RXL_MARK(IPV6_LINK_LOCAL_SRC, TRAP_TO_CPU, ROUTER_EXP, false),
4390         MLXSW_SP_RXL_MARK(IPV6_ALL_NODES_LINK, TRAP_TO_CPU, ROUTER_EXP, false),
4391         MLXSW_SP_RXL_MARK(IPV6_ALL_ROUTERS_LINK, TRAP_TO_CPU, ROUTER_EXP,
4392                           false),
4393         MLXSW_SP_RXL_MARK(IPV4_OSPF, TRAP_TO_CPU, OSPF, false),
4394         MLXSW_SP_RXL_MARK(IPV6_OSPF, TRAP_TO_CPU, OSPF, false),
4395         MLXSW_SP_RXL_MARK(IPV6_DHCP, TRAP_TO_CPU, DHCP, false),
4396         MLXSW_SP_RXL_MARK(RTR_INGRESS0, TRAP_TO_CPU, REMOTE_ROUTE, false),
4397         MLXSW_SP_RXL_MARK(IPV4_BGP, TRAP_TO_CPU, BGP, false),
4398         MLXSW_SP_RXL_MARK(IPV6_BGP, TRAP_TO_CPU, BGP, false),
4399         MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
4400                           false),
4401         MLXSW_SP_RXL_MARK(L3_IPV6_ROUTER_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
4402                           false),
4403         MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_SOLICITATION, TRAP_TO_CPU, IPV6_ND,
4404                           false),
4405         MLXSW_SP_RXL_MARK(L3_IPV6_NEIGHBOR_ADVERTISMENT, TRAP_TO_CPU, IPV6_ND,
4406                           false),
4407         MLXSW_SP_RXL_MARK(L3_IPV6_REDIRECTION, TRAP_TO_CPU, IPV6_ND, false),
4408         MLXSW_SP_RXL_MARK(IPV6_MC_LINK_LOCAL_DEST, TRAP_TO_CPU, ROUTER_EXP,
4409                           false),
4410         MLXSW_SP_RXL_MARK(HOST_MISS_IPV4, TRAP_TO_CPU, HOST_MISS, false),
4411         MLXSW_SP_RXL_MARK(HOST_MISS_IPV6, TRAP_TO_CPU, HOST_MISS, false),
4412         MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV4, TRAP_TO_CPU, ROUTER_EXP, false),
4413         MLXSW_SP_RXL_MARK(ROUTER_ALERT_IPV6, TRAP_TO_CPU, ROUTER_EXP, false),
4414         MLXSW_SP_RXL_MARK(IPIP_DECAP_ERROR, TRAP_TO_CPU, ROUTER_EXP, false),
4415         MLXSW_SP_RXL_MARK(DECAP_ECN0, TRAP_TO_CPU, ROUTER_EXP, false),
4416         MLXSW_SP_RXL_MARK(IPV4_VRRP, TRAP_TO_CPU, VRRP, false),
4417         MLXSW_SP_RXL_MARK(IPV6_VRRP, TRAP_TO_CPU, VRRP, false),
4418         /* PKT Sample trap */
4419         MLXSW_RXL(mlxsw_sp_rx_listener_sample_func, PKT_SAMPLE, MIRROR_TO_CPU,
4420                   false, SP_IP2ME, DISCARD),
4421         /* ACL trap */
4422         MLXSW_SP_RXL_NO_MARK(ACL0, TRAP_TO_CPU, IP2ME, false),
4423         /* Multicast Router Traps */
4424         MLXSW_SP_RXL_MARK(IPV4_PIM, TRAP_TO_CPU, PIM, false),
4425         MLXSW_SP_RXL_MARK(IPV6_PIM, TRAP_TO_CPU, PIM, false),
4426         MLXSW_SP_RXL_MARK(RPF, TRAP_TO_CPU, RPF, false),
4427         MLXSW_SP_RXL_MARK(ACL1, TRAP_TO_CPU, MULTICAST, false),
4428         MLXSW_SP_RXL_L3_MARK(ACL2, TRAP_TO_CPU, MULTICAST, false),
4429         /* NVE traps */
4430         MLXSW_SP_RXL_MARK(NVE_ENCAP_ARP, TRAP_TO_CPU, ARP, false),
4431         MLXSW_SP_RXL_NO_MARK(NVE_DECAP_ARP, TRAP_TO_CPU, ARP, false),
4432         /* PTP traps */
4433         MLXSW_RXL(mlxsw_sp_rx_listener_ptp, PTP0, TRAP_TO_CPU,
4434                   false, SP_PTP0, DISCARD),
4435         MLXSW_SP_RXL_NO_MARK(PTP1, TRAP_TO_CPU, PTP1, false),
4436 };
4437
4438 static const struct mlxsw_listener mlxsw_sp1_listener[] = {
4439         /* Events */
4440         MLXSW_EVENTL(mlxsw_sp1_ptp_egr_fifo_event_func, PTP_EGR_FIFO, SP_PTP0),
4441         MLXSW_EVENTL(mlxsw_sp1_ptp_ing_fifo_event_func, PTP_ING_FIFO, SP_PTP0),
4442 };
4443
4444 static int mlxsw_sp_cpu_policers_set(struct mlxsw_core *mlxsw_core)
4445 {
4446         char qpcr_pl[MLXSW_REG_QPCR_LEN];
4447         enum mlxsw_reg_qpcr_ir_units ir_units;
4448         int max_cpu_policers;
4449         bool is_bytes;
4450         u8 burst_size;
4451         u32 rate;
4452         int i, err;
4453
4454         if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_CPU_POLICERS))
4455                 return -EIO;
4456
4457         max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
4458
4459         ir_units = MLXSW_REG_QPCR_IR_UNITS_M;
4460         for (i = 0; i < max_cpu_policers; i++) {
4461                 is_bytes = false;
4462                 switch (i) {
4463                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
4464                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
4465                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
4466                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
4467                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
4468                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
4469                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR:
4470                         rate = 128;
4471                         burst_size = 7;
4472                         break;
4473                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
4474                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
4475                         rate = 16 * 1024;
4476                         burst_size = 10;
4477                         break;
4478                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
4479                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
4480                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
4481                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
4482                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
4483                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
4484                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
4485                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
4486                         rate = 1024;
4487                         burst_size = 7;
4488                         break;
4489                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
4490                         rate = 1024;
4491                         burst_size = 7;
4492                         break;
4493                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0:
4494                         rate = 24 * 1024;
4495                         burst_size = 12;
4496                         break;
4497                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1:
4498                         rate = 19 * 1024;
4499                         burst_size = 12;
4500                         break;
4501                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP:
4502                         rate = 360;
4503                         burst_size = 7;
4504                         break;
4505                 default:
4506                         continue;
4507                 }
4508
4509                 mlxsw_reg_qpcr_pack(qpcr_pl, i, ir_units, is_bytes, rate,
4510                                     burst_size);
4511                 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(qpcr), qpcr_pl);
4512                 if (err)
4513                         return err;
4514         }
4515
4516         return 0;
4517 }
4518
4519 static int mlxsw_sp_trap_groups_set(struct mlxsw_core *mlxsw_core)
4520 {
4521         char htgt_pl[MLXSW_REG_HTGT_LEN];
4522         enum mlxsw_reg_htgt_trap_group i;
4523         int max_cpu_policers;
4524         int max_trap_groups;
4525         u8 priority, tc;
4526         u16 policer_id;
4527         int err;
4528
4529         if (!MLXSW_CORE_RES_VALID(mlxsw_core, MAX_TRAP_GROUPS))
4530                 return -EIO;
4531
4532         max_trap_groups = MLXSW_CORE_RES_GET(mlxsw_core, MAX_TRAP_GROUPS);
4533         max_cpu_policers = MLXSW_CORE_RES_GET(mlxsw_core, MAX_CPU_POLICERS);
4534
4535         for (i = 0; i < max_trap_groups; i++) {
4536                 policer_id = i;
4537                 switch (i) {
4538                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_STP:
4539                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP:
4540                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP:
4541                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF:
4542                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM:
4543                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0:
4544                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP:
4545                         priority = 5;
4546                         tc = 5;
4547                         break;
4548                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP:
4549                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP:
4550                         priority = 4;
4551                         tc = 4;
4552                         break;
4553                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP:
4554                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME:
4555                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD:
4556                         priority = 3;
4557                         tc = 3;
4558                         break;
4559                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP:
4560                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND:
4561                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF:
4562                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1:
4563                         priority = 2;
4564                         tc = 2;
4565                         break;
4566                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS:
4567                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP:
4568                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE:
4569                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST:
4570                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR:
4571                         priority = 1;
4572                         tc = 1;
4573                         break;
4574                 case MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT:
4575                         priority = MLXSW_REG_HTGT_DEFAULT_PRIORITY;
4576                         tc = MLXSW_REG_HTGT_DEFAULT_TC;
4577                         policer_id = MLXSW_REG_HTGT_INVALID_POLICER;
4578                         break;
4579                 default:
4580                         continue;
4581                 }
4582
4583                 if (max_cpu_policers <= policer_id &&
4584                     policer_id != MLXSW_REG_HTGT_INVALID_POLICER)
4585                         return -EIO;
4586
4587                 mlxsw_reg_htgt_pack(htgt_pl, i, policer_id, priority, tc);
4588                 err = mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
4589                 if (err)
4590                         return err;
4591         }
4592
4593         return 0;
4594 }
4595
4596 static int mlxsw_sp_traps_register(struct mlxsw_sp *mlxsw_sp,
4597                                    const struct mlxsw_listener listeners[],
4598                                    size_t listeners_count)
4599 {
4600         int i;
4601         int err;
4602
4603         for (i = 0; i < listeners_count; i++) {
4604                 err = mlxsw_core_trap_register(mlxsw_sp->core,
4605                                                &listeners[i],
4606                                                mlxsw_sp);
4607                 if (err)
4608                         goto err_listener_register;
4609
4610         }
4611         return 0;
4612
4613 err_listener_register:
4614         for (i--; i >= 0; i--) {
4615                 mlxsw_core_trap_unregister(mlxsw_sp->core,
4616                                            &listeners[i],
4617                                            mlxsw_sp);
4618         }
4619         return err;
4620 }
4621
4622 static void mlxsw_sp_traps_unregister(struct mlxsw_sp *mlxsw_sp,
4623                                       const struct mlxsw_listener listeners[],
4624                                       size_t listeners_count)
4625 {
4626         int i;
4627
4628         for (i = 0; i < listeners_count; i++) {
4629                 mlxsw_core_trap_unregister(mlxsw_sp->core,
4630                                            &listeners[i],
4631                                            mlxsw_sp);
4632         }
4633 }
4634
4635 static int mlxsw_sp_traps_init(struct mlxsw_sp *mlxsw_sp)
4636 {
4637         int err;
4638
4639         err = mlxsw_sp_cpu_policers_set(mlxsw_sp->core);
4640         if (err)
4641                 return err;
4642
4643         err = mlxsw_sp_trap_groups_set(mlxsw_sp->core);
4644         if (err)
4645                 return err;
4646
4647         err = mlxsw_sp_traps_register(mlxsw_sp, mlxsw_sp_listener,
4648                                       ARRAY_SIZE(mlxsw_sp_listener));
4649         if (err)
4650                 return err;
4651
4652         err = mlxsw_sp_traps_register(mlxsw_sp, mlxsw_sp->listeners,
4653                                       mlxsw_sp->listeners_count);
4654         if (err)
4655                 goto err_extra_traps_init;
4656
4657         return 0;
4658
4659 err_extra_traps_init:
4660         mlxsw_sp_traps_unregister(mlxsw_sp, mlxsw_sp_listener,
4661                                   ARRAY_SIZE(mlxsw_sp_listener));
4662         return err;
4663 }
4664
4665 static void mlxsw_sp_traps_fini(struct mlxsw_sp *mlxsw_sp)
4666 {
4667         mlxsw_sp_traps_unregister(mlxsw_sp, mlxsw_sp->listeners,
4668                                   mlxsw_sp->listeners_count);
4669         mlxsw_sp_traps_unregister(mlxsw_sp, mlxsw_sp_listener,
4670                                   ARRAY_SIZE(mlxsw_sp_listener));
4671 }
4672
4673 #define MLXSW_SP_LAG_SEED_INIT 0xcafecafe
4674
4675 static int mlxsw_sp_lag_init(struct mlxsw_sp *mlxsw_sp)
4676 {
4677         char slcr_pl[MLXSW_REG_SLCR_LEN];
4678         u32 seed;
4679         int err;
4680
4681         seed = jhash(mlxsw_sp->base_mac, sizeof(mlxsw_sp->base_mac),
4682                      MLXSW_SP_LAG_SEED_INIT);
4683         mlxsw_reg_slcr_pack(slcr_pl, MLXSW_REG_SLCR_LAG_HASH_SMAC |
4684                                      MLXSW_REG_SLCR_LAG_HASH_DMAC |
4685                                      MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE |
4686                                      MLXSW_REG_SLCR_LAG_HASH_VLANID |
4687                                      MLXSW_REG_SLCR_LAG_HASH_SIP |
4688                                      MLXSW_REG_SLCR_LAG_HASH_DIP |
4689                                      MLXSW_REG_SLCR_LAG_HASH_SPORT |
4690                                      MLXSW_REG_SLCR_LAG_HASH_DPORT |
4691                                      MLXSW_REG_SLCR_LAG_HASH_IPPROTO, seed);
4692         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcr), slcr_pl);
4693         if (err)
4694                 return err;
4695
4696         if (!MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG) ||
4697             !MLXSW_CORE_RES_VALID(mlxsw_sp->core, MAX_LAG_MEMBERS))
4698                 return -EIO;
4699
4700         mlxsw_sp->lags = kcalloc(MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG),
4701                                  sizeof(struct mlxsw_sp_upper),
4702                                  GFP_KERNEL);
4703         if (!mlxsw_sp->lags)
4704                 return -ENOMEM;
4705
4706         return 0;
4707 }
4708
4709 static void mlxsw_sp_lag_fini(struct mlxsw_sp *mlxsw_sp)
4710 {
4711         kfree(mlxsw_sp->lags);
4712 }
4713
4714 static int mlxsw_sp_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
4715 {
4716         char htgt_pl[MLXSW_REG_HTGT_LEN];
4717
4718         mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
4719                             MLXSW_REG_HTGT_INVALID_POLICER,
4720                             MLXSW_REG_HTGT_DEFAULT_PRIORITY,
4721                             MLXSW_REG_HTGT_DEFAULT_TC);
4722         return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
4723 }
4724
4725 static const struct mlxsw_sp_ptp_ops mlxsw_sp1_ptp_ops = {
4726         .clock_init     = mlxsw_sp1_ptp_clock_init,
4727         .clock_fini     = mlxsw_sp1_ptp_clock_fini,
4728         .init           = mlxsw_sp1_ptp_init,
4729         .fini           = mlxsw_sp1_ptp_fini,
4730         .receive        = mlxsw_sp1_ptp_receive,
4731         .transmitted    = mlxsw_sp1_ptp_transmitted,
4732         .hwtstamp_get   = mlxsw_sp1_ptp_hwtstamp_get,
4733         .hwtstamp_set   = mlxsw_sp1_ptp_hwtstamp_set,
4734         .shaper_work    = mlxsw_sp1_ptp_shaper_work,
4735         .get_ts_info    = mlxsw_sp1_ptp_get_ts_info,
4736         .get_stats_count = mlxsw_sp1_get_stats_count,
4737         .get_stats_strings = mlxsw_sp1_get_stats_strings,
4738         .get_stats      = mlxsw_sp1_get_stats,
4739 };
4740
4741 static const struct mlxsw_sp_ptp_ops mlxsw_sp2_ptp_ops = {
4742         .clock_init     = mlxsw_sp2_ptp_clock_init,
4743         .clock_fini     = mlxsw_sp2_ptp_clock_fini,
4744         .init           = mlxsw_sp2_ptp_init,
4745         .fini           = mlxsw_sp2_ptp_fini,
4746         .receive        = mlxsw_sp2_ptp_receive,
4747         .transmitted    = mlxsw_sp2_ptp_transmitted,
4748         .hwtstamp_get   = mlxsw_sp2_ptp_hwtstamp_get,
4749         .hwtstamp_set   = mlxsw_sp2_ptp_hwtstamp_set,
4750         .shaper_work    = mlxsw_sp2_ptp_shaper_work,
4751         .get_ts_info    = mlxsw_sp2_ptp_get_ts_info,
4752         .get_stats_count = mlxsw_sp2_get_stats_count,
4753         .get_stats_strings = mlxsw_sp2_get_stats_strings,
4754         .get_stats      = mlxsw_sp2_get_stats,
4755 };
4756
4757 static int mlxsw_sp_netdevice_event(struct notifier_block *unused,
4758                                     unsigned long event, void *ptr);
4759
4760 static int mlxsw_sp_init(struct mlxsw_core *mlxsw_core,
4761                          const struct mlxsw_bus_info *mlxsw_bus_info)
4762 {
4763         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4764         int err;
4765
4766         mlxsw_sp->core = mlxsw_core;
4767         mlxsw_sp->bus_info = mlxsw_bus_info;
4768
4769         err = mlxsw_sp_fw_rev_validate(mlxsw_sp);
4770         if (err)
4771                 return err;
4772
4773         err = mlxsw_sp_base_mac_get(mlxsw_sp);
4774         if (err) {
4775                 dev_err(mlxsw_sp->bus_info->dev, "Failed to get base mac\n");
4776                 return err;
4777         }
4778
4779         err = mlxsw_sp_kvdl_init(mlxsw_sp);
4780         if (err) {
4781                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize KVDL\n");
4782                 return err;
4783         }
4784
4785         err = mlxsw_sp_fids_init(mlxsw_sp);
4786         if (err) {
4787                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize FIDs\n");
4788                 goto err_fids_init;
4789         }
4790
4791         err = mlxsw_sp_traps_init(mlxsw_sp);
4792         if (err) {
4793                 dev_err(mlxsw_sp->bus_info->dev, "Failed to set traps\n");
4794                 goto err_traps_init;
4795         }
4796
4797         err = mlxsw_sp_devlink_traps_init(mlxsw_sp);
4798         if (err) {
4799                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize devlink traps\n");
4800                 goto err_devlink_traps_init;
4801         }
4802
4803         err = mlxsw_sp_buffers_init(mlxsw_sp);
4804         if (err) {
4805                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize buffers\n");
4806                 goto err_buffers_init;
4807         }
4808
4809         err = mlxsw_sp_lag_init(mlxsw_sp);
4810         if (err) {
4811                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize LAG\n");
4812                 goto err_lag_init;
4813         }
4814
4815         /* Initialize SPAN before router and switchdev, so that those components
4816          * can call mlxsw_sp_span_respin().
4817          */
4818         err = mlxsw_sp_span_init(mlxsw_sp);
4819         if (err) {
4820                 dev_err(mlxsw_sp->bus_info->dev, "Failed to init span system\n");
4821                 goto err_span_init;
4822         }
4823
4824         err = mlxsw_sp_switchdev_init(mlxsw_sp);
4825         if (err) {
4826                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize switchdev\n");
4827                 goto err_switchdev_init;
4828         }
4829
4830         err = mlxsw_sp_counter_pool_init(mlxsw_sp);
4831         if (err) {
4832                 dev_err(mlxsw_sp->bus_info->dev, "Failed to init counter pool\n");
4833                 goto err_counter_pool_init;
4834         }
4835
4836         err = mlxsw_sp_afa_init(mlxsw_sp);
4837         if (err) {
4838                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL actions\n");
4839                 goto err_afa_init;
4840         }
4841
4842         err = mlxsw_sp_nve_init(mlxsw_sp);
4843         if (err) {
4844                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize NVE\n");
4845                 goto err_nve_init;
4846         }
4847
4848         err = mlxsw_sp_acl_init(mlxsw_sp);
4849         if (err) {
4850                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize ACL\n");
4851                 goto err_acl_init;
4852         }
4853
4854         err = mlxsw_sp_router_init(mlxsw_sp);
4855         if (err) {
4856                 dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize router\n");
4857                 goto err_router_init;
4858         }
4859
4860         if (mlxsw_sp->bus_info->read_frc_capable) {
4861                 /* NULL is a valid return value from clock_init */
4862                 mlxsw_sp->clock =
4863                         mlxsw_sp->ptp_ops->clock_init(mlxsw_sp,
4864                                                       mlxsw_sp->bus_info->dev);
4865                 if (IS_ERR(mlxsw_sp->clock)) {
4866                         err = PTR_ERR(mlxsw_sp->clock);
4867                         dev_err(mlxsw_sp->bus_info->dev, "Failed to init ptp clock\n");
4868                         goto err_ptp_clock_init;
4869                 }
4870         }
4871
4872         if (mlxsw_sp->clock) {
4873                 /* NULL is a valid return value from ptp_ops->init */
4874                 mlxsw_sp->ptp_state = mlxsw_sp->ptp_ops->init(mlxsw_sp);
4875                 if (IS_ERR(mlxsw_sp->ptp_state)) {
4876                         err = PTR_ERR(mlxsw_sp->ptp_state);
4877                         dev_err(mlxsw_sp->bus_info->dev, "Failed to initialize PTP\n");
4878                         goto err_ptp_init;
4879                 }
4880         }
4881
4882         /* Initialize netdevice notifier after router and SPAN is initialized,
4883          * so that the event handler can use router structures and call SPAN
4884          * respin.
4885          */
4886         mlxsw_sp->netdevice_nb.notifier_call = mlxsw_sp_netdevice_event;
4887         err = register_netdevice_notifier(&mlxsw_sp->netdevice_nb);
4888         if (err) {
4889                 dev_err(mlxsw_sp->bus_info->dev, "Failed to register netdev notifier\n");
4890                 goto err_netdev_notifier;
4891         }
4892
4893         err = mlxsw_sp_dpipe_init(mlxsw_sp);
4894         if (err) {
4895                 dev_err(mlxsw_sp->bus_info->dev, "Failed to init pipeline debug\n");
4896                 goto err_dpipe_init;
4897         }
4898
4899         err = mlxsw_sp_ports_create(mlxsw_sp);
4900         if (err) {
4901                 dev_err(mlxsw_sp->bus_info->dev, "Failed to create ports\n");
4902                 goto err_ports_create;
4903         }
4904
4905         return 0;
4906
4907 err_ports_create:
4908         mlxsw_sp_dpipe_fini(mlxsw_sp);
4909 err_dpipe_init:
4910         unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
4911 err_netdev_notifier:
4912         if (mlxsw_sp->clock)
4913                 mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state);
4914 err_ptp_init:
4915         if (mlxsw_sp->clock)
4916                 mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock);
4917 err_ptp_clock_init:
4918         mlxsw_sp_router_fini(mlxsw_sp);
4919 err_router_init:
4920         mlxsw_sp_acl_fini(mlxsw_sp);
4921 err_acl_init:
4922         mlxsw_sp_nve_fini(mlxsw_sp);
4923 err_nve_init:
4924         mlxsw_sp_afa_fini(mlxsw_sp);
4925 err_afa_init:
4926         mlxsw_sp_counter_pool_fini(mlxsw_sp);
4927 err_counter_pool_init:
4928         mlxsw_sp_switchdev_fini(mlxsw_sp);
4929 err_switchdev_init:
4930         mlxsw_sp_span_fini(mlxsw_sp);
4931 err_span_init:
4932         mlxsw_sp_lag_fini(mlxsw_sp);
4933 err_lag_init:
4934         mlxsw_sp_buffers_fini(mlxsw_sp);
4935 err_buffers_init:
4936         mlxsw_sp_devlink_traps_fini(mlxsw_sp);
4937 err_devlink_traps_init:
4938         mlxsw_sp_traps_fini(mlxsw_sp);
4939 err_traps_init:
4940         mlxsw_sp_fids_fini(mlxsw_sp);
4941 err_fids_init:
4942         mlxsw_sp_kvdl_fini(mlxsw_sp);
4943         return err;
4944 }
4945
4946 static int mlxsw_sp1_init(struct mlxsw_core *mlxsw_core,
4947                           const struct mlxsw_bus_info *mlxsw_bus_info)
4948 {
4949         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4950
4951         mlxsw_sp->req_rev = &mlxsw_sp1_fw_rev;
4952         mlxsw_sp->fw_filename = MLXSW_SP1_FW_FILENAME;
4953         mlxsw_sp->kvdl_ops = &mlxsw_sp1_kvdl_ops;
4954         mlxsw_sp->afa_ops = &mlxsw_sp1_act_afa_ops;
4955         mlxsw_sp->afk_ops = &mlxsw_sp1_afk_ops;
4956         mlxsw_sp->mr_tcam_ops = &mlxsw_sp1_mr_tcam_ops;
4957         mlxsw_sp->acl_tcam_ops = &mlxsw_sp1_acl_tcam_ops;
4958         mlxsw_sp->nve_ops_arr = mlxsw_sp1_nve_ops_arr;
4959         mlxsw_sp->mac_mask = mlxsw_sp1_mac_mask;
4960         mlxsw_sp->rif_ops_arr = mlxsw_sp1_rif_ops_arr;
4961         mlxsw_sp->sb_vals = &mlxsw_sp1_sb_vals;
4962         mlxsw_sp->port_type_speed_ops = &mlxsw_sp1_port_type_speed_ops;
4963         mlxsw_sp->ptp_ops = &mlxsw_sp1_ptp_ops;
4964         mlxsw_sp->listeners = mlxsw_sp1_listener;
4965         mlxsw_sp->listeners_count = ARRAY_SIZE(mlxsw_sp1_listener);
4966
4967         return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info);
4968 }
4969
4970 static int mlxsw_sp2_init(struct mlxsw_core *mlxsw_core,
4971                           const struct mlxsw_bus_info *mlxsw_bus_info)
4972 {
4973         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4974
4975         mlxsw_sp->kvdl_ops = &mlxsw_sp2_kvdl_ops;
4976         mlxsw_sp->afa_ops = &mlxsw_sp2_act_afa_ops;
4977         mlxsw_sp->afk_ops = &mlxsw_sp2_afk_ops;
4978         mlxsw_sp->mr_tcam_ops = &mlxsw_sp2_mr_tcam_ops;
4979         mlxsw_sp->acl_tcam_ops = &mlxsw_sp2_acl_tcam_ops;
4980         mlxsw_sp->nve_ops_arr = mlxsw_sp2_nve_ops_arr;
4981         mlxsw_sp->mac_mask = mlxsw_sp2_mac_mask;
4982         mlxsw_sp->rif_ops_arr = mlxsw_sp2_rif_ops_arr;
4983         mlxsw_sp->sb_vals = &mlxsw_sp2_sb_vals;
4984         mlxsw_sp->port_type_speed_ops = &mlxsw_sp2_port_type_speed_ops;
4985         mlxsw_sp->ptp_ops = &mlxsw_sp2_ptp_ops;
4986
4987         return mlxsw_sp_init(mlxsw_core, mlxsw_bus_info);
4988 }
4989
4990 static void mlxsw_sp_fini(struct mlxsw_core *mlxsw_core)
4991 {
4992         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
4993
4994         mlxsw_sp_ports_remove(mlxsw_sp);
4995         mlxsw_sp_dpipe_fini(mlxsw_sp);
4996         unregister_netdevice_notifier(&mlxsw_sp->netdevice_nb);
4997         if (mlxsw_sp->clock) {
4998                 mlxsw_sp->ptp_ops->fini(mlxsw_sp->ptp_state);
4999                 mlxsw_sp->ptp_ops->clock_fini(mlxsw_sp->clock);
5000         }
5001         mlxsw_sp_router_fini(mlxsw_sp);
5002         mlxsw_sp_acl_fini(mlxsw_sp);
5003         mlxsw_sp_nve_fini(mlxsw_sp);
5004         mlxsw_sp_afa_fini(mlxsw_sp);
5005         mlxsw_sp_counter_pool_fini(mlxsw_sp);
5006         mlxsw_sp_switchdev_fini(mlxsw_sp);
5007         mlxsw_sp_span_fini(mlxsw_sp);
5008         mlxsw_sp_lag_fini(mlxsw_sp);
5009         mlxsw_sp_buffers_fini(mlxsw_sp);
5010         mlxsw_sp_devlink_traps_fini(mlxsw_sp);
5011         mlxsw_sp_traps_fini(mlxsw_sp);
5012         mlxsw_sp_fids_fini(mlxsw_sp);
5013         mlxsw_sp_kvdl_fini(mlxsw_sp);
5014 }
5015
5016 /* Per-FID flood tables are used for both "true" 802.1D FIDs and emulated
5017  * 802.1Q FIDs
5018  */
5019 #define MLXSW_SP_FID_FLOOD_TABLE_SIZE   (MLXSW_SP_FID_8021D_MAX + \
5020                                          VLAN_VID_MASK - 1)
5021
5022 static const struct mlxsw_config_profile mlxsw_sp1_config_profile = {
5023         .used_max_mid                   = 1,
5024         .max_mid                        = MLXSW_SP_MID_MAX,
5025         .used_flood_tables              = 1,
5026         .used_flood_mode                = 1,
5027         .flood_mode                     = 3,
5028         .max_fid_flood_tables           = 3,
5029         .fid_flood_table_size           = MLXSW_SP_FID_FLOOD_TABLE_SIZE,
5030         .used_max_ib_mc                 = 1,
5031         .max_ib_mc                      = 0,
5032         .used_max_pkey                  = 1,
5033         .max_pkey                       = 0,
5034         .used_kvd_sizes                 = 1,
5035         .kvd_hash_single_parts          = 59,
5036         .kvd_hash_double_parts          = 41,
5037         .kvd_linear_size                = MLXSW_SP_KVD_LINEAR_SIZE,
5038         .swid_config                    = {
5039                 {
5040                         .used_type      = 1,
5041                         .type           = MLXSW_PORT_SWID_TYPE_ETH,
5042                 }
5043         },
5044 };
5045
5046 static const struct mlxsw_config_profile mlxsw_sp2_config_profile = {
5047         .used_max_mid                   = 1,
5048         .max_mid                        = MLXSW_SP_MID_MAX,
5049         .used_flood_tables              = 1,
5050         .used_flood_mode                = 1,
5051         .flood_mode                     = 3,
5052         .max_fid_flood_tables           = 3,
5053         .fid_flood_table_size           = MLXSW_SP_FID_FLOOD_TABLE_SIZE,
5054         .used_max_ib_mc                 = 1,
5055         .max_ib_mc                      = 0,
5056         .used_max_pkey                  = 1,
5057         .max_pkey                       = 0,
5058         .swid_config                    = {
5059                 {
5060                         .used_type      = 1,
5061                         .type           = MLXSW_PORT_SWID_TYPE_ETH,
5062                 }
5063         },
5064 };
5065
5066 static void
5067 mlxsw_sp_resource_size_params_prepare(struct mlxsw_core *mlxsw_core,
5068                                       struct devlink_resource_size_params *kvd_size_params,
5069                                       struct devlink_resource_size_params *linear_size_params,
5070                                       struct devlink_resource_size_params *hash_double_size_params,
5071                                       struct devlink_resource_size_params *hash_single_size_params)
5072 {
5073         u32 single_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
5074                                                  KVD_SINGLE_MIN_SIZE);
5075         u32 double_size_min = MLXSW_CORE_RES_GET(mlxsw_core,
5076                                                  KVD_DOUBLE_MIN_SIZE);
5077         u32 kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
5078         u32 linear_size_min = 0;
5079
5080         devlink_resource_size_params_init(kvd_size_params, kvd_size, kvd_size,
5081                                           MLXSW_SP_KVD_GRANULARITY,
5082                                           DEVLINK_RESOURCE_UNIT_ENTRY);
5083         devlink_resource_size_params_init(linear_size_params, linear_size_min,
5084                                           kvd_size - single_size_min -
5085                                           double_size_min,
5086                                           MLXSW_SP_KVD_GRANULARITY,
5087                                           DEVLINK_RESOURCE_UNIT_ENTRY);
5088         devlink_resource_size_params_init(hash_double_size_params,
5089                                           double_size_min,
5090                                           kvd_size - single_size_min -
5091                                           linear_size_min,
5092                                           MLXSW_SP_KVD_GRANULARITY,
5093                                           DEVLINK_RESOURCE_UNIT_ENTRY);
5094         devlink_resource_size_params_init(hash_single_size_params,
5095                                           single_size_min,
5096                                           kvd_size - double_size_min -
5097                                           linear_size_min,
5098                                           MLXSW_SP_KVD_GRANULARITY,
5099                                           DEVLINK_RESOURCE_UNIT_ENTRY);
5100 }
5101
5102 static int mlxsw_sp1_resources_kvd_register(struct mlxsw_core *mlxsw_core)
5103 {
5104         struct devlink *devlink = priv_to_devlink(mlxsw_core);
5105         struct devlink_resource_size_params hash_single_size_params;
5106         struct devlink_resource_size_params hash_double_size_params;
5107         struct devlink_resource_size_params linear_size_params;
5108         struct devlink_resource_size_params kvd_size_params;
5109         u32 kvd_size, single_size, double_size, linear_size;
5110         const struct mlxsw_config_profile *profile;
5111         int err;
5112
5113         profile = &mlxsw_sp1_config_profile;
5114         if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
5115                 return -EIO;
5116
5117         mlxsw_sp_resource_size_params_prepare(mlxsw_core, &kvd_size_params,
5118                                               &linear_size_params,
5119                                               &hash_double_size_params,
5120                                               &hash_single_size_params);
5121
5122         kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
5123         err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
5124                                         kvd_size, MLXSW_SP_RESOURCE_KVD,
5125                                         DEVLINK_RESOURCE_ID_PARENT_TOP,
5126                                         &kvd_size_params);
5127         if (err)
5128                 return err;
5129
5130         linear_size = profile->kvd_linear_size;
5131         err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_LINEAR,
5132                                         linear_size,
5133                                         MLXSW_SP_RESOURCE_KVD_LINEAR,
5134                                         MLXSW_SP_RESOURCE_KVD,
5135                                         &linear_size_params);
5136         if (err)
5137                 return err;
5138
5139         err = mlxsw_sp1_kvdl_resources_register(mlxsw_core);
5140         if  (err)
5141                 return err;
5142
5143         double_size = kvd_size - linear_size;
5144         double_size *= profile->kvd_hash_double_parts;
5145         double_size /= profile->kvd_hash_double_parts +
5146                        profile->kvd_hash_single_parts;
5147         double_size = rounddown(double_size, MLXSW_SP_KVD_GRANULARITY);
5148         err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_DOUBLE,
5149                                         double_size,
5150                                         MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
5151                                         MLXSW_SP_RESOURCE_KVD,
5152                                         &hash_double_size_params);
5153         if (err)
5154                 return err;
5155
5156         single_size = kvd_size - double_size - linear_size;
5157         err = devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD_HASH_SINGLE,
5158                                         single_size,
5159                                         MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
5160                                         MLXSW_SP_RESOURCE_KVD,
5161                                         &hash_single_size_params);
5162         if (err)
5163                 return err;
5164
5165         return 0;
5166 }
5167
5168 static int mlxsw_sp2_resources_kvd_register(struct mlxsw_core *mlxsw_core)
5169 {
5170         struct devlink *devlink = priv_to_devlink(mlxsw_core);
5171         struct devlink_resource_size_params kvd_size_params;
5172         u32 kvd_size;
5173
5174         if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SIZE))
5175                 return -EIO;
5176
5177         kvd_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE);
5178         devlink_resource_size_params_init(&kvd_size_params, kvd_size, kvd_size,
5179                                           MLXSW_SP_KVD_GRANULARITY,
5180                                           DEVLINK_RESOURCE_UNIT_ENTRY);
5181
5182         return devlink_resource_register(devlink, MLXSW_SP_RESOURCE_NAME_KVD,
5183                                          kvd_size, MLXSW_SP_RESOURCE_KVD,
5184                                          DEVLINK_RESOURCE_ID_PARENT_TOP,
5185                                          &kvd_size_params);
5186 }
5187
5188 static int mlxsw_sp1_resources_register(struct mlxsw_core *mlxsw_core)
5189 {
5190         return mlxsw_sp1_resources_kvd_register(mlxsw_core);
5191 }
5192
5193 static int mlxsw_sp2_resources_register(struct mlxsw_core *mlxsw_core)
5194 {
5195         return mlxsw_sp2_resources_kvd_register(mlxsw_core);
5196 }
5197
5198 static int mlxsw_sp_kvd_sizes_get(struct mlxsw_core *mlxsw_core,
5199                                   const struct mlxsw_config_profile *profile,
5200                                   u64 *p_single_size, u64 *p_double_size,
5201                                   u64 *p_linear_size)
5202 {
5203         struct devlink *devlink = priv_to_devlink(mlxsw_core);
5204         u32 double_size;
5205         int err;
5206
5207         if (!MLXSW_CORE_RES_VALID(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
5208             !MLXSW_CORE_RES_VALID(mlxsw_core, KVD_DOUBLE_MIN_SIZE))
5209                 return -EIO;
5210
5211         /* The hash part is what left of the kvd without the
5212          * linear part. It is split to the single size and
5213          * double size by the parts ratio from the profile.
5214          * Both sizes must be a multiplications of the
5215          * granularity from the profile. In case the user
5216          * provided the sizes they are obtained via devlink.
5217          */
5218         err = devlink_resource_size_get(devlink,
5219                                         MLXSW_SP_RESOURCE_KVD_LINEAR,
5220                                         p_linear_size);
5221         if (err)
5222                 *p_linear_size = profile->kvd_linear_size;
5223
5224         err = devlink_resource_size_get(devlink,
5225                                         MLXSW_SP_RESOURCE_KVD_HASH_DOUBLE,
5226                                         p_double_size);
5227         if (err) {
5228                 double_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
5229                               *p_linear_size;
5230                 double_size *= profile->kvd_hash_double_parts;
5231                 double_size /= profile->kvd_hash_double_parts +
5232                                profile->kvd_hash_single_parts;
5233                 *p_double_size = rounddown(double_size,
5234                                            MLXSW_SP_KVD_GRANULARITY);
5235         }
5236
5237         err = devlink_resource_size_get(devlink,
5238                                         MLXSW_SP_RESOURCE_KVD_HASH_SINGLE,
5239                                         p_single_size);
5240         if (err)
5241                 *p_single_size = MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) -
5242                                  *p_double_size - *p_linear_size;
5243
5244         /* Check results are legal. */
5245         if (*p_single_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_SINGLE_MIN_SIZE) ||
5246             *p_double_size < MLXSW_CORE_RES_GET(mlxsw_core, KVD_DOUBLE_MIN_SIZE) ||
5247             MLXSW_CORE_RES_GET(mlxsw_core, KVD_SIZE) < *p_linear_size)
5248                 return -EIO;
5249
5250         return 0;
5251 }
5252
5253 static int
5254 mlxsw_sp_devlink_param_fw_load_policy_validate(struct devlink *devlink, u32 id,
5255                                                union devlink_param_value val,
5256                                                struct netlink_ext_ack *extack)
5257 {
5258         if ((val.vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER) &&
5259             (val.vu8 != DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_FLASH)) {
5260                 NL_SET_ERR_MSG_MOD(extack, "'fw_load_policy' must be 'driver' or 'flash'");
5261                 return -EINVAL;
5262         }
5263
5264         return 0;
5265 }
5266
5267 static const struct devlink_param mlxsw_sp_devlink_params[] = {
5268         DEVLINK_PARAM_GENERIC(FW_LOAD_POLICY,
5269                               BIT(DEVLINK_PARAM_CMODE_DRIVERINIT),
5270                               NULL, NULL,
5271                               mlxsw_sp_devlink_param_fw_load_policy_validate),
5272 };
5273
5274 static int mlxsw_sp_params_register(struct mlxsw_core *mlxsw_core)
5275 {
5276         struct devlink *devlink = priv_to_devlink(mlxsw_core);
5277         union devlink_param_value value;
5278         int err;
5279
5280         err = devlink_params_register(devlink, mlxsw_sp_devlink_params,
5281                                       ARRAY_SIZE(mlxsw_sp_devlink_params));
5282         if (err)
5283                 return err;
5284
5285         value.vu8 = DEVLINK_PARAM_FW_LOAD_POLICY_VALUE_DRIVER;
5286         devlink_param_driverinit_value_set(devlink,
5287                                            DEVLINK_PARAM_GENERIC_ID_FW_LOAD_POLICY,
5288                                            value);
5289         return 0;
5290 }
5291
5292 static void mlxsw_sp_params_unregister(struct mlxsw_core *mlxsw_core)
5293 {
5294         devlink_params_unregister(priv_to_devlink(mlxsw_core),
5295                                   mlxsw_sp_devlink_params,
5296                                   ARRAY_SIZE(mlxsw_sp_devlink_params));
5297 }
5298
5299 static int
5300 mlxsw_sp_params_acl_region_rehash_intrvl_get(struct devlink *devlink, u32 id,
5301                                              struct devlink_param_gset_ctx *ctx)
5302 {
5303         struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
5304         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
5305
5306         ctx->val.vu32 = mlxsw_sp_acl_region_rehash_intrvl_get(mlxsw_sp);
5307         return 0;
5308 }
5309
5310 static int
5311 mlxsw_sp_params_acl_region_rehash_intrvl_set(struct devlink *devlink, u32 id,
5312                                              struct devlink_param_gset_ctx *ctx)
5313 {
5314         struct mlxsw_core *mlxsw_core = devlink_priv(devlink);
5315         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
5316
5317         return mlxsw_sp_acl_region_rehash_intrvl_set(mlxsw_sp, ctx->val.vu32);
5318 }
5319
5320 static const struct devlink_param mlxsw_sp2_devlink_params[] = {
5321         DEVLINK_PARAM_DRIVER(MLXSW_DEVLINK_PARAM_ID_ACL_REGION_REHASH_INTERVAL,
5322                              "acl_region_rehash_interval",
5323                              DEVLINK_PARAM_TYPE_U32,
5324                              BIT(DEVLINK_PARAM_CMODE_RUNTIME),
5325                              mlxsw_sp_params_acl_region_rehash_intrvl_get,
5326                              mlxsw_sp_params_acl_region_rehash_intrvl_set,
5327                              NULL),
5328 };
5329
5330 static int mlxsw_sp2_params_register(struct mlxsw_core *mlxsw_core)
5331 {
5332         struct devlink *devlink = priv_to_devlink(mlxsw_core);
5333         union devlink_param_value value;
5334         int err;
5335
5336         err = mlxsw_sp_params_register(mlxsw_core);
5337         if (err)
5338                 return err;
5339
5340         err = devlink_params_register(devlink, mlxsw_sp2_devlink_params,
5341                                       ARRAY_SIZE(mlxsw_sp2_devlink_params));
5342         if (err)
5343                 goto err_devlink_params_register;
5344
5345         value.vu32 = 0;
5346         devlink_param_driverinit_value_set(devlink,
5347                                            MLXSW_DEVLINK_PARAM_ID_ACL_REGION_REHASH_INTERVAL,
5348                                            value);
5349         return 0;
5350
5351 err_devlink_params_register:
5352         mlxsw_sp_params_unregister(mlxsw_core);
5353         return err;
5354 }
5355
5356 static void mlxsw_sp2_params_unregister(struct mlxsw_core *mlxsw_core)
5357 {
5358         devlink_params_unregister(priv_to_devlink(mlxsw_core),
5359                                   mlxsw_sp2_devlink_params,
5360                                   ARRAY_SIZE(mlxsw_sp2_devlink_params));
5361         mlxsw_sp_params_unregister(mlxsw_core);
5362 }
5363
5364 static void mlxsw_sp_ptp_transmitted(struct mlxsw_core *mlxsw_core,
5365                                      struct sk_buff *skb, u8 local_port)
5366 {
5367         struct mlxsw_sp *mlxsw_sp = mlxsw_core_driver_priv(mlxsw_core);
5368
5369         skb_pull(skb, MLXSW_TXHDR_LEN);
5370         mlxsw_sp->ptp_ops->transmitted(mlxsw_sp, skb, local_port);
5371 }
5372
5373 static struct mlxsw_driver mlxsw_sp1_driver = {
5374         .kind                           = mlxsw_sp1_driver_name,
5375         .priv_size                      = sizeof(struct mlxsw_sp),
5376         .init                           = mlxsw_sp1_init,
5377         .fini                           = mlxsw_sp_fini,
5378         .basic_trap_groups_set          = mlxsw_sp_basic_trap_groups_set,
5379         .port_split                     = mlxsw_sp_port_split,
5380         .port_unsplit                   = mlxsw_sp_port_unsplit,
5381         .sb_pool_get                    = mlxsw_sp_sb_pool_get,
5382         .sb_pool_set                    = mlxsw_sp_sb_pool_set,
5383         .sb_port_pool_get               = mlxsw_sp_sb_port_pool_get,
5384         .sb_port_pool_set               = mlxsw_sp_sb_port_pool_set,
5385         .sb_tc_pool_bind_get            = mlxsw_sp_sb_tc_pool_bind_get,
5386         .sb_tc_pool_bind_set            = mlxsw_sp_sb_tc_pool_bind_set,
5387         .sb_occ_snapshot                = mlxsw_sp_sb_occ_snapshot,
5388         .sb_occ_max_clear               = mlxsw_sp_sb_occ_max_clear,
5389         .sb_occ_port_pool_get           = mlxsw_sp_sb_occ_port_pool_get,
5390         .sb_occ_tc_port_bind_get        = mlxsw_sp_sb_occ_tc_port_bind_get,
5391         .flash_update                   = mlxsw_sp_flash_update,
5392         .trap_init                      = mlxsw_sp_trap_init,
5393         .trap_fini                      = mlxsw_sp_trap_fini,
5394         .trap_action_set                = mlxsw_sp_trap_action_set,
5395         .trap_group_init                = mlxsw_sp_trap_group_init,
5396         .txhdr_construct                = mlxsw_sp_txhdr_construct,
5397         .resources_register             = mlxsw_sp1_resources_register,
5398         .kvd_sizes_get                  = mlxsw_sp_kvd_sizes_get,
5399         .params_register                = mlxsw_sp_params_register,
5400         .params_unregister              = mlxsw_sp_params_unregister,
5401         .ptp_transmitted                = mlxsw_sp_ptp_transmitted,
5402         .txhdr_len                      = MLXSW_TXHDR_LEN,
5403         .profile                        = &mlxsw_sp1_config_profile,
5404         .res_query_enabled              = true,
5405 };
5406
5407 static struct mlxsw_driver mlxsw_sp2_driver = {
5408         .kind                           = mlxsw_sp2_driver_name,
5409         .priv_size                      = sizeof(struct mlxsw_sp),
5410         .init                           = mlxsw_sp2_init,
5411         .fini                           = mlxsw_sp_fini,
5412         .basic_trap_groups_set          = mlxsw_sp_basic_trap_groups_set,
5413         .port_split                     = mlxsw_sp_port_split,
5414         .port_unsplit                   = mlxsw_sp_port_unsplit,
5415         .sb_pool_get                    = mlxsw_sp_sb_pool_get,
5416         .sb_pool_set                    = mlxsw_sp_sb_pool_set,
5417         .sb_port_pool_get               = mlxsw_sp_sb_port_pool_get,
5418         .sb_port_pool_set               = mlxsw_sp_sb_port_pool_set,
5419         .sb_tc_pool_bind_get            = mlxsw_sp_sb_tc_pool_bind_get,
5420         .sb_tc_pool_bind_set            = mlxsw_sp_sb_tc_pool_bind_set,
5421         .sb_occ_snapshot                = mlxsw_sp_sb_occ_snapshot,
5422         .sb_occ_max_clear               = mlxsw_sp_sb_occ_max_clear,
5423         .sb_occ_port_pool_get           = mlxsw_sp_sb_occ_port_pool_get,
5424         .sb_occ_tc_port_bind_get        = mlxsw_sp_sb_occ_tc_port_bind_get,
5425         .flash_update                   = mlxsw_sp_flash_update,
5426         .trap_init                      = mlxsw_sp_trap_init,
5427         .trap_fini                      = mlxsw_sp_trap_fini,
5428         .trap_action_set                = mlxsw_sp_trap_action_set,
5429         .trap_group_init                = mlxsw_sp_trap_group_init,
5430         .txhdr_construct                = mlxsw_sp_txhdr_construct,
5431         .resources_register             = mlxsw_sp2_resources_register,
5432         .params_register                = mlxsw_sp2_params_register,
5433         .params_unregister              = mlxsw_sp2_params_unregister,
5434         .ptp_transmitted                = mlxsw_sp_ptp_transmitted,
5435         .txhdr_len                      = MLXSW_TXHDR_LEN,
5436         .profile                        = &mlxsw_sp2_config_profile,
5437         .res_query_enabled              = true,
5438 };
5439
5440 static struct mlxsw_driver mlxsw_sp3_driver = {
5441         .kind                           = mlxsw_sp3_driver_name,
5442         .priv_size                      = sizeof(struct mlxsw_sp),
5443         .init                           = mlxsw_sp2_init,
5444         .fini                           = mlxsw_sp_fini,
5445         .basic_trap_groups_set          = mlxsw_sp_basic_trap_groups_set,
5446         .port_split                     = mlxsw_sp_port_split,
5447         .port_unsplit                   = mlxsw_sp_port_unsplit,
5448         .sb_pool_get                    = mlxsw_sp_sb_pool_get,
5449         .sb_pool_set                    = mlxsw_sp_sb_pool_set,
5450         .sb_port_pool_get               = mlxsw_sp_sb_port_pool_get,
5451         .sb_port_pool_set               = mlxsw_sp_sb_port_pool_set,
5452         .sb_tc_pool_bind_get            = mlxsw_sp_sb_tc_pool_bind_get,
5453         .sb_tc_pool_bind_set            = mlxsw_sp_sb_tc_pool_bind_set,
5454         .sb_occ_snapshot                = mlxsw_sp_sb_occ_snapshot,
5455         .sb_occ_max_clear               = mlxsw_sp_sb_occ_max_clear,
5456         .sb_occ_port_pool_get           = mlxsw_sp_sb_occ_port_pool_get,
5457         .sb_occ_tc_port_bind_get        = mlxsw_sp_sb_occ_tc_port_bind_get,
5458         .flash_update                   = mlxsw_sp_flash_update,
5459         .trap_init                      = mlxsw_sp_trap_init,
5460         .trap_fini                      = mlxsw_sp_trap_fini,
5461         .trap_action_set                = mlxsw_sp_trap_action_set,
5462         .trap_group_init                = mlxsw_sp_trap_group_init,
5463         .txhdr_construct                = mlxsw_sp_txhdr_construct,
5464         .resources_register             = mlxsw_sp2_resources_register,
5465         .params_register                = mlxsw_sp2_params_register,
5466         .params_unregister              = mlxsw_sp2_params_unregister,
5467         .ptp_transmitted                = mlxsw_sp_ptp_transmitted,
5468         .txhdr_len                      = MLXSW_TXHDR_LEN,
5469         .profile                        = &mlxsw_sp2_config_profile,
5470         .res_query_enabled              = true,
5471 };
5472
5473 bool mlxsw_sp_port_dev_check(const struct net_device *dev)
5474 {
5475         return dev->netdev_ops == &mlxsw_sp_port_netdev_ops;
5476 }
5477
5478 static int mlxsw_sp_lower_dev_walk(struct net_device *lower_dev, void *data)
5479 {
5480         struct mlxsw_sp_port **p_mlxsw_sp_port = data;
5481         int ret = 0;
5482
5483         if (mlxsw_sp_port_dev_check(lower_dev)) {
5484                 *p_mlxsw_sp_port = netdev_priv(lower_dev);
5485                 ret = 1;
5486         }
5487
5488         return ret;
5489 }
5490
5491 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find(struct net_device *dev)
5492 {
5493         struct mlxsw_sp_port *mlxsw_sp_port;
5494
5495         if (mlxsw_sp_port_dev_check(dev))
5496                 return netdev_priv(dev);
5497
5498         mlxsw_sp_port = NULL;
5499         netdev_walk_all_lower_dev(dev, mlxsw_sp_lower_dev_walk, &mlxsw_sp_port);
5500
5501         return mlxsw_sp_port;
5502 }
5503
5504 struct mlxsw_sp *mlxsw_sp_lower_get(struct net_device *dev)
5505 {
5506         struct mlxsw_sp_port *mlxsw_sp_port;
5507
5508         mlxsw_sp_port = mlxsw_sp_port_dev_lower_find(dev);
5509         return mlxsw_sp_port ? mlxsw_sp_port->mlxsw_sp : NULL;
5510 }
5511
5512 struct mlxsw_sp_port *mlxsw_sp_port_dev_lower_find_rcu(struct net_device *dev)
5513 {
5514         struct mlxsw_sp_port *mlxsw_sp_port;
5515
5516         if (mlxsw_sp_port_dev_check(dev))
5517                 return netdev_priv(dev);
5518
5519         mlxsw_sp_port = NULL;
5520         netdev_walk_all_lower_dev_rcu(dev, mlxsw_sp_lower_dev_walk,
5521                                       &mlxsw_sp_port);
5522
5523         return mlxsw_sp_port;
5524 }
5525
5526 struct mlxsw_sp_port *mlxsw_sp_port_lower_dev_hold(struct net_device *dev)
5527 {
5528         struct mlxsw_sp_port *mlxsw_sp_port;
5529
5530         rcu_read_lock();
5531         mlxsw_sp_port = mlxsw_sp_port_dev_lower_find_rcu(dev);
5532         if (mlxsw_sp_port)
5533                 dev_hold(mlxsw_sp_port->dev);
5534         rcu_read_unlock();
5535         return mlxsw_sp_port;
5536 }
5537
5538 void mlxsw_sp_port_dev_put(struct mlxsw_sp_port *mlxsw_sp_port)
5539 {
5540         dev_put(mlxsw_sp_port->dev);
5541 }
5542
5543 static void
5544 mlxsw_sp_port_lag_uppers_cleanup(struct mlxsw_sp_port *mlxsw_sp_port,
5545                                  struct net_device *lag_dev)
5546 {
5547         struct net_device *br_dev = netdev_master_upper_dev_get(lag_dev);
5548         struct net_device *upper_dev;
5549         struct list_head *iter;
5550
5551         if (netif_is_bridge_port(lag_dev))
5552                 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, lag_dev, br_dev);
5553
5554         netdev_for_each_upper_dev_rcu(lag_dev, upper_dev, iter) {
5555                 if (!netif_is_bridge_port(upper_dev))
5556                         continue;
5557                 br_dev = netdev_master_upper_dev_get(upper_dev);
5558                 mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev, br_dev);
5559         }
5560 }
5561
5562 static int mlxsw_sp_lag_create(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
5563 {
5564         char sldr_pl[MLXSW_REG_SLDR_LEN];
5565
5566         mlxsw_reg_sldr_lag_create_pack(sldr_pl, lag_id);
5567         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
5568 }
5569
5570 static int mlxsw_sp_lag_destroy(struct mlxsw_sp *mlxsw_sp, u16 lag_id)
5571 {
5572         char sldr_pl[MLXSW_REG_SLDR_LEN];
5573
5574         mlxsw_reg_sldr_lag_destroy_pack(sldr_pl, lag_id);
5575         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
5576 }
5577
5578 static int mlxsw_sp_lag_col_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
5579                                      u16 lag_id, u8 port_index)
5580 {
5581         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5582         char slcor_pl[MLXSW_REG_SLCOR_LEN];
5583
5584         mlxsw_reg_slcor_port_add_pack(slcor_pl, mlxsw_sp_port->local_port,
5585                                       lag_id, port_index);
5586         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
5587 }
5588
5589 static int mlxsw_sp_lag_col_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
5590                                         u16 lag_id)
5591 {
5592         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5593         char slcor_pl[MLXSW_REG_SLCOR_LEN];
5594
5595         mlxsw_reg_slcor_port_remove_pack(slcor_pl, mlxsw_sp_port->local_port,
5596                                          lag_id);
5597         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
5598 }
5599
5600 static int mlxsw_sp_lag_col_port_enable(struct mlxsw_sp_port *mlxsw_sp_port,
5601                                         u16 lag_id)
5602 {
5603         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5604         char slcor_pl[MLXSW_REG_SLCOR_LEN];
5605
5606         mlxsw_reg_slcor_col_enable_pack(slcor_pl, mlxsw_sp_port->local_port,
5607                                         lag_id);
5608         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
5609 }
5610
5611 static int mlxsw_sp_lag_col_port_disable(struct mlxsw_sp_port *mlxsw_sp_port,
5612                                          u16 lag_id)
5613 {
5614         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5615         char slcor_pl[MLXSW_REG_SLCOR_LEN];
5616
5617         mlxsw_reg_slcor_col_disable_pack(slcor_pl, mlxsw_sp_port->local_port,
5618                                          lag_id);
5619         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(slcor), slcor_pl);
5620 }
5621
5622 static int mlxsw_sp_lag_index_get(struct mlxsw_sp *mlxsw_sp,
5623                                   struct net_device *lag_dev,
5624                                   u16 *p_lag_id)
5625 {
5626         struct mlxsw_sp_upper *lag;
5627         int free_lag_id = -1;
5628         u64 max_lag;
5629         int i;
5630
5631         max_lag = MLXSW_CORE_RES_GET(mlxsw_sp->core, MAX_LAG);
5632         for (i = 0; i < max_lag; i++) {
5633                 lag = mlxsw_sp_lag_get(mlxsw_sp, i);
5634                 if (lag->ref_count) {
5635                         if (lag->dev == lag_dev) {
5636                                 *p_lag_id = i;
5637                                 return 0;
5638                         }
5639                 } else if (free_lag_id < 0) {
5640                         free_lag_id = i;
5641                 }
5642         }
5643         if (free_lag_id < 0)
5644                 return -EBUSY;
5645         *p_lag_id = free_lag_id;
5646         return 0;
5647 }
5648
5649 static bool
5650 mlxsw_sp_master_lag_check(struct mlxsw_sp *mlxsw_sp,
5651                           struct net_device *lag_dev,
5652                           struct netdev_lag_upper_info *lag_upper_info,
5653                           struct netlink_ext_ack *extack)
5654 {
5655         u16 lag_id;
5656
5657         if (mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id) != 0) {
5658                 NL_SET_ERR_MSG_MOD(extack, "Exceeded number of supported LAG devices");
5659                 return false;
5660         }
5661         if (lag_upper_info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
5662                 NL_SET_ERR_MSG_MOD(extack, "LAG device using unsupported Tx type");
5663                 return false;
5664         }
5665         return true;
5666 }
5667
5668 static int mlxsw_sp_port_lag_index_get(struct mlxsw_sp *mlxsw_sp,
5669                                        u16 lag_id, u8 *p_port_index)
5670 {
5671         u64 max_lag_members;
5672         int i;
5673
5674         max_lag_members = MLXSW_CORE_RES_GET(mlxsw_sp->core,
5675                                              MAX_LAG_MEMBERS);
5676         for (i = 0; i < max_lag_members; i++) {
5677                 if (!mlxsw_sp_port_lagged_get(mlxsw_sp, lag_id, i)) {
5678                         *p_port_index = i;
5679                         return 0;
5680                 }
5681         }
5682         return -EBUSY;
5683 }
5684
5685 static int mlxsw_sp_port_lag_join(struct mlxsw_sp_port *mlxsw_sp_port,
5686                                   struct net_device *lag_dev)
5687 {
5688         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5689         struct mlxsw_sp_upper *lag;
5690         u16 lag_id;
5691         u8 port_index;
5692         int err;
5693
5694         err = mlxsw_sp_lag_index_get(mlxsw_sp, lag_dev, &lag_id);
5695         if (err)
5696                 return err;
5697         lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
5698         if (!lag->ref_count) {
5699                 err = mlxsw_sp_lag_create(mlxsw_sp, lag_id);
5700                 if (err)
5701                         return err;
5702                 lag->dev = lag_dev;
5703         }
5704
5705         err = mlxsw_sp_port_lag_index_get(mlxsw_sp, lag_id, &port_index);
5706         if (err)
5707                 return err;
5708         err = mlxsw_sp_lag_col_port_add(mlxsw_sp_port, lag_id, port_index);
5709         if (err)
5710                 goto err_col_port_add;
5711
5712         mlxsw_core_lag_mapping_set(mlxsw_sp->core, lag_id, port_index,
5713                                    mlxsw_sp_port->local_port);
5714         mlxsw_sp_port->lag_id = lag_id;
5715         mlxsw_sp_port->lagged = 1;
5716         lag->ref_count++;
5717
5718         /* Port is no longer usable as a router interface */
5719         if (mlxsw_sp_port->default_vlan->fid)
5720                 mlxsw_sp_port_vlan_router_leave(mlxsw_sp_port->default_vlan);
5721
5722         return 0;
5723
5724 err_col_port_add:
5725         if (!lag->ref_count)
5726                 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
5727         return err;
5728 }
5729
5730 static void mlxsw_sp_port_lag_leave(struct mlxsw_sp_port *mlxsw_sp_port,
5731                                     struct net_device *lag_dev)
5732 {
5733         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5734         u16 lag_id = mlxsw_sp_port->lag_id;
5735         struct mlxsw_sp_upper *lag;
5736
5737         if (!mlxsw_sp_port->lagged)
5738                 return;
5739         lag = mlxsw_sp_lag_get(mlxsw_sp, lag_id);
5740         WARN_ON(lag->ref_count == 0);
5741
5742         mlxsw_sp_lag_col_port_remove(mlxsw_sp_port, lag_id);
5743
5744         /* Any VLANs configured on the port are no longer valid */
5745         mlxsw_sp_port_vlan_flush(mlxsw_sp_port, false);
5746         mlxsw_sp_port_vlan_cleanup(mlxsw_sp_port->default_vlan);
5747         /* Make the LAG and its directly linked uppers leave bridges they
5748          * are memeber in
5749          */
5750         mlxsw_sp_port_lag_uppers_cleanup(mlxsw_sp_port, lag_dev);
5751
5752         if (lag->ref_count == 1)
5753                 mlxsw_sp_lag_destroy(mlxsw_sp, lag_id);
5754
5755         mlxsw_core_lag_mapping_clear(mlxsw_sp->core, lag_id,
5756                                      mlxsw_sp_port->local_port);
5757         mlxsw_sp_port->lagged = 0;
5758         lag->ref_count--;
5759
5760         /* Make sure untagged frames are allowed to ingress */
5761         mlxsw_sp_port_pvid_set(mlxsw_sp_port, MLXSW_SP_DEFAULT_VID);
5762 }
5763
5764 static int mlxsw_sp_lag_dist_port_add(struct mlxsw_sp_port *mlxsw_sp_port,
5765                                       u16 lag_id)
5766 {
5767         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5768         char sldr_pl[MLXSW_REG_SLDR_LEN];
5769
5770         mlxsw_reg_sldr_lag_add_port_pack(sldr_pl, lag_id,
5771                                          mlxsw_sp_port->local_port);
5772         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
5773 }
5774
5775 static int mlxsw_sp_lag_dist_port_remove(struct mlxsw_sp_port *mlxsw_sp_port,
5776                                          u16 lag_id)
5777 {
5778         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5779         char sldr_pl[MLXSW_REG_SLDR_LEN];
5780
5781         mlxsw_reg_sldr_lag_remove_port_pack(sldr_pl, lag_id,
5782                                             mlxsw_sp_port->local_port);
5783         return mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(sldr), sldr_pl);
5784 }
5785
5786 static int
5787 mlxsw_sp_port_lag_col_dist_enable(struct mlxsw_sp_port *mlxsw_sp_port)
5788 {
5789         int err;
5790
5791         err = mlxsw_sp_lag_col_port_enable(mlxsw_sp_port,
5792                                            mlxsw_sp_port->lag_id);
5793         if (err)
5794                 return err;
5795
5796         err = mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id);
5797         if (err)
5798                 goto err_dist_port_add;
5799
5800         return 0;
5801
5802 err_dist_port_add:
5803         mlxsw_sp_lag_col_port_disable(mlxsw_sp_port, mlxsw_sp_port->lag_id);
5804         return err;
5805 }
5806
5807 static int
5808 mlxsw_sp_port_lag_col_dist_disable(struct mlxsw_sp_port *mlxsw_sp_port)
5809 {
5810         int err;
5811
5812         err = mlxsw_sp_lag_dist_port_remove(mlxsw_sp_port,
5813                                             mlxsw_sp_port->lag_id);
5814         if (err)
5815                 return err;
5816
5817         err = mlxsw_sp_lag_col_port_disable(mlxsw_sp_port,
5818                                             mlxsw_sp_port->lag_id);
5819         if (err)
5820                 goto err_col_port_disable;
5821
5822         return 0;
5823
5824 err_col_port_disable:
5825         mlxsw_sp_lag_dist_port_add(mlxsw_sp_port, mlxsw_sp_port->lag_id);
5826         return err;
5827 }
5828
5829 static int mlxsw_sp_port_lag_changed(struct mlxsw_sp_port *mlxsw_sp_port,
5830                                      struct netdev_lag_lower_state_info *info)
5831 {
5832         if (info->tx_enabled)
5833                 return mlxsw_sp_port_lag_col_dist_enable(mlxsw_sp_port);
5834         else
5835                 return mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port);
5836 }
5837
5838 static int mlxsw_sp_port_stp_set(struct mlxsw_sp_port *mlxsw_sp_port,
5839                                  bool enable)
5840 {
5841         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5842         enum mlxsw_reg_spms_state spms_state;
5843         char *spms_pl;
5844         u16 vid;
5845         int err;
5846
5847         spms_state = enable ? MLXSW_REG_SPMS_STATE_FORWARDING :
5848                               MLXSW_REG_SPMS_STATE_DISCARDING;
5849
5850         spms_pl = kmalloc(MLXSW_REG_SPMS_LEN, GFP_KERNEL);
5851         if (!spms_pl)
5852                 return -ENOMEM;
5853         mlxsw_reg_spms_pack(spms_pl, mlxsw_sp_port->local_port);
5854
5855         for (vid = 0; vid < VLAN_N_VID; vid++)
5856                 mlxsw_reg_spms_vid_pack(spms_pl, vid, spms_state);
5857
5858         err = mlxsw_reg_write(mlxsw_sp->core, MLXSW_REG(spms), spms_pl);
5859         kfree(spms_pl);
5860         return err;
5861 }
5862
5863 static int mlxsw_sp_port_ovs_join(struct mlxsw_sp_port *mlxsw_sp_port)
5864 {
5865         u16 vid = 1;
5866         int err;
5867
5868         err = mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, true);
5869         if (err)
5870                 return err;
5871         err = mlxsw_sp_port_stp_set(mlxsw_sp_port, true);
5872         if (err)
5873                 goto err_port_stp_set;
5874         err = mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2,
5875                                      true, false);
5876         if (err)
5877                 goto err_port_vlan_set;
5878
5879         for (; vid <= VLAN_N_VID - 1; vid++) {
5880                 err = mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
5881                                                      vid, false);
5882                 if (err)
5883                         goto err_vid_learning_set;
5884         }
5885
5886         return 0;
5887
5888 err_vid_learning_set:
5889         for (vid--; vid >= 1; vid--)
5890                 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port, vid, true);
5891 err_port_vlan_set:
5892         mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
5893 err_port_stp_set:
5894         mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
5895         return err;
5896 }
5897
5898 static void mlxsw_sp_port_ovs_leave(struct mlxsw_sp_port *mlxsw_sp_port)
5899 {
5900         u16 vid;
5901
5902         for (vid = VLAN_N_VID - 1; vid >= 1; vid--)
5903                 mlxsw_sp_port_vid_learning_set(mlxsw_sp_port,
5904                                                vid, true);
5905
5906         mlxsw_sp_port_vlan_set(mlxsw_sp_port, 1, VLAN_N_VID - 2,
5907                                false, false);
5908         mlxsw_sp_port_stp_set(mlxsw_sp_port, false);
5909         mlxsw_sp_port_vp_mode_set(mlxsw_sp_port, false);
5910 }
5911
5912 static bool mlxsw_sp_bridge_has_multiple_vxlans(struct net_device *br_dev)
5913 {
5914         unsigned int num_vxlans = 0;
5915         struct net_device *dev;
5916         struct list_head *iter;
5917
5918         netdev_for_each_lower_dev(br_dev, dev, iter) {
5919                 if (netif_is_vxlan(dev))
5920                         num_vxlans++;
5921         }
5922
5923         return num_vxlans > 1;
5924 }
5925
5926 static bool mlxsw_sp_bridge_vxlan_vlan_is_valid(struct net_device *br_dev)
5927 {
5928         DECLARE_BITMAP(vlans, VLAN_N_VID) = {0};
5929         struct net_device *dev;
5930         struct list_head *iter;
5931
5932         netdev_for_each_lower_dev(br_dev, dev, iter) {
5933                 u16 pvid;
5934                 int err;
5935
5936                 if (!netif_is_vxlan(dev))
5937                         continue;
5938
5939                 err = mlxsw_sp_vxlan_mapped_vid(dev, &pvid);
5940                 if (err || !pvid)
5941                         continue;
5942
5943                 if (test_and_set_bit(pvid, vlans))
5944                         return false;
5945         }
5946
5947         return true;
5948 }
5949
5950 static bool mlxsw_sp_bridge_vxlan_is_valid(struct net_device *br_dev,
5951                                            struct netlink_ext_ack *extack)
5952 {
5953         if (br_multicast_enabled(br_dev)) {
5954                 NL_SET_ERR_MSG_MOD(extack, "Multicast can not be enabled on a bridge with a VxLAN device");
5955                 return false;
5956         }
5957
5958         if (!br_vlan_enabled(br_dev) &&
5959             mlxsw_sp_bridge_has_multiple_vxlans(br_dev)) {
5960                 NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices are not supported in a VLAN-unaware bridge");
5961                 return false;
5962         }
5963
5964         if (br_vlan_enabled(br_dev) &&
5965             !mlxsw_sp_bridge_vxlan_vlan_is_valid(br_dev)) {
5966                 NL_SET_ERR_MSG_MOD(extack, "Multiple VxLAN devices cannot have the same VLAN as PVID and egress untagged");
5967                 return false;
5968         }
5969
5970         return true;
5971 }
5972
5973 static int mlxsw_sp_netdevice_port_upper_event(struct net_device *lower_dev,
5974                                                struct net_device *dev,
5975                                                unsigned long event, void *ptr)
5976 {
5977         struct netdev_notifier_changeupper_info *info;
5978         struct mlxsw_sp_port *mlxsw_sp_port;
5979         struct netlink_ext_ack *extack;
5980         struct net_device *upper_dev;
5981         struct mlxsw_sp *mlxsw_sp;
5982         int err = 0;
5983
5984         mlxsw_sp_port = netdev_priv(dev);
5985         mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
5986         info = ptr;
5987         extack = netdev_notifier_info_to_extack(&info->info);
5988
5989         switch (event) {
5990         case NETDEV_PRECHANGEUPPER:
5991                 upper_dev = info->upper_dev;
5992                 if (!is_vlan_dev(upper_dev) &&
5993                     !netif_is_lag_master(upper_dev) &&
5994                     !netif_is_bridge_master(upper_dev) &&
5995                     !netif_is_ovs_master(upper_dev) &&
5996                     !netif_is_macvlan(upper_dev)) {
5997                         NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
5998                         return -EINVAL;
5999                 }
6000                 if (!info->linking)
6001                         break;
6002                 if (netif_is_bridge_master(upper_dev) &&
6003                     !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) &&
6004                     mlxsw_sp_bridge_has_vxlan(upper_dev) &&
6005                     !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
6006                         return -EOPNOTSUPP;
6007                 if (netdev_has_any_upper_dev(upper_dev) &&
6008                     (!netif_is_bridge_master(upper_dev) ||
6009                      !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
6010                                                           upper_dev))) {
6011                         NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
6012                         return -EINVAL;
6013                 }
6014                 if (netif_is_lag_master(upper_dev) &&
6015                     !mlxsw_sp_master_lag_check(mlxsw_sp, upper_dev,
6016                                                info->upper_info, extack))
6017                         return -EINVAL;
6018                 if (netif_is_lag_master(upper_dev) && vlan_uses_dev(dev)) {
6019                         NL_SET_ERR_MSG_MOD(extack, "Master device is a LAG master and this device has a VLAN");
6020                         return -EINVAL;
6021                 }
6022                 if (netif_is_lag_port(dev) && is_vlan_dev(upper_dev) &&
6023                     !netif_is_lag_master(vlan_dev_real_dev(upper_dev))) {
6024                         NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on a LAG port");
6025                         return -EINVAL;
6026                 }
6027                 if (netif_is_macvlan(upper_dev) &&
6028                     !mlxsw_sp_rif_find_by_dev(mlxsw_sp, lower_dev)) {
6029                         NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
6030                         return -EOPNOTSUPP;
6031                 }
6032                 if (netif_is_ovs_master(upper_dev) && vlan_uses_dev(dev)) {
6033                         NL_SET_ERR_MSG_MOD(extack, "Master device is an OVS master and this device has a VLAN");
6034                         return -EINVAL;
6035                 }
6036                 if (netif_is_ovs_port(dev) && is_vlan_dev(upper_dev)) {
6037                         NL_SET_ERR_MSG_MOD(extack, "Can not put a VLAN on an OVS port");
6038                         return -EINVAL;
6039                 }
6040                 break;
6041         case NETDEV_CHANGEUPPER:
6042                 upper_dev = info->upper_dev;
6043                 if (netif_is_bridge_master(upper_dev)) {
6044                         if (info->linking)
6045                                 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
6046                                                                 lower_dev,
6047                                                                 upper_dev,
6048                                                                 extack);
6049                         else
6050                                 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
6051                                                            lower_dev,
6052                                                            upper_dev);
6053                 } else if (netif_is_lag_master(upper_dev)) {
6054                         if (info->linking) {
6055                                 err = mlxsw_sp_port_lag_join(mlxsw_sp_port,
6056                                                              upper_dev);
6057                         } else {
6058                                 mlxsw_sp_port_lag_col_dist_disable(mlxsw_sp_port);
6059                                 mlxsw_sp_port_lag_leave(mlxsw_sp_port,
6060                                                         upper_dev);
6061                         }
6062                 } else if (netif_is_ovs_master(upper_dev)) {
6063                         if (info->linking)
6064                                 err = mlxsw_sp_port_ovs_join(mlxsw_sp_port);
6065                         else
6066                                 mlxsw_sp_port_ovs_leave(mlxsw_sp_port);
6067                 } else if (netif_is_macvlan(upper_dev)) {
6068                         if (!info->linking)
6069                                 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
6070                 } else if (is_vlan_dev(upper_dev)) {
6071                         struct net_device *br_dev;
6072
6073                         if (!netif_is_bridge_port(upper_dev))
6074                                 break;
6075                         if (info->linking)
6076                                 break;
6077                         br_dev = netdev_master_upper_dev_get(upper_dev);
6078                         mlxsw_sp_port_bridge_leave(mlxsw_sp_port, upper_dev,
6079                                                    br_dev);
6080                 }
6081                 break;
6082         }
6083
6084         return err;
6085 }
6086
6087 static int mlxsw_sp_netdevice_port_lower_event(struct net_device *dev,
6088                                                unsigned long event, void *ptr)
6089 {
6090         struct netdev_notifier_changelowerstate_info *info;
6091         struct mlxsw_sp_port *mlxsw_sp_port;
6092         int err;
6093
6094         mlxsw_sp_port = netdev_priv(dev);
6095         info = ptr;
6096
6097         switch (event) {
6098         case NETDEV_CHANGELOWERSTATE:
6099                 if (netif_is_lag_port(dev) && mlxsw_sp_port->lagged) {
6100                         err = mlxsw_sp_port_lag_changed(mlxsw_sp_port,
6101                                                         info->lower_state_info);
6102                         if (err)
6103                                 netdev_err(dev, "Failed to reflect link aggregation lower state change\n");
6104                 }
6105                 break;
6106         }
6107
6108         return 0;
6109 }
6110
6111 static int mlxsw_sp_netdevice_port_event(struct net_device *lower_dev,
6112                                          struct net_device *port_dev,
6113                                          unsigned long event, void *ptr)
6114 {
6115         switch (event) {
6116         case NETDEV_PRECHANGEUPPER:
6117         case NETDEV_CHANGEUPPER:
6118                 return mlxsw_sp_netdevice_port_upper_event(lower_dev, port_dev,
6119                                                            event, ptr);
6120         case NETDEV_CHANGELOWERSTATE:
6121                 return mlxsw_sp_netdevice_port_lower_event(port_dev, event,
6122                                                            ptr);
6123         }
6124
6125         return 0;
6126 }
6127
6128 static int mlxsw_sp_netdevice_lag_event(struct net_device *lag_dev,
6129                                         unsigned long event, void *ptr)
6130 {
6131         struct net_device *dev;
6132         struct list_head *iter;
6133         int ret;
6134
6135         netdev_for_each_lower_dev(lag_dev, dev, iter) {
6136                 if (mlxsw_sp_port_dev_check(dev)) {
6137                         ret = mlxsw_sp_netdevice_port_event(lag_dev, dev, event,
6138                                                             ptr);
6139                         if (ret)
6140                                 return ret;
6141                 }
6142         }
6143
6144         return 0;
6145 }
6146
6147 static int mlxsw_sp_netdevice_port_vlan_event(struct net_device *vlan_dev,
6148                                               struct net_device *dev,
6149                                               unsigned long event, void *ptr,
6150                                               u16 vid)
6151 {
6152         struct mlxsw_sp_port *mlxsw_sp_port = netdev_priv(dev);
6153         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_port->mlxsw_sp;
6154         struct netdev_notifier_changeupper_info *info = ptr;
6155         struct netlink_ext_ack *extack;
6156         struct net_device *upper_dev;
6157         int err = 0;
6158
6159         extack = netdev_notifier_info_to_extack(&info->info);
6160
6161         switch (event) {
6162         case NETDEV_PRECHANGEUPPER:
6163                 upper_dev = info->upper_dev;
6164                 if (!netif_is_bridge_master(upper_dev) &&
6165                     !netif_is_macvlan(upper_dev)) {
6166                         NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
6167                         return -EINVAL;
6168                 }
6169                 if (!info->linking)
6170                         break;
6171                 if (netif_is_bridge_master(upper_dev) &&
6172                     !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp, upper_dev) &&
6173                     mlxsw_sp_bridge_has_vxlan(upper_dev) &&
6174                     !mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
6175                         return -EOPNOTSUPP;
6176                 if (netdev_has_any_upper_dev(upper_dev) &&
6177                     (!netif_is_bridge_master(upper_dev) ||
6178                      !mlxsw_sp_bridge_device_is_offloaded(mlxsw_sp,
6179                                                           upper_dev))) {
6180                         NL_SET_ERR_MSG_MOD(extack, "Enslaving a port to a device that already has an upper device is not supported");
6181                         return -EINVAL;
6182                 }
6183                 if (netif_is_macvlan(upper_dev) &&
6184                     !mlxsw_sp_rif_find_by_dev(mlxsw_sp, vlan_dev)) {
6185                         NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
6186                         return -EOPNOTSUPP;
6187                 }
6188                 break;
6189         case NETDEV_CHANGEUPPER:
6190                 upper_dev = info->upper_dev;
6191                 if (netif_is_bridge_master(upper_dev)) {
6192                         if (info->linking)
6193                                 err = mlxsw_sp_port_bridge_join(mlxsw_sp_port,
6194                                                                 vlan_dev,
6195                                                                 upper_dev,
6196                                                                 extack);
6197                         else
6198                                 mlxsw_sp_port_bridge_leave(mlxsw_sp_port,
6199                                                            vlan_dev,
6200                                                            upper_dev);
6201                 } else if (netif_is_macvlan(upper_dev)) {
6202                         if (!info->linking)
6203                                 mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
6204                 } else {
6205                         err = -EINVAL;
6206                         WARN_ON(1);
6207                 }
6208                 break;
6209         }
6210
6211         return err;
6212 }
6213
6214 static int mlxsw_sp_netdevice_lag_port_vlan_event(struct net_device *vlan_dev,
6215                                                   struct net_device *lag_dev,
6216                                                   unsigned long event,
6217                                                   void *ptr, u16 vid)
6218 {
6219         struct net_device *dev;
6220         struct list_head *iter;
6221         int ret;
6222
6223         netdev_for_each_lower_dev(lag_dev, dev, iter) {
6224                 if (mlxsw_sp_port_dev_check(dev)) {
6225                         ret = mlxsw_sp_netdevice_port_vlan_event(vlan_dev, dev,
6226                                                                  event, ptr,
6227                                                                  vid);
6228                         if (ret)
6229                                 return ret;
6230                 }
6231         }
6232
6233         return 0;
6234 }
6235
6236 static int mlxsw_sp_netdevice_bridge_vlan_event(struct net_device *vlan_dev,
6237                                                 struct net_device *br_dev,
6238                                                 unsigned long event, void *ptr,
6239                                                 u16 vid)
6240 {
6241         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(vlan_dev);
6242         struct netdev_notifier_changeupper_info *info = ptr;
6243         struct netlink_ext_ack *extack;
6244         struct net_device *upper_dev;
6245
6246         if (!mlxsw_sp)
6247                 return 0;
6248
6249         extack = netdev_notifier_info_to_extack(&info->info);
6250
6251         switch (event) {
6252         case NETDEV_PRECHANGEUPPER:
6253                 upper_dev = info->upper_dev;
6254                 if (!netif_is_macvlan(upper_dev)) {
6255                         NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
6256                         return -EOPNOTSUPP;
6257                 }
6258                 if (!info->linking)
6259                         break;
6260                 if (netif_is_macvlan(upper_dev) &&
6261                     !mlxsw_sp_rif_find_by_dev(mlxsw_sp, vlan_dev)) {
6262                         NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
6263                         return -EOPNOTSUPP;
6264                 }
6265                 break;
6266         case NETDEV_CHANGEUPPER:
6267                 upper_dev = info->upper_dev;
6268                 if (info->linking)
6269                         break;
6270                 if (netif_is_macvlan(upper_dev))
6271                         mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
6272                 break;
6273         }
6274
6275         return 0;
6276 }
6277
6278 static int mlxsw_sp_netdevice_vlan_event(struct net_device *vlan_dev,
6279                                          unsigned long event, void *ptr)
6280 {
6281         struct net_device *real_dev = vlan_dev_real_dev(vlan_dev);
6282         u16 vid = vlan_dev_vlan_id(vlan_dev);
6283
6284         if (mlxsw_sp_port_dev_check(real_dev))
6285                 return mlxsw_sp_netdevice_port_vlan_event(vlan_dev, real_dev,
6286                                                           event, ptr, vid);
6287         else if (netif_is_lag_master(real_dev))
6288                 return mlxsw_sp_netdevice_lag_port_vlan_event(vlan_dev,
6289                                                               real_dev, event,
6290                                                               ptr, vid);
6291         else if (netif_is_bridge_master(real_dev))
6292                 return mlxsw_sp_netdevice_bridge_vlan_event(vlan_dev, real_dev,
6293                                                             event, ptr, vid);
6294
6295         return 0;
6296 }
6297
6298 static int mlxsw_sp_netdevice_bridge_event(struct net_device *br_dev,
6299                                            unsigned long event, void *ptr)
6300 {
6301         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(br_dev);
6302         struct netdev_notifier_changeupper_info *info = ptr;
6303         struct netlink_ext_ack *extack;
6304         struct net_device *upper_dev;
6305
6306         if (!mlxsw_sp)
6307                 return 0;
6308
6309         extack = netdev_notifier_info_to_extack(&info->info);
6310
6311         switch (event) {
6312         case NETDEV_PRECHANGEUPPER:
6313                 upper_dev = info->upper_dev;
6314                 if (!is_vlan_dev(upper_dev) && !netif_is_macvlan(upper_dev)) {
6315                         NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
6316                         return -EOPNOTSUPP;
6317                 }
6318                 if (!info->linking)
6319                         break;
6320                 if (netif_is_macvlan(upper_dev) &&
6321                     !mlxsw_sp_rif_find_by_dev(mlxsw_sp, br_dev)) {
6322                         NL_SET_ERR_MSG_MOD(extack, "macvlan is only supported on top of router interfaces");
6323                         return -EOPNOTSUPP;
6324                 }
6325                 break;
6326         case NETDEV_CHANGEUPPER:
6327                 upper_dev = info->upper_dev;
6328                 if (info->linking)
6329                         break;
6330                 if (is_vlan_dev(upper_dev))
6331                         mlxsw_sp_rif_destroy_by_dev(mlxsw_sp, upper_dev);
6332                 if (netif_is_macvlan(upper_dev))
6333                         mlxsw_sp_rif_macvlan_del(mlxsw_sp, upper_dev);
6334                 break;
6335         }
6336
6337         return 0;
6338 }
6339
6340 static int mlxsw_sp_netdevice_macvlan_event(struct net_device *macvlan_dev,
6341                                             unsigned long event, void *ptr)
6342 {
6343         struct mlxsw_sp *mlxsw_sp = mlxsw_sp_lower_get(macvlan_dev);
6344         struct netdev_notifier_changeupper_info *info = ptr;
6345         struct netlink_ext_ack *extack;
6346
6347         if (!mlxsw_sp || event != NETDEV_PRECHANGEUPPER)
6348                 return 0;
6349
6350         extack = netdev_notifier_info_to_extack(&info->info);
6351
6352         /* VRF enslavement is handled in mlxsw_sp_netdevice_vrf_event() */
6353         NL_SET_ERR_MSG_MOD(extack, "Unknown upper device type");
6354
6355         return -EOPNOTSUPP;
6356 }
6357
6358 static bool mlxsw_sp_is_vrf_event(unsigned long event, void *ptr)
6359 {
6360         struct netdev_notifier_changeupper_info *info = ptr;
6361
6362         if (event != NETDEV_PRECHANGEUPPER && event != NETDEV_CHANGEUPPER)
6363                 return false;
6364         return netif_is_l3_master(info->upper_dev);
6365 }
6366
6367 static int mlxsw_sp_netdevice_vxlan_event(struct mlxsw_sp *mlxsw_sp,
6368                                           struct net_device *dev,
6369                                           unsigned long event, void *ptr)
6370 {
6371         struct netdev_notifier_changeupper_info *cu_info;
6372         struct netdev_notifier_info *info = ptr;
6373         struct netlink_ext_ack *extack;
6374         struct net_device *upper_dev;
6375
6376         extack = netdev_notifier_info_to_extack(info);
6377
6378         switch (event) {
6379         case NETDEV_CHANGEUPPER:
6380                 cu_info = container_of(info,
6381                                        struct netdev_notifier_changeupper_info,
6382                                        info);
6383                 upper_dev = cu_info->upper_dev;
6384                 if (!netif_is_bridge_master(upper_dev))
6385                         return 0;
6386                 if (!mlxsw_sp_lower_get(upper_dev))
6387                         return 0;
6388                 if (!mlxsw_sp_bridge_vxlan_is_valid(upper_dev, extack))
6389                         return -EOPNOTSUPP;
6390                 if (cu_info->linking) {
6391                         if (!netif_running(dev))
6392                                 return 0;
6393                         /* When the bridge is VLAN-aware, the VNI of the VxLAN
6394                          * device needs to be mapped to a VLAN, but at this
6395                          * point no VLANs are configured on the VxLAN device
6396                          */
6397                         if (br_vlan_enabled(upper_dev))
6398                                 return 0;
6399                         return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev,
6400                                                           dev, 0, extack);
6401                 } else {
6402                         /* VLANs were already flushed, which triggered the
6403                          * necessary cleanup
6404                          */
6405                         if (br_vlan_enabled(upper_dev))
6406                                 return 0;
6407                         mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev);
6408                 }
6409                 break;
6410         case NETDEV_PRE_UP:
6411                 upper_dev = netdev_master_upper_dev_get(dev);
6412                 if (!upper_dev)
6413                         return 0;
6414                 if (!netif_is_bridge_master(upper_dev))
6415                         return 0;
6416                 if (!mlxsw_sp_lower_get(upper_dev))
6417                         return 0;
6418                 return mlxsw_sp_bridge_vxlan_join(mlxsw_sp, upper_dev, dev, 0,
6419                                                   extack);
6420         case NETDEV_DOWN:
6421                 upper_dev = netdev_master_upper_dev_get(dev);
6422                 if (!upper_dev)
6423                         return 0;
6424                 if (!netif_is_bridge_master(upper_dev))
6425                         return 0;
6426                 if (!mlxsw_sp_lower_get(upper_dev))
6427                         return 0;
6428                 mlxsw_sp_bridge_vxlan_leave(mlxsw_sp, dev);
6429                 break;
6430         }
6431
6432         return 0;
6433 }
6434
6435 static int mlxsw_sp_netdevice_event(struct notifier_block *nb,
6436                                     unsigned long event, void *ptr)
6437 {
6438         struct net_device *dev = netdev_notifier_info_to_dev(ptr);
6439         struct mlxsw_sp_span_entry *span_entry;
6440         struct mlxsw_sp *mlxsw_sp;
6441         int err = 0;
6442
6443         mlxsw_sp = container_of(nb, struct mlxsw_sp, netdevice_nb);
6444         if (event == NETDEV_UNREGISTER) {
6445                 span_entry = mlxsw_sp_span_entry_find_by_port(mlxsw_sp, dev);
6446                 if (span_entry)
6447                         mlxsw_sp_span_entry_invalidate(mlxsw_sp, span_entry);
6448         }
6449         mlxsw_sp_span_respin(mlxsw_sp);
6450
6451         if (netif_is_vxlan(dev))
6452                 err = mlxsw_sp_netdevice_vxlan_event(mlxsw_sp, dev, event, ptr);
6453         if (mlxsw_sp_netdev_is_ipip_ol(mlxsw_sp, dev))
6454                 err = mlxsw_sp_netdevice_ipip_ol_event(mlxsw_sp, dev,
6455                                                        event, ptr);
6456         else if (mlxsw_sp_netdev_is_ipip_ul(mlxsw_sp, dev))
6457                 err = mlxsw_sp_netdevice_ipip_ul_event(mlxsw_sp, dev,
6458                                                        event, ptr);
6459         else if (event == NETDEV_PRE_CHANGEADDR ||
6460                  event == NETDEV_CHANGEADDR ||
6461                  event == NETDEV_CHANGEMTU)
6462                 err = mlxsw_sp_netdevice_router_port_event(dev, event, ptr);
6463         else if (mlxsw_sp_is_vrf_event(event, ptr))
6464                 err = mlxsw_sp_netdevice_vrf_event(dev, event, ptr);
6465         else if (mlxsw_sp_port_dev_check(dev))
6466                 err = mlxsw_sp_netdevice_port_event(dev, dev, event, ptr);
6467         else if (netif_is_lag_master(dev))
6468                 err = mlxsw_sp_netdevice_lag_event(dev, event, ptr);
6469         else if (is_vlan_dev(dev))
6470                 err = mlxsw_sp_netdevice_vlan_event(dev, event, ptr);
6471         else if (netif_is_bridge_master(dev))
6472                 err = mlxsw_sp_netdevice_bridge_event(dev, event, ptr);
6473         else if (netif_is_macvlan(dev))
6474                 err = mlxsw_sp_netdevice_macvlan_event(dev, event, ptr);
6475
6476         return notifier_from_errno(err);
6477 }
6478
6479 static struct notifier_block mlxsw_sp_inetaddr_valid_nb __read_mostly = {
6480         .notifier_call = mlxsw_sp_inetaddr_valid_event,
6481 };
6482
6483 static struct notifier_block mlxsw_sp_inet6addr_valid_nb __read_mostly = {
6484         .notifier_call = mlxsw_sp_inet6addr_valid_event,
6485 };
6486
6487 static const struct pci_device_id mlxsw_sp1_pci_id_table[] = {
6488         {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM), 0},
6489         {0, },
6490 };
6491
6492 static struct pci_driver mlxsw_sp1_pci_driver = {
6493         .name = mlxsw_sp1_driver_name,
6494         .id_table = mlxsw_sp1_pci_id_table,
6495 };
6496
6497 static const struct pci_device_id mlxsw_sp2_pci_id_table[] = {
6498         {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM2), 0},
6499         {0, },
6500 };
6501
6502 static struct pci_driver mlxsw_sp2_pci_driver = {
6503         .name = mlxsw_sp2_driver_name,
6504         .id_table = mlxsw_sp2_pci_id_table,
6505 };
6506
6507 static const struct pci_device_id mlxsw_sp3_pci_id_table[] = {
6508         {PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SPECTRUM3), 0},
6509         {0, },
6510 };
6511
6512 static struct pci_driver mlxsw_sp3_pci_driver = {
6513         .name = mlxsw_sp3_driver_name,
6514         .id_table = mlxsw_sp3_pci_id_table,
6515 };
6516
6517 static int __init mlxsw_sp_module_init(void)
6518 {
6519         int err;
6520
6521         register_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
6522         register_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
6523
6524         err = mlxsw_core_driver_register(&mlxsw_sp1_driver);
6525         if (err)
6526                 goto err_sp1_core_driver_register;
6527
6528         err = mlxsw_core_driver_register(&mlxsw_sp2_driver);
6529         if (err)
6530                 goto err_sp2_core_driver_register;
6531
6532         err = mlxsw_core_driver_register(&mlxsw_sp3_driver);
6533         if (err)
6534                 goto err_sp3_core_driver_register;
6535
6536         err = mlxsw_pci_driver_register(&mlxsw_sp1_pci_driver);
6537         if (err)
6538                 goto err_sp1_pci_driver_register;
6539
6540         err = mlxsw_pci_driver_register(&mlxsw_sp2_pci_driver);
6541         if (err)
6542                 goto err_sp2_pci_driver_register;
6543
6544         err = mlxsw_pci_driver_register(&mlxsw_sp3_pci_driver);
6545         if (err)
6546                 goto err_sp3_pci_driver_register;
6547
6548         return 0;
6549
6550 err_sp3_pci_driver_register:
6551         mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
6552 err_sp2_pci_driver_register:
6553         mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver);
6554 err_sp1_pci_driver_register:
6555         mlxsw_core_driver_unregister(&mlxsw_sp3_driver);
6556 err_sp3_core_driver_register:
6557         mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
6558 err_sp2_core_driver_register:
6559         mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
6560 err_sp1_core_driver_register:
6561         unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
6562         unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
6563         return err;
6564 }
6565
6566 static void __exit mlxsw_sp_module_exit(void)
6567 {
6568         mlxsw_pci_driver_unregister(&mlxsw_sp3_pci_driver);
6569         mlxsw_pci_driver_unregister(&mlxsw_sp2_pci_driver);
6570         mlxsw_pci_driver_unregister(&mlxsw_sp1_pci_driver);
6571         mlxsw_core_driver_unregister(&mlxsw_sp3_driver);
6572         mlxsw_core_driver_unregister(&mlxsw_sp2_driver);
6573         mlxsw_core_driver_unregister(&mlxsw_sp1_driver);
6574         unregister_inet6addr_validator_notifier(&mlxsw_sp_inet6addr_valid_nb);
6575         unregister_inetaddr_validator_notifier(&mlxsw_sp_inetaddr_valid_nb);
6576 }
6577
6578 module_init(mlxsw_sp_module_init);
6579 module_exit(mlxsw_sp_module_exit);
6580
6581 MODULE_LICENSE("Dual BSD/GPL");
6582 MODULE_AUTHOR("Jiri Pirko <jiri@mellanox.com>");
6583 MODULE_DESCRIPTION("Mellanox Spectrum driver");
6584 MODULE_DEVICE_TABLE(pci, mlxsw_sp1_pci_id_table);
6585 MODULE_DEVICE_TABLE(pci, mlxsw_sp2_pci_id_table);
6586 MODULE_DEVICE_TABLE(pci, mlxsw_sp3_pci_id_table);
6587 /*(DEBLOBBED)*/