drivers/net/ethernet/mellanox/mlx5/core/steering/dr_action.c

   1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
   2 /* Copyright (c) 2019 Mellanox Technologies. */
   3
   4 #include "dr_types.h"
   5
   6 enum dr_action_domain {
   7         DR_ACTION_DOMAIN_NIC_INGRESS,
   8         DR_ACTION_DOMAIN_NIC_EGRESS,
   9         DR_ACTION_DOMAIN_FDB_INGRESS,
  10         DR_ACTION_DOMAIN_FDB_EGRESS,
  11         DR_ACTION_DOMAIN_MAX,
  12 };
  13
  14 enum dr_action_valid_state {
  15         DR_ACTION_STATE_ERR,
  16         DR_ACTION_STATE_NO_ACTION,
  17         DR_ACTION_STATE_REFORMAT,
  18         DR_ACTION_STATE_MODIFY_HDR,
  19         DR_ACTION_STATE_MODIFY_VLAN,
  20         DR_ACTION_STATE_NON_TERM,
  21         DR_ACTION_STATE_TERM,
  22         DR_ACTION_STATE_MAX,
  23 };
  24
  25 static const enum dr_action_valid_state
  26 next_action_state[DR_ACTION_DOMAIN_MAX][DR_ACTION_STATE_MAX][DR_ACTION_TYP_MAX] = {
  27         [DR_ACTION_DOMAIN_NIC_INGRESS] = {
  28                 [DR_ACTION_STATE_NO_ACTION] = {
  29                         [DR_ACTION_TYP_DROP]            = DR_ACTION_STATE_TERM,
  30                         [DR_ACTION_TYP_QP]              = DR_ACTION_STATE_TERM,
  31                         [DR_ACTION_TYP_FT]              = DR_ACTION_STATE_TERM,
  32                         [DR_ACTION_TYP_TAG]             = DR_ACTION_STATE_NON_TERM,
  33                         [DR_ACTION_TYP_CTR]             = DR_ACTION_STATE_NON_TERM,
  34                         [DR_ACTION_TYP_TNL_L2_TO_L2]    = DR_ACTION_STATE_REFORMAT,
  35                         [DR_ACTION_TYP_TNL_L3_TO_L2]    = DR_ACTION_STATE_REFORMAT,
  36                         [DR_ACTION_TYP_MODIFY_HDR]      = DR_ACTION_STATE_MODIFY_HDR,
  37                         [DR_ACTION_TYP_POP_VLAN]        = DR_ACTION_STATE_MODIFY_VLAN,
  38                 },
  39                 [DR_ACTION_STATE_REFORMAT] = {
  40                         [DR_ACTION_TYP_DROP]            = DR_ACTION_STATE_TERM,
  41                         [DR_ACTION_TYP_QP]              = DR_ACTION_STATE_TERM,
  42                         [DR_ACTION_TYP_FT]              = DR_ACTION_STATE_TERM,
  43                         [DR_ACTION_TYP_TAG]             = DR_ACTION_STATE_REFORMAT,
  44                         [DR_ACTION_TYP_CTR]             = DR_ACTION_STATE_REFORMAT,
  45                         [DR_ACTION_TYP_MODIFY_HDR]      = DR_ACTION_STATE_MODIFY_HDR,
  46                         [DR_ACTION_TYP_POP_VLAN]        = DR_ACTION_STATE_MODIFY_VLAN,
  47                 },
  48                 [DR_ACTION_STATE_MODIFY_HDR] = {
  49                         [DR_ACTION_TYP_DROP]            = DR_ACTION_STATE_TERM,
  50                         [DR_ACTION_TYP_QP]              = DR_ACTION_STATE_TERM,
  51                         [DR_ACTION_TYP_FT]              = DR_ACTION_STATE_TERM,
  52                         [DR_ACTION_TYP_TAG]             = DR_ACTION_STATE_MODIFY_HDR,
  53                         [DR_ACTION_TYP_CTR]             = DR_ACTION_STATE_MODIFY_HDR,
  54                 },
  55                 [DR_ACTION_STATE_MODIFY_VLAN] = {
  56                         [DR_ACTION_TYP_DROP]            = DR_ACTION_STATE_TERM,
  57                         [DR_ACTION_TYP_QP]              = DR_ACTION_STATE_TERM,
  58                         [DR_ACTION_TYP_FT]              = DR_ACTION_STATE_TERM,
  59                         [DR_ACTION_TYP_TAG]             = DR_ACTION_STATE_MODIFY_VLAN,
  60                         [DR_ACTION_TYP_CTR]             = DR_ACTION_STATE_MODIFY_VLAN,
  61                         [DR_ACTION_TYP_POP_VLAN]        = DR_ACTION_STATE_MODIFY_VLAN,
  62                         [DR_ACTION_TYP_MODIFY_HDR]      = DR_ACTION_STATE_MODIFY_HDR,
  63                 },
  64                 [DR_ACTION_STATE_NON_TERM] = {
  65                         [DR_ACTION_TYP_DROP]            = DR_ACTION_STATE_TERM,
  66                         [DR_ACTION_TYP_QP]              = DR_ACTION_STATE_TERM,
  67                         [DR_ACTION_TYP_FT]              = DR_ACTION_STATE_TERM,
  68                         [DR_ACTION_TYP_TAG]             = DR_ACTION_STATE_NON_TERM,
  69                         [DR_ACTION_TYP_CTR]             = DR_ACTION_STATE_NON_TERM,
  70                         [DR_ACTION_TYP_TNL_L2_TO_L2]    = DR_ACTION_STATE_REFORMAT,
  71                         [DR_ACTION_TYP_TNL_L3_TO_L2]    = DR_ACTION_STATE_REFORMAT,
  72                         [DR_ACTION_TYP_MODIFY_HDR]      = DR_ACTION_STATE_MODIFY_HDR,
  73                         [DR_ACTION_TYP_POP_VLAN]        = DR_ACTION_STATE_MODIFY_VLAN,
  74                 },
  75                 [DR_ACTION_STATE_TERM] = {
  76                         [DR_ACTION_TYP_CTR]             = DR_ACTION_STATE_TERM,
  77                 },
  78         },
  79         [DR_ACTION_DOMAIN_NIC_EGRESS] = {
  80                 [DR_ACTION_STATE_NO_ACTION] = {
  81                         [DR_ACTION_TYP_DROP]            = DR_ACTION_STATE_TERM,
  82                         [DR_ACTION_TYP_FT]              = DR_ACTION_STATE_TERM,
  83                         [DR_ACTION_TYP_CTR]             = DR_ACTION_STATE_NON_TERM,
  84                         [DR_ACTION_TYP_L2_TO_TNL_L2]    = DR_ACTION_STATE_REFORMAT,
  85                         [DR_ACTION_TYP_L2_TO_TNL_L3]    = DR_ACTION_STATE_REFORMAT,
  86                         [DR_ACTION_TYP_MODIFY_HDR]      = DR_ACTION_STATE_MODIFY_HDR,
  87                         [DR_ACTION_TYP_PUSH_VLAN]       = DR_ACTION_STATE_MODIFY_VLAN,
  88                 },
  89                 [DR_ACTION_STATE_REFORMAT] = {
  90                         [DR_ACTION_TYP_DROP]            = DR_ACTION_STATE_TERM,
  91                         [DR_ACTION_TYP_FT]              = DR_ACTION_STATE_TERM,
  92                         [DR_ACTION_TYP_CTR]             = DR_ACTION_STATE_REFORMAT,
  93                 },
  94                 [DR_ACTION_STATE_MODIFY_HDR] = {
  95                         [DR_ACTION_TYP_DROP]            = DR_ACTION_STATE_TERM,
  96                         [DR_ACTION_TYP_FT]              = DR_ACTION_STATE_TERM,
  97                         [DR_ACTION_TYP_CTR]             = DR_ACTION_STATE_MODIFY_HDR,
  98                         [DR_ACTION_TYP_L2_TO_TNL_L2]    = DR_ACTION_STATE_REFORMAT,
  99                         [DR_ACTION_TYP_L2_TO_TNL_L3]    = DR_ACTION_STATE_REFORMAT,
 100                         [DR_ACTION_TYP_PUSH_VLAN]       = DR_ACTION_STATE_MODIFY_VLAN,
 101                 },
 102                 [DR_ACTION_STATE_MODIFY_VLAN] = {
 103                         [DR_ACTION_TYP_DROP]            = DR_ACTION_STATE_TERM,
 104                         [DR_ACTION_TYP_FT]              = DR_ACTION_STATE_TERM,
 105                         [DR_ACTION_TYP_CTR]             = DR_ACTION_STATE_MODIFY_VLAN,
 106                         [DR_ACTION_TYP_PUSH_VLAN]       = DR_ACTION_STATE_MODIFY_VLAN,
 107                         [DR_ACTION_TYP_L2_TO_TNL_L2]    = DR_ACTION_STATE_REFORMAT,
 108                         [DR_ACTION_TYP_L2_TO_TNL_L3]    = DR_ACTION_STATE_REFORMAT,
 109                 },
 110                 [DR_ACTION_STATE_NON_TERM] = {
 111                         [DR_ACTION_TYP_DROP]            = DR_ACTION_STATE_TERM,
 112                         [DR_ACTION_TYP_FT]              = DR_ACTION_STATE_TERM,
 113                         [DR_ACTION_TYP_CTR]             = DR_ACTION_STATE_NON_TERM,
 114                         [DR_ACTION_TYP_L2_TO_TNL_L2]    = DR_ACTION_STATE_REFORMAT,
 115                         [DR_ACTION_TYP_L2_TO_TNL_L3]    = DR_ACTION_STATE_REFORMAT,
 116                         [DR_ACTION_TYP_MODIFY_HDR]      = DR_ACTION_STATE_MODIFY_HDR,
 117                         [DR_ACTION_TYP_PUSH_VLAN]       = DR_ACTION_STATE_MODIFY_VLAN,
 118                 },
 119                 [DR_ACTION_STATE_TERM] = {
 120                         [DR_ACTION_TYP_CTR]             = DR_ACTION_STATE_TERM,
 121                 },
 122         },
 123         [DR_ACTION_DOMAIN_FDB_INGRESS] = {
 124                 [DR_ACTION_STATE_NO_ACTION] = {
 125                         [DR_ACTION_TYP_DROP]            = DR_ACTION_STATE_TERM,
 126                         [DR_ACTION_TYP_FT]              = DR_ACTION_STATE_TERM,
 127                         [DR_ACTION_TYP_CTR]             = DR_ACTION_STATE_NON_TERM,
 128                         [DR_ACTION_TYP_TNL_L2_TO_L2]    = DR_ACTION_STATE_REFORMAT,
 129                         [DR_ACTION_TYP_TNL_L3_TO_L2]    = DR_ACTION_STATE_REFORMAT,
 130                         [DR_ACTION_TYP_MODIFY_HDR]      = DR_ACTION_STATE_MODIFY_HDR,
 131                         [DR_ACTION_TYP_POP_VLAN]        = DR_ACTION_STATE_MODIFY_VLAN,
 132                         [DR_ACTION_TYP_VPORT]           = DR_ACTION_STATE_TERM,
 133                 },
 134                 [DR_ACTION_STATE_REFORMAT] = {
 135                         [DR_ACTION_TYP_DROP]            = DR_ACTION_STATE_TERM,
 136                         [DR_ACTION_TYP_FT]              = DR_ACTION_STATE_TERM,
 137                         [DR_ACTION_TYP_CTR]             = DR_ACTION_STATE_REFORMAT,
 138                         [DR_ACTION_TYP_MODIFY_HDR]      = DR_ACTION_STATE_MODIFY_HDR,
 139                         [DR_ACTION_TYP_POP_VLAN]        = DR_ACTION_STATE_MODIFY_VLAN,
 140                         [DR_ACTION_TYP_VPORT]           = DR_ACTION_STATE_TERM,
 141                 },
 142                 [DR_ACTION_STATE_MODIFY_HDR] = {
 143                         [DR_ACTION_TYP_DROP]            = DR_ACTION_STATE_TERM,
 144                         [DR_ACTION_TYP_FT]              = DR_ACTION_STATE_TERM,
 145                         [DR_ACTION_TYP_CTR]             = DR_ACTION_STATE_MODIFY_HDR,
 146                         [DR_ACTION_TYP_VPORT]           = DR_ACTION_STATE_TERM,
 147                 },
 148                 [DR_ACTION_STATE_MODIFY_VLAN] = {
 149                         [DR_ACTION_TYP_DROP]            = DR_ACTION_STATE_TERM,
 150                         [DR_ACTION_TYP_FT]              = DR_ACTION_STATE_TERM,
 151                         [DR_ACTION_TYP_POP_VLAN]        = DR_ACTION_STATE_MODIFY_VLAN,
 152                         [DR_ACTION_TYP_CTR]             = DR_ACTION_STATE_MODIFY_VLAN,
 153                         [DR_ACTION_TYP_VPORT]           = DR_ACTION_STATE_TERM,
 154                         [DR_ACTION_TYP_MODIFY_HDR]      = DR_ACTION_STATE_MODIFY_HDR,
 155                 },
 156                 [DR_ACTION_STATE_NON_TERM] = {
 157                         [DR_ACTION_TYP_DROP]            = DR_ACTION_STATE_TERM,
 158                         [DR_ACTION_TYP_FT]              = DR_ACTION_STATE_TERM,
 159                         [DR_ACTION_TYP_CTR]             = DR_ACTION_STATE_NON_TERM,
 160                         [DR_ACTION_TYP_TNL_L2_TO_L2]    = DR_ACTION_STATE_REFORMAT,
 161                         [DR_ACTION_TYP_TNL_L3_TO_L2]    = DR_ACTION_STATE_REFORMAT,
 162                         [DR_ACTION_TYP_MODIFY_HDR]      = DR_ACTION_STATE_MODIFY_HDR,
 163                         [DR_ACTION_TYP_POP_VLAN]        = DR_ACTION_STATE_MODIFY_VLAN,
 164                         [DR_ACTION_TYP_VPORT]           = DR_ACTION_STATE_TERM,
 165                 },
 166                 [DR_ACTION_STATE_TERM] = {
 167                         [DR_ACTION_TYP_CTR]             = DR_ACTION_STATE_TERM,
 168                 },
 169         },
 170         [DR_ACTION_DOMAIN_FDB_EGRESS] = {
 171                 [DR_ACTION_STATE_NO_ACTION] = {
 172                         [DR_ACTION_TYP_DROP]            = DR_ACTION_STATE_TERM,
 173                         [DR_ACTION_TYP_FT]              = DR_ACTION_STATE_TERM,
 174                         [DR_ACTION_TYP_CTR]             = DR_ACTION_STATE_NON_TERM,
 175                         [DR_ACTION_TYP_MODIFY_HDR]      = DR_ACTION_STATE_MODIFY_HDR,
 176                         [DR_ACTION_TYP_L2_TO_TNL_L2]    = DR_ACTION_STATE_REFORMAT,
 177                         [DR_ACTION_TYP_L2_TO_TNL_L3]    = DR_ACTION_STATE_REFORMAT,
 178                         [DR_ACTION_TYP_PUSH_VLAN]       = DR_ACTION_STATE_MODIFY_VLAN,
 179                         [DR_ACTION_TYP_VPORT]           = DR_ACTION_STATE_TERM,
 180                 },
 181                 [DR_ACTION_STATE_REFORMAT] = {
 182                         [DR_ACTION_TYP_DROP]            = DR_ACTION_STATE_TERM,
 183                         [DR_ACTION_TYP_FT]              = DR_ACTION_STATE_TERM,
 184                         [DR_ACTION_TYP_CTR]             = DR_ACTION_STATE_REFORMAT,
 185                         [DR_ACTION_TYP_VPORT]           = DR_ACTION_STATE_TERM,
 186                 },
 187                 [DR_ACTION_STATE_MODIFY_HDR] = {
 188                         [DR_ACTION_TYP_DROP]            = DR_ACTION_STATE_TERM,
 189                         [DR_ACTION_TYP_FT]              = DR_ACTION_STATE_TERM,
 190                         [DR_ACTION_TYP_CTR]             = DR_ACTION_STATE_MODIFY_HDR,
 191                         [DR_ACTION_TYP_L2_TO_TNL_L2]    = DR_ACTION_STATE_REFORMAT,
 192                         [DR_ACTION_TYP_L2_TO_TNL_L3]    = DR_ACTION_STATE_REFORMAT,
 193                         [DR_ACTION_TYP_PUSH_VLAN]       = DR_ACTION_STATE_MODIFY_VLAN,
 194                         [DR_ACTION_TYP_VPORT]           = DR_ACTION_STATE_TERM,
 195                 },
 196                 [DR_ACTION_STATE_MODIFY_VLAN] = {
 197                         [DR_ACTION_TYP_DROP]            = DR_ACTION_STATE_TERM,
 198                         [DR_ACTION_TYP_FT]              = DR_ACTION_STATE_TERM,
 199                         [DR_ACTION_TYP_PUSH_VLAN]       = DR_ACTION_STATE_MODIFY_VLAN,
 200                         [DR_ACTION_TYP_CTR]             = DR_ACTION_STATE_MODIFY_VLAN,
 201                         [DR_ACTION_TYP_L2_TO_TNL_L2]    = DR_ACTION_STATE_REFORMAT,
 202                         [DR_ACTION_TYP_L2_TO_TNL_L3]    = DR_ACTION_STATE_REFORMAT,
 203                         [DR_ACTION_TYP_VPORT]           = DR_ACTION_STATE_TERM,
 204                 },
 205                 [DR_ACTION_STATE_NON_TERM] = {
 206                         [DR_ACTION_TYP_DROP]            = DR_ACTION_STATE_TERM,
 207                         [DR_ACTION_TYP_FT]              = DR_ACTION_STATE_TERM,
 208                         [DR_ACTION_TYP_CTR]             = DR_ACTION_STATE_NON_TERM,
 209                         [DR_ACTION_TYP_MODIFY_HDR]      = DR_ACTION_STATE_MODIFY_HDR,
 210                         [DR_ACTION_TYP_L2_TO_TNL_L2]    = DR_ACTION_STATE_REFORMAT,
 211                         [DR_ACTION_TYP_L2_TO_TNL_L3]    = DR_ACTION_STATE_REFORMAT,
 212                         [DR_ACTION_TYP_PUSH_VLAN]       = DR_ACTION_STATE_MODIFY_VLAN,
 213                         [DR_ACTION_TYP_VPORT]           = DR_ACTION_STATE_TERM,
 214                 },
 215                 [DR_ACTION_STATE_TERM] = {
 216                         [DR_ACTION_TYP_CTR]             = DR_ACTION_STATE_TERM,
 217                 },
 218         },
 219 };
 220
 221 struct dr_action_modify_field_conv {
 222         u16 hw_field;
 223         u8 start;
 224         u8 end;
 225         u8 l3_type;
 226         u8 l4_type;
 227 };
 228
 229 static const struct dr_action_modify_field_conv dr_action_conv_arr[] = {
 230         [MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16] = {
 231                 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L2_1, .start = 16, .end = 47,
 232         },
 233         [MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0] = {
 234                 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L2_1, .start = 0, .end = 15,
 235         },
 236         [MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE] = {
 237                 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L2_2, .start = 32, .end = 47,
 238         },
 239         [MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16] = {
 240                 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L2_0, .start = 16, .end = 47,
 241         },
 242         [MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0] = {
 243                 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L2_0, .start = 0, .end = 15,
 244         },
 245         [MLX5_ACTION_IN_FIELD_OUT_IP_DSCP] = {
 246                 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_1, .start = 0, .end = 5,
 247         },
 248         [MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS] = {
 249                 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L4_0, .start = 48, .end = 56,
 250                 .l4_type = MLX5DR_ACTION_MDFY_HW_HDR_L4_TCP,
 251         },
 252         [MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT] = {
 253                 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L4_0, .start = 0, .end = 15,
 254                 .l4_type = MLX5DR_ACTION_MDFY_HW_HDR_L4_TCP,
 255         },
 256         [MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT] = {
 257                 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L4_0, .start = 16, .end = 31,
 258                 .l4_type = MLX5DR_ACTION_MDFY_HW_HDR_L4_TCP,
 259         },
 260         [MLX5_ACTION_IN_FIELD_OUT_IP_TTL] = {
 261                 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_1, .start = 8, .end = 15,
 262                 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV4,
 263         },
 264         [MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT] = {
 265                 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_1, .start = 8, .end = 15,
 266                 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6,
 267         },
 268         [MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT] = {
 269                 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L4_0, .start = 0, .end = 15,
 270                 .l4_type = MLX5DR_ACTION_MDFY_HW_HDR_L4_UDP,
 271         },
 272         [MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT] = {
 273                 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L4_0, .start = 16, .end = 31,
 274                 .l4_type = MLX5DR_ACTION_MDFY_HW_HDR_L4_UDP,
 275         },
 276         [MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96] = {
 277                 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_3, .start = 32, .end = 63,
 278                 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6,
 279         },
 280         [MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64] = {
 281                 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_3, .start = 0, .end = 31,
 282                 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6,
 283         },
 284         [MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32] = {
 285                 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_4, .start = 32, .end = 63,
 286                 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6,
 287         },
 288         [MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0] = {
 289                 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_4, .start = 0, .end = 31,
 290                 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6,
 291         },
 292         [MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96] = {
 293                 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_0, .start = 32, .end = 63,
 294                 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6,
 295         },
 296         [MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64] = {
 297                 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_0, .start = 0, .end = 31,
 298                 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6,
 299         },
 300         [MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32] = {
 301                 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_2, .start = 32, .end = 63,
 302                 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6,
 303         },
 304         [MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0] = {
 305                 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_2, .start = 0, .end = 31,
 306                 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV6,
 307         },
 308         [MLX5_ACTION_IN_FIELD_OUT_SIPV4] = {
 309                 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_0, .start = 0, .end = 31,
 310                 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV4,
 311         },
 312         [MLX5_ACTION_IN_FIELD_OUT_DIPV4] = {
 313                 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L3_0, .start = 32, .end = 63,
 314                 .l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_IPV4,
 315         },
 316         [MLX5_ACTION_IN_FIELD_METADATA_REG_A] = {
 317                 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_METADATA, .start = 0, .end = 31,
 318         },
 319         [MLX5_ACTION_IN_FIELD_METADATA_REG_B] = {
 320                 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_METADATA, .start = 32, .end = 63,
 321         },
 322         [MLX5_ACTION_IN_FIELD_METADATA_REG_C_0] = {
 323                 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_REG_0, .start = 32, .end = 63,
 324         },
 325         [MLX5_ACTION_IN_FIELD_METADATA_REG_C_1] = {
 326                 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_REG_0, .start = 0, .end = 31,
 327         },
 328         [MLX5_ACTION_IN_FIELD_METADATA_REG_C_2] = {
 329                 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_REG_1, .start = 32, .end = 63,
 330         },
 331         [MLX5_ACTION_IN_FIELD_METADATA_REG_C_3] = {
 332                 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_REG_1, .start = 0, .end = 31,
 333         },
 334         [MLX5_ACTION_IN_FIELD_METADATA_REG_C_4] = {
 335                 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_REG_2, .start = 32, .end = 63,
 336         },
 337         [MLX5_ACTION_IN_FIELD_METADATA_REG_C_5] = {
 338                 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_REG_2, .start = 0, .end = 31,
 339         },
 340         [MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM] = {
 341                 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L4_1, .start = 32, .end = 63,
 342         },
 343         [MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM] = {
 344                 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L4_1, .start = 0, .end = 31,
 345         },
 346         [MLX5_ACTION_IN_FIELD_OUT_FIRST_VID] = {
 347                 .hw_field = MLX5DR_ACTION_MDFY_HW_FLD_L2_2, .start = 0, .end = 15,
 348         },
 349 };
 350
 351 #define MAX_VLANS 2
 352 struct dr_action_vlan_info {
 353         int     count;
 354         u32     headers[MAX_VLANS];
 355 };
 356
 357 struct dr_action_apply_attr {
 358         u32     modify_index;
 359         u16     modify_actions;
 360         u32     decap_index;
 361         u16     decap_actions;
 362         u8      decap_with_vlan:1;
 363         u64     final_icm_addr;
 364         u32     flow_tag;
 365         u32     ctr_id;
 366         u16     gvmi;
 367         u16     hit_gvmi;
 368         u32     reformat_id;
 369         u32     reformat_size;
 370         struct  dr_action_vlan_info vlans;
 371 };
 372
 373 static int
 374 dr_action_reformat_to_action_type(enum mlx5dr_action_reformat_type reformat_type,
 375                                   enum mlx5dr_action_type *action_type)
 376 {
 377         switch (reformat_type) {
 378         case DR_ACTION_REFORMAT_TYP_TNL_L2_TO_L2:
 379                 *action_type = DR_ACTION_TYP_TNL_L2_TO_L2;
 380                 break;
 381         case DR_ACTION_REFORMAT_TYP_L2_TO_TNL_L2:
 382                 *action_type = DR_ACTION_TYP_L2_TO_TNL_L2;
 383                 break;
 384         case DR_ACTION_REFORMAT_TYP_TNL_L3_TO_L2:
 385                 *action_type = DR_ACTION_TYP_TNL_L3_TO_L2;
 386                 break;
 387         case DR_ACTION_REFORMAT_TYP_L2_TO_TNL_L3:
 388                 *action_type = DR_ACTION_TYP_L2_TO_TNL_L3;
 389                 break;
 390         default:
 391                 return -EINVAL;
 392         }
 393
 394         return 0;
 395 }
 396
 397 static void dr_actions_init_next_ste(u8 **last_ste,
 398                                      u32 *added_stes,
 399                                      enum mlx5dr_ste_entry_type entry_type,
 400                                      u16 gvmi)
 401 {
 402         (*added_stes)++;
 403         *last_ste += DR_STE_SIZE;
 404         mlx5dr_ste_init(*last_ste, MLX5DR_STE_LU_TYPE_DONT_CARE, entry_type, gvmi);
 405 }
 406
 407 static void dr_actions_apply_tx(struct mlx5dr_domain *dmn,
 408                                 u8 *action_type_set,
 409                                 u8 *last_ste,
 410                                 struct dr_action_apply_attr *attr,
 411                                 u32 *added_stes)
 412 {
 413         bool encap = action_type_set[DR_ACTION_TYP_L2_TO_TNL_L2] ||
 414                 action_type_set[DR_ACTION_TYP_L2_TO_TNL_L3];
 415
 416         /* We want to make sure the modify header comes before L2
 417          * encapsulation. The reason for that is that we support
 418          * modify headers for outer headers only
 419          */
 420         if (action_type_set[DR_ACTION_TYP_MODIFY_HDR]) {
 421                 mlx5dr_ste_set_entry_type(last_ste, MLX5DR_STE_TYPE_MODIFY_PKT);
 422                 mlx5dr_ste_set_rewrite_actions(last_ste,
 423                                                attr->modify_actions,
 424                                                attr->modify_index);
 425         }
 426
 427         if (action_type_set[DR_ACTION_TYP_PUSH_VLAN]) {
 428                 int i;
 429
 430                 for (i = 0; i < attr->vlans.count; i++) {
 431                         if (i || action_type_set[DR_ACTION_TYP_MODIFY_HDR])
 432                                 dr_actions_init_next_ste(&last_ste,
 433                                                          added_stes,
 434                                                          MLX5DR_STE_TYPE_TX,
 435                                                          attr->gvmi);
 436
 437                         mlx5dr_ste_set_tx_push_vlan(last_ste,
 438                                                     attr->vlans.headers[i],
 439                                                     encap);
 440                 }
 441         }
 442
 443         if (encap) {
 444                 /* Modify header and encapsulation require a different STEs.
 445                  * Since modify header STE format doesn't support encapsulation
 446                  * tunneling_action.
 447                  */
 448                 if (action_type_set[DR_ACTION_TYP_MODIFY_HDR] ||
 449                     action_type_set[DR_ACTION_TYP_PUSH_VLAN])
 450                         dr_actions_init_next_ste(&last_ste,
 451                                                  added_stes,
 452                                                  MLX5DR_STE_TYPE_TX,
 453                                                  attr->gvmi);
 454
 455                 mlx5dr_ste_set_tx_encap(last_ste,
 456                                         attr->reformat_id,
 457                                         attr->reformat_size,
 458                                         action_type_set[DR_ACTION_TYP_L2_TO_TNL_L3]);
 459                 /* Whenever prio_tag_required enabled, we can be sure that the
 460                  * previous table (ACL) already push vlan to our packet,
 461                  * And due to HW limitation we need to set this bit, otherwise
 462                  * push vlan + reformat will not work.
 463                  */
 464                 if (MLX5_CAP_GEN(dmn->mdev, prio_tag_required))
 465                         mlx5dr_ste_set_go_back_bit(last_ste);
 466         }
 467
 468         if (action_type_set[DR_ACTION_TYP_CTR])
 469                 mlx5dr_ste_set_counter_id(last_ste, attr->ctr_id);
 470 }
 471
 472 static void dr_actions_apply_rx(u8 *action_type_set,
 473                                 u8 *last_ste,
 474                                 struct dr_action_apply_attr *attr,
 475                                 u32 *added_stes)
 476 {
 477         if (action_type_set[DR_ACTION_TYP_CTR])
 478                 mlx5dr_ste_set_counter_id(last_ste, attr->ctr_id);
 479
 480         if (action_type_set[DR_ACTION_TYP_TNL_L3_TO_L2]) {
 481                 mlx5dr_ste_set_entry_type(last_ste, MLX5DR_STE_TYPE_MODIFY_PKT);
 482                 mlx5dr_ste_set_rx_decap_l3(last_ste, attr->decap_with_vlan);
 483                 mlx5dr_ste_set_rewrite_actions(last_ste,
 484                                                attr->decap_actions,
 485                                                attr->decap_index);
 486         }
 487
 488         if (action_type_set[DR_ACTION_TYP_TNL_L2_TO_L2])
 489                 mlx5dr_ste_set_rx_decap(last_ste);
 490
 491         if (action_type_set[DR_ACTION_TYP_POP_VLAN]) {
 492                 int i;
 493
 494                 for (i = 0; i < attr->vlans.count; i++) {
 495                         if (i ||
 496                             action_type_set[DR_ACTION_TYP_TNL_L2_TO_L2] ||
 497                             action_type_set[DR_ACTION_TYP_TNL_L3_TO_L2])
 498                                 dr_actions_init_next_ste(&last_ste,
 499                                                          added_stes,
 500                                                          MLX5DR_STE_TYPE_RX,
 501                                                          attr->gvmi);
 502
 503                         mlx5dr_ste_set_rx_pop_vlan(last_ste);
 504                 }
 505         }
 506
 507         if (action_type_set[DR_ACTION_TYP_MODIFY_HDR]) {
 508                 if (mlx5dr_ste_get_entry_type(last_ste) == MLX5DR_STE_TYPE_MODIFY_PKT)
 509                         dr_actions_init_next_ste(&last_ste,
 510                                                  added_stes,
 511                                                  MLX5DR_STE_TYPE_MODIFY_PKT,
 512                                                  attr->gvmi);
 513                 else
 514                         mlx5dr_ste_set_entry_type(last_ste, MLX5DR_STE_TYPE_MODIFY_PKT);
 515
 516                 mlx5dr_ste_set_rewrite_actions(last_ste,
 517                                                attr->modify_actions,
 518                                                attr->modify_index);
 519         }
 520
 521         if (action_type_set[DR_ACTION_TYP_TAG]) {
 522                 if (mlx5dr_ste_get_entry_type(last_ste) == MLX5DR_STE_TYPE_MODIFY_PKT)
 523                         dr_actions_init_next_ste(&last_ste,
 524                                                  added_stes,
 525                                                  MLX5DR_STE_TYPE_RX,
 526                                                  attr->gvmi);
 527
 528                 mlx5dr_ste_rx_set_flow_tag(last_ste, attr->flow_tag);
 529         }
 530 }
 531
 532 /* Apply the actions on the rule STE array starting from the last_ste.
 533  * Actions might require more than one STE, new_num_stes will return
 534  * the new size of the STEs array, rule with actions.
 535  */
 536 static void dr_actions_apply(struct mlx5dr_domain *dmn,
 537                              enum mlx5dr_ste_entry_type ste_type,
 538                              u8 *action_type_set,
 539                              u8 *last_ste,
 540                              struct dr_action_apply_attr *attr,
 541                              u32 *new_num_stes)
 542 {
 543         u32 added_stes = 0;
 544
 545         if (ste_type == MLX5DR_STE_TYPE_RX)
 546                 dr_actions_apply_rx(action_type_set, last_ste, attr, &added_stes);
 547         else
 548                 dr_actions_apply_tx(dmn, action_type_set, last_ste, attr, &added_stes);
 549
 550         last_ste += added_stes * DR_STE_SIZE;
 551         *new_num_stes += added_stes;
 552
 553         mlx5dr_ste_set_hit_gvmi(last_ste, attr->hit_gvmi);
 554         mlx5dr_ste_set_hit_addr(last_ste, attr->final_icm_addr, 1);
 555 }
 556
 557 static enum dr_action_domain
 558 dr_action_get_action_domain(enum mlx5dr_domain_type domain,
 559                             enum mlx5dr_ste_entry_type ste_type)
 560 {
 561         switch (domain) {
 562         case MLX5DR_DOMAIN_TYPE_NIC_RX:
 563                 return DR_ACTION_DOMAIN_NIC_INGRESS;
 564         case MLX5DR_DOMAIN_TYPE_NIC_TX:
 565                 return DR_ACTION_DOMAIN_NIC_EGRESS;
 566         case MLX5DR_DOMAIN_TYPE_FDB:
 567                 if (ste_type == MLX5DR_STE_TYPE_RX)
 568                         return DR_ACTION_DOMAIN_FDB_INGRESS;
 569                 return DR_ACTION_DOMAIN_FDB_EGRESS;
 570         default:
 571                 WARN_ON(true);
 572                 return DR_ACTION_DOMAIN_MAX;
 573         }
 574 }
 575
 576 static
 577 int dr_action_validate_and_get_next_state(enum dr_action_domain action_domain,
 578                                           u32 action_type,
 579                                           u32 *state)
 580 {
 581         u32 cur_state = *state;
 582
 583         /* Check action state machine is valid */
 584         *state = next_action_state[action_domain][cur_state][action_type];
 585
 586         if (*state == DR_ACTION_STATE_ERR)
 587                 return -EOPNOTSUPP;
 588
 589         return 0;
 590 }
 591
 592 static int dr_action_handle_cs_recalc(struct mlx5dr_domain *dmn,
 593                                       struct mlx5dr_action *dest_action,
 594                                       u64 *final_icm_addr)
 595 {
 596         int ret;
 597
 598         switch (dest_action->action_type) {
 599         case DR_ACTION_TYP_FT:
 600                 /* Allow destination flow table only if table is a terminating
 601                  * table, since there is an *assumption* that in such case FW
 602                  * will recalculate the CS.
 603                  */
 604                 if (dest_action->dest_tbl.is_fw_tbl) {
 605                         *final_icm_addr = dest_action->dest_tbl.fw_tbl.rx_icm_addr;
 606                 } else {
 607                         mlx5dr_dbg(dmn,
 608                                    "Destination FT should be terminating when modify TTL is used\n");
 609                         return -EINVAL;
 610                 }
 611                 break;
 612
 613         case DR_ACTION_TYP_VPORT:
 614                 /* If destination is vport we will get the FW flow table
 615                  * that recalculates the CS and forwards to the vport.
 616                  */
 617                 ret = mlx5dr_domain_cache_get_recalc_cs_ft_addr(dest_action->vport.dmn,
 618                                                                 dest_action->vport.caps->num,
 619                                                                 final_icm_addr);
 620                 if (ret) {
 621                         mlx5dr_err(dmn, "Failed to get FW cs recalc flow table\n");
 622                         return ret;
 623                 }
 624                 break;
 625
 626         default:
 627                 break;
 628         }
 629
 630         return 0;
 631 }
 632
 633 #define WITH_VLAN_NUM_HW_ACTIONS 6
 634
 635 int mlx5dr_actions_build_ste_arr(struct mlx5dr_matcher *matcher,
 636                                  struct mlx5dr_matcher_rx_tx *nic_matcher,
 637                                  struct mlx5dr_action *actions[],
 638                                  u32 num_actions,
 639                                  u8 *ste_arr,
 640                                  u32 *new_hw_ste_arr_sz)
 641 {
 642         struct mlx5dr_domain_rx_tx *nic_dmn = nic_matcher->nic_tbl->nic_dmn;
 643         bool rx_rule = nic_dmn->ste_type == MLX5DR_STE_TYPE_RX;
 644         struct mlx5dr_domain *dmn = matcher->tbl->dmn;
 645         u8 action_type_set[DR_ACTION_TYP_MAX] = {};
 646         struct mlx5dr_action *dest_action = NULL;
 647         u32 state = DR_ACTION_STATE_NO_ACTION;
 648         struct dr_action_apply_attr attr = {};
 649         enum dr_action_domain action_domain;
 650         bool recalc_cs_required = false;
 651         u8 *last_ste;
 652         int i, ret;
 653
 654         attr.gvmi = dmn->info.caps.gvmi;
 655         attr.hit_gvmi = dmn->info.caps.gvmi;
 656         attr.final_icm_addr = nic_dmn->default_icm_addr;
 657         action_domain = dr_action_get_action_domain(dmn->type, nic_dmn->ste_type);
 658
 659         for (i = 0; i < num_actions; i++) {
 660                 struct mlx5dr_action *action;
 661                 int max_actions_type = 1;
 662                 u32 action_type;
 663
 664                 action = actions[i];
 665                 action_type = action->action_type;
 666
 667                 switch (action_type) {
 668                 case DR_ACTION_TYP_DROP:
 669                         attr.final_icm_addr = nic_dmn->drop_icm_addr;
 670                         break;
 671                 case DR_ACTION_TYP_FT:
 672                         dest_action = action;
 673                         if (!action->dest_tbl.is_fw_tbl) {
 674                                 if (action->dest_tbl.tbl->dmn != dmn) {
 675                                         mlx5dr_dbg(dmn,
 676                                                    "Destination table belongs to a different domain\n");
 677                                         goto out_invalid_arg;
 678                                 }
 679                                 if (action->dest_tbl.tbl->level <= matcher->tbl->level) {
 680                                         mlx5dr_dbg(dmn,
 681                                                    "Destination table level should be higher than source table\n");
 682                                         goto out_invalid_arg;
 683                                 }
 684                                 attr.final_icm_addr = rx_rule ?
 685                                         action->dest_tbl.tbl->rx.s_anchor->chunk->icm_addr :
 686                                         action->dest_tbl.tbl->tx.s_anchor->chunk->icm_addr;
 687                         } else {
 688                                 struct mlx5dr_cmd_query_flow_table_details output;
 689                                 int ret;
 690
 691                                 /* get the relevant addresses */
 692                                 if (!action->dest_tbl.fw_tbl.rx_icm_addr) {
 693                                         ret = mlx5dr_cmd_query_flow_table(action->dest_tbl.fw_tbl.mdev,
 694                                                                           action->dest_tbl.fw_tbl.ft->type,
 695                                                                           action->dest_tbl.fw_tbl.ft->id,
 696                                                                           &output);
 697                                         if (!ret) {
 698                                                 action->dest_tbl.fw_tbl.tx_icm_addr =
 699                                                         output.sw_owner_icm_root_1;
 700                                                 action->dest_tbl.fw_tbl.rx_icm_addr =
 701                                                         output.sw_owner_icm_root_0;
 702                                         } else {
 703                                                 mlx5dr_dbg(dmn,
 704                                                            "Failed mlx5_cmd_query_flow_table ret: %d\n",
 705                                                            ret);
 706                                                 return ret;
 707                                         }
 708                                 }
 709                                 attr.final_icm_addr = rx_rule ?
 710                                         action->dest_tbl.fw_tbl.rx_icm_addr :
 711                                         action->dest_tbl.fw_tbl.tx_icm_addr;
 712                         }
 713                         break;
 714                 case DR_ACTION_TYP_QP:
 715                         mlx5dr_info(dmn, "Domain doesn't support QP\n");
 716                         goto out_invalid_arg;
 717                 case DR_ACTION_TYP_CTR:
 718                         attr.ctr_id = action->ctr.ctr_id +
 719                                 action->ctr.offeset;
 720                         break;
 721                 case DR_ACTION_TYP_TAG:
 722                         attr.flow_tag = action->flow_tag;
 723                         break;
 724                 case DR_ACTION_TYP_TNL_L2_TO_L2:
 725                         break;
 726                 case DR_ACTION_TYP_TNL_L3_TO_L2:
 727                         attr.decap_index = action->rewrite.index;
 728                         attr.decap_actions = action->rewrite.num_of_actions;
 729                         attr.decap_with_vlan =
 730                                 attr.decap_actions == WITH_VLAN_NUM_HW_ACTIONS;
 731                         break;
 732                 case DR_ACTION_TYP_MODIFY_HDR:
 733                         attr.modify_index = action->rewrite.index;
 734                         attr.modify_actions = action->rewrite.num_of_actions;
 735                         recalc_cs_required = action->rewrite.modify_ttl;
 736                         break;
 737                 case DR_ACTION_TYP_L2_TO_TNL_L2:
 738                 case DR_ACTION_TYP_L2_TO_TNL_L3:
 739                         attr.reformat_size = action->reformat.reformat_size;
 740                         attr.reformat_id = action->reformat.reformat_id;
 741                         break;
 742                 case DR_ACTION_TYP_VPORT:
 743                         attr.hit_gvmi = action->vport.caps->vhca_gvmi;
 744                         dest_action = action;
 745                         if (rx_rule) {
 746                                 /* Loopback on WIRE vport is not supported */
 747                                 if (action->vport.caps->num == WIRE_PORT)
 748                                         goto out_invalid_arg;
 749
 750                                 attr.final_icm_addr = action->vport.caps->icm_address_rx;
 751                         } else {
 752                                 attr.final_icm_addr = action->vport.caps->icm_address_tx;
 753                         }
 754                         break;
 755                 case DR_ACTION_TYP_POP_VLAN:
 756                         max_actions_type = MAX_VLANS;
 757                         attr.vlans.count++;
 758                         break;
 759                 case DR_ACTION_TYP_PUSH_VLAN:
 760                         max_actions_type = MAX_VLANS;
 761                         if (attr.vlans.count == MAX_VLANS)
 762                                 return -EINVAL;
 763
 764                         attr.vlans.headers[attr.vlans.count++] = action->push_vlan.vlan_hdr;
 765                         break;
 766                 default:
 767                         goto out_invalid_arg;
 768                 }
 769
 770                 /* Check action duplication */
 771                 if (++action_type_set[action_type] > max_actions_type) {
 772                         mlx5dr_dbg(dmn, "Action type %d supports only max %d time(s)\n",
 773                                    action_type, max_actions_type);
 774                         goto out_invalid_arg;
 775                 }
 776
 777                 /* Check action state machine is valid */
 778                 if (dr_action_validate_and_get_next_state(action_domain,
 779                                                           action_type,
 780                                                           &state)) {
 781                         mlx5dr_dbg(dmn, "Invalid action sequence provided\n");
 782                         return -EOPNOTSUPP;
 783                 }
 784         }
 785
 786         *new_hw_ste_arr_sz = nic_matcher->num_of_builders;
 787         last_ste = ste_arr + DR_STE_SIZE * (nic_matcher->num_of_builders - 1);
 788
 789         /* Due to a HW bug, modifying TTL on RX flows will cause an incorrect
 790          * checksum calculation. In this case we will use a FW table to
 791          * recalculate.
 792          */
 793         if (dmn->type == MLX5DR_DOMAIN_TYPE_FDB &&
 794             rx_rule && recalc_cs_required && dest_action) {
 795                 ret = dr_action_handle_cs_recalc(dmn, dest_action, &attr.final_icm_addr);
 796                 if (ret) {
 797                         mlx5dr_dbg(dmn,
 798                                    "Failed to handle checksum recalculation err %d\n",
 799                                    ret);
 800                         return ret;
 801                 }
 802         }
 803
 804         dr_actions_apply(dmn,
 805                          nic_dmn->ste_type,
 806                          action_type_set,
 807                          last_ste,
 808                          &attr,
 809                          new_hw_ste_arr_sz);
 810
 811         return 0;
 812
 813 out_invalid_arg:
 814         return -EINVAL;
 815 }
 816
 817 #define CVLAN_ETHERTYPE 0x8100
 818 #define SVLAN_ETHERTYPE 0x88a8
 819 #define HDR_LEN_L2_ONLY 14
 820 #define HDR_LEN_L2_VLAN 18
 821 #define REWRITE_HW_ACTION_NUM 6
 822
 823 static int dr_actions_l2_rewrite(struct mlx5dr_domain *dmn,
 824                                  struct mlx5dr_action *action,
 825                                  void *data, size_t data_sz)
 826 {
 827         struct mlx5_ifc_l2_hdr_bits *l2_hdr = data;
 828         u64 ops[REWRITE_HW_ACTION_NUM] = {};
 829         u32 hdr_fld_4b;
 830         u16 hdr_fld_2b;
 831         u16 vlan_type;
 832         bool vlan;
 833         int i = 0;
 834         int ret;
 835
 836         vlan = (data_sz != HDR_LEN_L2_ONLY);
 837
 838         /* dmac_47_16 */
 839         MLX5_SET(dr_action_hw_set, ops + i,
 840                  opcode, MLX5DR_ACTION_MDFY_HW_OP_SET);
 841         MLX5_SET(dr_action_hw_set, ops + i,
 842                  destination_length, 0);
 843         MLX5_SET(dr_action_hw_set, ops + i,
 844                  destination_field_code, MLX5DR_ACTION_MDFY_HW_FLD_L2_0);
 845         MLX5_SET(dr_action_hw_set, ops + i,
 846                  destination_left_shifter, 16);
 847         hdr_fld_4b = MLX5_GET(l2_hdr, l2_hdr, dmac_47_16);
 848         MLX5_SET(dr_action_hw_set, ops + i,
 849                  inline_data, hdr_fld_4b);
 850         i++;
 851
 852         /* smac_47_16 */
 853         MLX5_SET(dr_action_hw_set, ops + i,
 854                  opcode, MLX5DR_ACTION_MDFY_HW_OP_SET);
 855         MLX5_SET(dr_action_hw_set, ops + i,
 856                  destination_length, 0);
 857         MLX5_SET(dr_action_hw_set, ops + i,
 858                  destination_field_code, MLX5DR_ACTION_MDFY_HW_FLD_L2_1);
 859         MLX5_SET(dr_action_hw_set, ops + i,
 860                  destination_left_shifter, 16);
 861         hdr_fld_4b = (MLX5_GET(l2_hdr, l2_hdr, smac_31_0) >> 16 |
 862                       MLX5_GET(l2_hdr, l2_hdr, smac_47_32) << 16);
 863         MLX5_SET(dr_action_hw_set, ops + i,
 864                  inline_data, hdr_fld_4b);
 865         i++;
 866
 867         /* dmac_15_0 */
 868         MLX5_SET(dr_action_hw_set, ops + i,
 869                  opcode, MLX5DR_ACTION_MDFY_HW_OP_SET);
 870         MLX5_SET(dr_action_hw_set, ops + i,
 871                  destination_length, 16);
 872         MLX5_SET(dr_action_hw_set, ops + i,
 873                  destination_field_code, MLX5DR_ACTION_MDFY_HW_FLD_L2_0);
 874         MLX5_SET(dr_action_hw_set, ops + i,
 875                  destination_left_shifter, 0);
 876         hdr_fld_2b = MLX5_GET(l2_hdr, l2_hdr, dmac_15_0);
 877         MLX5_SET(dr_action_hw_set, ops + i,
 878                  inline_data, hdr_fld_2b);
 879         i++;
 880
 881         /* ethertype + (optional) vlan */
 882         MLX5_SET(dr_action_hw_set, ops + i,
 883                  opcode, MLX5DR_ACTION_MDFY_HW_OP_SET);
 884         MLX5_SET(dr_action_hw_set, ops + i,
 885                  destination_field_code, MLX5DR_ACTION_MDFY_HW_FLD_L2_2);
 886         MLX5_SET(dr_action_hw_set, ops + i,
 887                  destination_left_shifter, 32);
 888         if (!vlan) {
 889                 hdr_fld_2b = MLX5_GET(l2_hdr, l2_hdr, ethertype);
 890                 MLX5_SET(dr_action_hw_set, ops + i, inline_data, hdr_fld_2b);
 891                 MLX5_SET(dr_action_hw_set, ops + i, destination_length, 16);
 892         } else {
 893                 hdr_fld_2b = MLX5_GET(l2_hdr, l2_hdr, ethertype);
 894                 vlan_type = hdr_fld_2b == SVLAN_ETHERTYPE ? DR_STE_SVLAN : DR_STE_CVLAN;
 895                 hdr_fld_2b = MLX5_GET(l2_hdr, l2_hdr, vlan);
 896                 hdr_fld_4b = (vlan_type << 16) | hdr_fld_2b;
 897                 MLX5_SET(dr_action_hw_set, ops + i, inline_data, hdr_fld_4b);
 898                 MLX5_SET(dr_action_hw_set, ops + i, destination_length, 18);
 899         }
 900         i++;
 901
 902         /* smac_15_0 */
 903         MLX5_SET(dr_action_hw_set, ops + i,
 904                  opcode, MLX5DR_ACTION_MDFY_HW_OP_SET);
 905         MLX5_SET(dr_action_hw_set, ops + i,
 906                  destination_length, 16);
 907         MLX5_SET(dr_action_hw_set, ops + i,
 908                  destination_field_code, MLX5DR_ACTION_MDFY_HW_FLD_L2_1);
 909         MLX5_SET(dr_action_hw_set, ops + i,
 910                  destination_left_shifter, 0);
 911         hdr_fld_2b = MLX5_GET(l2_hdr, l2_hdr, smac_31_0);
 912         MLX5_SET(dr_action_hw_set, ops + i,
 913                  inline_data, hdr_fld_2b);
 914         i++;
 915
 916         if (vlan) {
 917                 MLX5_SET(dr_action_hw_set, ops + i,
 918                          opcode, MLX5DR_ACTION_MDFY_HW_OP_SET);
 919                 hdr_fld_2b = MLX5_GET(l2_hdr, l2_hdr, vlan_type);
 920                 MLX5_SET(dr_action_hw_set, ops + i,
 921                          inline_data, hdr_fld_2b);
 922                 MLX5_SET(dr_action_hw_set, ops + i,
 923                          destination_length, 16);
 924                 MLX5_SET(dr_action_hw_set, ops + i,
 925                          destination_field_code, MLX5DR_ACTION_MDFY_HW_FLD_L2_2);
 926                 MLX5_SET(dr_action_hw_set, ops + i,
 927                          destination_left_shifter, 0);
 928                 i++;
 929         }
 930
 931         action->rewrite.data = (void *)ops;
 932         action->rewrite.num_of_actions = i;
 933
 934         ret = mlx5dr_send_postsend_action(dmn, action);
 935         if (ret) {
 936                 mlx5dr_dbg(dmn, "Writing encapsulation action to ICM failed\n");
 937                 return ret;
 938         }
 939
 940         return 0;
 941 }
 942
 943 static struct mlx5dr_action *
 944 dr_action_create_generic(enum mlx5dr_action_type action_type)
 945 {
 946         struct mlx5dr_action *action;
 947
 948         action = kzalloc(sizeof(*action), GFP_KERNEL);
 949         if (!action)
 950                 return NULL;
 951
 952         action->action_type = action_type;
 953         refcount_set(&action->refcount, 1);
 954
 955         return action;
 956 }
 957
 958 struct mlx5dr_action *mlx5dr_action_create_drop(void)
 959 {
 960         return dr_action_create_generic(DR_ACTION_TYP_DROP);
 961 }
 962
 963 struct mlx5dr_action *
 964 mlx5dr_action_create_dest_table(struct mlx5dr_table *tbl)
 965 {
 966         struct mlx5dr_action *action;
 967
 968         refcount_inc(&tbl->refcount);
 969
 970         action = dr_action_create_generic(DR_ACTION_TYP_FT);
 971         if (!action)
 972                 goto dec_ref;
 973
 974         action->dest_tbl.tbl = tbl;
 975
 976         return action;
 977
 978 dec_ref:
 979         refcount_dec(&tbl->refcount);
 980         return NULL;
 981 }
 982
 983 struct mlx5dr_action *
 984 mlx5dr_create_action_dest_flow_fw_table(struct mlx5_flow_table *ft,
 985                                         struct mlx5_core_dev *mdev)
 986 {
 987         struct mlx5dr_action *action;
 988
 989         action = dr_action_create_generic(DR_ACTION_TYP_FT);
 990         if (!action)
 991                 return NULL;
 992
 993         action->dest_tbl.is_fw_tbl = 1;
 994         action->dest_tbl.fw_tbl.ft = ft;
 995         action->dest_tbl.fw_tbl.mdev = mdev;
 996
 997         return action;
 998 }
 999
1000 struct mlx5dr_action *
1001 mlx5dr_action_create_flow_counter(u32 counter_id)
1002 {
1003         struct mlx5dr_action *action;
1004
1005         action = dr_action_create_generic(DR_ACTION_TYP_CTR);
1006         if (!action)
1007                 return NULL;
1008
1009         action->ctr.ctr_id = counter_id;
1010
1011         return action;
1012 }
1013
1014 struct mlx5dr_action *mlx5dr_action_create_tag(u32 tag_value)
1015 {
1016         struct mlx5dr_action *action;
1017
1018         action = dr_action_create_generic(DR_ACTION_TYP_TAG);
1019         if (!action)
1020                 return NULL;
1021
1022         action->flow_tag = tag_value & 0xffffff;
1023
1024         return action;
1025 }
1026
1027 static int
1028 dr_action_verify_reformat_params(enum mlx5dr_action_type reformat_type,
1029                                  struct mlx5dr_domain *dmn,
1030                                  size_t data_sz,
1031                                  void *data)
1032 {
1033         if ((!data && data_sz) || (data && !data_sz) || reformat_type >
1034                 DR_ACTION_TYP_L2_TO_TNL_L3) {
1035                 mlx5dr_dbg(dmn, "Invalid reformat parameter!\n");
1036                 goto out_err;
1037         }
1038
1039         if (dmn->type == MLX5DR_DOMAIN_TYPE_FDB)
1040                 return 0;
1041
1042         if (dmn->type == MLX5DR_DOMAIN_TYPE_NIC_RX) {
1043                 if (reformat_type != DR_ACTION_TYP_TNL_L2_TO_L2 &&
1044                     reformat_type != DR_ACTION_TYP_TNL_L3_TO_L2) {
1045                         mlx5dr_dbg(dmn, "Action reformat type not support on RX domain\n");
1046                         goto out_err;
1047                 }
1048         } else if (dmn->type == MLX5DR_DOMAIN_TYPE_NIC_TX) {
1049                 if (reformat_type != DR_ACTION_TYP_L2_TO_TNL_L2 &&
1050                     reformat_type != DR_ACTION_TYP_L2_TO_TNL_L3) {
1051                         mlx5dr_dbg(dmn, "Action reformat type not support on TX domain\n");
1052                         goto out_err;
1053                 }
1054         }
1055
1056         return 0;
1057
1058 out_err:
1059         return -EINVAL;
1060 }
1061
1062 #define ACTION_CACHE_LINE_SIZE 64
1063
1064 static int
1065 dr_action_create_reformat_action(struct mlx5dr_domain *dmn,
1066                                  size_t data_sz, void *data,
1067                                  struct mlx5dr_action *action)
1068 {
1069         u32 reformat_id;
1070         int ret;
1071
1072         switch (action->action_type) {
1073         case DR_ACTION_TYP_L2_TO_TNL_L2:
1074         case DR_ACTION_TYP_L2_TO_TNL_L3:
1075         {
1076                 enum mlx5_reformat_ctx_type rt;
1077
1078                 if (action->action_type == DR_ACTION_TYP_L2_TO_TNL_L2)
1079                         rt = MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL;
1080                 else
1081                         rt = MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL;
1082
1083                 ret = mlx5dr_cmd_create_reformat_ctx(dmn->mdev, rt, data_sz, data,
1084                                                      &reformat_id);
1085                 if (ret)
1086                         return ret;
1087
1088                 action->reformat.reformat_id = reformat_id;
1089                 action->reformat.reformat_size = data_sz;
1090                 return 0;
1091         }
1092         case DR_ACTION_TYP_TNL_L2_TO_L2:
1093         {
1094                 return 0;
1095         }
1096         case DR_ACTION_TYP_TNL_L3_TO_L2:
1097         {
1098                 /* Only Ethernet frame is supported, with VLAN (18) or without (14) */
1099                 if (data_sz != HDR_LEN_L2_ONLY && data_sz != HDR_LEN_L2_VLAN)
1100                         return -EINVAL;
1101
1102                 action->rewrite.chunk = mlx5dr_icm_alloc_chunk(dmn->action_icm_pool,
1103                                                                DR_CHUNK_SIZE_8);
1104                 if (!action->rewrite.chunk)
1105                         return -ENOMEM;
1106
1107                 action->rewrite.index = (action->rewrite.chunk->icm_addr -
1108                                          dmn->info.caps.hdr_modify_icm_addr) /
1109                                          ACTION_CACHE_LINE_SIZE;
1110
1111                 ret = dr_actions_l2_rewrite(dmn, action, data, data_sz);
1112                 if (ret) {
1113                         mlx5dr_icm_free_chunk(action->rewrite.chunk);
1114                         return ret;
1115                 }
1116                 return 0;
1117         }
1118         default:
1119                 mlx5dr_info(dmn, "Reformat type is not supported %d\n", action->action_type);
1120                 return -EINVAL;
1121         }
1122 }
1123
1124 struct mlx5dr_action *mlx5dr_action_create_pop_vlan(void)
1125 {
1126         return dr_action_create_generic(DR_ACTION_TYP_POP_VLAN);
1127 }
1128
1129 struct mlx5dr_action *mlx5dr_action_create_push_vlan(struct mlx5dr_domain *dmn,
1130                                                      __be32 vlan_hdr)
1131 {
1132         u32 vlan_hdr_h = ntohl(vlan_hdr);
1133         u16 ethertype = vlan_hdr_h >> 16;
1134         struct mlx5dr_action *action;
1135
1136         if (ethertype != SVLAN_ETHERTYPE && ethertype != CVLAN_ETHERTYPE) {
1137                 mlx5dr_dbg(dmn, "Invalid vlan ethertype\n");
1138                 return NULL;
1139         }
1140
1141         action = dr_action_create_generic(DR_ACTION_TYP_PUSH_VLAN);
1142         if (!action)
1143                 return NULL;
1144
1145         action->push_vlan.vlan_hdr = vlan_hdr_h;
1146         return action;
1147 }
1148
1149 struct mlx5dr_action *
1150 mlx5dr_action_create_packet_reformat(struct mlx5dr_domain *dmn,
1151                                      enum mlx5dr_action_reformat_type reformat_type,
1152                                      size_t data_sz,
1153                                      void *data)
1154 {
1155         enum mlx5dr_action_type action_type;
1156         struct mlx5dr_action *action;
1157         int ret;
1158
1159         refcount_inc(&dmn->refcount);
1160
1161         /* General checks */
1162         ret = dr_action_reformat_to_action_type(reformat_type, &action_type);
1163         if (ret) {
1164                 mlx5dr_dbg(dmn, "Invalid reformat_type provided\n");
1165                 goto dec_ref;
1166         }
1167
1168         ret = dr_action_verify_reformat_params(action_type, dmn, data_sz, data);
1169         if (ret)
1170                 goto dec_ref;
1171
1172         action = dr_action_create_generic(action_type);
1173         if (!action)
1174                 goto dec_ref;
1175
1176         action->reformat.dmn = dmn;
1177
1178         ret = dr_action_create_reformat_action(dmn,
1179                                                data_sz,
1180                                                data,
1181                                                action);
1182         if (ret) {
1183                 mlx5dr_dbg(dmn, "Failed creating reformat action %d\n", ret);
1184                 goto free_action;
1185         }
1186
1187         return action;
1188
1189 free_action:
1190         kfree(action);
1191 dec_ref:
1192         refcount_dec(&dmn->refcount);
1193         return NULL;
1194 }
1195
1196 static const struct dr_action_modify_field_conv *
1197 dr_action_modify_get_hw_info(u16 sw_field)
1198 {
1199         const struct dr_action_modify_field_conv *hw_action_info;
1200
1201         if (sw_field >= ARRAY_SIZE(dr_action_conv_arr))
1202                 goto not_found;
1203
1204         hw_action_info = &dr_action_conv_arr[sw_field];
1205         if (!hw_action_info->end && !hw_action_info->start)
1206                 goto not_found;
1207
1208         return hw_action_info;
1209
1210 not_found:
1211         return NULL;
1212 }
1213
1214 static int
1215 dr_action_modify_sw_to_hw(struct mlx5dr_domain *dmn,
1216                           __be64 *sw_action,
1217                           __be64 *hw_action,
1218                           const struct dr_action_modify_field_conv **ret_hw_info)
1219 {
1220         const struct dr_action_modify_field_conv *hw_action_info;
1221         u8 offset, length, max_length, action;
1222         u16 sw_field;
1223         u8 hw_opcode;
1224         u32 data;
1225
1226         /* Get SW modify action data */
1227         action = MLX5_GET(set_action_in, sw_action, action_type);
1228         length = MLX5_GET(set_action_in, sw_action, length);
1229         offset = MLX5_GET(set_action_in, sw_action, offset);
1230         sw_field = MLX5_GET(set_action_in, sw_action, field);
1231         data = MLX5_GET(set_action_in, sw_action, data);
1232
1233         /* Convert SW data to HW modify action format */
1234         hw_action_info = dr_action_modify_get_hw_info(sw_field);
1235         if (!hw_action_info) {
1236                 mlx5dr_dbg(dmn, "Modify action invalid field given\n");
1237                 return -EINVAL;
1238         }
1239
1240         max_length = hw_action_info->end - hw_action_info->start + 1;
1241
1242         switch (action) {
1243         case MLX5_ACTION_TYPE_SET:
1244                 hw_opcode = MLX5DR_ACTION_MDFY_HW_OP_SET;
1245                 /* PRM defines that length zero specific length of 32bits */
1246                 if (!length)
1247                         length = 32;
1248
1249                 if (length + offset > max_length) {
1250                         mlx5dr_dbg(dmn, "Modify action length + offset exceeds limit\n");
1251                         return -EINVAL;
1252                 }
1253                 break;
1254
1255         case MLX5_ACTION_TYPE_ADD:
1256                 hw_opcode = MLX5DR_ACTION_MDFY_HW_OP_ADD;
1257                 offset = 0;
1258                 length = max_length;
1259                 break;
1260
1261         default:
1262                 mlx5dr_info(dmn, "Unsupported action_type for modify action\n");
1263                 return -EOPNOTSUPP;
1264         }
1265
1266         MLX5_SET(dr_action_hw_set, hw_action, opcode, hw_opcode);
1267
1268         MLX5_SET(dr_action_hw_set, hw_action, destination_field_code,
1269                  hw_action_info->hw_field);
1270
1271         MLX5_SET(dr_action_hw_set, hw_action, destination_left_shifter,
1272                  hw_action_info->start + offset);
1273
1274         MLX5_SET(dr_action_hw_set, hw_action, destination_length,
1275                  length == 32 ? 0 : length);
1276
1277         MLX5_SET(dr_action_hw_set, hw_action, inline_data, data);
1278
1279         *ret_hw_info = hw_action_info;
1280
1281         return 0;
1282 }
1283
1284 static int
1285 dr_action_modify_check_field_limitation(struct mlx5dr_domain *dmn,
1286                                         const __be64 *sw_action)
1287 {
1288         u16 sw_field;
1289         u8 action;
1290
1291         sw_field = MLX5_GET(set_action_in, sw_action, field);
1292         action = MLX5_GET(set_action_in, sw_action, action_type);
1293
1294         /* Check if SW field is supported in current domain (RX/TX) */
1295         if (action == MLX5_ACTION_TYPE_SET) {
1296                 if (sw_field == MLX5_ACTION_IN_FIELD_METADATA_REG_A) {
1297                         if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_TX) {
1298                                 mlx5dr_dbg(dmn, "Unsupported field %d for RX/FDB set action\n",
1299                                            sw_field);
1300                                 return -EINVAL;
1301                         }
1302                 }
1303
1304                 if (sw_field == MLX5_ACTION_IN_FIELD_METADATA_REG_B) {
1305                         if (dmn->type != MLX5DR_DOMAIN_TYPE_NIC_RX) {
1306                                 mlx5dr_dbg(dmn, "Unsupported field %d for TX/FDB set action\n",
1307                                            sw_field);
1308                                 return -EINVAL;
1309                         }
1310                 }
1311         } else if (action == MLX5_ACTION_TYPE_ADD) {
1312                 if (sw_field != MLX5_ACTION_IN_FIELD_OUT_IP_TTL &&
1313                     sw_field != MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT &&
1314                     sw_field != MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM &&
1315                     sw_field != MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM) {
1316                         mlx5dr_dbg(dmn, "Unsupported field %d for add action\n", sw_field);
1317                         return -EINVAL;
1318                 }
1319         } else {
1320                 mlx5dr_info(dmn, "Unsupported action %d modify action\n", action);
1321                 return -EOPNOTSUPP;
1322         }
1323
1324         return 0;
1325 }
1326
1327 static bool
1328 dr_action_modify_check_is_ttl_modify(const u64 *sw_action)
1329 {
1330         u16 sw_field = MLX5_GET(set_action_in, sw_action, field);
1331
1332         return sw_field == MLX5_ACTION_IN_FIELD_OUT_IP_TTL;
1333 }
1334
1335 static int dr_actions_convert_modify_header(struct mlx5dr_domain *dmn,
1336                                             u32 max_hw_actions,
1337                                             u32 num_sw_actions,
1338                                             __be64 sw_actions[],
1339                                             __be64 hw_actions[],
1340                                             u32 *num_hw_actions,
1341                                             bool *modify_ttl)
1342 {
1343         const struct dr_action_modify_field_conv *hw_action_info;
1344         u16 hw_field = MLX5DR_ACTION_MDFY_HW_FLD_RESERVED;
1345         u32 l3_type = MLX5DR_ACTION_MDFY_HW_HDR_L3_NONE;
1346         u32 l4_type = MLX5DR_ACTION_MDFY_HW_HDR_L4_NONE;
1347         int ret, i, hw_idx = 0;
1348         __be64 *sw_action;
1349         __be64 hw_action;
1350
1351         *modify_ttl = false;
1352
1353         for (i = 0; i < num_sw_actions; i++) {
1354                 sw_action = &sw_actions[i];
1355
1356                 ret = dr_action_modify_check_field_limitation(dmn, sw_action);
1357                 if (ret)
1358                         return ret;
1359
1360                 if (!(*modify_ttl))
1361                         *modify_ttl = dr_action_modify_check_is_ttl_modify(sw_action);
1362
1363                 /* Convert SW action to HW action */
1364                 ret = dr_action_modify_sw_to_hw(dmn,
1365                                                 sw_action,
1366                                                 &hw_action,
1367                                                 &hw_action_info);
1368                 if (ret)
1369                         return ret;
1370
1371                 /* Due to a HW limitation we cannot modify 2 different L3 types */
1372                 if (l3_type && hw_action_info->l3_type &&
1373                     hw_action_info->l3_type != l3_type) {
1374                         mlx5dr_dbg(dmn, "Action list can't support two different L3 types\n");
1375                         return -EINVAL;
1376                 }
1377                 if (hw_action_info->l3_type)
1378                         l3_type = hw_action_info->l3_type;
1379
1380                 /* Due to a HW limitation we cannot modify two different L4 types */
1381                 if (l4_type && hw_action_info->l4_type &&
1382                     hw_action_info->l4_type != l4_type) {
1383                         mlx5dr_dbg(dmn, "Action list can't support two different L4 types\n");
1384                         return -EINVAL;
1385                 }
1386                 if (hw_action_info->l4_type)
1387                         l4_type = hw_action_info->l4_type;
1388
1389                 /* HW reads and executes two actions at once this means we
1390                  * need to create a gap if two actions access the same field
1391                  */
1392                 if ((hw_idx % 2) && hw_field == hw_action_info->hw_field) {
1393                         /* Check if after gap insertion the total number of HW
1394                          * modify actions doesn't exceeds the limit
1395                          */
1396                         hw_idx++;
1397                         if ((num_sw_actions + hw_idx - i) >= max_hw_actions) {
1398                                 mlx5dr_dbg(dmn, "Modify header action number exceeds HW limit\n");
1399                                 return -EINVAL;
1400                         }
1401                 }
1402                 hw_field = hw_action_info->hw_field;
1403
1404                 hw_actions[hw_idx] = hw_action;
1405                 hw_idx++;
1406         }
1407
1408         *num_hw_actions = hw_idx;
1409
1410         return 0;
1411 }
1412
1413 static int dr_action_create_modify_action(struct mlx5dr_domain *dmn,
1414                                           size_t actions_sz,
1415                                           __be64 actions[],
1416                                           struct mlx5dr_action *action)
1417 {
1418         struct mlx5dr_icm_chunk *chunk;
1419         u32 max_hw_actions;
1420         u32 num_hw_actions;
1421         u32 num_sw_actions;
1422         __be64 *hw_actions;
1423         bool modify_ttl;
1424         int ret;
1425
1426         num_sw_actions = actions_sz / DR_MODIFY_ACTION_SIZE;
1427         max_hw_actions = mlx5dr_icm_pool_chunk_size_to_entries(DR_CHUNK_SIZE_16);
1428
1429         if (num_sw_actions > max_hw_actions) {
1430                 mlx5dr_dbg(dmn, "Max number of actions %d exceeds limit %d\n",
1431                            num_sw_actions, max_hw_actions);
1432                 return -EINVAL;
1433         }
1434
1435         chunk = mlx5dr_icm_alloc_chunk(dmn->action_icm_pool, DR_CHUNK_SIZE_16);
1436         if (!chunk)
1437                 return -ENOMEM;
1438
1439         hw_actions = kcalloc(1, max_hw_actions * DR_MODIFY_ACTION_SIZE, GFP_KERNEL);
1440         if (!hw_actions) {
1441                 ret = -ENOMEM;
1442                 goto free_chunk;
1443         }
1444
1445         ret = dr_actions_convert_modify_header(dmn,
1446                                                max_hw_actions,
1447                                                num_sw_actions,
1448                                                actions,
1449                                                hw_actions,
1450                                                &num_hw_actions,
1451                                                &modify_ttl);
1452         if (ret)
1453                 goto free_hw_actions;
1454
1455         action->rewrite.chunk = chunk;
1456         action->rewrite.modify_ttl = modify_ttl;
1457         action->rewrite.data = (u8 *)hw_actions;
1458         action->rewrite.num_of_actions = num_hw_actions;
1459         action->rewrite.index = (chunk->icm_addr -
1460                                  dmn->info.caps.hdr_modify_icm_addr) /
1461                                  ACTION_CACHE_LINE_SIZE;
1462
1463         ret = mlx5dr_send_postsend_action(dmn, action);
1464         if (ret)
1465                 goto free_hw_actions;
1466
1467         return 0;
1468
1469 free_hw_actions:
1470         kfree(hw_actions);
1471 free_chunk:
1472         mlx5dr_icm_free_chunk(chunk);
1473         return ret;
1474 }
1475
1476 struct mlx5dr_action *
1477 mlx5dr_action_create_modify_header(struct mlx5dr_domain *dmn,
1478                                    u32 flags,
1479                                    size_t actions_sz,
1480                                    __be64 actions[])
1481 {
1482         struct mlx5dr_action *action;
1483         int ret = 0;
1484
1485         refcount_inc(&dmn->refcount);
1486
1487         if (actions_sz % DR_MODIFY_ACTION_SIZE) {
1488                 mlx5dr_dbg(dmn, "Invalid modify actions size provided\n");
1489                 goto dec_ref;
1490         }
1491
1492         action = dr_action_create_generic(DR_ACTION_TYP_MODIFY_HDR);
1493         if (!action)
1494                 goto dec_ref;
1495
1496         action->rewrite.dmn = dmn;
1497
1498         ret = dr_action_create_modify_action(dmn,
1499                                              actions_sz,
1500                                              actions,
1501                                              action);
1502         if (ret) {
1503                 mlx5dr_dbg(dmn, "Failed creating modify header action %d\n", ret);
1504                 goto free_action;
1505         }
1506
1507         return action;
1508
1509 free_action:
1510         kfree(action);
1511 dec_ref:
1512         refcount_dec(&dmn->refcount);
1513         return NULL;
1514 }
1515
1516 struct mlx5dr_action *
1517 mlx5dr_action_create_dest_vport(struct mlx5dr_domain *dmn,
1518                                 u32 vport, u8 vhca_id_valid,
1519                                 u16 vhca_id)
1520 {
1521         struct mlx5dr_cmd_vport_cap *vport_cap;
1522         struct mlx5dr_domain *vport_dmn;
1523         struct mlx5dr_action *action;
1524         u8 peer_vport;
1525
1526         peer_vport = vhca_id_valid && (vhca_id != dmn->info.caps.gvmi);
1527         vport_dmn = peer_vport ? dmn->peer_dmn : dmn;
1528         if (!vport_dmn) {
1529                 mlx5dr_dbg(dmn, "No peer vport domain for given vhca_id\n");
1530                 return NULL;
1531         }
1532
1533         if (vport_dmn->type != MLX5DR_DOMAIN_TYPE_FDB) {
1534                 mlx5dr_dbg(dmn, "Domain doesn't support vport actions\n");
1535                 return NULL;
1536         }
1537
1538         vport_cap = mlx5dr_get_vport_cap(&vport_dmn->info.caps, vport);
1539         if (!vport_cap) {
1540                 mlx5dr_dbg(dmn, "Failed to get vport %d caps\n", vport);
1541                 return NULL;
1542         }
1543
1544         action = dr_action_create_generic(DR_ACTION_TYP_VPORT);
1545         if (!action)
1546                 return NULL;
1547
1548         action->vport.dmn = vport_dmn;
1549         action->vport.caps = vport_cap;
1550
1551         return action;
1552 }
1553
1554 int mlx5dr_action_destroy(struct mlx5dr_action *action)
1555 {
1556         if (refcount_read(&action->refcount) > 1)
1557                 return -EBUSY;
1558
1559         switch (action->action_type) {
1560         case DR_ACTION_TYP_FT:
1561                 if (!action->dest_tbl.is_fw_tbl)
1562                         refcount_dec(&action->dest_tbl.tbl->refcount);
1563                 break;
1564         case DR_ACTION_TYP_TNL_L2_TO_L2:
1565                 refcount_dec(&action->reformat.dmn->refcount);
1566                 break;
1567         case DR_ACTION_TYP_TNL_L3_TO_L2:
1568                 mlx5dr_icm_free_chunk(action->rewrite.chunk);
1569                 refcount_dec(&action->reformat.dmn->refcount);
1570                 break;
1571         case DR_ACTION_TYP_L2_TO_TNL_L2:
1572         case DR_ACTION_TYP_L2_TO_TNL_L3:
1573                 mlx5dr_cmd_destroy_reformat_ctx((action->reformat.dmn)->mdev,
1574                                                 action->reformat.reformat_id);
1575                 refcount_dec(&action->reformat.dmn->refcount);
1576                 break;
1577         case DR_ACTION_TYP_MODIFY_HDR:
1578                 mlx5dr_icm_free_chunk(action->rewrite.chunk);
1579                 kfree(action->rewrite.data);
1580                 refcount_dec(&action->rewrite.dmn->refcount);
1581                 break;
1582         default:
1583                 break;
1584         }
1585
1586         kfree(action);
1587         return 0;
1588 }