drivers/net/ethernet/mellanox/mlx5/core/fpga/cmd.c

   1 /*
   2  * Copyright (c) 2017, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/etherdevice.h>
  34 #include <linux/mlx5/cmd.h>
  35 #include <linux/mlx5/driver.h>
  36 #include <linux/mlx5/device.h>
  37
  38 #include "mlx5_core.h"
  39 #include "fpga/cmd.h"
  40
  41 #define MLX5_FPGA_ACCESS_REG_SZ (MLX5_ST_SZ_DW(fpga_access_reg) + \
  42                                  MLX5_FPGA_ACCESS_REG_SIZE_MAX)
  43
  44 int mlx5_fpga_access_reg(struct mlx5_core_dev *dev, u8 size, u64 addr,
  45                          void *buf, bool write)
  46 {
  47         u32 in[MLX5_FPGA_ACCESS_REG_SZ] = {0};
  48         u32 out[MLX5_FPGA_ACCESS_REG_SZ];
  49         int err;
  50
  51         if (size & 3)
  52                 return -EINVAL;
  53         if (addr & 3)
  54                 return -EINVAL;
  55         if (size > MLX5_FPGA_ACCESS_REG_SIZE_MAX)
  56                 return -EINVAL;
  57
  58         MLX5_SET(fpga_access_reg, in, size, size);
  59         MLX5_SET64(fpga_access_reg, in, address, addr);
  60         if (write)
  61                 memcpy(MLX5_ADDR_OF(fpga_access_reg, in, data), buf, size);
  62
  63         err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
  64                                    MLX5_REG_FPGA_ACCESS_REG, 0, write);
  65         if (err)
  66                 return err;
  67
  68         if (!write)
  69                 memcpy(buf, MLX5_ADDR_OF(fpga_access_reg, out, data), size);
  70
  71         return 0;
  72 }
  73
  74 int mlx5_fpga_caps(struct mlx5_core_dev *dev)
  75 {
  76         u32 in[MLX5_ST_SZ_DW(fpga_cap)] = {0};
  77
  78         return mlx5_core_access_reg(dev, in, sizeof(in), dev->caps.fpga,
  79                                     MLX5_ST_SZ_BYTES(fpga_cap),
  80                                     MLX5_REG_FPGA_CAP, 0, 0);
  81 }
  82
  83 int mlx5_fpga_ctrl_op(struct mlx5_core_dev *dev, u8 op)
  84 {
  85         u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0};
  86         u32 out[MLX5_ST_SZ_DW(fpga_ctrl)];
  87
  88         MLX5_SET(fpga_ctrl, in, operation, op);
  89
  90         return mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
  91                                     MLX5_REG_FPGA_CTRL, 0, true);
  92 }
  93
  94 int mlx5_fpga_sbu_caps(struct mlx5_core_dev *dev, void *caps, int size)
  95 {
  96         unsigned int cap_size = MLX5_CAP_FPGA(dev, sandbox_extended_caps_len);
  97         u64 addr = MLX5_CAP64_FPGA(dev, sandbox_extended_caps_addr);
  98         unsigned int read;
  99         int ret = 0;
 100
 101         if (cap_size > size) {
 102                 mlx5_core_warn(dev, "Not enough buffer %u for FPGA SBU caps %u",
 103                                size, cap_size);
 104                 return -EINVAL;
 105         }
 106
 107         while (cap_size > 0) {
 108                 read = min_t(unsigned int, cap_size,
 109                              MLX5_FPGA_ACCESS_REG_SIZE_MAX);
 110
 111                 ret = mlx5_fpga_access_reg(dev, read, addr, caps, false);
 112                 if (ret) {
 113                         mlx5_core_warn(dev, "Error reading FPGA SBU caps %u bytes at address 0x%llx: %d",
 114                                        read, addr, ret);
 115                         return ret;
 116                 }
 117
 118                 cap_size -= read;
 119                 addr += read;
 120                 caps += read;
 121         }
 122
 123         return ret;
 124 }
 125
 126 int mlx5_fpga_query(struct mlx5_core_dev *dev, struct mlx5_fpga_query *query)
 127 {
 128         u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0};
 129         u32 out[MLX5_ST_SZ_DW(fpga_ctrl)];
 130         int err;
 131
 132         err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
 133                                    MLX5_REG_FPGA_CTRL, 0, false);
 134         if (err)
 135                 return err;
 136
 137         query->status = MLX5_GET(fpga_ctrl, out, status);
 138         query->admin_image = MLX5_GET(fpga_ctrl, out, flash_select_admin);
 139         query->oper_image = MLX5_GET(fpga_ctrl, out, flash_select_oper);
 140         return 0;
 141 }
 142
 143 int mlx5_fpga_create_qp(struct mlx5_core_dev *dev, void *fpga_qpc,
 144                         u32 *fpga_qpn)
 145 {
 146         u32 in[MLX5_ST_SZ_DW(fpga_create_qp_in)] = {0};
 147         u32 out[MLX5_ST_SZ_DW(fpga_create_qp_out)];
 148         int ret;
 149
 150         MLX5_SET(fpga_create_qp_in, in, opcode, MLX5_CMD_OP_FPGA_CREATE_QP);
 151         memcpy(MLX5_ADDR_OF(fpga_create_qp_in, in, fpga_qpc), fpga_qpc,
 152                MLX5_FLD_SZ_BYTES(fpga_create_qp_in, fpga_qpc));
 153
 154         ret = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
 155         if (ret)
 156                 return ret;
 157
 158         memcpy(fpga_qpc, MLX5_ADDR_OF(fpga_create_qp_out, out, fpga_qpc),
 159                MLX5_FLD_SZ_BYTES(fpga_create_qp_out, fpga_qpc));
 160         *fpga_qpn = MLX5_GET(fpga_create_qp_out, out, fpga_qpn);
 161         return ret;
 162 }
 163
 164 int mlx5_fpga_modify_qp(struct mlx5_core_dev *dev, u32 fpga_qpn,
 165                         enum mlx5_fpga_qpc_field_select fields,
 166                         void *fpga_qpc)
 167 {
 168         u32 in[MLX5_ST_SZ_DW(fpga_modify_qp_in)] = {0};
 169         u32 out[MLX5_ST_SZ_DW(fpga_modify_qp_out)];
 170
 171         MLX5_SET(fpga_modify_qp_in, in, opcode, MLX5_CMD_OP_FPGA_MODIFY_QP);
 172         MLX5_SET(fpga_modify_qp_in, in, field_select, fields);
 173         MLX5_SET(fpga_modify_qp_in, in, fpga_qpn, fpga_qpn);
 174         memcpy(MLX5_ADDR_OF(fpga_modify_qp_in, in, fpga_qpc), fpga_qpc,
 175                MLX5_FLD_SZ_BYTES(fpga_modify_qp_in, fpga_qpc));
 176
 177         return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
 178 }
 179
 180 int mlx5_fpga_query_qp(struct mlx5_core_dev *dev,
 181                        u32 fpga_qpn, void *fpga_qpc)
 182 {
 183         u32 in[MLX5_ST_SZ_DW(fpga_query_qp_in)] = {0};
 184         u32 out[MLX5_ST_SZ_DW(fpga_query_qp_out)];
 185         int ret;
 186
 187         MLX5_SET(fpga_query_qp_in, in, opcode, MLX5_CMD_OP_FPGA_QUERY_QP);
 188         MLX5_SET(fpga_query_qp_in, in, fpga_qpn, fpga_qpn);
 189
 190         ret = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
 191         if (ret)
 192                 return ret;
 193
 194         memcpy(fpga_qpc, MLX5_ADDR_OF(fpga_query_qp_out, out, fpga_qpc),
 195                MLX5_FLD_SZ_BYTES(fpga_query_qp_out, fpga_qpc));
 196         return ret;
 197 }
 198
 199 int mlx5_fpga_destroy_qp(struct mlx5_core_dev *dev, u32 fpga_qpn)
 200 {
 201         u32 in[MLX5_ST_SZ_DW(fpga_destroy_qp_in)] = {0};
 202         u32 out[MLX5_ST_SZ_DW(fpga_destroy_qp_out)];
 203
 204         MLX5_SET(fpga_destroy_qp_in, in, opcode, MLX5_CMD_OP_FPGA_DESTROY_QP);
 205         MLX5_SET(fpga_destroy_qp_in, in, fpga_qpn, fpga_qpn);
 206
 207         return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
 208 }
 209
 210 int mlx5_fpga_query_qp_counters(struct mlx5_core_dev *dev, u32 fpga_qpn,
 211                                 bool clear, struct mlx5_fpga_qp_counters *data)
 212 {
 213         u32 in[MLX5_ST_SZ_DW(fpga_query_qp_counters_in)] = {0};
 214         u32 out[MLX5_ST_SZ_DW(fpga_query_qp_counters_out)];
 215         int ret;
 216
 217         MLX5_SET(fpga_query_qp_counters_in, in, opcode,
 218                  MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS);
 219         MLX5_SET(fpga_query_qp_counters_in, in, clear, clear);
 220         MLX5_SET(fpga_query_qp_counters_in, in, fpga_qpn, fpga_qpn);
 221
 222         ret = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
 223         if (ret)
 224                 return ret;
 225
 226         data->rx_ack_packets = MLX5_GET64(fpga_query_qp_counters_out, out,
 227                                           rx_ack_packets);
 228         data->rx_send_packets = MLX5_GET64(fpga_query_qp_counters_out, out,
 229                                            rx_send_packets);
 230         data->tx_ack_packets = MLX5_GET64(fpga_query_qp_counters_out, out,
 231                                           tx_ack_packets);
 232         data->tx_send_packets = MLX5_GET64(fpga_query_qp_counters_out, out,
 233                                            tx_send_packets);
 234         data->rx_total_drop = MLX5_GET64(fpga_query_qp_counters_out, out,
 235                                          rx_total_drop);
 236
 237         return ret;
 238 }