2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/interrupt.h>
34 #include <linux/notifier.h>
35 #include <linux/module.h>
36 #include <linux/mlx5/driver.h>
37 #include <linux/mlx5/vport.h>
38 #include <linux/mlx5/eq.h>
39 #include <linux/mlx5/cmd.h>
40 #ifdef CONFIG_RFS_ACCEL
41 #include <linux/cpu_rmap.h>
43 #include "mlx5_core.h"
45 #include "fpga/core.h"
47 #include "lib/clock.h"
48 #include "diag/fw_tracer.h"
51 MLX5_EQE_OWNER_INIT_VAL = 0x1,
55 MLX5_EQ_STATE_ARMED = 0x9,
56 MLX5_EQ_STATE_FIRED = 0xa,
57 MLX5_EQ_STATE_ALWAYS_ARMED = 0xb,
61 MLX5_EQ_DOORBEL_OFFSET = 0x40,
64 /* budget must be smaller than MLX5_NUM_SPARE_EQE to guarantee that we update
65 * the ci before we polled all the entries in the EQ. MLX5_NUM_SPARE_EQE is
66 * used to set the EQ size, budget must be smaller than the EQ size.
69 MLX5_EQ_POLLING_BUDGET = 128,
72 static_assert(MLX5_EQ_POLLING_BUDGET <= MLX5_NUM_SPARE_EQE);
74 struct mlx5_eq_table {
75 struct list_head comp_eqs_list;
76 struct mlx5_eq_async pages_eq;
77 struct mlx5_eq_async cmd_eq;
78 struct mlx5_eq_async async_eq;
80 struct atomic_notifier_head nh[MLX5_EVENT_TYPE_MAX];
82 /* Since CQ DB is stored in async_eq */
83 struct mlx5_nb cq_err_nb;
85 struct mutex lock; /* sync async eqs creations */
87 struct mlx5_irq_table *irq_table;
90 #define MLX5_ASYNC_EVENT_MASK ((1ull << MLX5_EVENT_TYPE_PATH_MIG) | \
91 (1ull << MLX5_EVENT_TYPE_COMM_EST) | \
92 (1ull << MLX5_EVENT_TYPE_SQ_DRAINED) | \
93 (1ull << MLX5_EVENT_TYPE_CQ_ERROR) | \
94 (1ull << MLX5_EVENT_TYPE_WQ_CATAS_ERROR) | \
95 (1ull << MLX5_EVENT_TYPE_PATH_MIG_FAILED) | \
96 (1ull << MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
97 (1ull << MLX5_EVENT_TYPE_WQ_ACCESS_ERROR) | \
98 (1ull << MLX5_EVENT_TYPE_PORT_CHANGE) | \
99 (1ull << MLX5_EVENT_TYPE_SRQ_CATAS_ERROR) | \
100 (1ull << MLX5_EVENT_TYPE_SRQ_LAST_WQE) | \
101 (1ull << MLX5_EVENT_TYPE_SRQ_RQ_LIMIT))
103 static int mlx5_cmd_destroy_eq(struct mlx5_core_dev *dev, u8 eqn)
105 u32 out[MLX5_ST_SZ_DW(destroy_eq_out)] = {0};
106 u32 in[MLX5_ST_SZ_DW(destroy_eq_in)] = {0};
108 MLX5_SET(destroy_eq_in, in, opcode, MLX5_CMD_OP_DESTROY_EQ);
109 MLX5_SET(destroy_eq_in, in, eq_number, eqn);
110 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
113 /* caller must eventually call mlx5_cq_put on the returned cq */
114 static struct mlx5_core_cq *mlx5_eq_cq_get(struct mlx5_eq *eq, u32 cqn)
116 struct mlx5_cq_table *table = &eq->cq_table;
117 struct mlx5_core_cq *cq = NULL;
120 cq = radix_tree_lookup(&table->tree, cqn);
128 static int mlx5_eq_comp_int(struct notifier_block *nb,
129 __always_unused unsigned long action,
130 __always_unused void *data)
132 struct mlx5_eq_comp *eq_comp =
133 container_of(nb, struct mlx5_eq_comp, irq_nb);
134 struct mlx5_eq *eq = &eq_comp->core;
135 struct mlx5_eqe *eqe;
139 eqe = next_eqe_sw(eq);
144 struct mlx5_core_cq *cq;
146 /* Make sure we read EQ entry contents after we've
147 * checked the ownership bit.
150 /* Assume (eqe->type) is always MLX5_EVENT_TYPE_COMP */
151 cqn = be32_to_cpu(eqe->data.comp.cqn) & 0xffffff;
153 cq = mlx5_eq_cq_get(eq, cqn);
159 mlx5_core_warn(eq->dev, "Completion event for bogus CQ 0x%x\n", cqn);
164 } while ((++num_eqes < MLX5_EQ_POLLING_BUDGET) && (eqe = next_eqe_sw(eq)));
170 tasklet_schedule(&eq_comp->tasklet_ctx.task);
175 /* Some architectures don't latch interrupts when they are disabled, so using
176 * mlx5_eq_poll_irq_disabled could end up losing interrupts while trying to
177 * avoid losing them. It is not recommended to use it, unless this is the last
180 u32 mlx5_eq_poll_irq_disabled(struct mlx5_eq_comp *eq)
184 disable_irq(eq->core.irqn);
185 count_eqe = eq->core.cons_index;
186 mlx5_eq_comp_int(&eq->irq_nb, 0, NULL);
187 count_eqe = eq->core.cons_index - count_eqe;
188 enable_irq(eq->core.irqn);
193 static int mlx5_eq_async_int(struct notifier_block *nb,
194 unsigned long action, void *data)
196 struct mlx5_eq_async *eq_async =
197 container_of(nb, struct mlx5_eq_async, irq_nb);
198 struct mlx5_eq *eq = &eq_async->core;
199 struct mlx5_eq_table *eqt;
200 struct mlx5_core_dev *dev;
201 struct mlx5_eqe *eqe;
205 eqt = dev->priv.eq_table;
207 eqe = next_eqe_sw(eq);
213 * Make sure we read EQ entry contents after we've
214 * checked the ownership bit.
218 atomic_notifier_call_chain(&eqt->nh[eqe->type], eqe->type, eqe);
219 atomic_notifier_call_chain(&eqt->nh[MLX5_EVENT_TYPE_NOTIFY_ANY], eqe->type, eqe);
223 } while ((++num_eqes < MLX5_EQ_POLLING_BUDGET) && (eqe = next_eqe_sw(eq)));
231 static void init_eq_buf(struct mlx5_eq *eq)
233 struct mlx5_eqe *eqe;
236 for (i = 0; i < eq->nent; i++) {
237 eqe = get_eqe(eq, i);
238 eqe->owner = MLX5_EQE_OWNER_INIT_VAL;
243 create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
244 struct mlx5_eq_param *param)
246 struct mlx5_cq_table *cq_table = &eq->cq_table;
247 u32 out[MLX5_ST_SZ_DW(create_eq_out)] = {0};
248 struct mlx5_priv *priv = &dev->priv;
249 u8 vecidx = param->irq_index;
258 memset(cq_table, 0, sizeof(*cq_table));
259 spin_lock_init(&cq_table->lock);
260 INIT_RADIX_TREE(&cq_table->tree, GFP_ATOMIC);
262 eq->nent = roundup_pow_of_two(param->nent + MLX5_NUM_SPARE_EQE);
264 err = mlx5_buf_alloc(dev, eq->nent * MLX5_EQE_SIZE, &eq->buf);
270 inlen = MLX5_ST_SZ_BYTES(create_eq_in) +
271 MLX5_FLD_SZ_BYTES(create_eq_in, pas[0]) * eq->buf.npages;
273 in = kvzalloc(inlen, GFP_KERNEL);
279 pas = (__be64 *)MLX5_ADDR_OF(create_eq_in, in, pas);
280 mlx5_fill_page_array(&eq->buf, pas);
282 MLX5_SET(create_eq_in, in, opcode, MLX5_CMD_OP_CREATE_EQ);
283 if (!param->mask[0] && MLX5_CAP_GEN(dev, log_max_uctx))
284 MLX5_SET(create_eq_in, in, uid, MLX5_SHARED_RESOURCE_UID);
286 for (i = 0; i < 4; i++)
287 MLX5_ARRAY_SET64(create_eq_in, in, event_bitmask, i,
290 eqc = MLX5_ADDR_OF(create_eq_in, in, eq_context_entry);
291 MLX5_SET(eqc, eqc, log_eq_size, ilog2(eq->nent));
292 MLX5_SET(eqc, eqc, uar_page, priv->uar->index);
293 MLX5_SET(eqc, eqc, intr, vecidx);
294 MLX5_SET(eqc, eqc, log_page_size,
295 eq->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
297 err = mlx5_cmd_exec(dev, in, inlen, out, sizeof(out));
302 eq->eqn = MLX5_GET(create_eq_out, out, eq_number);
303 eq->irqn = pci_irq_vector(dev->pdev, vecidx);
305 eq->doorbell = priv->uar->map + MLX5_EQ_DOORBEL_OFFSET;
307 err = mlx5_debug_eq_add(dev, eq);
315 mlx5_cmd_destroy_eq(dev, eq->eqn);
321 mlx5_buf_free(dev, &eq->buf);
326 * mlx5_eq_enable - Enable EQ for receiving EQEs
327 * @dev : Device which owns the eq
329 * @nb : Notifier call block
331 * Must be called after EQ is created in device.
333 * @return: 0 if no error
335 int mlx5_eq_enable(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
336 struct notifier_block *nb)
338 struct mlx5_eq_table *eq_table = dev->priv.eq_table;
341 err = mlx5_irq_attach_nb(eq_table->irq_table, eq->vecidx, nb);
347 EXPORT_SYMBOL(mlx5_eq_enable);
350 * mlx5_eq_disable - Disable EQ for receiving EQEs
351 * @dev : Device which owns the eq
352 * @eq : EQ to disable
353 * @nb : Notifier call block
355 * Must be called before EQ is destroyed.
357 void mlx5_eq_disable(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
358 struct notifier_block *nb)
360 struct mlx5_eq_table *eq_table = dev->priv.eq_table;
362 mlx5_irq_detach_nb(eq_table->irq_table, eq->vecidx, nb);
364 EXPORT_SYMBOL(mlx5_eq_disable);
366 static int destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
370 mlx5_debug_eq_remove(dev, eq);
372 err = mlx5_cmd_destroy_eq(dev, eq->eqn);
374 mlx5_core_warn(dev, "failed to destroy a previously created eq: eqn %d\n",
376 synchronize_irq(eq->irqn);
378 mlx5_buf_free(dev, &eq->buf);
383 int mlx5_eq_add_cq(struct mlx5_eq *eq, struct mlx5_core_cq *cq)
385 struct mlx5_cq_table *table = &eq->cq_table;
388 spin_lock(&table->lock);
389 err = radix_tree_insert(&table->tree, cq->cqn, cq);
390 spin_unlock(&table->lock);
395 void mlx5_eq_del_cq(struct mlx5_eq *eq, struct mlx5_core_cq *cq)
397 struct mlx5_cq_table *table = &eq->cq_table;
398 struct mlx5_core_cq *tmp;
400 spin_lock(&table->lock);
401 tmp = radix_tree_delete(&table->tree, cq->cqn);
402 spin_unlock(&table->lock);
405 mlx5_core_dbg(eq->dev, "cq 0x%x not found in eq 0x%x tree\n",
411 mlx5_core_dbg(eq->dev, "corruption on cqn 0x%x in eq 0x%x\n",
415 int mlx5_eq_table_init(struct mlx5_core_dev *dev)
417 struct mlx5_eq_table *eq_table;
420 eq_table = kvzalloc(sizeof(*eq_table), GFP_KERNEL);
424 dev->priv.eq_table = eq_table;
426 mlx5_eq_debugfs_init(dev);
428 mutex_init(&eq_table->lock);
429 for (i = 0; i < MLX5_EVENT_TYPE_MAX; i++)
430 ATOMIC_INIT_NOTIFIER_HEAD(&eq_table->nh[i]);
432 eq_table->irq_table = dev->priv.irq_table;
436 void mlx5_eq_table_cleanup(struct mlx5_core_dev *dev)
438 mlx5_eq_debugfs_cleanup(dev);
439 kvfree(dev->priv.eq_table);
444 static int create_async_eq(struct mlx5_core_dev *dev,
445 struct mlx5_eq *eq, struct mlx5_eq_param *param)
447 struct mlx5_eq_table *eq_table = dev->priv.eq_table;
450 mutex_lock(&eq_table->lock);
451 /* Async EQs must share irq index 0 */
452 if (param->irq_index != 0) {
457 err = create_map_eq(dev, eq, param);
459 mutex_unlock(&eq_table->lock);
463 static int destroy_async_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
465 struct mlx5_eq_table *eq_table = dev->priv.eq_table;
468 mutex_lock(&eq_table->lock);
469 err = destroy_unmap_eq(dev, eq);
470 mutex_unlock(&eq_table->lock);
474 static int cq_err_event_notifier(struct notifier_block *nb,
475 unsigned long type, void *data)
477 struct mlx5_eq_table *eqt;
478 struct mlx5_core_cq *cq;
479 struct mlx5_eqe *eqe;
483 /* type == MLX5_EVENT_TYPE_CQ_ERROR */
485 eqt = mlx5_nb_cof(nb, struct mlx5_eq_table, cq_err_nb);
486 eq = &eqt->async_eq.core;
489 cqn = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff;
490 mlx5_core_warn(eq->dev, "CQ error on CQN 0x%x, syndrome 0x%x\n",
491 cqn, eqe->data.cq_err.syndrome);
493 cq = mlx5_eq_cq_get(eq, cqn);
495 mlx5_core_warn(eq->dev, "Async event for bogus CQ 0x%x\n", cqn);
507 static void gather_user_async_events(struct mlx5_core_dev *dev, u64 mask[4])
509 __be64 *user_unaffiliated_events;
510 __be64 *user_affiliated_events;
513 user_affiliated_events =
514 MLX5_CAP_DEV_EVENT(dev, user_affiliated_events);
515 user_unaffiliated_events =
516 MLX5_CAP_DEV_EVENT(dev, user_unaffiliated_events);
518 for (i = 0; i < 4; i++)
519 mask[i] |= be64_to_cpu(user_affiliated_events[i] |
520 user_unaffiliated_events[i]);
523 static void gather_async_events_mask(struct mlx5_core_dev *dev, u64 mask[4])
525 u64 async_event_mask = MLX5_ASYNC_EVENT_MASK;
527 if (MLX5_VPORT_MANAGER(dev))
528 async_event_mask |= (1ull << MLX5_EVENT_TYPE_NIC_VPORT_CHANGE);
530 if (MLX5_CAP_GEN(dev, general_notification_event))
531 async_event_mask |= (1ull << MLX5_EVENT_TYPE_GENERAL_EVENT);
533 if (MLX5_CAP_GEN(dev, port_module_event))
534 async_event_mask |= (1ull << MLX5_EVENT_TYPE_PORT_MODULE_EVENT);
536 mlx5_core_dbg(dev, "port_module_event is not set\n");
538 if (MLX5_PPS_CAP(dev))
539 async_event_mask |= (1ull << MLX5_EVENT_TYPE_PPS_EVENT);
541 if (MLX5_CAP_GEN(dev, fpga))
542 async_event_mask |= (1ull << MLX5_EVENT_TYPE_FPGA_ERROR) |
543 (1ull << MLX5_EVENT_TYPE_FPGA_QP_ERROR);
544 if (MLX5_CAP_GEN_MAX(dev, dct))
545 async_event_mask |= (1ull << MLX5_EVENT_TYPE_DCT_DRAINED);
547 if (MLX5_CAP_GEN(dev, temp_warn_event))
548 async_event_mask |= (1ull << MLX5_EVENT_TYPE_TEMP_WARN_EVENT);
550 if (MLX5_CAP_MCAM_REG(dev, tracer_registers))
551 async_event_mask |= (1ull << MLX5_EVENT_TYPE_DEVICE_TRACER);
553 if (MLX5_CAP_GEN(dev, max_num_of_monitor_counters))
554 async_event_mask |= (1ull << MLX5_EVENT_TYPE_MONITOR_COUNTER);
556 if (mlx5_eswitch_is_funcs_handler(dev))
558 (1ull << MLX5_EVENT_TYPE_ESW_FUNCTIONS_CHANGED);
560 mask[0] = async_event_mask;
562 if (MLX5_CAP_GEN(dev, event_cap))
563 gather_user_async_events(dev, mask);
566 static int create_async_eqs(struct mlx5_core_dev *dev)
568 struct mlx5_eq_table *table = dev->priv.eq_table;
569 struct mlx5_eq_param param = {};
572 MLX5_NB_INIT(&table->cq_err_nb, cq_err_event_notifier, CQ_ERROR);
573 mlx5_eq_notifier_register(dev, &table->cq_err_nb);
575 table->cmd_eq.irq_nb.notifier_call = mlx5_eq_async_int;
576 param = (struct mlx5_eq_param) {
578 .nent = MLX5_NUM_CMD_EQE,
581 param.mask[0] = 1ull << MLX5_EVENT_TYPE_CMD;
582 err = create_async_eq(dev, &table->cmd_eq.core, ¶m);
584 mlx5_core_warn(dev, "failed to create cmd EQ %d\n", err);
587 err = mlx5_eq_enable(dev, &table->cmd_eq.core, &table->cmd_eq.irq_nb);
589 mlx5_core_warn(dev, "failed to enable cmd EQ %d\n", err);
592 mlx5_cmd_use_events(dev);
594 table->async_eq.irq_nb.notifier_call = mlx5_eq_async_int;
595 param = (struct mlx5_eq_param) {
597 .nent = MLX5_NUM_ASYNC_EQE,
600 gather_async_events_mask(dev, param.mask);
601 err = create_async_eq(dev, &table->async_eq.core, ¶m);
603 mlx5_core_warn(dev, "failed to create async EQ %d\n", err);
606 err = mlx5_eq_enable(dev, &table->async_eq.core,
607 &table->async_eq.irq_nb);
609 mlx5_core_warn(dev, "failed to enable async EQ %d\n", err);
613 table->pages_eq.irq_nb.notifier_call = mlx5_eq_async_int;
614 param = (struct mlx5_eq_param) {
616 .nent = /* TODO: sriov max_vf + */ 1,
619 param.mask[0] = 1ull << MLX5_EVENT_TYPE_PAGE_REQUEST;
620 err = create_async_eq(dev, &table->pages_eq.core, ¶m);
622 mlx5_core_warn(dev, "failed to create pages EQ %d\n", err);
625 err = mlx5_eq_enable(dev, &table->pages_eq.core,
626 &table->pages_eq.irq_nb);
628 mlx5_core_warn(dev, "failed to enable pages EQ %d\n", err);
635 destroy_async_eq(dev, &table->pages_eq.core);
637 mlx5_eq_disable(dev, &table->async_eq.core, &table->async_eq.irq_nb);
639 destroy_async_eq(dev, &table->async_eq.core);
641 mlx5_cmd_use_polling(dev);
642 mlx5_eq_disable(dev, &table->cmd_eq.core, &table->cmd_eq.irq_nb);
644 destroy_async_eq(dev, &table->cmd_eq.core);
646 mlx5_eq_notifier_unregister(dev, &table->cq_err_nb);
650 static void destroy_async_eqs(struct mlx5_core_dev *dev)
652 struct mlx5_eq_table *table = dev->priv.eq_table;
655 mlx5_eq_disable(dev, &table->pages_eq.core, &table->pages_eq.irq_nb);
656 err = destroy_async_eq(dev, &table->pages_eq.core);
658 mlx5_core_err(dev, "failed to destroy pages eq, err(%d)\n",
661 mlx5_eq_disable(dev, &table->async_eq.core, &table->async_eq.irq_nb);
662 err = destroy_async_eq(dev, &table->async_eq.core);
664 mlx5_core_err(dev, "failed to destroy async eq, err(%d)\n",
667 mlx5_cmd_use_polling(dev);
669 mlx5_eq_disable(dev, &table->cmd_eq.core, &table->cmd_eq.irq_nb);
670 err = destroy_async_eq(dev, &table->cmd_eq.core);
672 mlx5_core_err(dev, "failed to destroy command eq, err(%d)\n",
675 mlx5_eq_notifier_unregister(dev, &table->cq_err_nb);
678 struct mlx5_eq *mlx5_get_async_eq(struct mlx5_core_dev *dev)
680 return &dev->priv.eq_table->async_eq.core;
683 void mlx5_eq_synchronize_async_irq(struct mlx5_core_dev *dev)
685 synchronize_irq(dev->priv.eq_table->async_eq.core.irqn);
688 void mlx5_eq_synchronize_cmd_irq(struct mlx5_core_dev *dev)
690 synchronize_irq(dev->priv.eq_table->cmd_eq.core.irqn);
693 /* Generic EQ API for mlx5_core consumers
694 * Needed For RDMA ODP EQ for now
697 mlx5_eq_create_generic(struct mlx5_core_dev *dev,
698 struct mlx5_eq_param *param)
700 struct mlx5_eq *eq = kvzalloc(sizeof(*eq), GFP_KERNEL);
704 return ERR_PTR(-ENOMEM);
706 err = create_async_eq(dev, eq, param);
714 EXPORT_SYMBOL(mlx5_eq_create_generic);
716 int mlx5_eq_destroy_generic(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
723 err = destroy_async_eq(dev, eq);
731 EXPORT_SYMBOL(mlx5_eq_destroy_generic);
733 struct mlx5_eqe *mlx5_eq_get_eqe(struct mlx5_eq *eq, u32 cc)
735 u32 ci = eq->cons_index + cc;
736 struct mlx5_eqe *eqe;
738 eqe = get_eqe(eq, ci & (eq->nent - 1));
739 eqe = ((eqe->owner & 1) ^ !!(ci & eq->nent)) ? NULL : eqe;
740 /* Make sure we read EQ entry contents after we've
741 * checked the ownership bit.
748 EXPORT_SYMBOL(mlx5_eq_get_eqe);
750 void mlx5_eq_update_ci(struct mlx5_eq *eq, u32 cc, bool arm)
752 __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2);
755 eq->cons_index += cc;
756 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24);
758 __raw_writel((__force u32)cpu_to_be32(val), addr);
759 /* We still want ordering, just not swabbing, so add a barrier */
762 EXPORT_SYMBOL(mlx5_eq_update_ci);
764 static void destroy_comp_eqs(struct mlx5_core_dev *dev)
766 struct mlx5_eq_table *table = dev->priv.eq_table;
767 struct mlx5_eq_comp *eq, *n;
769 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
771 mlx5_eq_disable(dev, &eq->core, &eq->irq_nb);
772 if (destroy_unmap_eq(dev, &eq->core))
773 mlx5_core_warn(dev, "failed to destroy comp EQ 0x%x\n",
775 tasklet_disable(&eq->tasklet_ctx.task);
780 static int create_comp_eqs(struct mlx5_core_dev *dev)
782 struct mlx5_eq_table *table = dev->priv.eq_table;
783 struct mlx5_eq_comp *eq;
789 INIT_LIST_HEAD(&table->comp_eqs_list);
790 ncomp_eqs = table->num_comp_eqs;
791 nent = MLX5_COMP_EQ_SIZE;
792 for (i = 0; i < ncomp_eqs; i++) {
793 int vecidx = i + MLX5_IRQ_VEC_COMP_BASE;
794 struct mlx5_eq_param param = {};
796 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
802 INIT_LIST_HEAD(&eq->tasklet_ctx.list);
803 INIT_LIST_HEAD(&eq->tasklet_ctx.process_list);
804 spin_lock_init(&eq->tasklet_ctx.lock);
805 tasklet_init(&eq->tasklet_ctx.task, mlx5_cq_tasklet_cb,
806 (unsigned long)&eq->tasklet_ctx);
808 eq->irq_nb.notifier_call = mlx5_eq_comp_int;
809 param = (struct mlx5_eq_param) {
813 err = create_map_eq(dev, &eq->core, ¶m);
818 err = mlx5_eq_enable(dev, &eq->core, &eq->irq_nb);
820 destroy_unmap_eq(dev, &eq->core);
825 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->core.eqn);
826 /* add tail, to keep the list ordered, for mlx5_vector2eqn to work */
827 list_add_tail(&eq->list, &table->comp_eqs_list);
833 destroy_comp_eqs(dev);
837 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
840 struct mlx5_eq_table *table = dev->priv.eq_table;
841 struct mlx5_eq_comp *eq, *n;
845 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
848 *irqn = eq->core.irqn;
856 EXPORT_SYMBOL(mlx5_vector2eqn);
858 unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev)
860 return dev->priv.eq_table->num_comp_eqs;
862 EXPORT_SYMBOL(mlx5_comp_vectors_count);
865 mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector)
867 int vecidx = vector + MLX5_IRQ_VEC_COMP_BASE;
869 return mlx5_irq_get_affinity_mask(dev->priv.eq_table->irq_table,
872 EXPORT_SYMBOL(mlx5_comp_irq_get_affinity_mask);
874 #ifdef CONFIG_RFS_ACCEL
875 struct cpu_rmap *mlx5_eq_table_get_rmap(struct mlx5_core_dev *dev)
877 return mlx5_irq_get_rmap(dev->priv.eq_table->irq_table);
881 struct mlx5_eq_comp *mlx5_eqn2comp_eq(struct mlx5_core_dev *dev, int eqn)
883 struct mlx5_eq_table *table = dev->priv.eq_table;
884 struct mlx5_eq_comp *eq;
886 list_for_each_entry(eq, &table->comp_eqs_list, list) {
887 if (eq->core.eqn == eqn)
891 return ERR_PTR(-ENOENT);
894 /* This function should only be called after mlx5_cmd_force_teardown_hca */
895 void mlx5_core_eq_free_irqs(struct mlx5_core_dev *dev)
897 struct mlx5_eq_table *table = dev->priv.eq_table;
899 mutex_lock(&table->lock); /* sync with create/destroy_async_eq */
900 mlx5_irq_table_destroy(dev);
901 mutex_unlock(&table->lock);
904 int mlx5_eq_table_create(struct mlx5_core_dev *dev)
906 struct mlx5_eq_table *eq_table = dev->priv.eq_table;
909 eq_table->num_comp_eqs =
910 mlx5_irq_get_num_comp(eq_table->irq_table);
912 err = create_async_eqs(dev);
914 mlx5_core_err(dev, "Failed to create async EQs\n");
918 err = create_comp_eqs(dev);
920 mlx5_core_err(dev, "Failed to create completion EQs\n");
926 destroy_async_eqs(dev);
931 void mlx5_eq_table_destroy(struct mlx5_core_dev *dev)
933 destroy_comp_eqs(dev);
934 destroy_async_eqs(dev);
937 int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb)
939 struct mlx5_eq_table *eqt = dev->priv.eq_table;
941 return atomic_notifier_chain_register(&eqt->nh[nb->event_type], &nb->nb);
943 EXPORT_SYMBOL(mlx5_eq_notifier_register);
945 int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb)
947 struct mlx5_eq_table *eqt = dev->priv.eq_table;
949 return atomic_notifier_chain_unregister(&eqt->nh[nb->event_type], &nb->nb);
951 EXPORT_SYMBOL(mlx5_eq_notifier_unregister);