2 * Copyright (c) 2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/prefetch.h>
35 #include <linux/ipv6.h>
36 #include <linux/tcp.h>
37 #include <linux/indirect_call_wrapper.h>
38 #include <net/ip6_checksum.h>
39 #include <net/page_pool.h>
40 #include <net/inet_ecn.h>
45 #include "ipoib/ipoib.h"
46 #include "en_accel/ipsec_rxtx.h"
47 #include "en_accel/tls_rxtx.h"
48 #include "lib/clock.h"
50 #include "en/xsk/rx.h"
51 #include "en/health.h"
53 static inline bool mlx5e_rx_hw_stamp(struct hwtstamp_config *config)
55 return config->rx_filter == HWTSTAMP_FILTER_ALL;
58 static inline void mlx5e_read_cqe_slot(struct mlx5_cqwq *wq,
61 u32 ci = mlx5_cqwq_ctr2ix(wq, cqcc);
63 memcpy(data, mlx5_cqwq_get_wqe(wq, ci), sizeof(struct mlx5_cqe64));
66 static inline void mlx5e_read_title_slot(struct mlx5e_rq *rq,
70 struct mlx5e_cq_decomp *cqd = &rq->cqd;
71 struct mlx5_cqe64 *title = &cqd->title;
73 mlx5e_read_cqe_slot(wq, cqcc, title);
74 cqd->left = be32_to_cpu(title->byte_cnt);
75 cqd->wqe_counter = be16_to_cpu(title->wqe_counter);
76 rq->stats->cqe_compress_blks++;
79 static inline void mlx5e_read_mini_arr_slot(struct mlx5_cqwq *wq,
80 struct mlx5e_cq_decomp *cqd,
83 mlx5e_read_cqe_slot(wq, cqcc, cqd->mini_arr);
84 cqd->mini_arr_idx = 0;
87 static inline void mlx5e_cqes_update_owner(struct mlx5_cqwq *wq, int n)
90 u8 op_own = mlx5_cqwq_get_ctr_wrap_cnt(wq, cqcc) & 1;
91 u32 ci = mlx5_cqwq_ctr2ix(wq, cqcc);
92 u32 wq_sz = mlx5_cqwq_get_size(wq);
93 u32 ci_top = min_t(u32, wq_sz, ci + n);
95 for (; ci < ci_top; ci++, n--) {
96 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(wq, ci);
101 if (unlikely(ci == wq_sz)) {
103 for (ci = 0; ci < n; ci++) {
104 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(wq, ci);
106 cqe->op_own = op_own;
111 static inline void mlx5e_decompress_cqe(struct mlx5e_rq *rq,
112 struct mlx5_cqwq *wq,
115 struct mlx5e_cq_decomp *cqd = &rq->cqd;
116 struct mlx5_mini_cqe8 *mini_cqe = &cqd->mini_arr[cqd->mini_arr_idx];
117 struct mlx5_cqe64 *title = &cqd->title;
119 title->byte_cnt = mini_cqe->byte_cnt;
120 title->check_sum = mini_cqe->checksum;
121 title->op_own &= 0xf0;
122 title->op_own |= 0x01 & (cqcc >> wq->fbc.log_sz);
123 title->wqe_counter = cpu_to_be16(cqd->wqe_counter);
125 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
126 cqd->wqe_counter += mpwrq_get_cqe_consumed_strides(title);
129 mlx5_wq_cyc_ctr2ix(&rq->wqe.wq, cqd->wqe_counter + 1);
132 static inline void mlx5e_decompress_cqe_no_hash(struct mlx5e_rq *rq,
133 struct mlx5_cqwq *wq,
136 struct mlx5e_cq_decomp *cqd = &rq->cqd;
138 mlx5e_decompress_cqe(rq, wq, cqcc);
139 cqd->title.rss_hash_type = 0;
140 cqd->title.rss_hash_result = 0;
143 static inline u32 mlx5e_decompress_cqes_cont(struct mlx5e_rq *rq,
144 struct mlx5_cqwq *wq,
145 int update_owner_only,
148 struct mlx5e_cq_decomp *cqd = &rq->cqd;
149 u32 cqcc = wq->cc + update_owner_only;
153 cqe_count = min_t(u32, cqd->left, budget_rem);
155 for (i = update_owner_only; i < cqe_count;
156 i++, cqd->mini_arr_idx++, cqcc++) {
157 if (cqd->mini_arr_idx == MLX5_MINI_CQE_ARRAY_SIZE)
158 mlx5e_read_mini_arr_slot(wq, cqd, cqcc);
160 mlx5e_decompress_cqe_no_hash(rq, wq, cqcc);
161 rq->handle_rx_cqe(rq, &cqd->title);
163 mlx5e_cqes_update_owner(wq, cqcc - wq->cc);
165 cqd->left -= cqe_count;
166 rq->stats->cqe_compress_pkts += cqe_count;
171 static inline u32 mlx5e_decompress_cqes_start(struct mlx5e_rq *rq,
172 struct mlx5_cqwq *wq,
175 struct mlx5e_cq_decomp *cqd = &rq->cqd;
178 mlx5e_read_title_slot(rq, wq, cc);
179 mlx5e_read_mini_arr_slot(wq, cqd, cc + 1);
180 mlx5e_decompress_cqe(rq, wq, cc);
181 rq->handle_rx_cqe(rq, &cqd->title);
184 return mlx5e_decompress_cqes_cont(rq, wq, 1, budget_rem) - 1;
187 static inline bool mlx5e_page_is_reserved(struct page *page)
189 return page_is_pfmemalloc(page) || page_to_nid(page) != numa_mem_id();
192 static inline bool mlx5e_rx_cache_put(struct mlx5e_rq *rq,
193 struct mlx5e_dma_info *dma_info)
195 struct mlx5e_page_cache *cache = &rq->page_cache;
196 u32 tail_next = (cache->tail + 1) & (MLX5E_CACHE_SIZE - 1);
197 struct mlx5e_rq_stats *stats = rq->stats;
199 if (tail_next == cache->head) {
204 if (unlikely(mlx5e_page_is_reserved(dma_info->page))) {
205 stats->cache_waive++;
209 cache->page_cache[cache->tail] = *dma_info;
210 cache->tail = tail_next;
214 static inline bool mlx5e_rx_cache_get(struct mlx5e_rq *rq,
215 struct mlx5e_dma_info *dma_info)
217 struct mlx5e_page_cache *cache = &rq->page_cache;
218 struct mlx5e_rq_stats *stats = rq->stats;
220 if (unlikely(cache->head == cache->tail)) {
221 stats->cache_empty++;
225 if (page_ref_count(cache->page_cache[cache->head].page) != 1) {
230 *dma_info = cache->page_cache[cache->head];
231 cache->head = (cache->head + 1) & (MLX5E_CACHE_SIZE - 1);
232 stats->cache_reuse++;
234 dma_sync_single_for_device(rq->pdev, dma_info->addr,
240 static inline int mlx5e_page_alloc_pool(struct mlx5e_rq *rq,
241 struct mlx5e_dma_info *dma_info)
243 if (mlx5e_rx_cache_get(rq, dma_info))
246 dma_info->page = page_pool_dev_alloc_pages(rq->page_pool);
247 if (unlikely(!dma_info->page))
250 dma_info->addr = dma_map_page(rq->pdev, dma_info->page, 0,
251 PAGE_SIZE, rq->buff.map_dir);
252 if (unlikely(dma_mapping_error(rq->pdev, dma_info->addr))) {
253 page_pool_recycle_direct(rq->page_pool, dma_info->page);
254 dma_info->page = NULL;
261 static inline int mlx5e_page_alloc(struct mlx5e_rq *rq,
262 struct mlx5e_dma_info *dma_info)
265 return mlx5e_xsk_page_alloc_umem(rq, dma_info);
267 return mlx5e_page_alloc_pool(rq, dma_info);
270 void mlx5e_page_dma_unmap(struct mlx5e_rq *rq, struct mlx5e_dma_info *dma_info)
272 dma_unmap_page(rq->pdev, dma_info->addr, PAGE_SIZE, rq->buff.map_dir);
275 void mlx5e_page_release_dynamic(struct mlx5e_rq *rq,
276 struct mlx5e_dma_info *dma_info,
279 if (likely(recycle)) {
280 if (mlx5e_rx_cache_put(rq, dma_info))
283 mlx5e_page_dma_unmap(rq, dma_info);
284 page_pool_recycle_direct(rq->page_pool, dma_info->page);
286 mlx5e_page_dma_unmap(rq, dma_info);
287 page_pool_release_page(rq->page_pool, dma_info->page);
288 put_page(dma_info->page);
292 static inline void mlx5e_page_release(struct mlx5e_rq *rq,
293 struct mlx5e_dma_info *dma_info,
297 /* The `recycle` parameter is ignored, and the page is always
298 * put into the Reuse Ring, because there is no way to return
299 * the page to the userspace when the interface goes down.
301 mlx5e_xsk_page_release(rq, dma_info);
303 mlx5e_page_release_dynamic(rq, dma_info, recycle);
306 static inline int mlx5e_get_rx_frag(struct mlx5e_rq *rq,
307 struct mlx5e_wqe_frag_info *frag)
312 /* On first frag (offset == 0), replenish page (dma_info actually).
313 * Other frags that point to the same dma_info (with a different
314 * offset) should just use the new one without replenishing again
317 err = mlx5e_page_alloc(rq, frag->di);
322 static inline void mlx5e_put_rx_frag(struct mlx5e_rq *rq,
323 struct mlx5e_wqe_frag_info *frag,
326 if (frag->last_in_page)
327 mlx5e_page_release(rq, frag->di, recycle);
330 static inline struct mlx5e_wqe_frag_info *get_frag(struct mlx5e_rq *rq, u16 ix)
332 return &rq->wqe.frags[ix << rq->wqe.info.log_num_frags];
335 static int mlx5e_alloc_rx_wqe(struct mlx5e_rq *rq, struct mlx5e_rx_wqe_cyc *wqe,
338 struct mlx5e_wqe_frag_info *frag = get_frag(rq, ix);
342 for (i = 0; i < rq->wqe.info.num_frags; i++, frag++) {
343 err = mlx5e_get_rx_frag(rq, frag);
347 wqe->data[i].addr = cpu_to_be64(frag->di->addr +
348 frag->offset + rq->buff.headroom);
355 mlx5e_put_rx_frag(rq, --frag, true);
360 static inline void mlx5e_free_rx_wqe(struct mlx5e_rq *rq,
361 struct mlx5e_wqe_frag_info *wi,
366 for (i = 0; i < rq->wqe.info.num_frags; i++, wi++)
367 mlx5e_put_rx_frag(rq, wi, recycle);
370 void mlx5e_dealloc_rx_wqe(struct mlx5e_rq *rq, u16 ix)
372 struct mlx5e_wqe_frag_info *wi = get_frag(rq, ix);
374 mlx5e_free_rx_wqe(rq, wi, false);
377 static int mlx5e_alloc_rx_wqes(struct mlx5e_rq *rq, u16 ix, u8 wqe_bulk)
379 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
384 int pages_desired = wqe_bulk << rq->wqe.info.log_num_frags;
386 if (unlikely(!mlx5e_xsk_pages_enough_umem(rq, pages_desired)))
390 for (i = 0; i < wqe_bulk; i++) {
391 struct mlx5e_rx_wqe_cyc *wqe = mlx5_wq_cyc_get_wqe(wq, ix + i);
393 err = mlx5e_alloc_rx_wqe(rq, wqe, ix + i);
402 mlx5e_dealloc_rx_wqe(rq, ix + i);
408 mlx5e_add_skb_frag(struct mlx5e_rq *rq, struct sk_buff *skb,
409 struct mlx5e_dma_info *di, u32 frag_offset, u32 len,
410 unsigned int truesize)
412 dma_sync_single_for_cpu(rq->pdev,
413 di->addr + frag_offset,
414 len, DMA_FROM_DEVICE);
415 page_ref_inc(di->page);
416 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
417 di->page, frag_offset, len, truesize);
421 mlx5e_copy_skb_header(struct device *pdev, struct sk_buff *skb,
422 struct mlx5e_dma_info *dma_info,
423 int offset_from, u32 headlen)
425 const void *from = page_address(dma_info->page) + offset_from;
426 /* Aligning len to sizeof(long) optimizes memcpy performance */
427 unsigned int len = ALIGN(headlen, sizeof(long));
429 dma_sync_single_for_cpu(pdev, dma_info->addr + offset_from, len,
431 skb_copy_to_linear_data(skb, from, len);
435 mlx5e_free_rx_mpwqe(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi, bool recycle)
438 struct mlx5e_dma_info *dma_info = wi->umr.dma_info;
441 /* A common case for AF_XDP. */
442 if (bitmap_full(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE))
445 no_xdp_xmit = bitmap_empty(wi->xdp_xmit_bitmap,
446 MLX5_MPWRQ_PAGES_PER_WQE);
448 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++)
449 if (no_xdp_xmit || !test_bit(i, wi->xdp_xmit_bitmap))
450 mlx5e_page_release(rq, &dma_info[i], recycle);
453 static void mlx5e_post_rx_mpwqe(struct mlx5e_rq *rq, u8 n)
455 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
458 u16 next_wqe_index = mlx5_wq_ll_get_wqe_next_ix(wq, wq->head);
460 mlx5_wq_ll_push(wq, next_wqe_index);
463 /* ensure wqes are visible to device before updating doorbell record */
466 mlx5_wq_ll_update_db_record(wq);
469 static inline void mlx5e_fill_icosq_frag_edge(struct mlx5e_icosq *sq,
470 struct mlx5_wq_cyc *wq,
473 struct mlx5e_sq_wqe_info *edge_wi, *wi = &sq->db.ico_wqe[pi];
475 edge_wi = wi + nnops;
477 /* fill sq frag edge with nops to avoid wqe wrapping two pages */
478 for (; wi < edge_wi; wi++) {
479 wi->opcode = MLX5_OPCODE_NOP;
481 mlx5e_post_nop(wq, sq->sqn, &sq->pc);
485 static int mlx5e_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
487 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
488 struct mlx5e_dma_info *dma_info = &wi->umr.dma_info[0];
489 struct mlx5e_icosq *sq = &rq->channel->icosq;
490 struct mlx5_wq_cyc *wq = &sq->wq;
491 struct mlx5e_umr_wqe *umr_wqe;
492 u16 xlt_offset = ix << (MLX5E_LOG_ALIGNED_MPWQE_PPW - 1);
493 u16 pi, contig_wqebbs_room;
498 unlikely(!mlx5e_xsk_pages_enough_umem(rq, MLX5_MPWRQ_PAGES_PER_WQE))) {
503 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
504 contig_wqebbs_room = mlx5_wq_cyc_get_contig_wqebbs(wq, pi);
505 if (unlikely(contig_wqebbs_room < MLX5E_UMR_WQEBBS)) {
506 mlx5e_fill_icosq_frag_edge(sq, wq, pi, contig_wqebbs_room);
507 pi = mlx5_wq_cyc_ctr2ix(wq, sq->pc);
510 umr_wqe = mlx5_wq_cyc_get_wqe(wq, pi);
511 memcpy(umr_wqe, &rq->mpwqe.umr_wqe, offsetof(struct mlx5e_umr_wqe, inline_mtts));
513 for (i = 0; i < MLX5_MPWRQ_PAGES_PER_WQE; i++, dma_info++) {
514 err = mlx5e_page_alloc(rq, dma_info);
517 umr_wqe->inline_mtts[i].ptag = cpu_to_be64(dma_info->addr | MLX5_EN_WR);
520 bitmap_zero(wi->xdp_xmit_bitmap, MLX5_MPWRQ_PAGES_PER_WQE);
521 wi->consumed_strides = 0;
523 umr_wqe->ctrl.opmod_idx_opcode =
524 cpu_to_be32((sq->pc << MLX5_WQE_CTRL_WQE_INDEX_SHIFT) |
526 umr_wqe->uctrl.xlt_offset = cpu_to_be16(xlt_offset);
528 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_UMR;
529 sq->db.ico_wqe[pi].num_wqebbs = MLX5E_UMR_WQEBBS;
530 sq->db.ico_wqe[pi].umr.rq = rq;
531 sq->pc += MLX5E_UMR_WQEBBS;
533 sq->doorbell_cseg = &umr_wqe->ctrl;
540 mlx5e_page_release(rq, dma_info, true);
544 rq->stats->buff_alloc_err++;
549 void mlx5e_dealloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix)
551 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[ix];
552 /* Don't recycle, this function is called on rq/netdev close */
553 mlx5e_free_rx_mpwqe(rq, wi, false);
556 bool mlx5e_post_rx_wqes(struct mlx5e_rq *rq)
558 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
562 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
565 wqe_bulk = rq->wqe.info.wqe_bulk;
567 if (mlx5_wq_cyc_missing(wq) < wqe_bulk)
571 u16 head = mlx5_wq_cyc_get_head(wq);
573 err = mlx5e_alloc_rx_wqes(rq, head, wqe_bulk);
575 rq->stats->buff_alloc_err++;
579 mlx5_wq_cyc_push_n(wq, wqe_bulk);
580 } while (mlx5_wq_cyc_missing(wq) >= wqe_bulk);
582 /* ensure wqes are visible to device before updating doorbell record */
585 mlx5_wq_cyc_update_db_record(wq);
590 int mlx5e_poll_ico_cq(struct mlx5e_cq *cq)
592 struct mlx5e_icosq *sq = container_of(cq, struct mlx5e_icosq, cq);
593 struct mlx5_cqe64 *cqe;
597 if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, &sq->state)))
600 cqe = mlx5_cqwq_get_cqe(&cq->wq);
604 /* sq->cc must be updated only after mlx5_cqwq_update_db_record(),
605 * otherwise a cq overrun may occur
614 mlx5_cqwq_pop(&cq->wq);
616 wqe_counter = be16_to_cpu(cqe->wqe_counter);
618 if (unlikely(get_cqe_opcode(cqe) != MLX5_CQE_REQ)) {
619 netdev_WARN_ONCE(cq->channel->netdev,
620 "Bad OP in ICOSQ CQE: 0x%x\n", get_cqe_opcode(cqe));
621 if (!test_and_set_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state))
622 queue_work(cq->channel->priv->wq, &sq->recover_work);
626 struct mlx5e_sq_wqe_info *wi;
629 last_wqe = (sqcc == wqe_counter);
631 ci = mlx5_wq_cyc_ctr2ix(&sq->wq, sqcc);
632 wi = &sq->db.ico_wqe[ci];
633 sqcc += wi->num_wqebbs;
635 if (likely(wi->opcode == MLX5_OPCODE_UMR))
636 wi->umr.rq->mpwqe.umr_completed++;
637 else if (unlikely(wi->opcode != MLX5_OPCODE_NOP))
638 netdev_WARN_ONCE(cq->channel->netdev,
639 "Bad OPCODE in ICOSQ WQE info: 0x%x\n",
644 } while ((++i < MLX5E_TX_CQ_POLL_BUDGET) && (cqe = mlx5_cqwq_get_cqe(&cq->wq)));
648 mlx5_cqwq_update_db_record(&cq->wq);
653 bool mlx5e_post_rx_mpwqes(struct mlx5e_rq *rq)
655 struct mlx5e_icosq *sq = &rq->channel->icosq;
656 struct mlx5_wq_ll *wq = &rq->mpwqe.wq;
657 u8 umr_completed = rq->mpwqe.umr_completed;
662 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
666 mlx5e_post_rx_mpwqe(rq, umr_completed);
667 rq->mpwqe.umr_in_progress -= umr_completed;
668 rq->mpwqe.umr_completed = 0;
671 missing = mlx5_wq_ll_missing(wq) - rq->mpwqe.umr_in_progress;
673 if (unlikely(rq->mpwqe.umr_in_progress > rq->mpwqe.umr_last_bulk))
674 rq->stats->congst_umr++;
676 #define UMR_WQE_BULK (2)
677 if (likely(missing < UMR_WQE_BULK))
680 head = rq->mpwqe.actual_wq_head;
683 alloc_err = mlx5e_alloc_rx_mpwqe(rq, head);
685 if (unlikely(alloc_err))
687 head = mlx5_wq_ll_get_wqe_next_ix(wq, head);
690 rq->mpwqe.umr_last_bulk = missing - i;
691 if (sq->doorbell_cseg) {
692 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, sq->doorbell_cseg);
693 sq->doorbell_cseg = NULL;
696 rq->mpwqe.umr_in_progress += rq->mpwqe.umr_last_bulk;
697 rq->mpwqe.actual_wq_head = head;
699 /* If XSK Fill Ring doesn't have enough frames, report the error, so
700 * that one of the actions can be performed:
701 * 1. If need_wakeup is used, signal that the application has to kick
702 * the driver when it refills the Fill Ring.
703 * 2. Otherwise, busy poll by rescheduling the NAPI poll.
705 if (unlikely(alloc_err == -ENOMEM && rq->umem))
711 static void mlx5e_lro_update_tcp_hdr(struct mlx5_cqe64 *cqe, struct tcphdr *tcp)
713 u8 l4_hdr_type = get_cqe_l4_hdr_type(cqe);
714 u8 tcp_ack = (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA) ||
715 (l4_hdr_type == CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA);
718 tcp->psh = get_cqe_lro_tcppsh(cqe);
722 tcp->ack_seq = cqe->lro_ack_seq_num;
723 tcp->window = cqe->lro_tcp_win;
727 static void mlx5e_lro_update_hdr(struct sk_buff *skb, struct mlx5_cqe64 *cqe,
730 struct ethhdr *eth = (struct ethhdr *)(skb->data);
732 int network_depth = 0;
738 proto = __vlan_get_protocol(skb, eth->h_proto, &network_depth);
740 tot_len = cqe_bcnt - network_depth;
741 ip_p = skb->data + network_depth;
743 if (proto == htons(ETH_P_IP)) {
744 struct iphdr *ipv4 = ip_p;
746 tcp = ip_p + sizeof(struct iphdr);
747 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
749 ipv4->ttl = cqe->lro_min_ttl;
750 ipv4->tot_len = cpu_to_be16(tot_len);
752 ipv4->check = ip_fast_csum((unsigned char *)ipv4,
755 mlx5e_lro_update_tcp_hdr(cqe, tcp);
756 check = csum_partial(tcp, tcp->doff * 4,
757 csum_unfold((__force __sum16)cqe->check_sum));
758 /* Almost done, don't forget the pseudo header */
759 tcp->check = csum_tcpudp_magic(ipv4->saddr, ipv4->daddr,
760 tot_len - sizeof(struct iphdr),
763 u16 payload_len = tot_len - sizeof(struct ipv6hdr);
764 struct ipv6hdr *ipv6 = ip_p;
766 tcp = ip_p + sizeof(struct ipv6hdr);
767 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
769 ipv6->hop_limit = cqe->lro_min_ttl;
770 ipv6->payload_len = cpu_to_be16(payload_len);
772 mlx5e_lro_update_tcp_hdr(cqe, tcp);
773 check = csum_partial(tcp, tcp->doff * 4,
774 csum_unfold((__force __sum16)cqe->check_sum));
775 /* Almost done, don't forget the pseudo header */
776 tcp->check = csum_ipv6_magic(&ipv6->saddr, &ipv6->daddr, payload_len,
781 static inline void mlx5e_skb_set_hash(struct mlx5_cqe64 *cqe,
784 u8 cht = cqe->rss_hash_type;
785 int ht = (cht & CQE_RSS_HTYPE_L4) ? PKT_HASH_TYPE_L4 :
786 (cht & CQE_RSS_HTYPE_IP) ? PKT_HASH_TYPE_L3 :
788 skb_set_hash(skb, be32_to_cpu(cqe->rss_hash_result), ht);
791 static inline bool is_last_ethertype_ip(struct sk_buff *skb, int *network_depth,
794 *proto = ((struct ethhdr *)skb->data)->h_proto;
795 *proto = __vlan_get_protocol(skb, *proto, network_depth);
797 if (*proto == htons(ETH_P_IP))
798 return pskb_may_pull(skb, *network_depth + sizeof(struct iphdr));
800 if (*proto == htons(ETH_P_IPV6))
801 return pskb_may_pull(skb, *network_depth + sizeof(struct ipv6hdr));
806 static inline void mlx5e_enable_ecn(struct mlx5e_rq *rq, struct sk_buff *skb)
808 int network_depth = 0;
813 if (unlikely(!is_last_ethertype_ip(skb, &network_depth, &proto)))
816 ip = skb->data + network_depth;
817 rc = ((proto == htons(ETH_P_IP)) ? IP_ECN_set_ce((struct iphdr *)ip) :
818 IP6_ECN_set_ce(skb, (struct ipv6hdr *)ip));
820 rq->stats->ecn_mark += !!rc;
823 static u8 get_ip_proto(struct sk_buff *skb, int network_depth, __be16 proto)
825 void *ip_p = skb->data + network_depth;
827 return (proto == htons(ETH_P_IP)) ? ((struct iphdr *)ip_p)->protocol :
828 ((struct ipv6hdr *)ip_p)->nexthdr;
831 #define short_frame(size) ((size) <= ETH_ZLEN + ETH_FCS_LEN)
833 #define MAX_PADDING 8
836 tail_padding_csum_slow(struct sk_buff *skb, int offset, int len,
837 struct mlx5e_rq_stats *stats)
839 stats->csum_complete_tail_slow++;
840 skb->csum = csum_block_add(skb->csum,
841 skb_checksum(skb, offset, len, 0),
846 tail_padding_csum(struct sk_buff *skb, int offset,
847 struct mlx5e_rq_stats *stats)
849 u8 tail_padding[MAX_PADDING];
850 int len = skb->len - offset;
853 if (unlikely(len > MAX_PADDING)) {
854 tail_padding_csum_slow(skb, offset, len, stats);
858 tail = skb_header_pointer(skb, offset, len, tail_padding);
859 if (unlikely(!tail)) {
860 tail_padding_csum_slow(skb, offset, len, stats);
864 stats->csum_complete_tail++;
865 skb->csum = csum_block_add(skb->csum, csum_partial(tail, len, 0), offset);
869 mlx5e_skb_csum_fixup(struct sk_buff *skb, int network_depth, __be16 proto,
870 struct mlx5e_rq_stats *stats)
876 /* Fixup vlan headers, if any */
877 if (network_depth > ETH_HLEN)
878 /* CQE csum is calculated from the IP header and does
879 * not cover VLAN headers (if present). This will add
880 * the checksum manually.
882 skb->csum = csum_partial(skb->data + ETH_HLEN,
883 network_depth - ETH_HLEN,
886 /* Fixup tail padding, if any */
888 case htons(ETH_P_IP):
889 ip4 = (struct iphdr *)(skb->data + network_depth);
890 pkt_len = network_depth + ntohs(ip4->tot_len);
892 case htons(ETH_P_IPV6):
893 ip6 = (struct ipv6hdr *)(skb->data + network_depth);
894 pkt_len = network_depth + sizeof(*ip6) + ntohs(ip6->payload_len);
900 if (likely(pkt_len >= skb->len))
903 tail_padding_csum(skb, pkt_len, stats);
906 static inline void mlx5e_handle_csum(struct net_device *netdev,
907 struct mlx5_cqe64 *cqe,
912 struct mlx5e_rq_stats *stats = rq->stats;
913 int network_depth = 0;
916 if (unlikely(!(netdev->features & NETIF_F_RXCSUM)))
920 skb->ip_summed = CHECKSUM_UNNECESSARY;
921 stats->csum_unnecessary++;
925 /* True when explicitly set via priv flag, or XDP prog is loaded */
926 if (test_bit(MLX5E_RQ_STATE_NO_CSUM_COMPLETE, &rq->state))
927 goto csum_unnecessary;
929 /* CQE csum doesn't cover padding octets in short ethernet
930 * frames. And the pad field is appended prior to calculating
931 * and appending the FCS field.
933 * Detecting these padded frames requires to verify and parse
934 * IP headers, so we simply force all those small frames to be
935 * CHECKSUM_UNNECESSARY even if they are not padded.
937 if (short_frame(skb->len))
938 goto csum_unnecessary;
940 if (likely(is_last_ethertype_ip(skb, &network_depth, &proto))) {
941 if (unlikely(get_ip_proto(skb, network_depth, proto) == IPPROTO_SCTP))
942 goto csum_unnecessary;
944 stats->csum_complete++;
945 skb->ip_summed = CHECKSUM_COMPLETE;
946 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
948 if (test_bit(MLX5E_RQ_STATE_CSUM_FULL, &rq->state))
949 return; /* CQE csum covers all received bytes */
951 /* csum might need some fixups ...*/
952 mlx5e_skb_csum_fixup(skb, network_depth, proto, stats);
957 if (likely((cqe->hds_ip_ext & CQE_L3_OK) &&
958 (cqe->hds_ip_ext & CQE_L4_OK))) {
959 skb->ip_summed = CHECKSUM_UNNECESSARY;
960 if (cqe_is_tunneled(cqe)) {
962 skb->encapsulation = 1;
963 stats->csum_unnecessary_inner++;
966 stats->csum_unnecessary++;
970 skb->ip_summed = CHECKSUM_NONE;
974 #define MLX5E_CE_BIT_MASK 0x80
976 static inline void mlx5e_build_rx_skb(struct mlx5_cqe64 *cqe,
981 u8 lro_num_seg = be32_to_cpu(cqe->srqn) >> 24;
982 struct mlx5e_rq_stats *stats = rq->stats;
983 struct net_device *netdev = rq->netdev;
985 skb->mac_len = ETH_HLEN;
987 #ifdef CONFIG_MLX5_EN_TLS
988 mlx5e_tls_handle_rx_skb(netdev, skb, &cqe_bcnt);
991 if (lro_num_seg > 1) {
992 mlx5e_lro_update_hdr(skb, cqe, cqe_bcnt);
993 skb_shinfo(skb)->gso_size = DIV_ROUND_UP(cqe_bcnt, lro_num_seg);
994 /* Subtract one since we already counted this as one
995 * "regular" packet in mlx5e_complete_rx_cqe()
997 stats->packets += lro_num_seg - 1;
998 stats->lro_packets++;
999 stats->lro_bytes += cqe_bcnt;
1002 if (unlikely(mlx5e_rx_hw_stamp(rq->tstamp)))
1003 skb_hwtstamps(skb)->hwtstamp =
1004 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
1006 skb_record_rx_queue(skb, rq->ix);
1008 if (likely(netdev->features & NETIF_F_RXHASH))
1009 mlx5e_skb_set_hash(cqe, skb);
1011 if (cqe_has_vlan(cqe)) {
1012 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1013 be16_to_cpu(cqe->vlan_info));
1014 stats->removed_vlan_packets++;
1017 skb->mark = be32_to_cpu(cqe->sop_drop_qpn) & MLX5E_TC_FLOW_ID_MASK;
1019 mlx5e_handle_csum(netdev, cqe, rq, skb, !!lro_num_seg);
1020 /* checking CE bit in cqe - MSB in ml_path field */
1021 if (unlikely(cqe->ml_path & MLX5E_CE_BIT_MASK))
1022 mlx5e_enable_ecn(rq, skb);
1024 skb->protocol = eth_type_trans(skb, netdev);
1027 static inline void mlx5e_complete_rx_cqe(struct mlx5e_rq *rq,
1028 struct mlx5_cqe64 *cqe,
1030 struct sk_buff *skb)
1032 struct mlx5e_rq_stats *stats = rq->stats;
1035 stats->bytes += cqe_bcnt;
1036 mlx5e_build_rx_skb(cqe, cqe_bcnt, rq, skb);
1040 struct sk_buff *mlx5e_build_linear_skb(struct mlx5e_rq *rq, void *va,
1041 u32 frag_size, u16 headroom,
1044 struct sk_buff *skb = build_skb(va, frag_size);
1046 if (unlikely(!skb)) {
1047 rq->stats->buff_alloc_err++;
1051 skb_reserve(skb, headroom);
1052 skb_put(skb, cqe_bcnt);
1058 mlx5e_skb_from_cqe_linear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
1059 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
1061 struct mlx5e_dma_info *di = wi->di;
1062 u16 rx_headroom = rq->buff.headroom;
1063 struct sk_buff *skb;
1068 va = page_address(di->page) + wi->offset;
1069 data = va + rx_headroom;
1070 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt);
1072 dma_sync_single_range_for_cpu(rq->pdev, di->addr, wi->offset,
1073 frag_size, DMA_FROM_DEVICE);
1074 prefetchw(va); /* xdp_frame data area */
1078 consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt, false);
1081 return NULL; /* page/packet was consumed by XDP */
1083 skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt);
1087 /* queue up for recycling/reuse */
1088 page_ref_inc(di->page);
1094 mlx5e_skb_from_cqe_nonlinear(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe,
1095 struct mlx5e_wqe_frag_info *wi, u32 cqe_bcnt)
1097 struct mlx5e_rq_frag_info *frag_info = &rq->wqe.info.arr[0];
1098 struct mlx5e_wqe_frag_info *head_wi = wi;
1099 u16 headlen = min_t(u32, MLX5E_RX_MAX_HEAD, cqe_bcnt);
1100 u16 frag_headlen = headlen;
1101 u16 byte_cnt = cqe_bcnt - headlen;
1102 struct sk_buff *skb;
1104 /* XDP is not supported in this configuration, as incoming packets
1105 * might spread among multiple pages.
1107 skb = napi_alloc_skb(rq->cq.napi,
1108 ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1109 if (unlikely(!skb)) {
1110 rq->stats->buff_alloc_err++;
1114 prefetchw(skb->data);
1117 u16 frag_consumed_bytes =
1118 min_t(u16, frag_info->frag_size - frag_headlen, byte_cnt);
1120 mlx5e_add_skb_frag(rq, skb, wi->di, wi->offset + frag_headlen,
1121 frag_consumed_bytes, frag_info->frag_stride);
1122 byte_cnt -= frag_consumed_bytes;
1129 mlx5e_copy_skb_header(rq->pdev, skb, head_wi->di, head_wi->offset, headlen);
1130 /* skb linear part was allocated with headlen and aligned to long */
1131 skb->tail += headlen;
1132 skb->len += headlen;
1137 static void trigger_report(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1139 struct mlx5_err_cqe *err_cqe = (struct mlx5_err_cqe *)cqe;
1141 if (cqe_syndrome_needs_recover(err_cqe->syndrome) &&
1142 !test_and_set_bit(MLX5E_RQ_STATE_RECOVERING, &rq->state))
1143 queue_work(rq->channel->priv->wq, &rq->recover_work);
1146 void mlx5e_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1148 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1149 struct mlx5e_wqe_frag_info *wi;
1150 struct sk_buff *skb;
1154 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1155 wi = get_frag(rq, ci);
1156 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1158 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1159 trigger_report(rq, cqe);
1160 rq->stats->wqe_err++;
1164 skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe,
1165 mlx5e_skb_from_cqe_linear,
1166 mlx5e_skb_from_cqe_nonlinear,
1167 rq, cqe, wi, cqe_bcnt);
1169 /* probably for XDP */
1170 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1171 /* do not return page to cache,
1172 * it will be returned on XDP_TX completion.
1179 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1180 napi_gro_receive(rq->cq.napi, skb);
1183 mlx5e_free_rx_wqe(rq, wi, true);
1185 mlx5_wq_cyc_pop(wq);
1188 #ifdef CONFIG_MLX5_ESWITCH
1189 void mlx5e_handle_rx_cqe_rep(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1191 struct net_device *netdev = rq->netdev;
1192 struct mlx5e_priv *priv = netdev_priv(netdev);
1193 struct mlx5e_rep_priv *rpriv = priv->ppriv;
1194 struct mlx5_eswitch_rep *rep = rpriv->rep;
1195 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1196 struct mlx5e_wqe_frag_info *wi;
1197 struct sk_buff *skb;
1201 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1202 wi = get_frag(rq, ci);
1203 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1205 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1206 rq->stats->wqe_err++;
1210 skb = rq->wqe.skb_from_cqe(rq, cqe, wi, cqe_bcnt);
1212 /* probably for XDP */
1213 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags)) {
1214 /* do not return page to cache,
1215 * it will be returned on XDP_TX completion.
1222 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1224 if (rep->vlan && skb_vlan_tag_present(skb))
1227 napi_gro_receive(rq->cq.napi, skb);
1230 mlx5e_free_rx_wqe(rq, wi, true);
1232 mlx5_wq_cyc_pop(wq);
1237 mlx5e_skb_from_cqe_mpwrq_nonlinear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1238 u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1240 u16 headlen = min_t(u16, MLX5E_RX_MAX_HEAD, cqe_bcnt);
1241 struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1242 u32 frag_offset = head_offset + headlen;
1243 u32 byte_cnt = cqe_bcnt - headlen;
1244 struct mlx5e_dma_info *head_di = di;
1245 struct sk_buff *skb;
1247 skb = napi_alloc_skb(rq->cq.napi,
1248 ALIGN(MLX5E_RX_MAX_HEAD, sizeof(long)));
1249 if (unlikely(!skb)) {
1250 rq->stats->buff_alloc_err++;
1254 prefetchw(skb->data);
1256 if (unlikely(frag_offset >= PAGE_SIZE)) {
1258 frag_offset -= PAGE_SIZE;
1262 u32 pg_consumed_bytes =
1263 min_t(u32, PAGE_SIZE - frag_offset, byte_cnt);
1264 unsigned int truesize =
1265 ALIGN(pg_consumed_bytes, BIT(rq->mpwqe.log_stride_sz));
1267 mlx5e_add_skb_frag(rq, skb, di, frag_offset,
1268 pg_consumed_bytes, truesize);
1269 byte_cnt -= pg_consumed_bytes;
1274 mlx5e_copy_skb_header(rq->pdev, skb, head_di, head_offset, headlen);
1275 /* skb linear part was allocated with headlen and aligned to long */
1276 skb->tail += headlen;
1277 skb->len += headlen;
1283 mlx5e_skb_from_cqe_mpwrq_linear(struct mlx5e_rq *rq, struct mlx5e_mpw_info *wi,
1284 u16 cqe_bcnt, u32 head_offset, u32 page_idx)
1286 struct mlx5e_dma_info *di = &wi->umr.dma_info[page_idx];
1287 u16 rx_headroom = rq->buff.headroom;
1288 u32 cqe_bcnt32 = cqe_bcnt;
1289 struct sk_buff *skb;
1294 /* Check packet size. Note LRO doesn't use linear SKB */
1295 if (unlikely(cqe_bcnt > rq->hw_mtu)) {
1296 rq->stats->oversize_pkts_sw_drop++;
1300 va = page_address(di->page) + head_offset;
1301 data = va + rx_headroom;
1302 frag_size = MLX5_SKB_FRAG_SZ(rx_headroom + cqe_bcnt32);
1304 dma_sync_single_range_for_cpu(rq->pdev, di->addr, head_offset,
1305 frag_size, DMA_FROM_DEVICE);
1306 prefetchw(va); /* xdp_frame data area */
1310 consumed = mlx5e_xdp_handle(rq, di, va, &rx_headroom, &cqe_bcnt32, false);
1313 if (__test_and_clear_bit(MLX5E_RQ_FLAG_XDP_XMIT, rq->flags))
1314 __set_bit(page_idx, wi->xdp_xmit_bitmap); /* non-atomic */
1315 return NULL; /* page/packet was consumed by XDP */
1318 skb = mlx5e_build_linear_skb(rq, va, frag_size, rx_headroom, cqe_bcnt32);
1322 /* queue up for recycling/reuse */
1323 page_ref_inc(di->page);
1328 void mlx5e_handle_rx_cqe_mpwrq(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1330 u16 cstrides = mpwrq_get_cqe_consumed_strides(cqe);
1331 u16 wqe_id = be16_to_cpu(cqe->wqe_id);
1332 struct mlx5e_mpw_info *wi = &rq->mpwqe.info[wqe_id];
1333 u16 stride_ix = mpwrq_get_cqe_stride_index(cqe);
1334 u32 wqe_offset = stride_ix << rq->mpwqe.log_stride_sz;
1335 u32 head_offset = wqe_offset & (PAGE_SIZE - 1);
1336 u32 page_idx = wqe_offset >> PAGE_SHIFT;
1337 struct mlx5e_rx_wqe_ll *wqe;
1338 struct mlx5_wq_ll *wq;
1339 struct sk_buff *skb;
1342 wi->consumed_strides += cstrides;
1344 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1345 trigger_report(rq, cqe);
1346 rq->stats->wqe_err++;
1350 if (unlikely(mpwrq_is_filler_cqe(cqe))) {
1351 struct mlx5e_rq_stats *stats = rq->stats;
1353 stats->mpwqe_filler_cqes++;
1354 stats->mpwqe_filler_strides += cstrides;
1358 cqe_bcnt = mpwrq_get_cqe_byte_cnt(cqe);
1360 skb = INDIRECT_CALL_2(rq->mpwqe.skb_from_cqe_mpwrq,
1361 mlx5e_skb_from_cqe_mpwrq_linear,
1362 mlx5e_skb_from_cqe_mpwrq_nonlinear,
1363 rq, wi, cqe_bcnt, head_offset, page_idx);
1367 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1368 napi_gro_receive(rq->cq.napi, skb);
1371 if (likely(wi->consumed_strides < rq->mpwqe.num_strides))
1375 wqe = mlx5_wq_ll_get_wqe(wq, wqe_id);
1376 mlx5e_free_rx_mpwqe(rq, wi, true);
1377 mlx5_wq_ll_pop(wq, cqe->wqe_id, &wqe->next.next_wqe_index);
1380 int mlx5e_poll_rx_cq(struct mlx5e_cq *cq, int budget)
1382 struct mlx5e_rq *rq = container_of(cq, struct mlx5e_rq, cq);
1383 struct mlx5_cqwq *cqwq = &cq->wq;
1384 struct mlx5_cqe64 *cqe;
1387 if (unlikely(!test_bit(MLX5E_RQ_STATE_ENABLED, &rq->state)))
1391 work_done += mlx5e_decompress_cqes_cont(rq, cqwq, 0, budget);
1392 if (rq->cqd.left || work_done >= budget)
1396 cqe = mlx5_cqwq_get_cqe(cqwq);
1398 if (unlikely(work_done))
1404 if (mlx5_get_cqe_format(cqe) == MLX5_COMPRESSED) {
1406 mlx5e_decompress_cqes_start(rq, cqwq,
1407 budget - work_done);
1411 mlx5_cqwq_pop(cqwq);
1413 INDIRECT_CALL_2(rq->handle_rx_cqe, mlx5e_handle_rx_cqe_mpwrq,
1414 mlx5e_handle_rx_cqe, rq, cqe);
1415 } while ((++work_done < budget) && (cqe = mlx5_cqwq_get_cqe(cqwq)));
1419 mlx5e_xdp_rx_poll_complete(rq);
1421 mlx5_cqwq_update_db_record(cqwq);
1423 /* ensure cq space is freed before enabling more cqes */
1429 #ifdef CONFIG_MLX5_CORE_IPOIB
1431 #define MLX5_IB_GRH_SGID_OFFSET 8
1432 #define MLX5_IB_GRH_DGID_OFFSET 24
1433 #define MLX5_GID_SIZE 16
1435 static inline void mlx5i_complete_rx_cqe(struct mlx5e_rq *rq,
1436 struct mlx5_cqe64 *cqe,
1438 struct sk_buff *skb)
1440 struct hwtstamp_config *tstamp;
1441 struct mlx5e_rq_stats *stats;
1442 struct net_device *netdev;
1443 struct mlx5e_priv *priv;
1444 char *pseudo_header;
1450 qpn = be32_to_cpu(cqe->sop_drop_qpn) & 0xffffff;
1451 netdev = mlx5i_pkey_get_netdev(rq->netdev, qpn);
1453 /* No mapping present, cannot process SKB. This might happen if a child
1454 * interface is going down while having unprocessed CQEs on parent RQ
1456 if (unlikely(!netdev)) {
1457 /* TODO: add drop counters support */
1459 pr_warn_once("Unable to map QPN %u to dev - dropping skb\n", qpn);
1463 priv = mlx5i_epriv(netdev);
1464 tstamp = &priv->tstamp;
1465 stats = &priv->channel_stats[rq->ix].rq;
1467 flags_rqpn = be32_to_cpu(cqe->flags_rqpn);
1468 g = (flags_rqpn >> 28) & 3;
1469 dgid = skb->data + MLX5_IB_GRH_DGID_OFFSET;
1470 if ((!g) || dgid[0] != 0xff)
1471 skb->pkt_type = PACKET_HOST;
1472 else if (memcmp(dgid, netdev->broadcast + 4, MLX5_GID_SIZE) == 0)
1473 skb->pkt_type = PACKET_BROADCAST;
1475 skb->pkt_type = PACKET_MULTICAST;
1477 /* Drop packets that this interface sent, ie multicast packets
1478 * that the HCA has replicated.
1480 if (g && (qpn == (flags_rqpn & 0xffffff)) &&
1481 (memcmp(netdev->dev_addr + 4, skb->data + MLX5_IB_GRH_SGID_OFFSET,
1482 MLX5_GID_SIZE) == 0)) {
1487 skb_pull(skb, MLX5_IB_GRH_BYTES);
1489 skb->protocol = *((__be16 *)(skb->data));
1491 if (netdev->features & NETIF_F_RXCSUM) {
1492 skb->ip_summed = CHECKSUM_COMPLETE;
1493 skb->csum = csum_unfold((__force __sum16)cqe->check_sum);
1494 stats->csum_complete++;
1496 skb->ip_summed = CHECKSUM_NONE;
1500 if (unlikely(mlx5e_rx_hw_stamp(tstamp)))
1501 skb_hwtstamps(skb)->hwtstamp =
1502 mlx5_timecounter_cyc2time(rq->clock, get_cqe_ts(cqe));
1504 skb_record_rx_queue(skb, rq->ix);
1506 if (likely(netdev->features & NETIF_F_RXHASH))
1507 mlx5e_skb_set_hash(cqe, skb);
1509 /* 20 bytes of ipoib header and 4 for encap existing */
1510 pseudo_header = skb_push(skb, MLX5_IPOIB_PSEUDO_LEN);
1511 memset(pseudo_header, 0, MLX5_IPOIB_PSEUDO_LEN);
1512 skb_reset_mac_header(skb);
1513 skb_pull(skb, MLX5_IPOIB_HARD_LEN);
1518 stats->bytes += cqe_bcnt;
1521 void mlx5i_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1523 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1524 struct mlx5e_wqe_frag_info *wi;
1525 struct sk_buff *skb;
1529 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1530 wi = get_frag(rq, ci);
1531 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1533 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1534 rq->stats->wqe_err++;
1538 skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe,
1539 mlx5e_skb_from_cqe_linear,
1540 mlx5e_skb_from_cqe_nonlinear,
1541 rq, cqe, wi, cqe_bcnt);
1545 mlx5i_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1546 if (unlikely(!skb->dev)) {
1547 dev_kfree_skb_any(skb);
1550 napi_gro_receive(rq->cq.napi, skb);
1553 mlx5e_free_rx_wqe(rq, wi, true);
1554 mlx5_wq_cyc_pop(wq);
1557 #endif /* CONFIG_MLX5_CORE_IPOIB */
1559 #ifdef CONFIG_MLX5_EN_IPSEC
1561 void mlx5e_ipsec_handle_rx_cqe(struct mlx5e_rq *rq, struct mlx5_cqe64 *cqe)
1563 struct mlx5_wq_cyc *wq = &rq->wqe.wq;
1564 struct mlx5e_wqe_frag_info *wi;
1565 struct sk_buff *skb;
1569 ci = mlx5_wq_cyc_ctr2ix(wq, be16_to_cpu(cqe->wqe_counter));
1570 wi = get_frag(rq, ci);
1571 cqe_bcnt = be32_to_cpu(cqe->byte_cnt);
1573 if (unlikely(MLX5E_RX_ERR_CQE(cqe))) {
1574 rq->stats->wqe_err++;
1578 skb = INDIRECT_CALL_2(rq->wqe.skb_from_cqe,
1579 mlx5e_skb_from_cqe_linear,
1580 mlx5e_skb_from_cqe_nonlinear,
1581 rq, cqe, wi, cqe_bcnt);
1582 if (unlikely(!skb)) /* a DROP, save the page-reuse checks */
1585 skb = mlx5e_ipsec_handle_rx_skb(rq->netdev, skb, &cqe_bcnt);
1589 mlx5e_complete_rx_cqe(rq, cqe, cqe_bcnt, skb);
1590 napi_gro_receive(rq->cq.napi, skb);
1593 mlx5e_free_rx_wqe(rq, wi, true);
1594 mlx5_wq_cyc_pop(wq);
1597 #endif /* CONFIG_MLX5_EN_IPSEC */